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source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC/smc.c @ 46

Last change on this file since 46 was 46, checked in by jrpelegrina, 4 years ago
First release to Xenial
File size: 31.3 KB

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1	/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
2
3	/This file is prepared for Doxygen automatic documentation generation./
4	/! \file ********************************************************************
5	*
6	* \brief SMC on EBI driver for AVR32 UC3.
7	*
8	* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
9	* - Supported devices: All AVR32 devices with a SMC module can be used.
10	* - AppNote:
11	*
12	* \author Atmel Corporation: http://www.atmel.com \n
13	* Support and FAQ: http://support.atmel.no/
14	*
15	******************************************************************************/
16
17	/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
18	*
19	* Redistribution and use in source and binary forms, with or without
20	* modification, are permitted provided that the following conditions are met:
21	*
22	* 1. Redistributions of source code must retain the above copyright notice, this
23	* list of conditions and the following disclaimer.
24	*
25	* 2. Redistributions in binary form must reproduce the above copyright notice,
26	* this list of conditions and the following disclaimer in the documentation
27	* and/or other materials provided with the distribution.
28	*
29	* 3. The name of Atmel may not be used to endorse or promote products derived
30	* from this software without specific prior written permission.
31	*
32	* 4. This software may only be redistributed and used in connection with an Atmel
33	* AVR product.
34	*
35	* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
36	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
37	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
38	* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
39	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
40	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
41	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
42	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
44	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
45	*
46	*/
47
48	#include "compiler.h"
49	#include "preprocessor.h"
50	#include "gpio.h"
51	#include "smc.h"
52
53	// Configure the SM Controller with SM setup and timing information for all chip select
54	#define SMC_CS_SETUP(ncs) { \
55	U32 nwe_setup = ((NWE_SETUP * hsb_mhz_up + 999) / 1000); \
56	U32 ncs_wr_setup = ((NCS_WR_SETUP * hsb_mhz_up + 999) / 1000); \
57	U32 nrd_setup = ((NRD_SETUP * hsb_mhz_up + 999) / 1000); \
58	U32 ncs_rd_setup = ((NCS_RD_SETUP * hsb_mhz_up + 999) / 1000); \
59	U32 nwe_pulse = ((NWE_PULSE * hsb_mhz_up + 999) / 1000); \
60	U32 ncs_wr_pulse = ((NCS_WR_PULSE * hsb_mhz_up + 999) / 1000); \
61	U32 nrd_pulse = ((NRD_PULSE * hsb_mhz_up + 999) / 1000); \
62	U32 ncs_rd_pulse = ((NCS_RD_PULSE * hsb_mhz_up + 999) / 1000); \
63	U32 nwe_cycle = ((NWE_CYCLE * hsb_mhz_up + 999) / 1000); \
64	U32 nrd_cycle = ((NRD_CYCLE * hsb_mhz_up + 999) / 1000); \
65	\
66	/* Some coherence checks... */ \
67	/* Ensures CS is active during Rd or Wr */ \
68	if( ncs_rd_setup + ncs_rd_pulse < nrd_setup + nrd_pulse ) \
69	ncs_rd_pulse = nrd_setup + nrd_pulse - ncs_rd_setup; \
70	if( ncs_wr_setup + ncs_wr_pulse < nwe_setup + nwe_pulse ) \
71	ncs_wr_pulse = nwe_setup + nwe_pulse - ncs_wr_setup; \
72	\
73	/* ncs_hold = n_cycle - ncs_setup - ncs_pulse */ \
74	/* n_hold = n_cycle - n_setup - n_pulse */ \
75	/* */ \
76	/* All holds parameters must be positive or null, so: */ \
77	/* nwe_cycle shall be >= ncs_wr_setup + ncs_wr_pulse */ \
78	if( nwe_cycle < ncs_wr_setup + ncs_wr_pulse ) \
79	nwe_cycle = ncs_wr_setup + ncs_wr_pulse; \
80	\
81	/* nwe_cycle shall be >= nwe_setup + nwe_pulse */ \
82	if( nwe_cycle < nwe_setup + nwe_pulse ) \
83	nwe_cycle = nwe_setup + nwe_pulse; \
84	\
85	/* nrd_cycle shall be >= ncs_rd_setup + ncs_rd_pulse */ \
86	if( nrd_cycle < ncs_rd_setup + ncs_rd_pulse ) \
87	nrd_cycle = ncs_rd_setup + ncs_rd_pulse; \
88	\
89	/* nrd_cycle shall be >= nrd_setup + nrd_pulse */ \
90	if( nrd_cycle < nrd_setup + nrd_pulse ) \
91	nrd_cycle = nrd_setup + nrd_pulse; \
92	\
93	AVR32_SMC.cs[ncs].setup = (nwe_setup << AVR32_SMC_SETUP0_NWE_SETUP_OFFSET) \| \
94	(ncs_wr_setup << AVR32_SMC_SETUP0_NCS_WR_SETUP_OFFSET) \| \
95	(nrd_setup << AVR32_SMC_SETUP0_NRD_SETUP_OFFSET) \| \
96	(ncs_rd_setup << AVR32_SMC_SETUP0_NCS_RD_SETUP_OFFSET); \
97	AVR32_SMC.cs[ncs].pulse = (nwe_pulse << AVR32_SMC_PULSE0_NWE_PULSE_OFFSET) \| \
98	(ncs_wr_pulse << AVR32_SMC_PULSE0_NCS_WR_PULSE_OFFSET) \| \
99	(nrd_pulse << AVR32_SMC_PULSE0_NRD_PULSE_OFFSET) \| \
100	(ncs_rd_pulse << AVR32_SMC_PULSE0_NCS_RD_PULSE_OFFSET); \
101	AVR32_SMC.cs[ncs].cycle = (nwe_cycle << AVR32_SMC_CYCLE0_NWE_CYCLE_OFFSET) \| \
102	(nrd_cycle << AVR32_SMC_CYCLE0_NRD_CYCLE_OFFSET); \
103	AVR32_SMC.cs[ncs].mode = (((NCS_CONTROLLED_READ) ? AVR32_SMC_MODE0_READ_MODE_NCS_CONTROLLED : \
104	AVR32_SMC_MODE0_READ_MODE_NRD_CONTROLLED) << AVR32_SMC_MODE0_READ_MODE_OFFSET) \| \
105	+ (((NCS_CONTROLLED_WRITE) ? AVR32_SMC_MODE0_WRITE_MODE_NCS_CONTROLLED : \
106	AVR32_SMC_MODE0_WRITE_MODE_NWE_CONTROLLED) << AVR32_SMC_MODE0_WRITE_MODE_OFFSET) \| \
107	(NWAIT_MODE << AVR32_SMC_MODE0_EXNW_MODE_OFFSET) \| \
108	(((SMC_8_BIT_CHIPS) ? AVR32_SMC_MODE0_BAT_BYTE_WRITE : \
109	AVR32_SMC_MODE0_BAT_BYTE_SELECT) << AVR32_SMC_MODE0_BAT_OFFSET) \| \
110	(((SMC_DBW <= 8 ) ? AVR32_SMC_MODE0_DBW_8_BITS : \
111	(SMC_DBW <= 16) ? AVR32_SMC_MODE0_DBW_16_BITS : \
112	AVR32_SMC_MODE0_DBW_32_BITS) << AVR32_SMC_MODE0_DBW_OFFSET) \| \
113	(TDF_CYCLES << AVR32_SMC_MODE0_TDF_CYCLES_OFFSET) \| \
114	(TDF_OPTIM << AVR32_SMC_MODE0_TDF_MODE_OFFSET) \| \
115	(PAGE_MODE << AVR32_SMC_MODE0_PMEN_OFFSET) \| \
116	(PAGE_SIZE << AVR32_SMC_MODE0_PS_OFFSET); \
117	smc_tab_cs_size[ncs] = (U8)EXT_SM_SIZE; \
118	}
119
120	static U8 smc_tab_cs_size[6];
121
122	static void smc_enable_muxed_pins(void);
123
124
125	void smc_init(unsigned long hsb_hz)
126	{
127	unsigned long hsb_mhz_up = (hsb_hz + 999999) / 1000000;
128
129	//! Whether to use the NCS0 pin
130	#ifdef SMC_USE_NCS0
131	#include SMC_COMPONENT_CS0
132
133	// Setup SMC for NCS0
134	SMC_CS_SETUP(0)
135
136	#ifdef SMC_DBW_GLOBAL
137	#if (SMC_DBW_GLOBAL < SMC_DBW)
138	#undef SMC_DBW_GLOBAL
139	#if (SMC_DBW == 8)
140	#define SMC_DBW_GLOBAL 8
141	#elif (SMC_DBW == 16)
142	#define SMC_DBW_GLOBAL 16
143	#elif (SMC_DBW == 32)
144	#define SMC_DBW_GLOBAL 32
145	#else
146	#error error in SMC_DBW size
147	#endif
148	#endif
149	#else
150	#if (SMC_DBW == 8)
151	#define SMC_DBW_GLOBAL 8
152	#elif (SMC_DBW == 16)
153	#define SMC_DBW_GLOBAL 16
154	#elif (SMC_DBW == 32)
155	#define SMC_DBW_GLOBAL 32
156	#else
157	#error error in SMC_DBW size
158	#endif
159	#endif
160
161	#ifdef SMC_8_BIT_CHIPS_GLOBAL
162	#if (SMC_8_BIT_CHIPS_GLOBAL < SMC_8_BIT)
163	#undef SMC_8_BIT_CHIPS_GLOBAL
164	#if (SMC_8_BIT_CHIPS == TRUE)
165	#define SMC_8_BIT_CHIPS_GLOBAL TRUE
166	#elif (SMC_8_BIT_CHIPS == FALSE)
167	#define SMC_8_BIT_CHIPS_GLOBAL FALSE
168	#else
169	#error error in SMC_8_BIT_CHIPS size
170	#endif
171	#endif
172	#else
173	#if (SMC_8_BIT_CHIPS == TRUE)
174	#define SMC_8_BIT_CHIPS_GLOBAL TRUE
175	#elif (SMC_8_BIT_CHIPS == FALSE)
176	#define SMC_8_BIT_CHIPS_GLOBAL FALSE
177	#else
178	#error error in SMC_8_BIT_CHIPS size
179	#endif
180	#endif
181
182	#ifdef NWAIT_MODE_GLOBAL
183	#if (NWAIT_MODE_GLOBAL < NWAIT_MODE)
184	#undef NWAIT_MODE_GLOBAL
185	#if (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
186	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_DISABLED
187	#elif (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
188	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_FROZEN
189	#else
190	#error error in NWAIT_MODE size
191	#endif
192	#endif
193	#else
194	#if (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
195	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_DISABLED
196	#elif (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
197	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_FROZEN
198	#else
199	#error error in NWAIT_MODE size
200	#endif
201	#endif
202
203	#undef EXT_SM_SIZE
204	#undef SMC_DBW
205	#undef SMC_8_BIT_CHIPS
206	#undef NWE_SETUP
207	#undef NCS_WR_SETUP
208	#undef NRD_SETUP
209	#undef NCS_RD_SETUP
210	#undef NCS_WR_PULSE
211	#undef NWE_PULSE
212	#undef NCS_RD_PULSE
213	#undef NRD_PULSE
214	#undef NCS_WR_HOLD
215	#undef NWE_HOLD
216	#undef NWE_CYCLE
217	#undef NCS_RD_HOLD
218	#undef NRD_CYCLE
219	#undef TDF_CYCLES
220	#undef TDF_OPTIM
221	#undef PAGE_MODE
222	#undef PAGE_SIZE
223	#undef NCS_CONTROLLED_READ
224	#undef NCS_CONTROLLED_WRITE
225	#undef NWAIT_MODE
226	#endif
227
228
229	//! Whether to use the NCS1 pin
230	#ifdef SMC_USE_NCS1
231	#include SMC_COMPONENT_CS1
232
233	// Enable SM mode for CS1 if necessary.
234	AVR32_HMATRIX.sfr[AVR32_EBI_HMATRIX_NR] &= ~(1 << AVR32_EBI_SDRAM_CS);
235	AVR32_HMATRIX.sfr[AVR32_EBI_HMATRIX_NR];
236
237	// Setup SMC for NCS1
238	SMC_CS_SETUP(1)
239
240	#ifdef SMC_DBW_GLOBAL
241	#if (SMC_DBW_GLOBAL < SMC_DBW)
242	#undef SMC_DBW_GLOBAL
243	#if (SMC_DBW == 8)
244	#define SMC_DBW_GLOBAL 8
245	#elif (SMC_DBW == 16)
246	#define SMC_DBW_GLOBAL 16
247	#elif (SMC_DBW == 32)
248	#define SMC_DBW_GLOBAL 32
249	#else
250	#error error in SMC_DBW size
251	#endif
252	#endif
253	#else
254	#if (SMC_DBW == 8)
255	#define SMC_DBW_GLOBAL 8
256	#elif (SMC_DBW == 16)
257	#define SMC_DBW_GLOBAL 16
258	#elif (SMC_DBW == 32)
259	#define SMC_DBW_GLOBAL 32
260	#else
261	#error error in SMC_DBW size
262	#endif
263	#endif
264
265	#ifdef SMC_8_BIT_CHIPS_GLOBAL
266	#if (SMC_8_BIT_CHIPS_GLOBAL < SMC_8_BIT)
267	#undef SMC_8_BIT_CHIPS_GLOBAL
268	#if (SMC_8_BIT_CHIPS == TRUE)
269	#define SMC_8_BIT_CHIPS_GLOBAL TRUE
270	#elif (SMC_8_BIT_CHIPS == FALSE)
271	#define SMC_8_BIT_CHIPS_GLOBAL FALSE
272	#else
273	#error error in SMC_8_BIT_CHIPS size
274	#endif
275	#endif
276	#else
277	#if (SMC_8_BIT_CHIPS == TRUE)
278	#define SMC_8_BIT_CHIPS_GLOBAL TRUE
279	#elif (SMC_8_BIT_CHIPS == FALSE)
280	#define SMC_8_BIT_CHIPS_GLOBAL FALSE
281	#else
282	#error error in SMC_8_BIT_CHIPS size
283	#endif
284	#endif
285
286	#ifdef NWAIT_MODE_GLOBAL
287	#if (NWAIT_MODE_GLOBAL < NWAIT_MODE)
288	#undef NWAIT_MODE_GLOBAL
289	#if (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
290	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_DISABLED
291	#elif (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
292	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_FROZEN
293	#else
294	#error error in NWAIT_MODE size
295	#endif
296	#endif
297	#else
298	#if (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
299	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_DISABLED
300	#elif (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
301	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_FROZEN
302	#else
303	#error error in NWAIT_MODE size
304	#endif
305	#endif
306
307	#undef EXT_SM_SIZE
308	#undef SMC_DBW
309	#undef SMC_8_BIT_CHIPS
310	#undef NWE_SETUP
311	#undef NCS_WR_SETUP
312	#undef NRD_SETUP
313	#undef NCS_RD_SETUP
314	#undef NCS_WR_PULSE
315	#undef NWE_PULSE
316	#undef NCS_RD_PULSE
317	#undef NRD_PULSE
318	#undef NCS_WR_HOLD
319	#undef NWE_HOLD
320	#undef NWE_CYCLE
321	#undef NCS_RD_HOLD
322	#undef NRD_CYCLE
323	#undef TDF_CYCLES
324	#undef TDF_OPTIM
325	#undef PAGE_MODE
326	#undef PAGE_SIZE
327	#undef NCS_CONTROLLED_READ
328	#undef NCS_CONTROLLED_WRITE
329	#undef NWAIT_MODE
330	#endif
331
332	//! Whether to use the NCS2 pin
333	#ifdef SMC_USE_NCS2
334	#include SMC_COMPONENT_CS2
335
336	// Setup SMC for NCS2
337	SMC_CS_SETUP(2)
338
339	#ifdef SMC_DBW_GLOBAL
340	#if (SMC_DBW_GLOBAL < SMC_DBW)
341	#undef SMC_DBW_GLOBAL
342	#if (SMC_DBW == 8)
343	#define SMC_DBW_GLOBAL 8
344	#elif (SMC_DBW == 16)
345	#define SMC_DBW_GLOBAL 16
346	#elif (SMC_DBW == 32)
347	#define SMC_DBW_GLOBAL 32
348	#else
349	#error error in SMC_DBW size
350	#endif
351	#endif
352	#else
353	#if (SMC_DBW == 8)
354	#define SMC_DBW_GLOBAL 8
355	#elif (SMC_DBW == 16)
356	#define SMC_DBW_GLOBAL 16
357	#elif (SMC_DBW == 32)
358	#define SMC_DBW_GLOBAL 32
359	#else
360	#error error in SMC_DBW size
361	#endif
362	#endif
363
364	#ifdef SMC_8_BIT_CHIPS_GLOBAL
365	#if (SMC_8_BIT_CHIPS_GLOBAL < SMC_8_BIT)
366	#undef SMC_8_BIT_CHIPS_GLOBAL
367	#if (SMC_8_BIT_CHIPS == TRUE)
368	#define SMC_8_BIT_CHIPS_GLOBAL TRUE
369	#elif (SMC_8_BIT_CHIPS == FALSE)
370	#define SMC_8_BIT_CHIPS_GLOBAL FALSE
371	#else
372	#error error in SMC_8_BIT_CHIPS size
373	#endif
374	#endif
375	#else
376	#if (SMC_8_BIT_CHIPS == TRUE)
377	#define SMC_8_BIT_CHIPS_GLOBAL TRUE
378	#elif (SMC_8_BIT_CHIPS == FALSE)
379	#define SMC_8_BIT_CHIPS_GLOBAL FALSE
380	#else
381	#error error in SMC_8_BIT_CHIPS size
382	#endif
383	#endif
384
385	#ifdef NWAIT_MODE_GLOBAL
386	#if (NWAIT_MODE_GLOBAL < NWAIT_MODE)
387	#undef NWAIT_MODE_GLOBAL
388	#if (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
389	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_DISABLED
390	#elif (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
391	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_FROZEN
392	#else
393	#error error in NWAIT_MODE size
394	#endif
395	#endif
396	#else
397	#if (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
398	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_DISABLED
399	#elif (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
400	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_FROZEN
401	#else
402	#error error in NWAIT_MODE size
403	#endif
404	#endif
405
406
407	#undef EXT_SM_SIZE
408	#undef SMC_DBW
409	#undef SMC_8_BIT_CHIPS
410	#undef NWE_SETUP
411	#undef NCS_WR_SETUP
412	#undef NRD_SETUP
413	#undef NCS_RD_SETUP
414	#undef NCS_WR_PULSE
415	#undef NWE_PULSE
416	#undef NCS_RD_PULSE
417	#undef NRD_PULSE
418	#undef NCS_WR_HOLD
419	#undef NWE_HOLD
420	#undef NWE_CYCLE
421	#undef NCS_RD_HOLD
422	#undef NRD_CYCLE
423	#undef TDF_CYCLES
424	#undef TDF_OPTIM
425	#undef PAGE_MODE
426	#undef PAGE_SIZE
427	#undef NCS_CONTROLLED_READ
428	#undef NCS_CONTROLLED_WRITE
429	#undef NWAIT_MODE
430	#endif
431
432	//! Whether to use the NCS3 pin
433	#ifdef SMC_USE_NCS3
434	#include SMC_COMPONENT_CS3
435
436	// Setup SMC for NCS3
437	SMC_CS_SETUP(3)
438
439	#ifdef SMC_DBW_GLOBAL
440	#if (SMC_DBW_GLOBAL < SMC_DBW)
441	#undef SMC_DBW_GLOBAL
442	#if (SMC_DBW == 8)
443	#define SMC_DBW_GLOBAL 8
444	#elif (SMC_DBW == 16)
445	#define SMC_DBW_GLOBAL 16
446	#elif (SMC_DBW == 32)
447	#define SMC_DBW_GLOBAL 32
448	#else
449	#error error in SMC_DBW size
450	#endif
451	#endif
452	#else
453	#if (SMC_DBW == 8)
454	#define SMC_DBW_GLOBAL 8
455	#elif (SMC_DBW == 16)
456	#define SMC_DBW_GLOBAL 16
457	#elif (SMC_DBW == 32)
458	#define SMC_DBW_GLOBAL 32
459	#else
460	#error error in SMC_DBW size
461	#endif
462	#endif
463
464	#ifdef SMC_8_BIT_CHIPS_GLOBAL
465	#if (SMC_8_BIT_CHIPS_GLOBAL < SMC_8_BIT)
466	#undef SMC_8_BIT_CHIPS_GLOBAL
467	#if (SMC_8_BIT_CHIPS == TRUE)
468	#define SMC_8_BIT_CHIPS_GLOBAL TRUE
469	#elif (SMC_8_BIT_CHIPS == FALSE)
470	#define SMC_8_BIT_CHIPS_GLOBAL FALSE
471	#else
472	#error error in SMC_8_BIT_CHIPS size
473	#endif
474	#endif
475	#else
476	#if (SMC_8_BIT_CHIPS == TRUE)
477	#define SMC_8_BIT_CHIPS_GLOBAL TRUE
478	#elif (SMC_8_BIT_CHIPS == FALSE)
479	#define SMC_8_BIT_CHIPS_GLOBAL FALSE
480	#else
481	#error error in SMC_8_BIT_CHIPS size
482	#endif
483	#endif
484
485	#ifdef NWAIT_MODE_GLOBAL
486	#if (NWAIT_MODE_GLOBAL < NWAIT_MODE)
487	#undef NWAIT_MODE_GLOBAL
488	#if (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
489	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_DISABLED
490	#elif (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
491	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_FROZEN
492	#else
493	#error error in NWAIT_MODE size
494	#endif
495	#endif
496	#else
497	#if (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
498	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_DISABLED
499	#elif (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
500	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_FROZEN
501	#else
502	#error error in NWAIT_MODE size
503	#endif
504	#endif
505
506
507	#undef EXT_SM_SIZE
508	#undef SMC_DBW
509	#undef SMC_8_BIT_CHIPS
510	#undef NWE_SETUP
511	#undef NCS_WR_SETUP
512	#undef NRD_SETUP
513	#undef NCS_RD_SETUP
514	#undef NCS_WR_PULSE
515	#undef NWE_PULSE
516	#undef NCS_RD_PULSE
517	#undef NRD_PULSE
518	#undef NCS_WR_HOLD
519	#undef NWE_HOLD
520	#undef NWE_CYCLE
521	#undef NCS_RD_HOLD
522	#undef NRD_CYCLE
523	#undef TDF_CYCLES
524	#undef TDF_OPTIM
525	#undef PAGE_MODE
526	#undef PAGE_SIZE
527	#undef NCS_CONTROLLED_READ
528	#undef NCS_CONTROLLED_WRITE
529	#undef NWAIT_MODE
530	#endif
531
532	//! Whether to use the NCS4 pin
533	#ifdef SMC_USE_NCS4
534	#include SMC_COMPONENT_CS4
535
536	// Setup SMC for NCS4
537	SMC_CS_SETUP(4)
538
539	#ifdef SMC_DBW_GLOBAL
540	#if (SMC_DBW_GLOBAL < SMC_DBW)
541	#undef SMC_DBW_GLOBAL
542	#if (SMC_DBW == 8)
543	#define SMC_DBW_GLOBAL 8
544	#elif (SMC_DBW == 16)
545	#define SMC_DBW_GLOBAL 16
546	#elif (SMC_DBW == 32)
547	#define SMC_DBW_GLOBAL 32
548	#else
549	#error error in SMC_DBW size
550	#endif
551	#endif
552	#else
553	#if (SMC_DBW == 8)
554	#define SMC_DBW_GLOBAL 8
555	#elif (SMC_DBW == 16)
556	#define SMC_DBW_GLOBAL 16
557	#elif (SMC_DBW == 32)
558	#define SMC_DBW_GLOBAL 32
559	#else
560	#error error in SMC_DBW size
561	#endif
562	#endif
563
564	#ifdef SMC_8_BIT_CHIPS_GLOBAL
565	#if (SMC_8_BIT_CHIPS_GLOBAL < SMC_8_BIT)
566	#undef SMC_8_BIT_CHIPS_GLOBAL
567	#if (SMC_8_BIT_CHIPS == TRUE)
568	#define SMC_8_BIT_CHIPS_GLOBAL TRUE
569	#elif (SMC_8_BIT_CHIPS == FALSE)
570	#define SMC_8_BIT_CHIPS_GLOBAL FALSE
571	#else
572	#error error in SMC_8_BIT_CHIPS size
573	#endif
574	#endif
575	#else
576	#if (SMC_8_BIT_CHIPS == TRUE)
577	#define SMC_8_BIT_CHIPS_GLOBAL TRUE
578	#elif (SMC_8_BIT_CHIPS == FALSE)
579	#define SMC_8_BIT_CHIPS_GLOBAL FALSE
580	#else
581	#error error in SMC_8_BIT_CHIPS size
582	#endif
583	#endif
584
585	#ifdef NWAIT_MODE_GLOBAL
586	#if (NWAIT_MODE_GLOBAL < NWAIT_MODE)
587	#undef NWAIT_MODE_GLOBAL
588	#if (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
589	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_DISABLED
590	#elif (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
591	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_FROZEN
592	#else
593	#error error in NWAIT_MODE size
594	#endif
595	#endif
596	#else
597	#if (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
598	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_DISABLED
599	#elif (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
600	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_FROZEN
601	#else
602	#error error in NWAIT_MODE size
603	#endif
604	#endif
605
606
607	#undef EXT_SM_SIZE
608	#undef SMC_DBW
609	#undef SMC_8_BIT_CHIPS
610	#undef NWE_SETUP
611	#undef NCS_WR_SETUP
612	#undef NRD_SETUP
613	#undef NCS_RD_SETUP
614	#undef NCS_WR_PULSE
615	#undef NWE_PULSE
616	#undef NCS_RD_PULSE
617	#undef NRD_PULSE
618	#undef NCS_WR_HOLD
619	#undef NWE_HOLD
620	#undef NWE_CYCLE
621	#undef NCS_RD_HOLD
622	#undef NRD_CYCLE
623	#undef TDF_CYCLES
624	#undef TDF_OPTIM
625	#undef PAGE_MODE
626	#undef PAGE_SIZE
627	#undef NCS_CONTROLLED_READ
628	#undef NCS_CONTROLLED_WRITE
629	#undef NWAIT_MODE
630	#endif
631
632	//! Whether to use the NCS5 pin
633	#ifdef SMC_USE_NCS5
634	#include SMC_COMPONENT_CS5
635
636	// Setup SMC for NCS5
637	SMC_CS_SETUP(5)
638
639	#ifdef SMC_DBW_GLOBAL
640	#if (SMC_DBW_GLOBAL < SMC_DBW)
641	#undef SMC_DBW_GLOBAL
642	#if (SMC_DBW == 8)
643	#define SMC_DBW_GLOBAL 8
644	#elif (SMC_DBW == 16)
645	#define SMC_DBW_GLOBAL 16
646	#elif (SMC_DBW == 32)
647	#define SMC_DBW_GLOBAL 32
648	#else
649	#error error in SMC_DBW size
650	#endif
651	#endif
652	#else
653	#if (SMC_DBW == 8)
654	#define SMC_DBW_GLOBAL 8
655	#elif (SMC_DBW == 16)
656	#define SMC_DBW_GLOBAL 16
657	#elif (SMC_DBW == 32)
658	#define SMC_DBW_GLOBAL 32
659	#else
660	#error error in SMC_DBW size
661	#endif
662	#endif
663
664	#ifdef SMC_8_BIT_CHIPS_GLOBAL
665	#if (SMC_8_BIT_CHIPS_GLOBAL < SMC_8_BIT)
666	#undef SMC_8_BIT_CHIPS_GLOBAL
667	#if (SMC_8_BIT_CHIPS == TRUE)
668	#define SMC_8_BIT_CHIPS_GLOBAL TRUE
669	#elif (SMC_8_BIT_CHIPS == FALSE)
670	#define SMC_8_BIT_CHIPS_GLOBAL FALSE
671	#else
672	#error error in SMC_8_BIT_CHIPS size
673	#endif
674	#endif
675	#else
676	#if (SMC_8_BIT_CHIPS == TRUE)
677	#define SMC_8_BIT_CHIPS_GLOBAL TRUE
678	#elif (SMC_8_BIT_CHIPS == FALSE)
679	#define SMC_8_BIT_CHIPS_GLOBAL FALSE
680	#else
681	#error error in SMC_8_BIT_CHIPS size
682	#endif
683	#endif
684
685	#ifdef NWAIT_MODE_GLOBAL
686	#if (NWAIT_MODE_GLOBAL < NWAIT_MODE)
687	#undef NWAIT_MODE_GLOBAL
688	#if (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
689	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_DISABLED
690	#elif (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
691	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_FROZEN
692	#else
693	#error error in NWAIT_MODE size
694	#endif
695	#endif
696	#else
697	#if (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
698	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_DISABLED
699	#elif (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
700	#define NWAIT_MODE_GLOBAL AVR32_SMC_EXNW_MODE_FROZEN
701	#else
702	#error error in NWAIT_MODE size
703	#endif
704	#endif
705
706
707	#undef EXT_SM_SIZE
708	#undef SMC_DBW
709	#undef SMC_8_BIT_CHIPS
710	#undef NWE_SETUP
711	#undef NCS_WR_SETUP
712	#undef NRD_SETUP
713	#undef NCS_RD_SETUP
714	#undef NCS_WR_PULSE
715	#undef NWE_PULSE
716	#undef NCS_RD_PULSE
717	#undef NRD_PULSE
718	#undef NCS_WR_HOLD
719	#undef NWE_HOLD
720	#undef NWE_CYCLE
721	#undef NCS_RD_HOLD
722	#undef NRD_CYCLE
723	#undef TDF_CYCLES
724	#undef TDF_OPTIM
725	#undef PAGE_MODE
726	#undef PAGE_SIZE
727	#undef NCS_CONTROLLED_READ
728	#undef NCS_CONTROLLED_WRITE
729	#undef NWAIT_MODE
730	#endif
731	// Put the multiplexed MCU pins used for the SM under control of the SMC.
732	smc_enable_muxed_pins();
733	}
734
735	/*! \brief Puts the multiplexed MCU pins used for the SMC
736	*
737	*/
738	static void smc_enable_muxed_pins(void)
739	{
740	static const gpio_map_t SMC_EBI_GPIO_MAP =
741	{
742	// Enable data pins.
743	#ifdef EBI_DATA_0
744	{ATPASTE2(EBI_DATA_0,_PIN),ATPASTE2(EBI_DATA_0,_FUNCTION)},
745	#endif
746	#ifdef EBI_DATA_1
747	{ATPASTE2(EBI_DATA_1,_PIN),ATPASTE2(EBI_DATA_1,_FUNCTION)},
748	#endif
749	#ifdef EBI_DATA_2
750	{ATPASTE2(EBI_DATA_2,_PIN),ATPASTE2(EBI_DATA_2,_FUNCTION)},
751	#endif
752	#ifdef EBI_DATA_3
753	{ATPASTE2(EBI_DATA_3,_PIN),ATPASTE2(EBI_DATA_3,_FUNCTION)},
754	#endif
755	#ifdef EBI_DATA_4
756	{ATPASTE2(EBI_DATA_4,_PIN),ATPASTE2(EBI_DATA_4,_FUNCTION)},
757	#endif
758	#ifdef EBI_DATA_5
759	{ATPASTE2(EBI_DATA_5,_PIN),ATPASTE2(EBI_DATA_5,_FUNCTION)},
760	#endif
761	#ifdef EBI_DATA_6
762	{ATPASTE2(EBI_DATA_6,_PIN),ATPASTE2(EBI_DATA_6,_FUNCTION)},
763	#endif
764	#ifdef EBI_DATA_7
765	{ATPASTE2(EBI_DATA_7,_PIN),ATPASTE2(EBI_DATA_7,_FUNCTION)},
766	#endif
767	#ifdef EBI_DATA_8
768	{ATPASTE2(EBI_DATA_8,_PIN),ATPASTE2(EBI_DATA_8,_FUNCTION)},
769	#endif
770	#ifdef EBI_DATA_9
771	{ATPASTE2(EBI_DATA_9,_PIN),ATPASTE2(EBI_DATA_9,_FUNCTION)},
772	#endif
773	#ifdef EBI_DATA_10
774	{ATPASTE2(EBI_DATA_10,_PIN),ATPASTE2(EBI_DATA_10,_FUNCTION)},
775	#endif
776	#ifdef EBI_DATA_11
777	{ATPASTE2(EBI_DATA_11,_PIN),ATPASTE2(EBI_DATA_11,_FUNCTION)},
778	#endif
779	#ifdef EBI_DATA_12
780	{ATPASTE2(EBI_DATA_12,_PIN),ATPASTE2(EBI_DATA_12,_FUNCTION)},
781	#endif
782	#ifdef EBI_DATA_13
783	{ATPASTE2(EBI_DATA_13,_PIN),ATPASTE2(EBI_DATA_13,_FUNCTION)},
784	#endif
785	#ifdef EBI_DATA_14
786	{ATPASTE2(EBI_DATA_14,_PIN),ATPASTE2(EBI_DATA_14,_FUNCTION)},
787	#endif
788	#ifdef EBI_DATA_15
789	{ATPASTE2(EBI_DATA_15,_PIN),ATPASTE2(EBI_DATA_15,_FUNCTION)},
790	#endif
791	#ifdef EBI_DATA_16
792	{ATPASTE2(EBI_DATA_16,_PIN),ATPASTE2(EBI_DATA_16,_FUNCTION)},
793	#endif
794	#ifdef EBI_DATA_17
795	{ATPASTE2(EBI_DATA_17,_PIN),ATPASTE2(EBI_DATA_17,_FUNCTION)},
796	#endif
797	#ifdef EBI_DATA_18
798	{ATPASTE2(EBI_DATA_18,_PIN),ATPASTE2(EBI_DATA_18,_FUNCTION)},
799	#endif
800	#ifdef EBI_DATA_19
801	{ATPASTE2(EBI_DATA_19,_PIN),ATPASTE2(EBI_DATA_19,_FUNCTION)},
802	#endif
803	#ifdef EBI_DATA_20
804	{ATPASTE2(EBI_DATA_20,_PIN),ATPASTE2(EBI_DATA_20,_FUNCTION)},
805	#endif
806	#ifdef EBI_DATA_21
807	{ATPASTE2(EBI_DATA_21,_PIN),ATPASTE2(EBI_DATA_21,_FUNCTION)},
808	#endif
809	#ifdef EBI_DATA_22
810	{ATPASTE2(EBI_DATA_22,_PIN),ATPASTE2(EBI_DATA_22,_FUNCTION)},
811	#endif
812	#ifdef EBI_DATA_23
813	{ATPASTE2(EBI_DATA_23,_PIN),ATPASTE2(EBI_DATA_23,_FUNCTION)},
814	#endif
815	#ifdef EBI_DATA_24
816	{ATPASTE2(EBI_DATA_24,_PIN),ATPASTE2(EBI_DATA_24,_FUNCTION)},
817	#endif
818	#ifdef EBI_DATA_25
819	{ATPASTE2(EBI_DATA_25,_PIN),ATPASTE2(EBI_DATA_25,_FUNCTION)},
820	#endif
821	#ifdef EBI_DATA_26
822	{ATPASTE2(EBI_DATA_26,_PIN),ATPASTE2(EBI_DATA_26,_FUNCTION)},
823	#endif
824	#ifdef EBI_DATA_27
825	{ATPASTE2(EBI_DATA_27,_PIN),ATPASTE2(EBI_DATA_27,_FUNCTION)},
826	#endif
827	#ifdef EBI_DATA_28
828	{ATPASTE2(EBI_DATA_28,_PIN),ATPASTE2(EBI_DATA_28,_FUNCTION)},
829	#endif
830	#ifdef EBI_DATA_29
831	{ATPASTE2(EBI_DATA_29,_PIN),ATPASTE2(EBI_DATA_29,_FUNCTION)},
832	#endif
833	#ifdef EBI_DATA_30
834	{ATPASTE2(EBI_DATA_30,_PIN),ATPASTE2(EBI_DATA_30,_FUNCTION)},
835	#endif
836	#ifdef EBI_DATA_31
837	{ATPASTE2(EBI_DATA_31,_PIN),ATPASTE2(EBI_DATA_31,_FUNCTION)},
838	#endif
839
840	// Enable address pins.
841	#if SMC_DBW_GLOBAL <= 8
842	#ifdef EBI_ADDR_0
843	{ATPASTE2(EBI_ADDR_0,_PIN),ATPASTE2(EBI_ADDR_0,_FUNCTION)},
844	#endif
845	#endif
846	#if SMC_DBW_GLOBAL <= 16
847	#ifdef EBI_ADDR_1
848	{ATPASTE2(EBI_ADDR_1,_PIN),ATPASTE2(EBI_ADDR_1,_FUNCTION)},
849	#endif
850	#endif
851
852	#ifdef EBI_ADDR_2
853	{ATPASTE2(EBI_ADDR_2,_PIN),ATPASTE2(EBI_ADDR_2,_FUNCTION)},
854	#endif
855	#ifdef EBI_ADDR_3
856	{ATPASTE2(EBI_ADDR_3,_PIN),ATPASTE2(EBI_ADDR_3,_FUNCTION)},
857	#endif
858	#ifdef EBI_ADDR_4
859	{ATPASTE2(EBI_ADDR_4,_PIN),ATPASTE2(EBI_ADDR_4,_FUNCTION)},
860	#endif
861	#ifdef EBI_ADDR_5
862	{ATPASTE2(EBI_ADDR_5,_PIN),ATPASTE2(EBI_ADDR_5,_FUNCTION)},
863	#endif
864	#ifdef EBI_ADDR_6
865	{ATPASTE2(EBI_ADDR_6,_PIN),ATPASTE2(EBI_ADDR_6,_FUNCTION)},
866	#endif
867	#ifdef EBI_ADDR_7
868	{ATPASTE2(EBI_ADDR_7,_PIN),ATPASTE2(EBI_ADDR_7,_FUNCTION)},
869	#endif
870	#ifdef EBI_ADDR_8
871	{ATPASTE2(EBI_ADDR_8,_PIN),ATPASTE2(EBI_ADDR_8,_FUNCTION)},
872	#endif
873	#ifdef EBI_ADDR_9
874	{ATPASTE2(EBI_ADDR_9,_PIN),ATPASTE2(EBI_ADDR_9,_FUNCTION)},
875	#endif
876	#ifdef EBI_ADDR_10
877	{ATPASTE2(EBI_ADDR_10,_PIN),ATPASTE2(EBI_ADDR_10,_FUNCTION)},
878	#endif
879	#ifdef EBI_ADDR_11
880	{ATPASTE2(EBI_ADDR_11,_PIN),ATPASTE2(EBI_ADDR_11,_FUNCTION)},
881	#endif
882	#ifdef EBI_ADDR_12
883	{ATPASTE2(EBI_ADDR_12,_PIN),ATPASTE2(EBI_ADDR_12,_FUNCTION)},
884	#endif
885	#ifdef EBI_ADDR_13
886	{ATPASTE2(EBI_ADDR_13,_PIN),ATPASTE2(EBI_ADDR_13,_FUNCTION)},
887	#endif
888	#ifdef EBI_ADDR_14
889	{ATPASTE2(EBI_ADDR_14,_PIN),ATPASTE2(EBI_ADDR_14,_FUNCTION)},
890	#endif
891	#ifdef EBI_ADDR_15
892	{ATPASTE2(EBI_ADDR_15,_PIN),ATPASTE2(EBI_ADDR_15,_FUNCTION)},
893	#endif
894	#ifdef EBI_ADDR_16
895	{ATPASTE2(EBI_ADDR_16,_PIN),ATPASTE2(EBI_ADDR_16,_FUNCTION)},
896	#endif
897	#ifdef EBI_ADDR_17
898	{ATPASTE2(EBI_ADDR_17,_PIN),ATPASTE2(EBI_ADDR_17,_FUNCTION)},
899	#endif
900	#ifdef EBI_ADDR_18
901	{ATPASTE2(EBI_ADDR_18,_PIN),ATPASTE2(EBI_ADDR_18,_FUNCTION)},
902	#endif
903	#ifdef EBI_ADDR_19
904	{ATPASTE2(EBI_ADDR_19,_PIN),ATPASTE2(EBI_ADDR_19,_FUNCTION)},
905	#endif
906	#ifdef EBI_ADDR_20
907	{ATPASTE2(EBI_ADDR_20,_PIN),ATPASTE2(EBI_ADDR_20,_FUNCTION)},
908	#endif
909	#ifdef EBI_ADDR_21
910	{ATPASTE2(EBI_ADDR_21,_PIN),ATPASTE2(EBI_ADDR_21,_FUNCTION)},
911	#endif
912	#ifdef EBI_ADDR_22
913	{ATPASTE2(EBI_ADDR_22,_PIN),ATPASTE2(EBI_ADDR_22,_FUNCTION)},
914	#endif
915	#ifdef EBI_ADDR_23
916	{ATPASTE2(EBI_ADDR_23,_PIN),ATPASTE2(EBI_ADDR_23,_FUNCTION)},
917	#endif
918
919	#if SMC_DBW_GLOBAL <= 8
920	#undef SMC_8_BIT_CHIPS
921	#define SMC_8_BIT_CHIPS TRUE
922	#endif
923
924	// Enable data mask pins.
925	#if !SMC_8_BIT_CHIPS_GLOBAL
926	#ifdef EBI_ADDR_0
927	{ATPASTE2(EBI_ADDR_0,_PIN),ATPASTE2(EBI_ADDR_0,_FUNCTION)},
928	#endif
929	#endif
930	#ifdef EBI_NWE0
931	{ATPASTE2(EBI_NWE0,_PIN),ATPASTE2(EBI_NWE0,_FUNCTION)},
932	#endif
933
934	#if SMC_DBW_GLOBAL >= 16
935	#ifdef EBI_NWE1
936	{ATPASTE2(EBI_NWE1,_PIN),ATPASTE2(EBI_NWE1,_FUNCTION)},
937	#endif
938	#if SMC_DBW_GLOBAL >= 32
939	#ifdef EBI_ADDR_1
940	{ATPASTE2(EBI_ADDR_1,_PIN),ATPASTE2(EBI_ADDR_1,_FUNCTION)},
941	#endif
942	#ifdef EBI_NWE3
943	{ATPASTE2(EBI_NWE3,_PIN),ATPASTE2(EBI_NWE3,_FUNCTION)},
944	#endif
945	#endif
946	#endif
947	#ifdef EBI_NRD
948	{ATPASTE2(EBI_NRD,_PIN),ATPASTE2(EBI_NRD,_FUNCTION)},
949	#endif
950
951	// Enable control pins.
952	#if NWAIT_MODE_GLOBAL != AVR32_SMC_EXNW_MODE_DISABLED
953	#ifdef EBI_NWAIT
954	{ATPASTE2(EBI_NWAIT,_PIN),ATPASTE2(EBI_NWAIT,_FUNCTION)},
955	#endif
956	#endif
957	#ifdef SMC_USE_NCS0
958	#ifdef EBI_NCS_0
959	{ATPASTE2(EBI_NCS_0,_PIN),ATPASTE2(EBI_NCS_0,_FUNCTION)},
960	#endif
961	#endif
962	#ifdef SMC_USE_NCS1
963	#ifdef EBI_NCS_1
964	{ATPASTE2(EBI_NCS_1,_PIN),ATPASTE2(EBI_NCS_1,_FUNCTION)},
965	#endif
966	#endif
967	#ifdef SMC_USE_NCS2
968	#ifdef EBI_NCS_2
969	{ATPASTE2(EBI_NCS_2,_PIN),ATPASTE2(EBI_NCS_2,_FUNCTION)},
970	#endif
971	#endif
972	#ifdef SMC_USE_NCS3
973	#ifdef EBI_NCS_3
974	{ATPASTE2(EBI_NCS_3,_PIN),ATPASTE2(EBI_NCS_3,_FUNCTION)},
975	#endif
976	#endif
977	#ifdef SMC_USE_NCS4
978	#ifdef EBI_NCS_4
979	{ATPASTE2(EBI_NCS_4,_PIN),ATPASTE2(EBI_NCS_4,_FUNCTION)},
980	#endif
981	#endif
982	#ifdef SMC_USE_NCS5
983	#ifdef EBI_NCS_5
984	{ATPASTE2(EBI_NCS_5,_PIN),ATPASTE2(EBI_NCS_5,_FUNCTION)},
985	#endif
986	#endif
987	};
988
989	gpio_enable_module(SMC_EBI_GPIO_MAP, sizeof(SMC_EBI_GPIO_MAP) / sizeof(SMC_EBI_GPIO_MAP[0]));
990	}
991
992	unsigned char smc_get_cs_size(unsigned char cs)
993	{
994	return smc_tab_cs_size[cs];
995	}

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