source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/arduino/avr/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/UTILS/compiler.h @ 4837

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1/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
2
3/*This file is prepared for Doxygen automatic documentation generation.*/
4/*! \file *********************************************************************
5 *
6 * \brief Compiler file for AVR32.
7 *
8 * This file defines commonly used types and macros.
9 *
10 * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
11 * - Supported devices:  All AVR32 devices can be used.
12 * - AppNote:
13 *
14 * \author               Atmel Corporation: http://www.atmel.com \n
15 *                       Support and FAQ: http://support.atmel.no/
16 *
17 ******************************************************************************/
18
19/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 *
24 * 1. Redistributions of source code must retain the above copyright notice, this
25 * list of conditions and the following disclaimer.
26 *
27 * 2. Redistributions in binary form must reproduce the above copyright notice,
28 * this list of conditions and the following disclaimer in the documentation
29 * and/or other materials provided with the distribution.
30 *
31 * 3. The name of Atmel may not be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * 4. This software may only be redistributed and used in connection with an Atmel
35 * AVR product.
36 *
37 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
38 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
39 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
40 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
41 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
43 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
44 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
46 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
47 *
48 */
49
50#ifndef _COMPILER_H_
51#define _COMPILER_H_
52
53#if ((defined __GNUC__) && (defined __AVR32__)) || (defined __ICCAVR32__ || defined __AAVR32__)
54#  include <avr32/io.h>
55#endif
56#if (defined __ICCAVR32__)
57#  include <intrinsics.h>
58#endif
59#include "preprocessor.h"
60
61#include "parts.h"
62
63
64//_____ D E C L A R A T I O N S ____________________________________________
65
66#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
67
68#include <stddef.h>
69#include <stdlib.h>
70
71
72#if (defined __ICCAVR32__)
73
74/*! \name Compiler Keywords
75 *
76 * Port of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32.
77 */
78//! @{
79#define __asm__             asm
80#define __inline__          inline
81#define __volatile__
82//! @}
83
84#endif
85
86
87/*! \name Usual Types
88 */
89//! @{
90typedef unsigned char           Bool; //!< Boolean.
91#ifndef __cplusplus
92#if !defined(__bool_true_false_are_defined)
93typedef unsigned char           bool; //!< Boolean.
94#endif
95#endif
96typedef signed char             S8 ;  //!< 8-bit signed integer.
97typedef unsigned char           U8 ;  //!< 8-bit unsigned integer.
98typedef signed short int        S16;  //!< 16-bit signed integer.
99typedef unsigned short int      U16;  //!< 16-bit unsigned integer.
100typedef signed long int         S32;  //!< 32-bit signed integer.
101typedef unsigned long int       U32;  //!< 32-bit unsigned integer.
102typedef signed long long int    S64;  //!< 64-bit signed integer.
103typedef unsigned long long int  U64;  //!< 64-bit unsigned integer.
104typedef float                   F32;  //!< 32-bit floating-point number.
105typedef double                  F64;  //!< 64-bit floating-point number.
106//! @}
107
108
109/*! \name Status Types
110 */
111//! @{
112typedef Bool                Status_bool_t;  //!< Boolean status.
113typedef U8                  Status_t;       //!< 8-bit-coded status.
114//! @}
115
116
117/*! \name Aliasing Aggregate Types
118 */
119//! @{
120
121//! 16-bit union.
122typedef union
123{
124  S16 s16   ;
125  U16 u16   ;
126  S8  s8 [2];
127  U8  u8 [2];
128} Union16;
129
130//! 32-bit union.
131typedef union
132{
133  S32 s32   ;
134  U32 u32   ;
135  S16 s16[2];
136  U16 u16[2];
137  S8  s8 [4];
138  U8  u8 [4];
139} Union32;
140
141//! 64-bit union.
142typedef union
143{
144  S64 s64   ;
145  U64 u64   ;
146  S32 s32[2];
147  U32 u32[2];
148  S16 s16[4];
149  U16 u16[4];
150  S8  s8 [8];
151  U8  u8 [8];
152} Union64;
153
154//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
155typedef union
156{
157  S64 *s64ptr;
158  U64 *u64ptr;
159  S32 *s32ptr;
160  U32 *u32ptr;
161  S16 *s16ptr;
162  U16 *u16ptr;
163  S8  *s8ptr ;
164  U8  *u8ptr ;
165} UnionPtr;
166
167//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
168typedef union
169{
170  volatile S64 *s64ptr;
171  volatile U64 *u64ptr;
172  volatile S32 *s32ptr;
173  volatile U32 *u32ptr;
174  volatile S16 *s16ptr;
175  volatile U16 *u16ptr;
176  volatile S8  *s8ptr ;
177  volatile U8  *u8ptr ;
178} UnionVPtr;
179
180//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
181typedef union
182{
183  const S64 *s64ptr;
184  const U64 *u64ptr;
185  const S32 *s32ptr;
186  const U32 *u32ptr;
187  const S16 *s16ptr;
188  const U16 *u16ptr;
189  const S8  *s8ptr ;
190  const U8  *u8ptr ;
191} UnionCPtr;
192
193//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
194typedef union
195{
196  const volatile S64 *s64ptr;
197  const volatile U64 *u64ptr;
198  const volatile S32 *s32ptr;
199  const volatile U32 *u32ptr;
200  const volatile S16 *s16ptr;
201  const volatile U16 *u16ptr;
202  const volatile S8  *s8ptr ;
203  const volatile U8  *u8ptr ;
204} UnionCVPtr;
205
206//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
207typedef struct
208{
209  S64 *s64ptr;
210  U64 *u64ptr;
211  S32 *s32ptr;
212  U32 *u32ptr;
213  S16 *s16ptr;
214  U16 *u16ptr;
215  S8  *s8ptr ;
216  U8  *u8ptr ;
217} StructPtr;
218
219//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
220typedef struct
221{
222  volatile S64 *s64ptr;
223  volatile U64 *u64ptr;
224  volatile S32 *s32ptr;
225  volatile U32 *u32ptr;
226  volatile S16 *s16ptr;
227  volatile U16 *u16ptr;
228  volatile S8  *s8ptr ;
229  volatile U8  *u8ptr ;
230} StructVPtr;
231
232//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
233typedef struct
234{
235  const S64 *s64ptr;
236  const U64 *u64ptr;
237  const S32 *s32ptr;
238  const U32 *u32ptr;
239  const S16 *s16ptr;
240  const U16 *u16ptr;
241  const S8  *s8ptr ;
242  const U8  *u8ptr ;
243} StructCPtr;
244
245//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
246typedef struct
247{
248  const volatile S64 *s64ptr;
249  const volatile U64 *u64ptr;
250  const volatile S32 *s32ptr;
251  const volatile U32 *u32ptr;
252  const volatile S16 *s16ptr;
253  const volatile U16 *u16ptr;
254  const volatile S8  *s8ptr ;
255  const volatile U8  *u8ptr ;
256} StructCVPtr;
257
258//! @}
259
260#endif  // __AVR32_ABI_COMPILER__
261
262
263//_____ M A C R O S ________________________________________________________
264
265/*! \name Usual Constants
266 */
267//! @{
268#define DISABLE   0
269#define ENABLE    1
270#define DISABLED  0
271#define ENABLED   1
272#define OFF       0
273#define ON        1
274#define FALSE     0
275#define TRUE      1
276#ifndef __cplusplus
277#if !defined(__bool_true_false_are_defined)
278#define false     FALSE
279#define true      TRUE
280#endif
281#endif
282#define KO        0
283#define OK        1
284#define PASS      0
285#define FAIL      1
286#define LOW       0
287#define HIGH      1
288#define CLR       0
289#define SET       1
290//! @}
291
292
293#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
294
295/*! \name Bit-Field Handling
296 */
297//! @{
298
299/*! \brief Reads the bits of a value specified by a given bit-mask.
300 *
301 * \param value Value to read bits from.
302 * \param mask  Bit-mask indicating bits to read.
303 *
304 * \return Read bits.
305 */
306#define Rd_bits( value, mask)        ((value) & (mask))
307
308/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.
309 *
310 * \param lvalue  C lvalue to write bits to.
311 * \param mask    Bit-mask indicating bits to write.
312 * \param bits    Bits to write.
313 *
314 * \return Resulting value with written bits.
315 */
316#define Wr_bits(lvalue, mask, bits)  ((lvalue) = ((lvalue) & ~(mask)) |\
317                                                 ((bits  ) &  (mask)))
318
319/*! \brief Tests the bits of a value specified by a given bit-mask.
320 *
321 * \param value Value of which to test bits.
322 * \param mask  Bit-mask indicating bits to test.
323 *
324 * \return \c 1 if at least one of the tested bits is set, else \c 0.
325 */
326#define Tst_bits( value, mask)  (Rd_bits(value, mask) != 0)
327
328/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.
329 *
330 * \param lvalue  C lvalue of which to clear bits.
331 * \param mask    Bit-mask indicating bits to clear.
332 *
333 * \return Resulting value with cleared bits.
334 */
335#define Clr_bits(lvalue, mask)  ((lvalue) &= ~(mask))
336
337/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.
338 *
339 * \param lvalue  C lvalue of which to set bits.
340 * \param mask    Bit-mask indicating bits to set.
341 *
342 * \return Resulting value with set bits.
343 */
344#define Set_bits(lvalue, mask)  ((lvalue) |=  (mask))
345
346/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.
347 *
348 * \param lvalue  C lvalue of which to toggle bits.
349 * \param mask    Bit-mask indicating bits to toggle.
350 *
351 * \return Resulting value with toggled bits.
352 */
353#define Tgl_bits(lvalue, mask)  ((lvalue) ^=  (mask))
354
355/*! \brief Reads the bit-field of a value specified by a given bit-mask.
356 *
357 * \param value Value to read a bit-field from.
358 * \param mask  Bit-mask indicating the bit-field to read.
359 *
360 * \return Read bit-field.
361 */
362#define Rd_bitfield( value, mask)           (Rd_bits( value, mask) >> ctz(mask))
363
364/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
365 *
366 * \param lvalue    C lvalue to write a bit-field to.
367 * \param mask      Bit-mask indicating the bit-field to write.
368 * \param bitfield  Bit-field to write.
369 *
370 * \return Resulting value with written bit-field.
371 */
372#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))
373
374//! @}
375
376
377/*! \brief This macro is used to test fatal errors.
378 *
379 * The macro tests if the expression is FALSE. If it is, a fatal error is
380 * detected and the application hangs up.
381 *
382 * \param expr  Expression to evaluate and supposed to be nonzero.
383 */
384#ifdef _ASSERT_ENABLE_
385  #define Assert(expr) \
386  {\
387    if (!(expr)) while (TRUE);\
388  }
389#else
390  #define Assert(expr)
391#endif
392
393
394/*! \name Zero-Bit Counting
395 *
396 * Under AVR32-GCC, __builtin_clz and __builtin_ctz behave like macros when
397 * applied to constant expressions (values known at compile time), so they are
398 * more optimized than the use of the corresponding assembly instructions and
399 * they can be used as constant expressions e.g. to initialize objects having
400 * static storage duration, and like the corresponding assembly instructions
401 * when applied to non-constant expressions (values unknown at compile time), so
402 * they are more optimized than an assembly periphrasis. Hence, clz and ctz
403 * ensure a possible and optimized behavior for both constant and non-constant
404 * expressions.
405 */
406//! @{
407
408/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
409 *
410 * \param u Value of which to count the leading zero bits.
411 *
412 * \return The count of leading zero bits in \a u.
413 */
414#if (defined __GNUC__)
415  #define clz(u)              __builtin_clz(u)
416#elif (defined __ICCAVR32__)
417  #define clz(u)              __count_leading_zeros(u)
418#endif
419
420/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
421 *
422 * \param u Value of which to count the trailing zero bits.
423 *
424 * \return The count of trailing zero bits in \a u.
425 */
426#if (defined __GNUC__)
427  #define ctz(u)              __builtin_ctz(u)
428#elif (defined __ICCAVR32__)
429  #define ctz(u)              __count_trailing_zeros(u)
430#endif
431
432//! @}
433
434
435/*! \name Bit Reversing
436 */
437//! @{
438
439/*! \brief Reverses the bits of \a u8.
440 *
441 * \param u8  U8 of which to reverse the bits.
442 *
443 * \return Value resulting from \a u8 with reversed bits.
444 */
445#define bit_reverse8(u8)    ((U8)(bit_reverse32((U8)(u8)) >> 24))
446
447/*! \brief Reverses the bits of \a u16.
448 *
449 * \param u16 U16 of which to reverse the bits.
450 *
451 * \return Value resulting from \a u16 with reversed bits.
452 */
453#define bit_reverse16(u16)  ((U16)(bit_reverse32((U16)(u16)) >> 16))
454
455/*! \brief Reverses the bits of \a u32.
456 *
457 * \param u32 U32 of which to reverse the bits.
458 *
459 * \return Value resulting from \a u32 with reversed bits.
460 */
461#if (defined __GNUC__)
462  #define bit_reverse32(u32) \
463  (\
464    {\
465      unsigned int __value = (U32)(u32);\
466      __asm__ ("brev\t%0" : "+r" (__value) :  : "cc");\
467      (U32)__value;\
468    }\
469  )
470#elif (defined __ICCAVR32__)
471  #define bit_reverse32(u32)  ((U32)__bit_reverse((U32)(u32)))
472#endif
473
474/*! \brief Reverses the bits of \a u64.
475 *
476 * \param u64 U64 of which to reverse the bits.
477 *
478 * \return Value resulting from \a u64 with reversed bits.
479 */
480#define bit_reverse64(u64)  ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\
481                                   ((U64)bit_reverse32((U64)(u64)) << 32)))
482
483//! @}
484
485
486/*! \name Alignment
487 */
488//! @{
489
490/*! \brief Tests alignment of the number \a val with the \a n boundary.
491 *
492 * \param val Input value.
493 * \param n   Boundary.
494 *
495 * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.
496 */
497#define Test_align(val, n     ) (!Tst_bits( val, (n) - 1     )   )
498
499/*! \brief Gets alignment of the number \a val with respect to the \a n boundary.
500 *
501 * \param val Input value.
502 * \param n   Boundary.
503 *
504 * \return Alignment of the number \a val with respect to the \a n boundary.
505 */
506#define Get_align( val, n     ) (  Rd_bits( val, (n) - 1     )   )
507
508/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.
509 *
510 * \param lval  Input/output lvalue.
511 * \param n     Boundary.
512 * \param alg   Alignment.
513 *
514 * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.
515 */
516#define Set_align(lval, n, alg) (  Wr_bits(lval, (n) - 1, alg)   )
517
518/*! \brief Aligns the number \a val with the upper \a n boundary.
519 *
520 * \param val Input value.
521 * \param n   Boundary.
522 *
523 * \return Value resulting from the number \a val aligned with the upper \a n boundary.
524 */
525#define Align_up(  val, n     ) (((val) + ((n) - 1)) & ~((n) - 1))
526
527/*! \brief Aligns the number \a val with the lower \a n boundary.
528 *
529 * \param val Input value.
530 * \param n   Boundary.
531 *
532 * \return Value resulting from the number \a val aligned with the lower \a n boundary.
533 */
534#define Align_down(val, n     ) ( (val)              & ~((n) - 1))
535
536//! @}
537
538
539/*! \name Mathematics
540 *
541 * The same considerations as for clz and ctz apply here but AVR32-GCC does not
542 * provide built-in functions to access the assembly instructions abs, min and
543 * max and it does not produce them by itself in most cases, so two sets of
544 * macros are defined here:
545 *   - Abs, Min and Max to apply to constant expressions (values known at
546 *     compile time);
547 *   - abs, min and max to apply to non-constant expressions (values unknown at
548 *     compile time).
549 */
550//! @{
551
552/*! \brief Takes the absolute value of \a a.
553 *
554 * \param a Input value.
555 *
556 * \return Absolute value of \a a.
557 *
558 * \note More optimized if only used with values known at compile time.
559 */
560#define Abs(a)              (((a) <  0 ) ? -(a) : (a))
561
562/*! \brief Takes the minimal value of \a a and \a b.
563 *
564 * \param a Input value.
565 * \param b Input value.
566 *
567 * \return Minimal value of \a a and \a b.
568 *
569 * \note More optimized if only used with values known at compile time.
570 */
571#define Min(a, b)           (((a) < (b)) ?  (a) : (b))
572
573/*! \brief Takes the maximal value of \a a and \a b.
574 *
575 * \param a Input value.
576 * \param b Input value.
577 *
578 * \return Maximal value of \a a and \a b.
579 *
580 * \note More optimized if only used with values known at compile time.
581 */
582#define Max(a, b)           (((a) > (b)) ?  (a) : (b))
583
584/*! \brief Takes the absolute value of \a a.
585 *
586 * \param a Input value.
587 *
588 * \return Absolute value of \a a.
589 *
590 * \note More optimized if only used with values unknown at compile time.
591 */
592#if (defined __GNUC__)
593  #define abs(a) \
594  (\
595    {\
596      int __value = (a);\
597      __asm__ ("abs\t%0" : "+r" (__value) :  : "cc");\
598      __value;\
599    }\
600  )
601#elif (defined __ICCAVR32__)
602  #define abs(a)      Abs(a)
603#endif
604
605/*! \brief Takes the minimal value of \a a and \a b.
606 *
607 * \param a Input value.
608 * \param b Input value.
609 *
610 * \return Minimal value of \a a and \a b.
611 *
612 * \note More optimized if only used with values unknown at compile time.
613 */
614#if (defined __GNUC__)
615  #define min(a, b) \
616  (\
617    {\
618      int __value, __arg_a = (a), __arg_b = (b);\
619      __asm__ ("min\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\
620      __value;\
621    }\
622  )
623#elif (defined __ICCAVR32__)
624  #define min(a, b)   __min(a, b)
625#endif
626
627/*! \brief Takes the maximal value of \a a and \a b.
628 *
629 * \param a Input value.
630 * \param b Input value.
631 *
632 * \return Maximal value of \a a and \a b.
633 *
634 * \note More optimized if only used with values unknown at compile time.
635 */
636#if (defined __GNUC__)
637  #define max(a, b) \
638  (\
639    {\
640      int __value, __arg_a = (a), __arg_b = (b);\
641      __asm__ ("max\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\
642      __value;\
643    }\
644  )
645#elif (defined __ICCAVR32__)
646  #define max(a, b)   __max(a, b)
647#endif
648
649//! @}
650
651
652/*! \brief Calls the routine at address \a addr.
653 *
654 * It generates a long call opcode.
655 *
656 * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if
657 * it is invoked from the CPU supervisor mode.
658 *
659 * \param addr  Address of the routine to call.
660 *
661 * \note It may be used as a long jump opcode in some special cases.
662 */
663#define Long_call(addr)                   ((*(void (*)(void))(addr))())
664
665/*! \brief Resets the CPU by software.
666 *
667 * \warning It shall not be called from the CPU application mode.
668 */
669#if (defined __GNUC__)
670  #define Reset_CPU() \
671  (\
672    {\
673      __asm__ __volatile__ (\
674        "lddpc   r9, 3f\n\t"\
675        "mfsr    r8, %[SR]\n\t"\
676        "bfextu  r8, r8, %[SR_M_OFFSET], %[SR_M_SIZE]\n\t"\
677        "cp.w    r8, 0b001\n\t"\
678        "breq    0f\n\t"\
679        "sub     r8, pc, $ - 1f\n\t"\
680        "pushm   r8-r9\n\t"\
681        "rete\n"\
682        "0:\n\t"\
683        "mtsr    %[SR], r9\n"\
684        "1:\n\t"\
685        "mov     r0, 0\n\t"\
686        "mov     r1, 0\n\t"\
687        "mov     r2, 0\n\t"\
688        "mov     r3, 0\n\t"\
689        "mov     r4, 0\n\t"\
690        "mov     r5, 0\n\t"\
691        "mov     r6, 0\n\t"\
692        "mov     r7, 0\n\t"\
693        "mov     r8, 0\n\t"\
694        "mov     r9, 0\n\t"\
695        "mov     r10, 0\n\t"\
696        "mov     r11, 0\n\t"\
697        "mov     r12, 0\n\t"\
698        "mov     sp, 0\n\t"\
699        "stdsp   sp[0], sp\n\t"\
700        "ldmts   sp, sp\n\t"\
701        "mov     lr, 0\n\t"\
702        "lddpc   pc, 2f\n\t"\
703        ".balign 4\n"\
704        "2:\n\t"\
705        ".word   _start\n"\
706        "3:\n\t"\
707        ".word   %[RESET_SR]"\
708        :\
709        : [SR] "i" (AVR32_SR),\
710          [SR_M_OFFSET] "i" (AVR32_SR_M_OFFSET),\
711          [SR_M_SIZE] "i" (AVR32_SR_M_SIZE),\
712          [RESET_SR] "i" (AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))\
713      );\
714    }\
715  )
716#elif (defined __ICCAVR32__)
717  #define Reset_CPU() \
718  {\
719    extern void *volatile __program_start;\
720    __asm__ __volatile__ (\
721      "mov     r7, LWRD(__program_start)\n\t"\
722      "orh     r7, HWRD(__program_start)\n\t"\
723      "mov     r9, LWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))")\n\t"\
724      "orh     r9, HWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))")\n\t"\
725      "mfsr    r8, "ASTRINGZ(AVR32_SR)"\n\t"\
726      "bfextu  r8, r8, "ASTRINGZ(AVR32_SR_M_OFFSET)", "ASTRINGZ(AVR32_SR_M_SIZE)"\n\t"\
727      "cp.w    r8, 001b\n\t"\
728      "breq    $ + 10\n\t"\
729      "sub     r8, pc, -12\n\t"\
730      "pushm   r8-r9\n\t"\
731      "rete\n\t"\
732      "mtsr    "ASTRINGZ(AVR32_SR)", r9\n\t"\
733      "mov     r0, 0\n\t"\
734      "mov     r1, 0\n\t"\
735      "mov     r2, 0\n\t"\
736      "mov     r3, 0\n\t"\
737      "mov     r4, 0\n\t"\
738      "mov     r5, 0\n\t"\
739      "mov     r6, 0\n\t"\
740      "st.w    r0[4], r7\n\t"\
741      "mov     r7, 0\n\t"\
742      "mov     r8, 0\n\t"\
743      "mov     r9, 0\n\t"\
744      "mov     r10, 0\n\t"\
745      "mov     r11, 0\n\t"\
746      "mov     r12, 0\n\t"\
747      "mov     sp, 0\n\t"\
748      "stdsp   sp[0], sp\n\t"\
749      "ldmts   sp, sp\n\t"\
750      "mov     lr, 0\n\t"\
751      "ld.w    pc, lr[4]"\
752    );\
753    __program_start;\
754  }
755#endif
756
757
758/*! \name System Register Access
759 */
760//! @{
761
762/*! \brief Gets the value of the \a sysreg system register.
763 *
764 * \param sysreg  Address of the system register of which to get the value.
765 *
766 * \return Value of the \a sysreg system register.
767 */
768#if (defined __GNUC__)
769  #define Get_system_register(sysreg)         __builtin_mfsr(sysreg)
770#elif (defined __ICCAVR32__)
771  #define Get_system_register(sysreg)         __get_system_register(sysreg)
772#endif
773
774/*! \brief Sets the value of the \a sysreg system register to \a value.
775 *
776 * \param sysreg  Address of the system register of which to set the value.
777 * \param value   Value to set the \a sysreg system register to.
778 */
779#if (defined __GNUC__)
780  #define Set_system_register(sysreg, value)  __builtin_mtsr(sysreg, value)
781#elif (defined __ICCAVR32__)
782  #define Set_system_register(sysreg, value)  __set_system_register(sysreg, value)
783#endif
784
785//! @}
786
787
788/*! \name CPU Status Register Access
789 */
790//! @{
791
792/*! \brief Tells whether exceptions are globally enabled.
793 *
794 * \return \c 1 if exceptions are globally enabled, else \c 0.
795 */
796#define Is_global_exception_enabled()         (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_EM_MASK))
797
798/*! \brief Disables exceptions globally.
799 */
800#if (defined __GNUC__)
801  #define Disable_global_exception()          ({__asm__ __volatile__ ("ssrf\t%0" :  : "i" (AVR32_SR_EM_OFFSET));})
802#elif (defined __ICCAVR32__)
803  #define Disable_global_exception()          (__set_status_flag(AVR32_SR_EM_OFFSET))
804#endif
805
806/*! \brief Enables exceptions globally.
807 */
808#if (defined __GNUC__)
809  #define Enable_global_exception()           ({__asm__ __volatile__ ("csrf\t%0" :  : "i" (AVR32_SR_EM_OFFSET));})
810#elif (defined __ICCAVR32__)
811  #define Enable_global_exception()           (__clear_status_flag(AVR32_SR_EM_OFFSET))
812#endif
813
814/*! \brief Tells whether interrupts are globally enabled.
815 *
816 * \return \c 1 if interrupts are globally enabled, else \c 0.
817 */
818#define Is_global_interrupt_enabled()         (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_GM_MASK))
819
820/*! \brief Disables interrupts globally.
821 */
822#if (defined __GNUC__)
823  #define Disable_global_interrupt()          ({__asm__ __volatile__ ("ssrf\t%0" :  : "i" (AVR32_SR_GM_OFFSET));})
824#elif (defined __ICCAVR32__)
825  #define Disable_global_interrupt()          (__disable_interrupt())
826#endif
827
828/*! \brief Enables interrupts globally.
829 */
830#if (defined __GNUC__)
831  #define Enable_global_interrupt()           ({__asm__ __volatile__ ("csrf\t%0" :  : "i" (AVR32_SR_GM_OFFSET));})
832#elif (defined __ICCAVR32__)
833  #define Enable_global_interrupt()           (__enable_interrupt())
834#endif
835
836/*! \brief Tells whether interrupt level \a int_level is enabled.
837 *
838 * \param int_level Interrupt level (0 to 3).
839 *
840 * \return \c 1 if interrupt level \a int_level is enabled, else \c 0.
841 */
842#define Is_interrupt_level_enabled(int_level) (!Tst_bits(Get_system_register(AVR32_SR), TPASTE3(AVR32_SR_I, int_level, M_MASK)))
843
844/*! \brief Disables interrupt level \a int_level.
845 *
846 * \param int_level Interrupt level to disable (0 to 3).
847 */
848#if (defined __GNUC__)
849  #define Disable_interrupt_level(int_level)  ({__asm__ __volatile__ ("ssrf\t%0" :  : "i" (TPASTE3(AVR32_SR_I, int_level, M_OFFSET)));})
850#elif (defined __ICCAVR32__)
851  #define Disable_interrupt_level(int_level)  (__set_status_flag(TPASTE3(AVR32_SR_I, int_level, M_OFFSET)))
852#endif
853
854/*! \brief Enables interrupt level \a int_level.
855 *
856 * \param int_level Interrupt level to enable (0 to 3).
857 */
858#if (defined __GNUC__)
859  #define Enable_interrupt_level(int_level)   ({__asm__ __volatile__ ("csrf\t%0" :  : "i" (TPASTE3(AVR32_SR_I, int_level, M_OFFSET)));})
860#elif (defined __ICCAVR32__)
861  #define Enable_interrupt_level(int_level)   (__clear_status_flag(TPASTE3(AVR32_SR_I, int_level, M_OFFSET)))
862#endif
863
864/*! \brief Protects subsequent code from interrupts.
865 */
866#define AVR32_ENTER_CRITICAL_REGION( ) \
867  { \
868  Bool global_interrupt_enabled = Is_global_interrupt_enabled(); \
869  Disable_global_interrupt(); // Disable the appropriate interrupts.
870
871/*! \brief This macro must always be used in conjunction with AVR32_ENTER_CRITICAL_REGION
872 *         so that interrupts are enabled again.
873 */
874#define AVR32_LEAVE_CRITICAL_REGION( ) \
875  if (global_interrupt_enabled) Enable_global_interrupt(); \
876  }
877
878//! @}
879
880
881/*! \name Debug Register Access
882 */
883//! @{
884
885/*! \brief Gets the value of the \a dbgreg debug register.
886 *
887 * \param dbgreg  Address of the debug register of which to get the value.
888 *
889 * \return Value of the \a dbgreg debug register.
890 */
891#if (defined __GNUC__)
892  #define Get_debug_register(dbgreg)          __builtin_mfdr(dbgreg)
893#elif (defined __ICCAVR32__)
894  #define Get_debug_register(dbgreg)          __get_debug_register(dbgreg)
895#endif
896
897/*! \brief Sets the value of the \a dbgreg debug register to \a value.
898 *
899 * \param dbgreg  Address of the debug register of which to set the value.
900 * \param value   Value to set the \a dbgreg debug register to.
901 */
902#if (defined __GNUC__)
903  #define Set_debug_register(dbgreg, value)   __builtin_mtdr(dbgreg, value)
904#elif (defined __ICCAVR32__)
905  #define Set_debug_register(dbgreg, value)   __set_debug_register(dbgreg, value)
906#endif
907
908//! @}
909
910#endif  // __AVR32_ABI_COMPILER__
911
912
913//! Boolean evaluating MCU little endianism.
914#if ((defined __GNUC__) && (defined __AVR32__)) || ((defined __ICCAVR32__) || (defined __AAVR32__))
915  #define LITTLE_ENDIAN_MCU     FALSE
916#else
917  #error If you are here, you should check what is exactly the processor you are using...
918  #define LITTLE_ENDIAN_MCU     FALSE
919#endif
920
921// Check that MCU endianism is correctly defined.
922#ifndef LITTLE_ENDIAN_MCU
923  #error YOU MUST define the MCU endianism with LITTLE_ENDIAN_MCU: either FALSE or TRUE
924#endif
925
926//! Boolean evaluating MCU big endianism.
927#define BIG_ENDIAN_MCU        (!LITTLE_ENDIAN_MCU)
928
929
930#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
931
932/*! \name MCU Endianism Handling
933 */
934//! @{
935
936#if (LITTLE_ENDIAN_MCU==TRUE)
937  #define LSB(u16)        (((U8  *)&(u16))[0])  //!< Least significant byte of \a u16.
938  #define MSB(u16)        (((U8  *)&(u16))[1])  //!< Most significant byte of \a u16.
939
940  #define LSH(u32)        (((U16 *)&(u32))[0])  //!< Least significant half-word of \a u32.
941  #define MSH(u32)        (((U16 *)&(u32))[1])  //!< Most significant half-word of \a u32.
942  #define LSB0W(u32)      (((U8  *)&(u32))[0])  //!< Least significant byte of 1st rank of \a u32.
943  #define LSB1W(u32)      (((U8  *)&(u32))[1])  //!< Least significant byte of 2nd rank of \a u32.
944  #define LSB2W(u32)      (((U8  *)&(u32))[2])  //!< Least significant byte of 3rd rank of \a u32.
945  #define LSB3W(u32)      (((U8  *)&(u32))[3])  //!< Least significant byte of 4th rank of \a u32.
946  #define MSB3W(u32)      LSB0W(u32)            //!< Most significant byte of 4th rank of \a u32.
947  #define MSB2W(u32)      LSB1W(u32)            //!< Most significant byte of 3rd rank of \a u32.
948  #define MSB1W(u32)      LSB2W(u32)            //!< Most significant byte of 2nd rank of \a u32.
949  #define MSB0W(u32)      LSB3W(u32)            //!< Most significant byte of 1st rank of \a u32.
950
951  #define LSW(u64)        (((U32 *)&(u64))[0])  //!< Least significant word of \a u64.
952  #define MSW(u64)        (((U32 *)&(u64))[1])  //!< Most significant word of \a u64.
953  #define LSH0(u64)       (((U16 *)&(u64))[0])  //!< Least significant half-word of 1st rank of \a u64.
954  #define LSH1(u64)       (((U16 *)&(u64))[1])  //!< Least significant half-word of 2nd rank of \a u64.
955  #define LSH2(u64)       (((U16 *)&(u64))[2])  //!< Least significant half-word of 3rd rank of \a u64.
956  #define LSH3(u64)       (((U16 *)&(u64))[3])  //!< Least significant half-word of 4th rank of \a u64.
957  #define MSH3(u64)       LSH0(u64)             //!< Most significant half-word of 4th rank of \a u64.
958  #define MSH2(u64)       LSH1(u64)             //!< Most significant half-word of 3rd rank of \a u64.
959  #define MSH1(u64)       LSH2(u64)             //!< Most significant half-word of 2nd rank of \a u64.
960  #define MSH0(u64)       LSH3(u64)             //!< Most significant half-word of 1st rank of \a u64.
961  #define LSB0D(u64)      (((U8  *)&(u64))[0])  //!< Least significant byte of 1st rank of \a u64.
962  #define LSB1D(u64)      (((U8  *)&(u64))[1])  //!< Least significant byte of 2nd rank of \a u64.
963  #define LSB2D(u64)      (((U8  *)&(u64))[2])  //!< Least significant byte of 3rd rank of \a u64.
964  #define LSB3D(u64)      (((U8  *)&(u64))[3])  //!< Least significant byte of 4th rank of \a u64.
965  #define LSB4D(u64)      (((U8  *)&(u64))[4])  //!< Least significant byte of 5th rank of \a u64.
966  #define LSB5D(u64)      (((U8  *)&(u64))[5])  //!< Least significant byte of 6th rank of \a u64.
967  #define LSB6D(u64)      (((U8  *)&(u64))[6])  //!< Least significant byte of 7th rank of \a u64.
968  #define LSB7D(u64)      (((U8  *)&(u64))[7])  //!< Least significant byte of 8th rank of \a u64.
969  #define MSB7D(u64)      LSB0D(u64)            //!< Most significant byte of 8th rank of \a u64.
970  #define MSB6D(u64)      LSB1D(u64)            //!< Most significant byte of 7th rank of \a u64.
971  #define MSB5D(u64)      LSB2D(u64)            //!< Most significant byte of 6th rank of \a u64.
972  #define MSB4D(u64)      LSB3D(u64)            //!< Most significant byte of 5th rank of \a u64.
973  #define MSB3D(u64)      LSB4D(u64)            //!< Most significant byte of 4th rank of \a u64.
974  #define MSB2D(u64)      LSB5D(u64)            //!< Most significant byte of 3rd rank of \a u64.
975  #define MSB1D(u64)      LSB6D(u64)            //!< Most significant byte of 2nd rank of \a u64.
976  #define MSB0D(u64)      LSB7D(u64)            //!< Most significant byte of 1st rank of \a u64.
977
978#elif (BIG_ENDIAN_MCU==TRUE)
979  #define MSB(u16)        (((U8  *)&(u16))[0])  //!< Most significant byte of \a u16.
980  #define LSB(u16)        (((U8  *)&(u16))[1])  //!< Least significant byte of \a u16.
981
982  #define MSH(u32)        (((U16 *)&(u32))[0])  //!< Most significant half-word of \a u32.
983  #define LSH(u32)        (((U16 *)&(u32))[1])  //!< Least significant half-word of \a u32.
984  #define MSB0W(u32)      (((U8  *)&(u32))[0])  //!< Most significant byte of 1st rank of \a u32.
985  #define MSB1W(u32)      (((U8  *)&(u32))[1])  //!< Most significant byte of 2nd rank of \a u32.
986  #define MSB2W(u32)      (((U8  *)&(u32))[2])  //!< Most significant byte of 3rd rank of \a u32.
987  #define MSB3W(u32)      (((U8  *)&(u32))[3])  //!< Most significant byte of 4th rank of \a u32.
988  #define LSB3W(u32)      MSB0W(u32)            //!< Least significant byte of 4th rank of \a u32.
989  #define LSB2W(u32)      MSB1W(u32)            //!< Least significant byte of 3rd rank of \a u32.
990  #define LSB1W(u32)      MSB2W(u32)            //!< Least significant byte of 2nd rank of \a u32.
991  #define LSB0W(u32)      MSB3W(u32)            //!< Least significant byte of 1st rank of \a u32.
992
993  #define MSW(u64)        (((U32 *)&(u64))[0])  //!< Most significant word of \a u64.
994  #define LSW(u64)        (((U32 *)&(u64))[1])  //!< Least significant word of \a u64.
995  #define MSH0(u64)       (((U16 *)&(u64))[0])  //!< Most significant half-word of 1st rank of \a u64.
996  #define MSH1(u64)       (((U16 *)&(u64))[1])  //!< Most significant half-word of 2nd rank of \a u64.
997  #define MSH2(u64)       (((U16 *)&(u64))[2])  //!< Most significant half-word of 3rd rank of \a u64.
998  #define MSH3(u64)       (((U16 *)&(u64))[3])  //!< Most significant half-word of 4th rank of \a u64.
999  #define LSH3(u64)       MSH0(u64)             //!< Least significant half-word of 4th rank of \a u64.
1000  #define LSH2(u64)       MSH1(u64)             //!< Least significant half-word of 3rd rank of \a u64.
1001  #define LSH1(u64)       MSH2(u64)             //!< Least significant half-word of 2nd rank of \a u64.
1002  #define LSH0(u64)       MSH3(u64)             //!< Least significant half-word of 1st rank of \a u64.
1003  #define MSB0D(u64)      (((U8  *)&(u64))[0])  //!< Most significant byte of 1st rank of \a u64.
1004  #define MSB1D(u64)      (((U8  *)&(u64))[1])  //!< Most significant byte of 2nd rank of \a u64.
1005  #define MSB2D(u64)      (((U8  *)&(u64))[2])  //!< Most significant byte of 3rd rank of \a u64.
1006  #define MSB3D(u64)      (((U8  *)&(u64))[3])  //!< Most significant byte of 4th rank of \a u64.
1007  #define MSB4D(u64)      (((U8  *)&(u64))[4])  //!< Most significant byte of 5th rank of \a u64.
1008  #define MSB5D(u64)      (((U8  *)&(u64))[5])  //!< Most significant byte of 6th rank of \a u64.
1009  #define MSB6D(u64)      (((U8  *)&(u64))[6])  //!< Most significant byte of 7th rank of \a u64.
1010  #define MSB7D(u64)      (((U8  *)&(u64))[7])  //!< Most significant byte of 8th rank of \a u64.
1011  #define LSB7D(u64)      MSB0D(u64)            //!< Least significant byte of 8th rank of \a u64.
1012  #define LSB6D(u64)      MSB1D(u64)            //!< Least significant byte of 7th rank of \a u64.
1013  #define LSB5D(u64)      MSB2D(u64)            //!< Least significant byte of 6th rank of \a u64.
1014  #define LSB4D(u64)      MSB3D(u64)            //!< Least significant byte of 5th rank of \a u64.
1015  #define LSB3D(u64)      MSB4D(u64)            //!< Least significant byte of 4th rank of \a u64.
1016  #define LSB2D(u64)      MSB5D(u64)            //!< Least significant byte of 3rd rank of \a u64.
1017  #define LSB1D(u64)      MSB6D(u64)            //!< Least significant byte of 2nd rank of \a u64.
1018  #define LSB0D(u64)      MSB7D(u64)            //!< Least significant byte of 1st rank of \a u64.
1019
1020#else
1021  #error  Unknown endianism.
1022#endif
1023
1024//! @}
1025
1026
1027/*! \name Endianism Conversion
1028 *
1029 * The same considerations as for clz and ctz apply here but AVR32-GCC's
1030 * __builtin_bswap_16 and __builtin_bswap_32 do not behave like macros when
1031 * applied to constant expressions, so two sets of macros are defined here:
1032 *   - Swap16, Swap32 and Swap64 to apply to constant expressions (values known
1033 *     at compile time);
1034 *   - swap16, swap32 and swap64 to apply to non-constant expressions (values
1035 *     unknown at compile time).
1036 */
1037//! @{
1038
1039/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
1040 *
1041 * \param u16 U16 of which to toggle the endianism.
1042 *
1043 * \return Value resulting from \a u16 with toggled endianism.
1044 *
1045 * \note More optimized if only used with values known at compile time.
1046 */
1047#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\
1048                           ((U16)(u16) << 8)))
1049
1050/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
1051 *
1052 * \param u32 U32 of which to toggle the endianism.
1053 *
1054 * \return Value resulting from \a u32 with toggled endianism.
1055 *
1056 * \note More optimized if only used with values known at compile time.
1057 */
1058#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\
1059                           ((U32)Swap16((U32)(u32)) << 16)))
1060
1061/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
1062 *
1063 * \param u64 U64 of which to toggle the endianism.
1064 *
1065 * \return Value resulting from \a u64 with toggled endianism.
1066 *
1067 * \note More optimized if only used with values known at compile time.
1068 */
1069#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\
1070                           ((U64)Swap32((U64)(u64)) << 32)))
1071
1072/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
1073 *
1074 * \param u16 U16 of which to toggle the endianism.
1075 *
1076 * \return Value resulting from \a u16 with toggled endianism.
1077 *
1078 * \note More optimized if only used with values unknown at compile time.
1079 */
1080#if (defined __GNUC__)
1081  #define swap16(u16) ((U16)__builtin_bswap_16((U16)(u16)))
1082#elif (defined __ICCAVR32__)
1083  #define swap16(u16) ((U16)__swap_bytes_in_halfwords((U16)(u16)))
1084#endif
1085
1086/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
1087 *
1088 * \param u32 U32 of which to toggle the endianism.
1089 *
1090 * \return Value resulting from \a u32 with toggled endianism.
1091 *
1092 * \note More optimized if only used with values unknown at compile time.
1093 */
1094#if (defined __GNUC__)
1095  #define swap32(u32) ((U32)__builtin_bswap_32((U32)(u32)))
1096#elif (defined __ICCAVR32__)
1097  #define swap32(u32) ((U32)__swap_bytes((U32)(u32)))
1098#endif
1099
1100/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
1101 *
1102 * \param u64 U64 of which to toggle the endianism.
1103 *
1104 * \return Value resulting from \a u64 with toggled endianism.
1105 *
1106 * \note More optimized if only used with values unknown at compile time.
1107 */
1108#define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\
1109                           ((U64)swap32((U64)(u64)) << 32)))
1110
1111//! @}
1112
1113
1114/*! \name Target Abstraction
1115 */
1116//! @{
1117
1118#define _GLOBEXT_           extern      //!< extern storage-class specifier.
1119#define _CONST_TYPE_        const       //!< const type qualifier.
1120#define _MEM_TYPE_SLOW_                 //!< Slow memory type.
1121#define _MEM_TYPE_MEDFAST_              //!< Fairly fast memory type.
1122#define _MEM_TYPE_FAST_                 //!< Fast memory type.
1123
1124typedef U8                  Byte;       //!< 8-bit unsigned integer.
1125
1126#define memcmp_ram2ram      memcmp      //!< Target-specific memcmp of RAM to RAM.
1127#define memcmp_code2ram     memcmp      //!< Target-specific memcmp of RAM to NVRAM.
1128#define memcpy_ram2ram      memcpy      //!< Target-specific memcpy from RAM to RAM.
1129#define memcpy_code2ram     memcpy      //!< Target-specific memcpy from NVRAM to RAM.
1130
1131#define LSB0(u32)           LSB0W(u32)  //!< Least significant byte of 1st rank of \a u32.
1132#define LSB1(u32)           LSB1W(u32)  //!< Least significant byte of 2nd rank of \a u32.
1133#define LSB2(u32)           LSB2W(u32)  //!< Least significant byte of 3rd rank of \a u32.
1134#define LSB3(u32)           LSB3W(u32)  //!< Least significant byte of 4th rank of \a u32.
1135#define MSB3(u32)           MSB3W(u32)  //!< Most significant byte of 4th rank of \a u32.
1136#define MSB2(u32)           MSB2W(u32)  //!< Most significant byte of 3rd rank of \a u32.
1137#define MSB1(u32)           MSB1W(u32)  //!< Most significant byte of 2nd rank of \a u32.
1138#define MSB0(u32)           MSB0W(u32)  //!< Most significant byte of 1st rank of \a u32.
1139
1140//! @}
1141
1142#endif  // __AVR32_ABI_COMPILER__
1143
1144
1145#endif  // _COMPILER_H_
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