source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/arduino/avr/firmwares/wifishield/wifi_dnld/src/SOFTWARE_FRAMEWORK/DRIVERS/INTC/intc.c @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 3 years ago

Adding new version

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1/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
2
3/*This file is prepared for Doxygen automatic documentation generation.*/
4/*! \file *********************************************************************
5 *
6 * \brief INTC driver for AVR32 UC3.
7 *
8 * AVR32 Interrupt Controller driver module.
9 *
10 * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
11 * - Supported devices:  All AVR32 devices with an INTC module can be used.
12 * - AppNote:
13 *
14 * \author               Atmel Corporation: http://www.atmel.com \n
15 *                       Support and FAQ: http://support.atmel.no/
16 *
17 ******************************************************************************/
18
19/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 *
24 * 1. Redistributions of source code must retain the above copyright notice, this
25 * list of conditions and the following disclaimer.
26 *
27 * 2. Redistributions in binary form must reproduce the above copyright notice,
28 * this list of conditions and the following disclaimer in the documentation
29 * and/or other materials provided with the distribution.
30 *
31 * 3. The name of Atmel may not be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * 4. This software may only be redistributed and used in connection with an Atmel
35 * AVR product.
36 *
37 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
38 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
39 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
40 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
41 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
43 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
44 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
46 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
47 *
48 */
49
50#include <avr32/io.h>
51#include "compiler.h"
52#include "preprocessor.h"
53#include "intc.h"
54
55// define _evba from exception.S
56extern void _evba;
57
58//! Values to store in the interrupt priority registers for the various interrupt priority levels.
59extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS];
60
61//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.
62//! Each line handler table contains a set of pointers to interrupt handlers.
63#if (defined __GNUC__)
64#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
65static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
66#elif (defined __ICCAVR32__)
67#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
68static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
69#endif
70MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);
71#undef DECL_INT_LINE_HANDLER_TABLE
72
73//! Table containing for each interrupt group the number of interrupt request
74//! lines and a pointer to the table of interrupt line handlers.
75static const struct
76{
77  unsigned int num_irqs;
78  volatile __int_handler *_int_line_handler_table;
79} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =
80{
81#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \
82  {AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},
83  MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)
84#undef INSERT_INT_LINE_HANDLER_TABLE
85};
86
87
88/*! \brief Default interrupt handler.
89 *
90 * \note Taken and adapted from Newlib.
91 */
92#if (defined __GNUC__)
93__attribute__((__interrupt__))
94#elif (defined __ICCAVR32__)
95__interrupt
96#endif
97static void _unhandled_interrupt(void)
98{
99  // Catch unregistered interrupts.
100  while (TRUE);
101}
102
103
104/*! \brief Gets the interrupt handler of the current event at the \a int_level
105 *         interrupt priority level (called from exception.S).
106 *
107 * \param int_level Interrupt priority level to handle.
108 *
109 * \return Interrupt handler to execute.
110 *
111 * \note Taken and adapted from Newlib.
112 */
113__int_handler _get_interrupt_handler(unsigned int int_level)
114{
115  // ICR3 is mapped first, ICR0 last.
116  // Code in exception.S puts int_level in R12 which is used by AVR32-GCC to
117  // pass a single argument to a function.
118  unsigned int int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_level];
119  unsigned int int_req = AVR32_INTC.irr[int_grp];
120
121  // As an interrupt may disappear while it is being fetched by the CPU
122  // (spurious interrupt caused by a delayed response from an MCU peripheral to
123  // an interrupt flag clear or interrupt disable instruction), check if there
124  // are remaining interrupt lines to process.
125  // If a spurious interrupt occurs, the status register (SR) contains an
126  // execution mode and interrupt level masks corresponding to a level 0
127  // interrupt, whatever the interrupt priority level causing the spurious
128  // event. This behavior has been chosen because a spurious interrupt has not
129  // to be a priority one and because it may not cause any trouble to other
130  // interrupts.
131  // However, these spurious interrupts place the hardware in an unstable state
132  // and could give problems in other/future versions of the CPU, so the
133  // software has to be written so that they never occur. The only safe way of
134  // achieving this is to always clear or disable peripheral interrupts with the
135  // following sequence:
136  // 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.
137  // 2: Perform the bus access to the peripheral register that clears or
138  //    disables the interrupt.
139  // 3: Wait until the interrupt has actually been cleared or disabled by the
140  //    peripheral. This is usually performed by reading from a register in the
141  //    same peripheral (it DOES NOT have to be the same register that was
142  //    accessed in step 2, but it MUST be in the same peripheral), what takes
143  //    bus system latencies into account, but peripheral internal latencies
144  //    (generally 0 cycle) also have to be considered.
145  // 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.
146  // Note that steps 1 and 4 are useless inside interrupt handlers as the
147  // corresponding interrupt level is automatically masked by IxM (unless IxM is
148  // explicitly cleared by the software).
149  //
150  // Get the right IRQ handler.
151  //
152  // If several interrupt lines are active in the group, the interrupt line with
153  // the highest number is selected. This is to be coherent with the
154  // prioritization of interrupt groups performed by the hardware interrupt
155  // controller.
156  //
157  // If no handler has been registered for the pending interrupt,
158  // _unhandled_interrupt will be selected thanks to the initialization of
159  // _int_line_handler_table_x by INTC_init_interrupts.
160  //
161  // exception.S will provide the interrupt handler with a clean interrupt stack
162  // frame, with nothing more pushed onto the stack. The interrupt handler must
163  // manage the `rete' instruction, what can be done thanks to pure assembly,
164  // inline assembly or the `__attribute__((__interrupt__))' C function
165  // attribute.
166  return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL;
167}
168
169//! Init EVBA address. This sequence might also be done in the UTILS/STARTUP/GCC/crt0.S
170static __inline__ void INTC_init_evba(void)
171{
172  Set_system_register(AVR32_EVBA, (int)&_evba );
173}
174
175void INTC_init_interrupts(void)
176{
177  unsigned int int_grp, int_req;
178
179  INTC_init_evba();
180
181  // For all interrupt groups,
182  for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)
183  {
184    // For all interrupt request lines of each group,
185    for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++)
186    {
187      // Assign _unhandled_interrupt as default interrupt handler.
188      _int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt;
189    }
190
191    // Set the interrupt group priority register to its default value.
192    // By default, all interrupt groups are linked to the interrupt priority
193    // level 0 and to the interrupt vector _int0.
194    AVR32_INTC.ipr[int_grp] = ipr_val[AVR32_INTC_INT0];
195  }
196}
197
198
199void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level)
200{
201  // Determine the group of the IRQ.
202  unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;
203
204  // Store in _int_line_handler_table_x the pointer to the interrupt handler, so
205  // that _get_interrupt_handler can retrieve it when the interrupt is vectored.
206  _int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler;
207
208  // Program the corresponding IPRX register to set the interrupt priority level
209  // and the interrupt vector offset that will be fetched by the core interrupt
210  // system.
211  // NOTE: The _intx functions are intermediate assembly functions between the
212  // core interrupt system and the user interrupt handler.
213  AVR32_INTC.ipr[int_grp] = ipr_val[int_level & (AVR32_INTC_IPR_INTLEVEL_MASK >> AVR32_INTC_IPR_INTLEVEL_OFFSET)];
214}
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