source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/io90pwm161.h @ 46

Last change on this file since 46 was 46, checked in by jrpelegrina, 4 years ago

First release to Xenial

File size: 18.4 KB
Line 
1/*****************************************************************************
2 *
3 * Copyright (C) 2014 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_AT90PWM161_H_INCLUDED
36#define _AVR_AT90PWM161_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "io90pwm161.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define ACSR    _SFR_IO8(0x00)
52#define AC1O    1
53#define AC2O    2
54#define AC3O    3
55#define AC1IF   5
56#define AC2IF   6
57#define AC3IF   7
58
59#define TIMSK1  _SFR_IO8(0x01)
60#define TOIE1   0
61#define ICIE1   5
62
63#define TIFR1   _SFR_IO8(0x02)
64#define TOV1    0
65#define ICF1    5
66
67#define PINB    _SFR_IO8(0x03)
68#define PINB7   7
69#define PINB6   6
70#define PINB5   5
71#define PINB4   4
72#define PINB3   3
73#define PINB2   2
74#define PINB1   1
75#define PINB0   0
76
77#define DDRB    _SFR_IO8(0x04)
78#define DDRB7   7
79#define DDRB6   6
80#define DDRB5   5
81#define DDRB4   4
82#define DDRB3   3
83#define DDRB2   2
84#define DDRB1   1
85#define DDRB0   0
86
87#define PORTB   _SFR_IO8(0x05)
88#define PORTB7  7
89#define PORTB6  6
90#define PORTB5  5
91#define PORTB4  4
92#define PORTB3  3
93#define PORTB2  2
94#define PORTB1  1
95#define PORTB0  0
96
97#define ADCSRA  _SFR_IO8(0x06)
98#define ADPS0   0
99#define ADPS1   1
100#define ADPS2   2
101#define ADIE    3
102#define ADIF    4
103#define ADATE   5
104#define ADSC    6
105#define ADEN    7
106
107#define ADCSRB  _SFR_IO8(0x07)
108#define ADTS0   0
109#define ADTS1   1
110#define ADTS2   2
111#define ADTS3   3
112#define ADSSEN  4
113#define ADNCDIS 6
114#define ADHSM   7
115
116#define ADMUX   _SFR_IO8(0x08)
117#define MUX0    0
118#define MUX1    1
119#define MUX2    2
120#define MUX3    3
121#define ADLAR   5
122#define REFS0   6
123#define REFS1   7
124
125#define PIND    _SFR_IO8(0x09)
126#define PIND7   7
127#define PIND6   6
128#define PIND5   5
129#define PIND4   4
130#define PIND3   3
131#define PIND2   2
132#define PIND1   1
133#define PIND0   0
134
135#define DDRD    _SFR_IO8(0x0A)
136#define DDRD7   7
137#define DDRD6   6
138#define DDRD5   5
139#define DDRD4   4
140#define DDRD3   3
141#define DDRD2   2
142#define DDRD1   1
143#define DDRD0   0
144
145#define PORTD   _SFR_IO8(0x0B)
146#define PORTD7  7
147#define PORTD6  6
148#define PORTD5  5
149#define PORTD4  4
150#define PORTD3  3
151#define PORTD2  2
152#define PORTD1  1
153#define PORTD0  0
154
155#define PINE    _SFR_IO8(0x0C)
156#define PINE2   2
157#define PINE1   1
158#define PINE0   0
159
160#define DDRE    _SFR_IO8(0x0D)
161#define DDRE2   2
162#define DDRE1   1
163#define DDRE0   0
164
165#define PORTE   _SFR_IO8(0x0E)
166#define PORTE2  2
167#define PORTE1  1
168#define PORTE0  0
169
170#define PIM0    _SFR_IO8(0x0F)
171#define PEOPE0  0
172#define PEOEPE0 1
173#define PEVE0A  3
174#define PEVE0B  4
175
176#define PIFR0   _SFR_IO8(0x10)
177#define PEOP0   0
178#define PRN00   1
179#define PRN01   2
180#define PEV0A   3
181#define PEV0B   4
182#define POAC0A  6
183#define POAC0B  7
184
185#define PCNF0   _SFR_IO8(0x11)
186#define PCLKSEL0 1
187#define POP0    2
188#define PMODE00 3
189#define PMODE01 4
190#define PLOCK0  5
191#define PALOCK0 6
192#define PFIFTY0 7
193
194#define PCTL0   _SFR_IO8(0x12)
195#define PRUN0   0
196#define PCCYC0  1
197#define PAOC0A  3
198#define PAOC0B  4
199#define PBFM00  2
200#define PBFM01  5
201#define PPRE00  6
202#define PPRE01  7
203
204#define PIM2    _SFR_IO8(0x13)
205#define PEOPE2  0
206#define PEOEPE2 1
207#define PEVE2A  3
208#define PEVE2B  4
209#define PSEIE2  5
210
211#define PIFR2   _SFR_IO8(0x14)
212#define PEOP2   0
213#define PRN20   1
214#define PRN21   2
215#define PEV2A   3
216#define PEV2B   4
217#define PSEI2   5
218#define POAC2A  6
219#define POAC2B  7
220
221#define PCNF2   _SFR_IO8(0x15)
222#define POME2   0
223#define PCLKSEL2 1
224#define POP2    2
225#define PMODE20 3
226#define PMODE21 4
227#define PLOCK2  5
228#define PALOCK2 6
229#define PFIFTY2 7
230
231#define PCTL2   _SFR_IO8(0x16)
232#define PRUN2   0
233#define PCCYC2  1
234#define PARUN2  2
235#define PAOC2A  3
236#define PAOC2B  4
237#define PBFM2   5
238#define PPRE20  6
239#define PPRE21  7
240
241#define SPCR    _SFR_IO8(0x17)
242#define SPR0    0
243#define SPR1    1
244#define CPHA    2
245#define CPOL    3
246#define MSTR    4
247#define DORD    5
248#define SPE     6
249#define SPIE    7
250
251#define SPSR    _SFR_IO8(0x18)
252#define SPI2X   0
253#define WCOL    6
254#define SPIF    7
255
256#define GPIOR0  _SFR_IO8(0x19)
257#define GPIOR00 0
258#define GPIOR01 1
259#define GPIOR02 2
260#define GPIOR03 3
261#define GPIOR04 4
262#define GPIOR05 5
263#define GPIOR06 6
264#define GPIOR07 7
265
266#define GPIOR1  _SFR_IO8(0x1A)
267#define GPIOR10 0
268#define GPIOR11 1
269#define GPIOR12 2
270#define GPIOR13 3
271#define GPIOR14 4
272#define GPIOR15 5
273#define GPIOR16 6
274#define GPIOR17 7
275
276#define GPIOR2  _SFR_IO8(0x1B)
277#define GPIOR20 0
278#define GPIOR21 1
279#define GPIOR22 2
280#define GPIOR23 3
281#define GPIOR24 4
282#define GPIOR25 5
283#define GPIOR26 6
284#define GPIOR27 7
285
286#define EECR    _SFR_IO8(0x1C)
287#define EERE    0
288#define EEWE    1
289#define EEMWE   2
290#define EERIE   3
291#define EEPM0   4
292#define EEPM1   5
293#define EEPAGE  6
294#define NVMBSY  7
295
296#define EEDR    _SFR_IO8(0x1D)
297
298/* Combine EEARL and EEARH */
299#define EEAR    _SFR_IO16(0x1E)
300
301#define EEARL   _SFR_IO8(0x1E)
302#define EEARH   _SFR_IO8(0x1F)
303
304#define EIFR    _SFR_IO8(0x20)
305#define INTF0   0
306#define INTF1   1
307#define INTF2   2
308
309#define EIMSK   _SFR_IO8(0x21)
310#define INT0    0
311#define INT1    1
312#define INT2    2
313
314/* Combine OCR0SBL and OCR0SBH */
315#define OCR0SB  _SFR_IO16(0x22)
316
317#define OCR0SBL _SFR_IO8(0x22)
318#define OCR0SBH _SFR_IO8(0x23)
319
320/* Combine OCR0RBL and OCR0RBH */
321#define OCR0RB  _SFR_IO16(0x24)
322
323#define OCR0RBL _SFR_IO8(0x24)
324#define OCR0RBH _SFR_IO8(0x25)
325
326/* Combine OCR2SBL and OCR2SBH */
327#define OCR2SB  _SFR_IO16(0x26)
328
329#define OCR2SBL _SFR_IO8(0x26)
330#define OCR2SBH _SFR_IO8(0x27)
331
332/* Combine OCR2RBL and OCR2RBH */
333#define OCR2RB  _SFR_IO16(0x28)
334
335#define OCR2RBL _SFR_IO8(0x28)
336#define OCR2RBH _SFR_IO8(0x29)
337
338/* Combine OCR0RAL and OCR0RAH */
339#define OCR0RA  _SFR_IO16(0x2A)
340
341#define OCR0RAL _SFR_IO8(0x2A)
342#define OCR0RAH _SFR_IO8(0x2B)
343
344/* Combine ADCL and ADCH */
345#ifndef __ASSEMBLER__
346#define ADC     _SFR_IO16(0x2C)
347#endif
348#define ADCW    _SFR_IO16(0x2C)
349
350#define ADCL    _SFR_IO8(0x2C)
351#define ADCH    _SFR_IO8(0x2D)
352
353/* Combine OCR2RAL and OCR2RAH */
354#define OCR2RA  _SFR_IO16(0x2E)
355
356#define OCR2RAL _SFR_IO8(0x2E)
357#define OCR2RAH _SFR_IO8(0x2F)
358
359/* Reserved [0x30..0x32] */
360
361#define SMCR    _SFR_IO8(0x33)
362#define SE      0
363#define SM0     1
364#define SM1     2
365#define SM2     3
366
367#define MCUSR   _SFR_IO8(0x34)
368#define PORF    0
369#define EXTRF   1
370#define BORF    2
371#define WDRF    3
372
373#define MCUCR   _SFR_IO8(0x35)
374#define IVCE    0
375#define IVSEL   1
376#define CKRC81  2
377#define RSTDIS  3
378#define PUD     4
379
380#define SPDR    _SFR_IO8(0x36)
381
382#define SPMCSR  _SFR_IO8(0x37)
383#define SPMEN   0
384#define PGERS   1
385#define PGWRT   2
386#define BLBSET  3
387#define RWWSRE  4
388#define SIGRD   5
389#define RWWSB   6
390#define SPMIE   7
391
392#define DACL    _SFR_IO8(0x38)
393#define DACL0   0
394#define DACL1   1
395#define DACL2   2
396#define DACL3   3
397#define DACL4   4
398#define DACL5   5
399#define DACL6   6
400#define DACL7   7
401
402#define DACH    _SFR_IO8(0x39)
403#define DACH0   0
404#define DACH1   1
405#define DACH2   2
406#define DACH3   3
407#define DACH4   4
408#define DACH5   5
409#define DACH6   6
410#define DACH7   7
411
412/* Combine TCNT1L and TCNT1H */
413#define TCNT1   _SFR_IO16(0x3A)
414
415#define TCNT1L  _SFR_IO8(0x3A)
416#define TCNT1H  _SFR_IO8(0x3B)
417
418/* Reserved [0x3C] */
419
420/* SP [0x3D..0x3E] */
421
422/* SREG [0x3F] */
423
424/* Combine OCR0SAL and OCR0SAH */
425#define OCR0SA  _SFR_MEM16(0x60)
426
427#define OCR0SAL _SFR_MEM8(0x60)
428#define OCR0SAH _SFR_MEM8(0x61)
429
430#define PFRC0A  _SFR_MEM8(0x62)
431#define PRFM0A0 0
432#define PRFM0A1 1
433#define PRFM0A2 2
434#define PRFM0A3 3
435#define PFLTE0A 4
436#define PELEV0A 5
437#define PISEL0A 6
438#define PCAE0A  7
439
440#define PFRC0B  _SFR_MEM8(0x63)
441#define PRFM0B0 0
442#define PRFM0B1 1
443#define PRFM0B2 2
444#define PRFM0B3 3
445#define PFLTE0B 4
446#define PELEV0B 5
447#define PISEL0B 6
448#define PCAE0B  7
449
450/* Combine OCR2SAL and OCR2SAH */
451#define OCR2SA  _SFR_MEM16(0x64)
452
453#define OCR2SAL _SFR_MEM8(0x64)
454#define OCR2SAH _SFR_MEM8(0x65)
455
456#define PFRC2A  _SFR_MEM8(0x66)
457#define PRFM2A0 0
458#define PRFM2A1 1
459#define PRFM2A2 2
460#define PRFM2A3 3
461#define PFLTE2A 4
462#define PELEV2A 5
463#define PISEL2A 6
464#define PCAE2A  7
465
466#define PFRC2B  _SFR_MEM8(0x67)
467#define PRFM2B0 0
468#define PRFM2B1 1
469#define PRFM2B2 2
470#define PRFM2B3 3
471#define PFLTE2B 4
472#define PELEV2B 5
473#define PISEL2B 6
474#define PCAE2B  7
475
476/* Combine PICR0L and PICR0H */
477#define PICR0   _SFR_MEM16(0x68)
478
479#define PICR0L  _SFR_MEM8(0x68)
480#define PICR0H  _SFR_MEM8(0x69)
481
482#define PSOC0   _SFR_MEM8(0x6A)
483#define POEN0A  0
484#define POEN0B  2
485#define PSYNC00 4
486#define PSYNC01 5
487#define PISEL0B1 6
488#define PISEL0A1 7
489
490/* Reserved [0x6B] */
491
492#define PICR2L  _SFR_MEM8(0x6C)
493
494#define PICR2H  _SFR_MEM8(0x6D)
495#define PICR28  0
496#define PICR29  1
497#define PICR210 2
498#define PICR211 3
499#define PCST2   7
500
501#define PSOC2   _SFR_MEM8(0x6E)
502#define POEN2A  0
503#define POEN2C  1
504#define POEN2B  2
505#define POEN2D  3
506#define PSYNC20 4
507#define PSYNC21 5
508#define POS22   6
509#define POS23   7
510
511#define POM2    _SFR_MEM8(0x6F)
512#define POMV2A0 0
513#define POMV2A1 1
514#define POMV2A2 2
515#define POMV2A3 3
516#define POMV2B0 4
517#define POMV2B1 5
518#define POMV2B2 6
519#define POMV2B3 7
520
521#define PCNFE2  _SFR_MEM8(0x70)
522#define PISEL2B1 0
523#define PISEL2A1 1
524#define PELEV2B1 2
525#define PELEV2A1 3
526#define PBFM21  4
527#define PASDLK20 5
528#define PASDLK21 6
529#define PASDLK22 7
530
531#define PASDLY2 _SFR_MEM8(0x71)
532
533/* Reserved [0x72..0x75] */
534
535#define DACON   _SFR_MEM8(0x76)
536#define DAEN    0
537#define DALA    2
538#define DATS0   4
539#define DATS1   5
540#define DATS2   6
541#define DAATE   7
542
543#define DIDR0   _SFR_MEM8(0x77)
544#define ADC0D   0
545#define ADC1D   1
546#define ADC2D   2
547#define ADC3D   3
548#define ADC4D   4
549#define ADC5D   5
550#define ADC6D   6
551#define ADC7D   7
552
553#define DIDR1   _SFR_MEM8(0x78)
554#define ADC9D   0
555#define ADC10D  1
556#define AMP0POSD 2
557#define ACMP1MD 3
558
559#define AMP0CSR _SFR_MEM8(0x79)
560#define AMP0TS0 0
561#define AMP0TS1 1
562#define AMP0GS  3
563#define AMP0G0  4
564#define AMP0G1  5
565#define AMP0IS  6
566#define AMP0EN  7
567
568#define AC1ECON _SFR_MEM8(0x7A)
569#define AC1H0   0
570#define AC1H1   1
571#define AC1H2   2
572#define AC1ICE  3
573#define AC1OE   4
574#define AC1OI   5
575
576#define AC2ECON _SFR_MEM8(0x7B)
577#define AC2H0   0
578#define AC2H1   1
579#define AC2H2   2
580#define AC2OE   4
581#define AC2OI   5
582
583#define AC3ECON _SFR_MEM8(0x7C)
584#define AC3H0   0
585#define AC3H1   1
586#define AC3H2   2
587#define AC3OE   4
588#define AC3OI   5
589
590#define AC1CON  _SFR_MEM8(0x7D)
591#define AC1M0   0
592#define AC1M1   1
593#define AC1M2   2
594#define AC1IS0  4
595#define AC1IS1  5
596#define AC1IE   6
597#define AC1EN   7
598
599#define AC2CON  _SFR_MEM8(0x7E)
600#define AC2M0   0
601#define AC2M1   1
602#define AC2M2   2
603#define AC2IS0  4
604#define AC2IS1  5
605#define AC2IE   6
606#define AC2EN   7
607
608#define AC3CON  _SFR_MEM8(0x7F)
609#define AC3M0   0
610#define AC3M1   1
611#define AC3M2   2
612#define AC3OEA  3
613#define AC3IS0  4
614#define AC3IS1  5
615#define AC3IE   6
616#define AC3EN   7
617
618#define BGCRR   _SFR_MEM8(0x80)
619#define BGCR0   0
620#define BGCR1   1
621#define BGCR2   2
622#define BGCR3   3
623
624#define BGCCR   _SFR_MEM8(0x81)
625#define BGCC0   0
626#define BGCC1   1
627#define BGCC2   2
628#define BGCC3   3
629
630#define WDTCSR  _SFR_MEM8(0x82)
631#define WDE     3
632#define WDCE    4
633#define WDP0    0
634#define WDP1    1
635#define WDP2    2
636#define WDP3    5
637#define WDIE    6
638#define WDIF    7
639
640#define CLKPR   _SFR_MEM8(0x83)
641#define CLKPS0  0
642#define CLKPS1  1
643#define CLKPS2  2
644#define CLKPS3  3
645#define CLKPCE  7
646
647#define CLKCSR  _SFR_MEM8(0x84)
648#define CLKC0   0
649#define CLKC1   1
650#define CLKC2   2
651#define CLKC3   3
652#define CLKRDY  4
653#define CLKCCE  7
654
655#define CLKSELR _SFR_MEM8(0x85)
656#define CKSEL0  0
657#define CKSEL1  1
658#define CKSEL2  2
659#define CKSEL3  3
660#define CSUT0   4
661#define CSUT1   5
662#define COUT    6
663
664#define PRR     _SFR_MEM8(0x86)
665#define PRADC   0
666#define PRSPI   2
667#define PRTIM1  4
668#define PRPSCR  5
669#define PRPSC2  7
670
671#define PLLCSR  _SFR_MEM8(0x87)
672#define PLOCK   0
673#define PLLE    1
674#define PLLF0   2
675#define PLLF1   3
676#define PLLF2   4
677#define PLLF3   5
678
679#define OSCCAL  _SFR_MEM8(0x88)
680#define OSCCAL0 0
681#define OSCCAL1 1
682#define OSCCAL2 2
683#define OSCCAL3 3
684#define OSCCAL4 4
685#define OSCCAL5 5
686#define OSCCAL6 6
687#define OSCCAL7 7
688
689#define EICRA   _SFR_MEM8(0x89)
690#define ISC00   0
691#define ISC01   1
692#define ISC10   2
693#define ISC11   3
694#define ISC20   4
695#define ISC21   5
696
697#define TCCR1B  _SFR_MEM8(0x8A)
698#define CS10    0
699#define CS11    1
700#define CS12    2
701#define WGM13   4
702#define ICES1   6
703#define ICNC1   7
704
705/* Reserved [0x8B] */
706
707/* Combine ICR1L and ICR1H */
708#define ICR1    _SFR_MEM16(0x8C)
709
710#define ICR1L   _SFR_MEM8(0x8C)
711#define ICR1H   _SFR_MEM8(0x8D)
712
713
714
715/* Interrupt vectors */
716/* Vector 0 is the reset vector */
717/* PSC2 Capture Event */
718#define PSC2_CAPT_vect            _VECTOR(1)
719#define PSC2_CAPT_vect_num        1
720
721/* PSC2 End Cycle */
722#define PSC2_EC_vect            _VECTOR(2)
723#define PSC2_EC_vect_num        2
724
725/* PSC2 End Of Enhanced Cycle */
726#define PSC2_EEC_vect            _VECTOR(3)
727#define PSC2_EEC_vect_num        3
728
729/* PSC0 Capture Event */
730#define PSC0_CAPT_vect            _VECTOR(4)
731#define PSC0_CAPT_vect_num        4
732
733/* PSC0 End Cycle */
734#define PSC0_EC_vect            _VECTOR(5)
735#define PSC0_EC_vect_num        5
736
737/* PSC0 End Of Enhanced Cycle */
738#define PSC0_EEC_vect            _VECTOR(6)
739#define PSC0_EEC_vect_num        6
740
741/* Analog Comparator 1 */
742#define ANALOG_COMP_1_vect            _VECTOR(7)
743#define ANALOG_COMP_1_vect_num        7
744
745/* Analog Comparator 2 */
746#define ANALOG_COMP_2_vect            _VECTOR(8)
747#define ANALOG_COMP_2_vect_num        8
748
749/* Analog Comparator 3 */
750#define ANALOG_COMP_3_vect            _VECTOR(9)
751#define ANALOG_COMP_3_vect_num        9
752
753/* External Interrupt Request 0 */
754#define INT0_vect            _VECTOR(10)
755#define INT0_vect_num        10
756
757/* Timer/Counter1 Capture Event */
758#define TIMER1_CAPT_vect            _VECTOR(11)
759#define TIMER1_CAPT_vect_num        11
760
761/* Timer/Counter1 Overflow */
762#define TIMER1_OVF_vect            _VECTOR(12)
763#define TIMER1_OVF_vect_num        12
764
765/* ADC Conversion Complete */
766#define ADC_vect            _VECTOR(13)
767#define ADC_vect_num        13
768
769/* External Interrupt Request 1 */
770#define INT1_vect            _VECTOR(14)
771#define INT1_vect_num        14
772
773/* SPI Serial Transfer Complet */
774#define SPI_STC_vect            _VECTOR(15)
775#define SPI_STC_vect_num        15
776
777/* External Interrupt Request 2 */
778#define INT2_vect            _VECTOR(16)
779#define INT2_vect_num        16
780
781/* Watchdog Timeout Interrupt */
782#define WDT_vect            _VECTOR(17)
783#define WDT_vect_num        17
784
785/* EEPROM Ready */
786#define EE_READY_vect            _VECTOR(18)
787#define EE_READY_vect_num        18
788
789/* Store Program Memory Read */
790#define SPM_READY_vect            _VECTOR(19)
791#define SPM_READY_vect_num        19
792
793#define _VECTORS_SIZE 80
794
795
796/* Constants */
797
798#define SPM_PAGESIZE 128
799#define FLASHSTART   0x0000
800#define FLASHEND     0x3FFF
801#define RAMSTART     0x0100
802#define RAMSIZE      1024
803#define RAMEND       0x04FF
804#define E2START     0
805#define E2SIZE      512
806#define E2PAGESIZE  4
807#define E2END       0x01FF
808#define XRAMEND      RAMEND
809
810
811/* Fuses */
812
813#define FUSE_MEMORY_SIZE 3
814
815/* Low Fuse Byte */
816#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
817#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
818#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
819#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
820#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
821#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
822#define FUSE_CKOUT       (unsigned char)~_BV(6)
823#define FUSE_CKDIV8      (unsigned char)~_BV(7)
824
825/* High Fuse Byte */
826#define FUSE_BOOTRST     (unsigned char)~_BV(0)
827#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
828#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
829#define FUSE_EESAVE      (unsigned char)~_BV(3)
830#define FUSE_WDTON       (unsigned char)~_BV(4)
831#define FUSE_SPIEN       (unsigned char)~_BV(5)
832#define FUSE_DWEN        (unsigned char)~_BV(6)
833#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
834
835/* Extended Fuse Byte */
836#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
837#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
838#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
839#define FUSE_PSCINRB     (unsigned char)~_BV(3)
840#define FUSE_PSCRV       (unsigned char)~_BV(4)
841#define FUSE_PSC0RB      (unsigned char)~_BV(5)
842#define FUSE_PSC2RBA     (unsigned char)~_BV(6)
843#define FUSE_PSC2RB      (unsigned char)~_BV(7)
844
845
846/* Lock Bits */
847#define __LOCK_BITS_EXIST
848#define __BOOT_LOCK_BITS_0_EXIST
849#define __BOOT_LOCK_BITS_1_EXIST
850
851
852/* Signature */
853#define SIGNATURE_0 0x1E
854#define SIGNATURE_1 0x94
855#define SIGNATURE_2 0x8B
856
857
858#endif /* #ifdef _AVR_AT90PWM161_H_INCLUDED */
859
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