source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/io90pwm2b.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

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1/* Copyright (c) 2007 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE.
30*/
31
32/* $Id: io90pwm2b.h 2225 2011-03-02 16:27:26Z arcanum $ */
33
34/* avr/io90pwm2b.h - definitions for AT90PWM2B */
35
36/* This file should only be included from <avr/io.h>, never directly. */
37
38#ifndef _AVR_IO_H_
39#  error "Include <avr/io.h> instead of this file."
40#endif
41
42#ifndef _AVR_IOXXX_H_
43#  define _AVR_IOXXX_H_ "io90pwm2b.h"
44#else
45#  error "Attempt to include more than one <avr/ioXXX.h> file."
46#endif
47
48
49#ifndef _AVR_IO90PWM2B_H_
50#define _AVR_IO90PWM2B_H_ 1
51
52/* Registers and associated bit numbers */
53
54#define PINB _SFR_IO8(0x03)
55#define PINB0 0
56#define PINB1 1
57#define PINB2 2
58#define PINB3 3
59#define PINB4 4
60#define PINB5 5
61#define PINB6 6
62#define PINB7 7
63
64#define DDRB _SFR_IO8(0x04)
65#define DDB0 0
66#define DDB1 1
67#define DDB2 2
68#define DDB3 3
69#define DDB4 4
70#define DDB5 5
71#define DDB6 6
72#define DDB7 7
73
74#define PORTB _SFR_IO8(0x05)
75#define PORTB0 0
76#define PORTB1 1
77#define PORTB2 2
78#define PORTB3 3
79#define PORTB4 4
80#define PORTB5 5
81#define PORTB6 6
82#define PORTB7 7
83     
84#define PINC _SFR_IO8(0x06)
85#define PINC0 0
86#define PINC1 1
87#define PINC2 2
88#define PINC3 3
89#define PINC4 4
90#define PINC5 5
91#define PINC6 6
92#define PINC7 7
93
94#define DDRC _SFR_IO8(0x07)
95#define DDC0 0
96#define DDC1 1
97#define DDC2 2
98#define DDC3 3
99#define DDC4 4
100#define DDC5 5
101#define DDC6 6
102#define DDC7 7
103
104#define PORTC _SFR_IO8(0x08)
105#define PORTC0 0
106#define PORTC1 1
107#define PORTC2 2
108#define PORTC3 3
109#define PORTC4 4
110#define PORTC5 5
111#define PORTC6 6
112#define PORTC7 7
113
114#define PIND _SFR_IO8(0x09)
115#define PIND0 0
116#define PIND1 1
117#define PIND2 2
118#define PIND3 3
119#define PIND4 4
120#define PIND5 5
121#define PIND6 6
122#define PIND7 7
123
124#define DDRD _SFR_IO8(0x0A)
125#define DDD0 0
126#define DDD1 1
127#define DDD2 2
128#define DDD3 3
129#define DDD4 4
130#define DDD5 5
131#define DDD6 6
132#define DDD7 7
133
134#define PORTD _SFR_IO8(0x0B)
135#define PORTD0 0
136#define PORTD1 1
137#define PORTD2 2
138#define PORTD3 3
139#define PORTD4 4
140#define PORTD5 5
141#define PORTD6 6
142#define PORTD7 7
143
144#define PINE _SFR_IO8(0x0C)
145#define PINE0 0
146#define PINE1 1
147#define PINE2 2
148
149#define DDRE _SFR_IO8(0x0D)
150#define DDE0 0
151#define DDE1 1
152#define DDE2 2
153
154#define PORTE _SFR_IO8(0x0E)
155#define PORTE0 0
156#define PORTE1 1
157#define PORTE2 2
158
159#define TIFR0 _SFR_IO8(0x15)
160#define TOV0 0
161#define OCF0A 1
162#define OCF0B 2
163
164#define TIFR1 _SFR_IO8(0x16)
165#define TOV1 0
166#define OCF1A 1
167#define OCF1B 2
168#define ICF1 5
169
170#define GPIOR1 _SFR_IO8(0x19)
171#define GPIOR10 0
172#define GPIOR11 1
173#define GPIOR12 2
174#define GPIOR13 3
175#define GPIOR14 4
176#define GPIOR15 5
177#define GPIOR16 6
178#define GPIOR17 7
179
180#define GPIOR2 _SFR_IO8(0x1A)
181#define GPIOR20 0
182#define GPIOR21 1
183#define GPIOR22 2
184#define GPIOR23 3
185#define GPIOR24 4
186#define GPIOR25 5
187#define GPIOR26 6
188#define GPIOR27 7
189
190#define GPIOR3 _SFR_IO8(0x1B)
191#define GPIOR30 0
192#define GPIOR31 1
193#define GPIOR32 2
194#define GPIOR33 3
195#define GPIOR34 4
196#define GPIOR35 5
197#define GPIOR36 6
198#define GPIOR37 7
199
200#define EIFR _SFR_IO8(0x1C)
201#define INTF0 0
202#define INTF1 1
203#define INTF2 2
204#define INTF3 3
205
206#define EIMSK _SFR_IO8(0x1D)
207#define INT0 0
208#define INT1 1
209#define INT2 2
210#define INT3 3
211
212#define GPIOR0 _SFR_IO8(0x1E)
213#define GPIOR00 0
214#define GPIOR01 1
215#define GPIOR02 2
216#define GPIOR03 3
217#define GPIOR04 4
218#define GPIOR05 5
219#define GPIOR06 6
220#define GPIOR07 7
221
222#define EECR _SFR_IO8(0x1F)
223#define EERE 0
224#define EEWE 1
225#define EEMWE 2
226#define EERIE 3
227#define EEPM0 4
228#define EEPM1 5
229
230#define EEDR _SFR_IO8(0x20)
231#define EEDR0 0
232#define EEDR1 1
233#define EEDR2 2
234#define EEDR3 3
235#define EEDR4 4
236#define EEDR5 5
237#define EEDR6 6
238#define EEDR7 7
239
240#define EEAR _SFR_IO16(0x21)
241
242#define EEARL _SFR_IO8(0x21)
243#define EEARL0 0
244#define EEARL1 1
245#define EEARL2 2
246#define EEARL3 3
247#define EEARL4 4
248#define EEARL5 5
249#define EEARL6 6
250#define EEARL7 7
251
252#define EEARH _SFR_IO8(0x22)
253#define EEAR8 0
254#define EEAR9 1
255#define EEAR10 2
256#define EEAR11 3
257
258#define GTCCR _SFR_IO8(0x23)
259#define PSR10 0
260#define PSRSYNC 0
261#define ICPSEL1 2
262#define TSM 3
263
264#define TCCR0A _SFR_IO8(0x24)
265#define WGM00 0
266#define WGM01 1
267#define COM0B0 4
268#define COM0B1 5
269#define COM0A0 6
270#define COM0A1 7
271
272#define TCCR0B _SFR_IO8(0x25)
273#define CS00 0
274#define CS01 1
275#define CS02 2
276#define WGM02 3
277#define FOC0B 6
278#define FOC0A 7
279
280#define TCNT0 _SFR_IO8(0x26)
281#define TCNT0_0 0
282#define TCNT0_1 1
283#define TCNT0_2 2
284#define TCNT0_3 3
285#define TCNT0_4 4
286#define TCNT0_5 5
287#define TCNT0_6 6
288#define TCNT0_7 7
289
290#define OCR0A _SFR_IO8(0x27)
291#define OCR0A_0 0
292#define OCR0A_1 1
293#define OCR0A_2 2
294#define OCR0A_3 3
295#define OCR0A_4 4
296#define OCR0A_5 5
297#define OCR0A_6 6
298#define OCR0A_7 7
299
300#define OCR0B _SFR_IO8(0x28)
301#define OCR0B_0 0
302#define OCR0B_1 1
303#define OCR0B_2 2
304#define OCR0B_3 3
305#define OCR0B_4 4
306#define OCR0B_5 5
307#define OCR0B_6 6
308#define OCR0B_7 7
309
310#define OCR0_0 0    /* Deprecated */
311#define OCR0_1 1    /* Deprecated */
312#define OCR0_2 2    /* Deprecated */
313#define OCR0_3 3    /* Deprecated */
314#define OCR0_4 4    /* Deprecated */
315#define OCR0_5 5    /* Deprecated */
316#define OCR0_6 6    /* Deprecated */
317#define OCR0_7 7    /* Deprecated */
318
319#define PLLCSR _SFR_IO8(0x29)
320#define PLOCK 0
321#define PLLE 1
322#define PLLF 2
323
324#define SPCR _SFR_IO8(0x2C)
325#define SPR0 0
326#define SPR1 1
327#define CPHA 2
328#define CPOL 3
329#define MSTR 4
330#define DORD 5
331#define SPE 6
332#define SPIE 7
333
334#define SPSR _SFR_IO8(0x2D)
335#define SPI2X 0
336#define WCOL 6
337#define SPIF 7
338
339#define SPDR _SFR_IO8(0x2E)
340#define SPDR0 0
341#define SPDR1 1
342#define SPDR2 2
343#define SPDR3 3
344#define SPDR4 4
345#define SPDR5 5
346#define SPDR6 6
347#define SPDR7 7
348
349#define ACSR _SFR_IO8(0x30)
350#define AC0O 0
351#define AC1O 1
352#define AC2O 2
353#define AC0IF 4
354#define AC1IF 5
355#define AC2IF 6
356#define ACCKDIV 7
357
358#define SMCR _SFR_IO8(0x33)
359#define SE 0
360#define SM0 1
361#define SM1 2
362#define SM2 3
363
364#define MCUSR _SFR_IO8(0x34)
365#define PORF 0
366#define EXTRF 1
367#define BORF 2
368#define WDRF 3
369
370#define MCUCR _SFR_IO8(0x35)
371#define IVCE 0
372#define IVSEL 1
373#define PUD 4
374#define SPIPS 7
375
376#define SPMCSR _SFR_IO8(0x37)
377#define SPMEN 0
378#define PGERS 1
379#define PGWRT 2
380#define BLBSET 3
381#define RWWSRE 4
382#define RWWSB 6
383#define SPMIE 7
384
385#define WDTCSR _SFR_MEM8(0x60)
386#define WDP0 0
387#define WDP1 1
388#define WDP2 2
389#define WDE 3
390#define WDCE 4
391#define WDP3 5
392#define WDIE 6
393#define WDIF 7
394
395#define CLKPR _SFR_MEM8(0x61)
396#define CLKPS0 0
397#define CLKPS1 1
398#define CLKPS2 2
399#define CLKPS3 3
400#define CLKPCE 7
401
402#define PRR _SFR_MEM8(0x64)
403#define PRADC 0
404#define PRUSART0 1
405#define PRSPI 2
406#define PRTIM0 3
407#define PRTIM1 4
408#define PRPSC0 5
409#define PRPSC1 6
410#define PRPSC2 7
411
412#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRPSC0)|(1<<PRPSC1)|(1<<PRPSC2))
413#define __AVR_HAVE_PRR_PRADC
414#define __AVR_HAVE_PRR_PRUSART0
415#define __AVR_HAVE_PRR_PRSPI
416#define __AVR_HAVE_PRR_PRTIM0
417#define __AVR_HAVE_PRR_PRTIM1
418#define __AVR_HAVE_PRR_PRPSC0
419#define __AVR_HAVE_PRR_PRPSC1
420#define __AVR_HAVE_PRR_PRPSC2
421
422#define OSCCAL _SFR_MEM8(0x66)
423#define CAL0 0
424#define CAL1 1
425#define CAL2 2
426#define CAL3 3
427#define CAL4 4
428#define CAL5 5
429#define CAL6 6
430
431#define EICRA _SFR_MEM8(0x69)
432#define ISC00 0
433#define ISC01 1
434#define ISC10 2
435#define ISC11 3
436#define ISC20 4
437#define ISC21 5
438#define ISC30 6
439#define ISC31 7
440
441#define TIMSK0 _SFR_MEM8(0x6E)
442#define TOIE0 0
443#define OCIE0A 1
444#define OCIE0B 2
445
446#define TIMSK1 _SFR_MEM8(0x6F)
447#define TOIE1 0
448#define OCIE1A 1
449#define OCIE1B 2
450#define ICIE1 5
451
452#define AMP0CSR _SFR_MEM8(0x76)
453#define AMP0TS0 0
454#define AMP0TS1 1
455#define AMP0G0 4
456#define AMP0G1 5
457#define AMP0IS 6
458#define AMP0EN 7
459
460#define AMP1CSR _SFR_MEM8(0x77)
461#define AMP1TS0 0
462#define AMP1TS1 1
463#define AMP1G0 4
464#define AMP1G1 5
465#define AMP1IS 6
466#define AMP1EN 7
467
468#ifndef __ASSEMBLER__
469#define ADC     _SFR_MEM16(0x78)
470#endif
471#define ADCW    _SFR_MEM16(0x78)
472
473#define ADCL _SFR_MEM8(0x78)
474#define ADCL0 0
475#define ADCL1 1
476#define ADCL2 2
477#define ADCL3 3
478#define ADCL4 4
479#define ADCL5 5
480#define ADCL6 6
481#define ADCL7 7
482
483#define ADCH _SFR_MEM8(0x79)
484#define ADCH0 0
485#define ADCH1 1
486#define ADCH2 2
487#define ADCH3 3
488#define ADCH4 4
489#define ADCH5 5
490#define ADCH6 6
491#define ADCH7 7
492
493#define ADCSRA _SFR_MEM8(0x7A)
494#define ADPS0 0
495#define ADPS1 1
496#define ADPS2 2
497#define ADIE 3
498#define ADIF 4
499#define ADATE 5
500#define ADSC 6
501#define ADEN 7
502
503#define ADCSRB _SFR_MEM8(0x7B)
504#define ADTS0 0
505#define ADTS1 1
506#define ADTS2 2
507#define ADTS3 3
508#define ADASCR 4
509#define ADHSM 7
510
511#define ADMUX _SFR_MEM8(0x7C)
512#define MUX0 0
513#define MUX1 1
514#define MUX2 2
515#define MUX3 3
516#define ADLAR 5
517#define REFS0 6
518#define REFS1 7
519
520#define DIDR0 _SFR_MEM8(0x7E)
521#define ADC0D 0
522#define ADC1D 1
523#define ADC2D 2
524#define ADC3D 3
525#define ADC4D 4
526#define ADC5D 5
527#define ADC6D 6
528#define ADC7D 7
529
530#define DIDR1 _SFR_MEM8(0x7F)
531#define ADC8D 0
532#define ADC9D 1
533#define ADC10D 2
534#define AMP0ND 3
535#define AMP0PD 4
536#define ACMP0D 5
537
538#define TCCR1A _SFR_MEM8(0x80)
539#define WGM10 0
540#define WGM11 1
541#define COM1B0 4
542#define COM1B1 5
543#define COM1A0 6
544#define COM1A1 7
545
546#define TCCR1B _SFR_MEM8(0x81)
547#define CS10 0
548#define CS11 1
549#define CS12 2
550#define WGM12 3
551#define WGM13 4
552#define ICES1 6
553#define ICNC1 7
554
555#define TCCR1C _SFR_MEM8(0x82)
556#define FOC1B 6
557#define FOC1A 7
558
559#define TCNT1 _SFR_MEM16(0x84)
560
561#define TCNT1L _SFR_MEM8(0x84)
562#define TCNT1L0 0
563#define TCNT1L1 1
564#define TCNT1L2 2
565#define TCNT1L3 3
566#define TCNT1L4 4
567#define TCNT1L5 5
568#define TCNT1L6 6
569#define TCNT1L7 7
570
571#define TCNT1H _SFR_MEM8(0x85)
572#define TCNT1H0 0
573#define TCNT1H1 1
574#define TCNT1H2 2
575#define TCNT1H3 3
576#define TCNT1H4 4
577#define TCNT1H5 5
578#define TCNT1H6 6
579#define TCNT1H7 7
580
581#define ICR1 _SFR_MEM16(0x86)
582
583#define ICR1L _SFR_MEM8(0x86)
584#define ICR1L0 0
585#define ICR1L1 1
586#define ICR1L2 2
587#define ICR1L3 3
588#define ICR1L4 4
589#define ICR1L5 5
590#define ICR1L6 6
591#define ICR1L7 7
592
593#define ICR1H _SFR_MEM8(0x87)
594#define ICR1H0 0
595#define ICR1H1 1
596#define ICR1H2 2
597#define ICR1H3 3
598#define ICR1H4 4
599#define ICR1H5 5
600#define ICR1H6 6
601#define ICR1H7 7
602
603#define OCR1A _SFR_MEM16(0x88)
604
605#define OCR1AL _SFR_MEM8(0x88)
606#define OCR1AL0 0
607#define OCR1AL1 1
608#define OCR1AL2 2
609#define OCR1AL3 3
610#define OCR1AL4 4
611#define OCR1AL5 5
612#define OCR1AL6 6
613#define OCR1AL7 7
614
615#define OCR1AH _SFR_MEM8(0x89)
616#define OCR1AH0 0
617#define OCR1AH1 1
618#define OCR1AH2 2
619#define OCR1AH3 3
620#define OCR1AH4 4
621#define OCR1AH5 5
622#define OCR1AH6 6
623#define OCR1AH7 7
624
625#define OCR1B _SFR_MEM16(0x8A)
626
627#define OCR1BL _SFR_MEM8(0x8A)
628#define OCR1BL0 0
629#define OCR1BL1 1
630#define OCR1BL2 2
631#define OCR1BL3 3
632#define OCR1BL4 4
633#define OCR1BL5 5
634#define OCR1BL6 6
635#define OCR1BL7 7
636
637#define OCR1BH _SFR_MEM8(0x8B)
638#define OCR1BH0 0
639#define OCR1BH1 1
640#define OCR1BH2 2
641#define OCR1BH3 3
642#define OCR1BH4 4
643#define OCR1BH5 5
644#define OCR1BH6 6
645#define OCR1BH7 7
646
647#define PIFR0 _SFR_MEM8(0xA0)
648#define PEOP0 0
649#define PRN00 1
650#define PRN01 2
651#define PEV0A 3
652#define PEV0B 4
653#define PSEI0 5
654#define POAC0A 6
655#define POAC0B 7
656
657#define PIM0 _SFR_MEM8(0xA1)
658#define PEOPE0 0
659#define PEVE0A 3
660#define PEVE0B 4
661#define PSEIE0 5
662
663#define PIFR1 _SFR_MEM8(0xA2)
664#define PEOP1 0
665#define PRN10 1
666#define PRN11 2
667#define PEV1A 3
668#define PEV1B 4
669#define PSEI1 5
670#define POAC1A 6
671#define POAC1B 7
672
673#define PIM1 _SFR_MEM8(0xA3)
674#define PEOPE1 0
675#define PEVE1A 3
676#define PEVE1B 4
677#define PSEIE1 5
678
679#define PIFR2 _SFR_MEM8(0xA4)
680#define PEOP2 0
681#define PRN20 1
682#define PRN21 2
683#define PEV2A 3
684#define PEV2B 4
685#define PSEI2 5
686#define POAC2A 6
687#define POAC2B 7
688
689#define PIM2 _SFR_MEM8(0xA5)
690#define PEOPE2 0
691#define PEVE2A 3
692#define PEVE2B 4
693#define PSEIE2 5
694
695#define DACON _SFR_MEM8(0xAA)
696#define DAEN 0
697#define DAOE 1
698#define DALA 2
699#define DATS0 4
700#define DATS1 5
701#define DATS2 6
702#define DAATE 7
703
704#define DAC _SFR_MEM16(0xAB)
705
706#define DACL _SFR_MEM8(0xAB)
707#define DACL0 0
708#define DACL1 1
709#define DACL2 2
710#define DACL3 3
711#define DACL4 4
712#define DACL5 5
713#define DACL6 6
714#define DACL7 7
715
716#define DACH _SFR_MEM8(0xAC)
717#define DACH0 0
718#define DACH1 1
719#define DACH2 2
720#define DACH3 3
721#define DACH4 4
722#define DACH5 5
723#define DACH6 6
724#define DACH7 7
725
726#define AC0CON _SFR_MEM8(0xAD)
727#define AC0M0 0
728#define AC0M1 1
729#define AC0M2 2
730#define AC0IS0 4
731#define AC0IS1 5
732#define AC0IE 6
733#define AC0EN 7
734
735#define AC1CON _SFR_MEM8(0xAE)
736#define AC1M0 0
737#define AC1M1 1
738#define AC1M2 2
739#define AC1ICE 3
740#define AC1IS0 4
741#define AC1IS1 5
742#define AC1IE 6
743#define AC1EN 7
744
745#define AC2CON _SFR_MEM8(0xAF)
746#define AC2M0 0
747#define AC2M1 1
748#define AC2M2 2
749#define AC2IS0 4
750#define AC2IS1 5
751#define AC2IE 6
752#define AC2EN 7
753
754#define UCSRA _SFR_MEM8(0xC0)
755#define MPCM 0
756#define U2X 1
757#define UPE 2
758#define DOR 3
759#define FE 4
760#define UDRE 5
761#define TXC 6
762#define RXC 7
763
764#define UCSRB _SFR_MEM8(0xC1)
765#define TXB8 0
766#define RXB8 1
767#define UCSZ2 2
768#define TXEN 3
769#define RXEN 4
770#define UDRIE 5
771#define TXCIE 6
772#define RXCIE 7
773
774#define UCSRC _SFR_MEM8(0xC2)
775#define UCPOL 0
776#define UCSZ0 1
777#define UCSZ1 2
778#define USBS 3
779#define UPM0 4
780#define UPM1 5
781#define UMSEL0 6
782
783#define UBRR _SFR_MEM16(0xC4)
784
785#define UBRRL _SFR_MEM8(0xC4)
786#define UBRR0 0
787#define UBRR1 1
788#define UBRR2 2
789#define UBRR3 3
790#define UBRR4 4
791#define UBRR5 5
792#define UBRR6 6
793#define UBRR7 7
794
795#define UBRRH _SFR_MEM8(0xC5)
796#define UBRR8 0
797#define UBRR9 1
798#define UBRR10 2
799#define UBRR11 3
800
801#define UDR _SFR_MEM8(0xC6)
802#define UDR0 0
803#define UDR1 1
804#define UDR2 2
805#define UDR3 3
806#define UDR4 4
807#define UDR5 5
808#define UDR6 6
809#define UDR7 7
810
811#define EUCSRA _SFR_MEM8(0xC8)
812#define URxS0 0
813#define URxS1 1
814#define URxS2 2
815#define URxS3 3
816#define UTxS0 4
817#define UTxS1 5
818#define UTxS2 6
819#define UTxS3 7
820
821#define EUCSRB _SFR_MEM8(0xC9)
822#define BODR 0
823#define EMCH 1
824#define EUSBS 3
825#define EUSART 4
826
827#define EUCSRC _SFR_MEM8(0xCA)
828#define STP0 0
829#define STP1 1
830#define F1617 2
831#define FEM 3
832
833#define MUBRR _SFR_MEM16(0xCC)
834
835#define MUBRRL _SFR_MEM8(0xCC)
836#define MUBRR0 0
837#define MUBRR1 1
838#define MUBRR2 2
839#define MUBRR3 3
840#define MUBRR4 4
841#define MUBRR5 5
842#define MUBRR6 6
843#define MUBRR7 7
844
845#define MUBRRH _SFR_MEM8(0xCD)
846#define MUBRR8 0
847#define MUBRR9 1
848#define MUBRR10 2
849#define MUBRR11 3
850#define MUBRR12 4
851#define MUBRR13 5
852#define MUBRR14 6
853#define MUBRR15 7
854
855#define EUDR _SFR_MEM8(0xCE)
856#define EUDR0 0
857#define EUDR1 1
858#define EUDR2 2
859#define EUDR3 3
860#define EUDR4 4
861#define EUDR5 5
862#define EUDR6 6
863#define EUDR7 7
864
865#define PSOC0 _SFR_MEM8(0xD0)
866#define POEN0A 0
867#define POEN0B 2
868#define PSYNC00 4
869#define PSYNC01 5
870
871#define OCR0SA _SFR_MEM16(0xD2)
872
873#define OCR0SAL _SFR_MEM8(0xD2)
874#define OCR0SA_0 0
875#define OCR0SA_1 1
876#define OCR0SA_2 2
877#define OCR0SA_3 3
878#define OCR0SA_4 4
879#define OCR0SA_5 5
880#define OCR0SA_6 6
881#define OCR0SA_7 7
882
883#define OCR0SAH _SFR_MEM8(0xD3)
884#define OCR0SA_8 0
885#define OCR0SA_9 1
886#define OCR0SA_00 2
887#define OCR0SA_01 3
888
889#define OCR0RA _SFR_MEM16(0xD4)
890
891#define OCR0RAL _SFR_MEM8(0xD4)
892#define OCR0RA_0 0
893#define OCR0RA_1 1
894#define OCR0RA_2 2
895#define OCR0RA_3 3
896#define OCR0RA_4 4
897#define OCR0RA_5 5
898#define OCR0RA_6 6
899#define OCR0RA_7 7
900
901#define OCR0RAH _SFR_MEM8(0xD5)
902#define OCR0RA_8 0
903#define OCR0RA_9 1
904#define OCR0RA_00 2
905#define OCR0RA_01 3
906
907#define OCR0SB _SFR_MEM16(0xD6)
908
909#define OCR0SBL _SFR_MEM8(0xD6)
910#define OCR0SB_0 0
911#define OCR0SB_1 1
912#define OCR0SB_2 2
913#define OCR0SB_3 3
914#define OCR0SB_4 4
915#define OCR0SB_5 5
916#define OCR0SB_6 6
917#define OCR0SB_7 7
918
919#define OCR0SBH _SFR_MEM8(0xD7)
920#define OCR0SB_8 0
921#define OCR0SB_9 1
922#define OCR0SB_00 2
923#define OCR0SB_01 3
924
925#define OCR0RB _SFR_MEM16(0xD8)
926
927#define OCR0RBL _SFR_MEM8(0xD8)
928#define OCR0RB_0 0
929#define OCR0RB_1 1
930#define OCR0RB_2 2
931#define OCR0RB_3 3
932#define OCR0RB_4 4
933#define OCR0RB_5 5
934#define OCR0RB_6 6
935#define OCR0RB_7 7
936
937#define OCR0RBH _SFR_MEM8(0xD9)
938#define OCR0RB_8 0
939#define OCR0RB_9 1
940#define OCR0RB_00 2
941#define OCR0RB_01 3
942#define OCR0RB_02 4
943#define OCR0RB_03 5
944#define OCR0RB_04 6
945#define OCR0RB_05 7
946
947#define PCNF0 _SFR_MEM8(0xDA)
948#define PCLKSEL0 1
949#define POP0 2
950#define PMODE00 3
951#define PMODE01 4
952#define PLOCK0 5
953#define PALOCK0 6
954#define PFIFTY0 7
955
956#define PCTL0 _SFR_MEM8(0xDB)
957#define PRUN0 0
958#define PCCYC0 1
959#define PARUN0 2
960#define PAOC0A 3
961#define PAOC0B 4
962#define PBFM0 5
963#define PPRE00 6
964#define PPRE01 7
965
966#define PFRC0A _SFR_MEM8(0xDC)
967#define PRFM0A0 0
968#define PRFM0A1 1
969#define PRFM0A2 2
970#define PRFM0A3 3
971#define PFLTE0A 4
972#define PELEV0A 5
973#define PISEL0A 6
974#define PCAE0A 7
975
976#define PFRC0B _SFR_MEM8(0xDD)
977#define PRFM0B0 0
978#define PRFM0B1 1
979#define PRFM0B2 2
980#define PRFM0B3 3
981#define PFLTE0B 4
982#define PELEV0B 5
983#define PISEL0B 6
984#define PCAE0B 7
985
986#define PICR0 _SFR_MEM16(0xDE)
987
988#define PICR0L _SFR_MEM8(0xDE)
989#define PICR0_0 0
990#define PICR0_1 1
991#define PICR0_2 2
992#define PICR0_3 3
993#define PICR0_4 4
994#define PICR0_5 5
995#define PICR0_6 6
996#define PICR0_7 7
997
998#define PICR0H _SFR_MEM8(0xDF)
999#define PICR0_8 0
1000#define PICR0_9 1
1001#define PICR0_10 2
1002#define PICR0_11 3
1003#define PCST0 7
1004
1005#define PSOC1 _SFR_MEM8(0xE0)
1006#define POEN1A 0
1007#define POEN1B 2
1008#define PSYNC1_0 4
1009#define PSYNC1_1 5
1010
1011#define OCR1SA _SFR_MEM16(0xE2)
1012
1013#define OCR1SAL _SFR_MEM8(0xE2)
1014#define OCR1SA_0 0
1015#define OCR1SA_1 1
1016#define OCR1SA_2 2
1017#define OCR1SA_3 3
1018#define OCR1SA_4 4
1019#define OCR1SA_5 5
1020#define OCR1SA_6 6
1021#define OCR1SA_7 7
1022
1023#define OCR1SAH _SFR_MEM8(0xE3)
1024#define OCR1SA_8 0
1025#define OCR1SA_9 1
1026#define OCR1SA_10 2
1027#define OCR1SA_11 3
1028
1029#define OCR1RA _SFR_MEM16(0xE4)
1030
1031#define OCR1RAL _SFR_MEM8(0xE4)
1032#define OCR1RA_0 0
1033#define OCR1RA_1 1
1034#define OCR1RA_2 2
1035#define OCR1RA_3 3
1036#define OCR1RA_4 4
1037#define OCR1RA_5 5
1038#define OCR1RA_6 6
1039#define OCR1RA_7 7
1040
1041#define OCR1RAH _SFR_MEM8(0xE5)
1042#define OCR1RA_8 0
1043#define OCR1RA_9 1
1044#define OCR1RA_10 2
1045#define OCR1RA_11 3
1046
1047#define OCR1SB _SFR_MEM16(0xE6)
1048
1049#define OCR1SBL _SFR_MEM8(0xE6)
1050#define OCR1SB_0 0
1051#define OCR1SB_1 1
1052#define OCR1SB_2 2
1053#define OCR1SB_3 3
1054#define OCR1SB_4 4
1055#define OCR1SB_5 5
1056#define OCR1SB_6 6
1057#define OCR1SB_7 7
1058
1059#define OCR1SBH _SFR_MEM8(0xE7)
1060#define OCR1SB_8 0
1061#define OCR1SB_9 1
1062#define OCR1SB_10 2
1063#define OCR1SB_11 3
1064
1065#define OCR1RB _SFR_MEM16(0xE8)
1066
1067#define OCR1RBL _SFR_MEM8(0xE8)
1068#define OCR1RB_0 0
1069#define OCR1RB_1 1
1070#define OCR1RB_2 2
1071#define OCR1RB_3 3
1072#define OCR1RB_4 4
1073#define OCR1RB_5 5
1074#define OCR1RB_6 6
1075#define OCR1RB_7 7
1076
1077#define OCR1RBH _SFR_MEM8(0xE9)
1078#define OCR1RB_8 0
1079#define OCR1RB_9 1
1080#define OCR1RB_10 2
1081#define OCR1RB_11 3
1082#define OCR1RB_12 4
1083#define OCR1RB_13 5
1084#define OCR1RB_14 6
1085#define OCR1RB_15 7
1086
1087#define PCNF1 _SFR_MEM8(0xEA)
1088#define PCLKSEL1 1
1089#define POP1 2
1090#define PMODE10 3
1091#define PMODE11 4
1092#define PLOCK1 5
1093#define PALOCK1 6
1094#define PFIFTY1 7
1095
1096#define PCTL1 _SFR_MEM8(0xEB)
1097#define PRUN1 0
1098#define PCCYC1 1
1099#define PARUN1 2
1100#define PAOC1A 3
1101#define PAOC1B 4
1102#define PBFM1 5
1103#define PPRE10 6
1104#define PPRE11 7
1105
1106#define PFRC1A _SFR_MEM8(0xEC)
1107#define PRFM1A0 0
1108#define PRFM1A1 1
1109#define PRFM1A2 2
1110#define PRFM1A3 3
1111#define PFLTE1A 4
1112#define PELEV1A 5
1113#define PISEL1A 6
1114#define PCAE1A 7
1115
1116#define PFRC1B _SFR_MEM8(0xED)
1117#define PRFM1B0 0
1118#define PRFM1B1 1
1119#define PRFM1B2 2
1120#define PRFM1B3 3
1121#define PFLTE1B 4
1122#define PELEV1B 5
1123#define PISEL1B 6
1124#define PCAE1B 7
1125
1126#define PICR1 _SFR_MEM16(0xEE)
1127
1128#define PICR1L _SFR_MEM8(0xEE)
1129#define PICR1_0 0
1130#define PICR1_1 1
1131#define PICR1_2 2
1132#define PICR1_3 3
1133#define PICR1_4 4
1134#define PICR1_5 5
1135#define PICR1_6 6
1136#define PICR1_7 7
1137
1138#define PICR1H _SFR_MEM8(0xEF)
1139#define PICR1_8 0
1140#define PICR1_9 1
1141#define PICR1_10 2
1142#define PICR1_11 3
1143#define PCST1 7
1144
1145#define PSOC2 _SFR_MEM8(0xF0)
1146#define POEN2A 0
1147#define POEN2C 1
1148#define POEN2B 2
1149#define POEN2D 3
1150#define PSYNC2_0 4
1151#define PSYNC2_1 5
1152#define POS22 6
1153#define POS23 7
1154
1155#define POM2 _SFR_MEM8(0xF1)
1156#define POMV2A0 0
1157#define POMV2A1 1
1158#define POMV2A2 2
1159#define POMV2A3 3
1160#define POMV2B0 4
1161#define POMV2B1 5
1162#define POMV2B2 6
1163#define POMV2B3 7
1164
1165#define OCR2SA _SFR_MEM16(0xF2)
1166
1167#define OCR2SAL _SFR_MEM8(0xF2)
1168#define OCR2SA_0 0
1169#define OCR2SA_1 1
1170#define OCR2SA_2 2
1171#define OCR2SA_3 3
1172#define OCR2SA_4 4
1173#define OCR2SA_5 5
1174#define OCR2SA_6 6
1175#define OCR2SA_7 7
1176
1177#define OCR2SAH _SFR_MEM8(0xF3)
1178#define OCR2SA_8 0
1179#define OCR2SA_9 1
1180#define OCR2SA_10 2
1181#define OCR2SA_11 3
1182
1183#define OCR2RA _SFR_MEM16(0xF4)
1184
1185#define OCR2RAL _SFR_MEM8(0xF4)
1186#define OCR2RA_0 0
1187#define OCR2RA_1 1
1188#define OCR2RA_2 2
1189#define OCR2RA_3 3
1190#define OCR2RA_4 4
1191#define OCR2RA_5 5
1192#define OCR2RA_6 6
1193#define OCR2RA_7 7
1194
1195#define OCR2RAH _SFR_MEM8(0xF5)
1196#define OCR2RA_8 0
1197#define OCR2RA_9 1
1198#define OCR2RA_10 2
1199#define OCR2RA_11 3
1200
1201#define OCR2SB _SFR_MEM16(0xF6)
1202
1203#define OCR2SBL _SFR_MEM8(0xF6)
1204#define OCR2SB_0 0
1205#define OCR2SB_1 1
1206#define OCR2SB_2 2
1207#define OCR2SB_3 3
1208#define OCR2SB_4 4
1209#define OCR2SB_5 5
1210#define OCR2SB_6 6
1211#define OCR2SB_7 7
1212
1213#define OCR2SBH _SFR_MEM8(0xF7)
1214#define OCR2SB_8 0
1215#define OCR2SB_9 1
1216#define OCR2SB_10 2
1217#define OCR2SB_11 3
1218
1219#define OCR2RB _SFR_MEM16(0xF8)
1220
1221#define OCR2RBL _SFR_MEM8(0xF8)
1222#define OCR2RB_0 0
1223#define OCR2RB_1 1
1224#define OCR2RB_2 2
1225#define OCR2RB_3 3
1226#define OCR2RB_4 4
1227#define OCR2RB_5 5
1228#define OCR2RB_6 6
1229#define OCR2RB_7 7
1230
1231#define OCR2RBH _SFR_MEM8(0xF9)
1232#define OCR2RB_8 0
1233#define OCR2RB_9 1
1234#define OCR2RB_10 2
1235#define OCR2RB_11 3
1236#define OCR2RB_12 4
1237#define OCR2RB_13 5
1238#define OCR2RB_14 6
1239#define OCR2RB_15 7
1240
1241#define PCNF2 _SFR_MEM8(0xFA)
1242#define POME2 0
1243#define PCLKSEL2 1
1244#define POP2 2
1245#define PMODE20 3
1246#define PMODE21 4
1247#define PLOCK2 5
1248#define PALOCK2 6
1249#define PFIFTY2 7
1250
1251#define PCTL2 _SFR_MEM8(0xFB)
1252#define PRUN2 0
1253#define PCCYC2 1
1254#define PARUN2 2
1255#define PAOC2A 3
1256#define PAOC2B 4
1257#define PBFM2 5
1258#define PPRE20 6
1259#define PPRE21 7
1260
1261#define PFRC2A _SFR_MEM8(0xFC)
1262#define PRFM2A0 0
1263#define PRFM2A1 1
1264#define PRFM2A2 2
1265#define PRFM2A3 3
1266#define PFLTE2A 4
1267#define PELEV2A 5
1268#define PISEL2A 6
1269#define PCAE2A 7
1270
1271#define PFRC2B _SFR_MEM8(0xFD)
1272#define PRFM2B0 0
1273#define PRFM2B1 1
1274#define PRFM2B2 2
1275#define PRFM2B3 3
1276#define PFLTE2B 4
1277#define PELEV2B 5
1278#define PISEL2B 6
1279#define PCAE2B 7
1280
1281#define PICR2 _SFR_MEM16(0xFE)
1282
1283#define PICR2L _SFR_MEM8(0xFE)
1284#define PICR2_0 0
1285#define PICR2_1 1
1286#define PICR2_2 2
1287#define PICR2_3 3
1288#define PICR2_4 4
1289#define PICR2_5 5
1290#define PICR2_6 6
1291#define PICR2_7 7
1292
1293#define PICR2H _SFR_MEM8(0xFF)
1294#define PICR2_8 0
1295#define PICR2_9 1
1296#define PICR2_10 2
1297#define PICR2_11 3
1298#define PCST2 7
1299
1300
1301
1302/* Interrupt Vectors */
1303/* Interrupt vector 0 is the reset vector. */
1304
1305#define PSC2_CAPT_vect_num  1
1306#define PSC2_CAPT_vect      _VECTOR(1)   /* PSC2 Capture Event */
1307
1308#define PSC2_EC_vect_num    2
1309#define PSC2_EC_vect        _VECTOR(2)   /* PSC2 End Cycle */
1310
1311#define PSC1_CAPT_vect_num  3
1312#define PSC1_CAPT_vect      _VECTOR(3)   /* PSC1 Capture Event */
1313
1314#define PSC1_EC_vect_num    4
1315#define PSC1_EC_vect        _VECTOR(4)   /* PSC1 End Cycle */
1316
1317#define PSC0_CAPT_vect_num  5
1318#define PSC0_CAPT_vect      _VECTOR(5)   /* PSC0 Capture Event */
1319
1320#define PSC0_EC_vect_num    6
1321#define PSC0_EC_vect        _VECTOR(6)   /* PSC0 End Cycle */
1322
1323#define ANALOG_COMP_0_vect_num  7
1324#define ANALOG_COMP_0_vect  _VECTOR(7)   /* Analog Comparator 0 */
1325
1326#define ANALOG_COMP_1_vect_num  8
1327#define ANALOG_COMP_1_vect  _VECTOR(8)   /* Analog Comparator 1 */
1328
1329#define ANALOG_COMP_2_vect_num 9
1330#define ANALOG_COMP_2_vect  _VECTOR(9)   /* Analog Comparator 2 */
1331
1332#define INT0_vect_num       10
1333#define INT0_vect           _VECTOR(10)  /* External Interrupt Request 0 */
1334
1335#define TIMER1_CAPT_vect_num 11
1336#define TIMER1_CAPT_vect    _VECTOR(11)  /* Timer/Counter1 Capture Event */
1337
1338#define TIMER1_COMPA_vect_num 12
1339#define TIMER1_COMPA_vect   _VECTOR(12)  /* Timer/Counter1 Compare Match A */
1340
1341#define TIMER1_COMPB_vect_num 13
1342#define TIMER1_COMPB_vect   _VECTOR(13)  /* Timer/Counter Compare Match B */
1343
1344/* Vector 14, Reserved */
1345
1346#define TIMER1_OVF_vect_num 15
1347#define TIMER1_OVF_vect     _VECTOR(15)  /* Timer/Counter1 Overflow */
1348
1349#define TIMER0_COMPA_vect_num 16
1350#define TIMER0_COMPA_vect   _VECTOR(16)  /* Timer/Counter0 Compare Match A */
1351
1352#define TIMER0_OVF_vect_num 17
1353#define TIMER0_OVF_vect     _VECTOR(17)  /* Timer/Counter0 Overflow */
1354
1355#define ADC_vect_num        18
1356#define ADC_vect            _VECTOR(18)  /* ADC Conversion Complete */
1357
1358#define INT1_vect_num       19
1359#define INT1_vect           _VECTOR(19)  /* External Interrupt Request 1 */
1360
1361#define SPI_STC_vect_num    20
1362#define SPI_STC_vect        _VECTOR(20)  /* SPI Serial Transfer Complete */
1363
1364#define USART_RX_vect_num   21
1365#define USART_RX_vect       _VECTOR(21)  /* USART, Rx Complete */
1366
1367#define USART_UDRE_vect_num  22
1368#define USART_UDRE_vect     _VECTOR(22)  /* USART Data Register Empty */
1369
1370#define USART_TX_vect_num   23
1371#define USART_TX_vect       _VECTOR(23)  /* USART, Tx Complete */
1372
1373#define INT2_vect_num       24
1374#define INT2_vect           _VECTOR(24)  /* External Interrupt Request 2 */
1375
1376#define WDT_vect_num        25
1377#define WDT_vect            _VECTOR(25)  /* Watchdog Timeout Interrupt */
1378
1379#define EE_READY_vect_num   26
1380#define EE_READY_vect       _VECTOR(26)  /* EEPROM Ready */
1381
1382#define TIMER0_COMPB_vect_num 27
1383#define TIMER0_COMPB_vect   _VECTOR(27)  /* Timer Counter 0 Compare Match B */
1384
1385#define INT3_vect_num       28
1386#define INT3_vect           _VECTOR(28)  /* External Interrupt Request 3 */
1387
1388/* Vector 29, Reserved */
1389
1390/* Vector 30, Reserved */
1391
1392#define SPM_READY_vect_num  31
1393#define SPM_READY_vect      _VECTOR(31)  /* Store Program Memory Read */
1394
1395#define _VECTORS_SIZE 64
1396
1397
1398
1399/* Memory Sizes */
1400#define RAMSTART       0x100
1401#define RAMEND         0x2FF
1402#define XRAMSIZE       0
1403#define XRAMEND        RAMEND
1404#define E2END          0x1FF
1405#define E2PAGESIZE     4
1406#define FLASHEND       0x1FFF
1407#define SPM_PAGESIZE   64
1408
1409
1410
1411/* Fuse Information */
1412
1413#define FUSE_MEMORY_SIZE 3
1414
1415/* Low Fuse Byte */
1416#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
1417#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
1418#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
1419#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
1420#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
1421#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
1422#define FUSE_CKOUT   (unsigned char)~_BV(6)  /* Oscillator output option */
1423#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
1424#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
1425
1426
1427/* High Fuse Byte */
1428#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
1429#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
1430#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown out detector trigger level */
1431#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
1432#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog timer always on */
1433#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
1434#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
1435#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
1436#define HFUSE_DEFAULT (FUSE_SPIEN)   
1437
1438
1439/* Extended Fuse Byte */
1440#define FUSE_BOOTRST (unsigned char)~_BV(0)  /* Select Reset Vector */
1441#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)  /* Select Boot Size */
1442#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)  /* Select Boot Size */
1443#define FUSE_PSCRV   (unsigned char)~_BV(4)  /* PSCOUT Reset Value */
1444#define FUSE_PSC0RB  (unsigned char)~_BV(5)  /* PSC0 Reset Behaviour */
1445#define FUSE_PSC1RB  (unsigned char)~_BV(6)  /* PSC1 Reset Behaviour */
1446#define FUSE_PSC2RB  (unsigned char)~_BV(7)  /* PSC2 Reset Behaviour */
1447#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
1448
1449
1450/* Lock Bits */
1451#define __LOCK_BITS_EXIST
1452#define __BOOT_LOCK_BITS_0_EXIST
1453#define __BOOT_LOCK_BITS_1_EXIST
1454
1455
1456/* Signature */
1457#define SIGNATURE_0 0x1E
1458#define SIGNATURE_1 0x93
1459#define SIGNATURE_2 0x83
1460
1461#define SLEEP_MODE_IDLE (0x00<<1)
1462#define SLEEP_MODE_ADC (0x01<<1)
1463#define SLEEP_MODE_PWR_DOWN (0x02<<1)
1464#define SLEEP_MODE_STANDBY (0x06<<1)
1465
1466#endif /* _AVR_IO90PWM2B_H_ */
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