source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/io90pwm81.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

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1/* Copyright (c) 2009 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: io90pwm81.h 2206 2011-02-11 06:58:02Z aboyapati $ */
32
33/* avr/io90pwm81.h - definitions for AT90PWM81 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "io90pwm81.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_AT90PWM81_H_
49#define _AVR_AT90PWM81_H_ 1
50
51
52/* Registers and associated bit numbers. */
53
54#define ACSR _SFR_IO8(0x00)
55#define AC1O 1
56#define AC2O 2
57#define AC3O 3
58#define AC1IF 5
59#define AC2IF 6
60#define AC3IF 7
61
62#define TIMSK1 _SFR_IO8(0x01)
63#define TOIE1 0
64#define ICIE1 5
65
66#define TIFR1 _SFR_IO8(0x02)
67#define TOV1 0
68#define ICF1 5
69
70#define PINB _SFR_IO8(0x03)
71#define PINB0 0
72#define PINB1 1
73#define PINB2 2
74#define PINB3 3
75#define PINB4 4
76#define PINB5 5
77#define PINB6 6
78#define PINB7 7
79
80#define DDRB _SFR_IO8(0x04)
81#define DDB0 0
82#define DDB1 1
83#define DDB2 2
84#define DDB3 3
85#define DDB4 4
86#define DDB5 5
87#define DDB6 6
88#define DDB7 7
89
90#define PORTB _SFR_IO8(0x05)
91#define PORTB0 0
92#define PORTB1 1
93#define PORTB2 2
94#define PORTB3 3
95#define PORTB4 4
96#define PORTB5 5
97#define PORTB6 6
98#define PORTB7 7
99
100#define ADCSRA _SFR_IO8(0x06)
101#define ADPS0 0
102#define ADPS1 1
103#define ADPS2 2
104#define ADIE 3
105#define ADIF 4
106#define ADATE 5
107#define ADSC 6
108#define ADEN 7
109
110#define ADCSRB _SFR_IO8(0x07)
111#define ADTS0 0
112#define ADTS1 1
113#define ADTS2 2
114#define ADTS3 3
115#define ADSSEN 4
116#define ADNCDIS 6
117#define ADHSM 7
118
119#define ADMUX _SFR_IO8(0x08)
120#define MUX0 0
121#define MUX1 1
122#define MUX2 2
123#define MUX3 3
124#define ADLAR 5
125#define REFS0 6
126#define REFS1 7
127
128#define PIND _SFR_IO8(0x09)
129#define PIND0 0
130#define PIND1 1
131#define PIND2 2
132#define PIND3 3
133#define PIND4 4
134#define PIND5 5
135#define PIND6 6
136#define PIND7 7
137
138#define DDRD _SFR_IO8(0x0A)
139#define DDD0 0
140#define DDD1 1
141#define DDD2 2
142#define DDD3 3
143#define DDD4 4
144#define DDD5 5
145#define DDD6 6
146#define DDD7 7
147
148#define PORTD _SFR_IO8(0x0B)
149#define PORTD0 0
150#define PORTD1 1
151#define PORTD2 2
152#define PORTD3 3
153#define PORTD4 4
154#define PORTD5 5
155#define PORTD6 6
156#define PORTD7 7
157
158#define PINE _SFR_IO8(0x0C)
159#define PINE0 0
160#define PINE1 1
161#define PINE2 2
162
163#define DDRE _SFR_IO8(0x0D)
164#define DDE0 0
165#define DDE1 1
166#define DDE2 2
167
168#define PORTE _SFR_IO8(0x0E)
169#define PORTE0 0
170#define PORTE1 1
171#define PORTE2 2
172
173#define PIM0 _SFR_IO8(0x0F)
174#define PEOPE0 0
175#define PEOEPE0 1
176#define PEVE0A 3
177#define PEVE0B 4
178
179#define PIFR0 _SFR_IO8(0x10)
180#define PEOP0 0
181#define PRN00 1
182#define PRN01 2
183#define PEV0A 3
184#define PEV0B 4
185#define POAC0A 6
186#define POAC0B 7
187
188#define PCNF0 _SFR_IO8(0x11)
189#define PCLKSEL0 1
190#define POP0 2
191#define PMODE00 3
192#define PMODE01 4
193#define PLOCK0 5
194#define PALOCK0 6
195#define PFIFTY0 7
196
197#define PCTL0 _SFR_IO8(0x12)
198#define PRUN0 0
199#define PCCYC0 1
200#define PBFM00 2
201#define PAOC0A 3
202#define PAOC0B 4
203#define PBFM01 5
204#define PPRE00 6
205#define PPRE01 7
206
207#define PIM2 _SFR_IO8(0x13)
208#define PEOPE2 0
209#define PEOEPE2 1
210#define PEVE2A 3
211#define PEVE2B 4
212#define PSEIE2 5
213
214#define PIFR2 _SFR_IO8(0x14)
215#define PEOP2 0
216#define PRN20 1
217#define PRN21 2
218#define PEV2A 3
219#define PEV2B 4
220#define PSEI2 5
221#define POAC2A 6
222#define POAC2B 7
223
224#define PCNF2 _SFR_IO8(0x15)
225#define POME2 0
226#define PCLKSEL2 1
227#define POP2 2
228#define PMODE20 3
229#define PMODE21 4
230#define PLOCK2 5
231#define PALOCK2 6
232#define PFIFTY2 7
233
234#define PCTL2 _SFR_IO8(0x16)
235#define PRUN2 0
236#define PCCYC2 1
237#define PARUN2 2
238#define PAOC2A 3
239#define PAOC2B 4
240#define PBFM2 5
241#define PPRE20 6
242#define PPRE21 7
243
244#define SPCR _SFR_IO8(0x17)
245#define SPR0 0
246#define SPR1 1
247#define CPHA 2
248#define CPOL 3
249#define MSTR 4
250#define DORD 5
251#define SPE 6
252#define SPIE 7
253
254#define SPSR _SFR_IO8(0x18)
255#define SPI2X 0
256#define WCOL 6
257#define SPIF 7
258
259#define GPIOR0 _SFR_IO8(0x19)
260#define GPIOR00 0
261#define GPIOR01 1
262#define GPIOR02 2
263#define GPIOR03 3
264#define GPIOR04 4
265#define GPIOR05 5
266#define GPIOR06 6
267#define GPIOR07 7
268
269#define GPIOR1 _SFR_IO8(0x1A)
270#define GPIOR10 0
271#define GPIOR11 1
272#define GPIOR12 2
273#define GPIOR13 3
274#define GPIOR14 4
275#define GPIOR15 5
276#define GPIOR16 6
277#define GPIOR17 7
278
279#define GPIOR2 _SFR_IO8(0x1B)
280#define GPIOR20 0
281#define GPIOR21 1
282#define GPIOR22 2
283#define GPIOR23 3
284#define GPIOR24 4
285#define GPIOR25 5
286#define GPIOR26 6
287#define GPIOR27 7
288
289#define EECR _SFR_IO8(0x1C)
290#define EERE 0
291#define EEWE 1
292#define EEMWE 2
293#define EERIE 3
294#define EEPM0 4
295#define EEPM1 5
296#define EEPAGE 6
297#define NVMBSY 7
298
299#define EEDR _SFR_IO8(0x1D)
300#define EEDR0 0
301#define EEDR1 1
302#define EEDR2 2
303#define EEDR3 3
304#define EEDR4 4
305#define EEDR5 5
306#define EEDR6 6
307#define EEDR7 7
308
309#define EEAR _SFR_IO16(0x1E)
310
311#define EEARL _SFR_IO8(0x1E)
312#define EEARL0 0
313#define EEARL1 1
314#define EEARL2 2
315#define EEARL3 3
316#define EEARL4 4
317#define EEARL5 5
318#define EEARL6 6
319#define EEARL7 7
320
321#define EEARH _SFR_IO8(0x1F)
322#define EEAR8 0
323
324#define EIFR _SFR_IO8(0x20)
325#define INTF0 0
326#define INTF1 1
327#define INTF2 2
328
329#define EIMSK _SFR_IO8(0x21)
330#define INT0 0
331#define INT1 1
332#define INT2 2
333
334#define OCR0SB _SFR_IO16(0x22)
335
336#define OCR0SBL _SFR_IO8(0x22)
337#define OCR0SB_0 0
338#define OCR0SB_1 1
339#define OCR0SB_2 2
340#define OCR0SB_3 3
341#define OCR0SB_4 4
342#define OCR0SB_5 5
343#define OCR0SB_6 6
344#define OCR0SB_7 7
345
346#define OCR0SBH _SFR_IO8(0x23)
347#define OCR0SB_8 0
348#define OCR0SB_9 1
349#define OCR0SB_00 2
350#define OCR0SB_01 3
351
352#define OCR0RB _SFR_IO16(0x24)
353
354#define OCR0RBL _SFR_IO8(0x24)
355#define OCR0RB_0 0
356#define OCR0RB_1 1
357#define OCR0RB_2 2
358#define OCR0RB_3 3
359#define OCR0RB_4 4
360#define OCR0RB_5 5
361#define OCR0RB_6 6
362#define OCR0RB_7 7
363
364#define OCR0RBH _SFR_IO8(0x25)
365#define OCR0RB_8 0
366#define OCR0RB_9 1
367#define OCR0RB_00 2
368#define OCR0RB_01 3
369#define OCR0RB_02 4
370#define OCR0RB_03 5
371#define OCR0RB_04 6
372#define OCR0RB_05 7
373
374#define OCR2SB _SFR_IO16(0x26)
375
376#define OCR2SBL _SFR_IO8(0x26)
377#define OCR2SB_0 0
378#define OCR2SB_1 1
379#define OCR2SB_2 2
380#define OCR2SB_3 3
381#define OCR2SB_4 4
382#define OCR2SB_5 5
383#define OCR2SB_6 6
384#define OCR2SB_7 7
385
386#define OCR2SBH _SFR_IO8(0x27)
387#define OCR2SB_8 0
388#define OCR2SB_9 1
389#define OCR2SB_10 2
390#define OCR2SB_11 3
391
392#define OCR2RB _SFR_IO16(0x28)
393
394#define OCR2RBL _SFR_IO8(0x28)
395#define OCR2RB_0 0
396#define OCR2RB_1 1
397#define OCR2RB_2 2
398#define OCR2RB_3 3
399#define OCR2RB_4 4
400#define OCR2RB_5 5
401#define OCR2RB_6 6
402#define OCR2RB_7 7
403
404#define OCR2RBH _SFR_IO8(0x29)
405#define OCR2RB_8 0
406#define OCR2RB_9 1
407#define OCR2RB_10 2
408#define OCR2RB_11 3
409#define OCR2RB_12 4
410#define OCR2RB_13 5
411#define OCR2RB_14 6
412#define OCR2RB_15 7
413
414#define OCR0RA _SFR_IO16(0x2A)
415
416#define OCR0RAL _SFR_IO8(0x2A)
417#define OCR0RA_0 0
418#define OCR0RA_1 1
419#define OCR0RA_2 2
420#define OCR0RA_3 3
421#define OCR0RA_4 4
422#define OCR0RA_5 5
423#define OCR0RA_6 6
424#define OCR0RA_7 7
425
426#define OCR0RAH _SFR_IO8(0x2B)
427#define OCR0RA_8 0
428#define OCR0RA_9 1
429#define OCR0RA_00 2
430#define OCR0RA_01 3
431
432#ifndef __ASSEMBLER__
433#define ADC _SFR_IO16(0x2C)
434#endif
435#define ADCW _SFR_IO16(0x2C)
436
437#define ADCL _SFR_IO8(0x2C)
438#define ADCL0 0
439#define ADCL1 1
440#define ADCL2 2
441#define ADCL3 3
442#define ADCL4 4
443#define ADCL5 5
444#define ADCL6 6
445#define ADCL7 7
446
447#define ADCH _SFR_IO8(0x2D)
448#define ADCH0 0
449#define ADCH1 1
450#define ADCH2 2
451#define ADCH3 3
452#define ADCH4 4
453#define ADCH5 5
454#define ADCH6 6
455#define ADCH7 7
456
457#define OCR2RA _SFR_IO16(0x2E)
458
459#define OCR2RAL _SFR_IO8(0x2E)
460#define OCR2RA_0 0
461#define OCR2RA_1 1
462#define OCR2RA_2 2
463#define OCR2RA_3 3
464#define OCR2RA_4 4
465#define OCR2RA_5 5
466#define OCR2RA_6 6
467#define OCR2RA_7 7
468
469#define OCR2RAH _SFR_IO8(0x2F)
470#define OCR2RA_8 0
471#define OCR2RA_9 1
472#define OCR2RA_10 2
473#define OCR2RA_11 3
474
475#define DWDR _SFR_IO8(0x31)
476
477#define MSMCR _SFR_IO8(0x32)
478
479#define SMCR _SFR_IO8(0x33)
480#define SE 0
481#define SM0 1
482#define SM1 2
483#define SM2 3
484
485#define MCUSR _SFR_IO8(0x34)
486#define PORF 0
487#define EXTRF 1
488#define BORF 2
489#define WDRF 3
490
491#define MCUCR _SFR_IO8(0x35)
492#define IVCE 0
493#define IVSEL 1
494#define CKRC81 2
495#define RSTDIS 3
496#define PUD 4
497
498#define SPDR _SFR_IO8(0x36)
499#define SPDR0 0
500#define SPDR1 1
501#define SPDR2 2
502#define SPDR3 3
503#define SPDR4 4
504#define SPDR5 5
505#define SPDR6 6
506#define SPDR7 7
507
508#define SPMCSR _SFR_IO8(0x37)
509#define SPMEN 0
510#define PGERS 1
511#define PGWRT 2
512#define BLBSET 3
513#define RWWSRE 4
514#define SIGRD 5
515#define RWWSB 6
516#define SPMIE 7
517
518#define DAC _SFR_IO16(0x38)
519
520#define DACL _SFR_IO8(0x38)
521#define DACL0 0
522#define DACL1 1
523#define DACL2 2
524#define DACL3 3
525#define DACL4 4
526#define DACL5 5
527#define DACL6 6
528#define DACL7 7
529
530#define DACH _SFR_IO8(0x39)
531#define DACH0 0
532#define DACH1 1
533#define DACH2 2
534#define DACH3 3
535#define DACH4 4
536#define DACH5 5
537#define DACH6 6
538#define DACH7 7
539
540#define TCNT1 _SFR_IO16(0x3A)
541
542#define TCNT1L _SFR_IO8(0x3A)
543#define TCNT1L0 0
544#define TCNT1L1 1
545#define TCNT1L2 2
546#define TCNT1L3 3
547#define TCNT1L4 4
548#define TCNT1L5 5
549#define TCNT1L6 6
550#define TCNT1L7 7
551
552#define TCNT1H _SFR_IO8(0x3B)
553#define TCNT1H0 0
554#define TCNT1H1 1
555#define TCNT1H2 2
556#define TCNT1H3 3
557#define TCNT1H4 4
558#define TCNT1H5 5
559#define TCNT1H6 6
560#define TCNT1H7 7
561
562#define OCR0SA _SFR_MEM16(0x60)
563
564#define OCR0SAL _SFR_MEM8(0x60)
565#define OCR0SA_0 0
566#define OCR0SA_1 1
567#define OCR0SA_2 2
568#define OCR0SA_3 3
569#define OCR0SA_4 4
570#define OCR0SA_5 5
571#define OCR0SA_6 6
572#define OCR0SA_7 7
573
574#define OCR0SAH _SFR_MEM8(0x61)
575#define OCR0SA_8 0
576#define OCR0SA_9 1
577#define OCR0SA_00 2
578#define OCR0SA_01 3
579
580#define PFRC0A _SFR_MEM8(0x62)
581#define PRFM0A0 0
582#define PRFM0A1 1
583#define PRFM0A2 2
584#define PRFM0A3 3
585#define PFLTE0A 4
586#define PELEV0A 5
587#define PISEL0A 6
588#define PCAE0A 7
589
590#define PFRC0B _SFR_MEM8(0x63)
591#define PRFM0B0 0
592#define PRFM0B1 1
593#define PRFM0B2 2
594#define PRFM0B3 3
595#define PFLTE0B 4
596#define PELEV0B 5
597#define PISEL0B 6
598#define PCAE0B 7
599
600#define OCR2SA _SFR_MEM16(0x64)
601
602#define OCR2SAL _SFR_MEM8(0x64)
603#define OCR2SA_0 0
604#define OCR2SA_1 1
605#define OCR2SA_2 2
606#define OCR2SA_3 3
607#define OCR2SA_4 4
608#define OCR2SA_5 5
609#define OCR2SA_6 6
610#define OCR2SA_7 7
611
612#define OCR2SAH _SFR_MEM8(0x65)
613#define OCR2SA_8 0
614#define OCR2SA_9 1
615#define OCR2SA_10 2
616#define OCR2SA_11 3
617
618#define PFRC2A _SFR_MEM8(0x66)
619#define PRFM2A0 0
620#define PRFM2A1 1
621#define PRFM2A2 2
622#define PRFM2A3 3
623#define PFLTE2A 4
624#define PELEV2A 5
625#define PISEL2A 6
626#define PCAE2A 7
627
628#define PFRC2B _SFR_MEM8(0x67)
629#define PRFM2B0 0
630#define PRFM2B1 1
631#define PRFM2B2 2
632#define PRFM2B3 3
633#define PFLTE2B 4
634#define PELEV2B 5
635#define PISEL2B 6
636#define PCAE2B 7
637
638#define PICR0 _SFR_MEM16(0x68)
639
640#define PICR0L _SFR_MEM8(0x68)
641#define PICR0_0 0
642#define PICR0_1 1
643#define PICR0_2 2
644#define PICR0_3 3
645#define PICR0_4 4
646#define PICR0_5 5
647#define PICR0_6 6
648#define PICR0_7 7
649
650#define PICR0H _SFR_MEM8(0x69)
651#define PICR0_8 0
652#define PICR0_9 1
653#define PICR0_10 2
654#define PICR0_11 3
655#define PCST0 7
656
657#define PSOC0 _SFR_MEM8(0x6A)
658#define POEN0A 0
659#define POEN0B 2
660#define PSYNC00 4
661#define PSYNC01 5
662#define PISEL0B1 6
663#define PISEL0A1 7
664
665#define PICR2 _SFR_MEM16(0x6C)
666
667#define PICR2L _SFR_MEM8(0x6C)
668#define PICR2_0 0
669#define PICR2_1 1
670#define PICR2_2 2
671#define PICR2_3 3
672#define PICR2_4 4
673#define PICR2_5 5
674#define PICR2_6 6
675#define PICR2_7 7
676
677#define PICR2H _SFR_MEM8(0x6D)
678#define PICR2_8 0
679#define PICR2_9 1
680#define PICR2_10 2
681#define PICR2_11 3
682#define PCST2 7
683
684#define PSOC2 _SFR_MEM8(0x6E)
685#define POEN2A 0
686#define POEN2C 1
687#define POEN2B 2
688#define POEN2D 3
689#define PSYNC2_0 4
690#define PSYNC2_1 5
691#define POS22 6
692#define POS23 7
693
694#define POM2 _SFR_MEM8(0x6F)
695#define POMV2A0 0
696#define POMV2A1 1
697#define POMV2A2 2
698#define POMV2A3 3
699#define POMV2B0 4
700#define POMV2B1 5
701#define POMV2B2 6
702#define POMV2B3 7
703
704#define PCNFE2 _SFR_MEM8(0x70)
705#define PISEL2B1 0
706#define PISEL2A1 1
707#define PELEV2B1 2
708#define PELEV2A1 3
709#define PBFM21 4
710#define PASDLK20 5
711#define PASDLK21 6
712#define PASDLK22 7
713
714#define PASDLY2 _SFR_MEM8(0x71)
715#define PASDLY2_0 0
716#define PASDLY2_1 1
717#define PASDLY2_2 2
718#define PASDLY2_3 3
719#define PASDLY2_4 4
720#define PASDLY2_5 5
721#define PASDLY2_6 6
722#define PASDLY2_7 7
723
724#define DACON _SFR_MEM8(0x76)
725#define DAEN 0
726#define DALA 2
727#define DATS0 4
728#define DATS1 5
729#define DATS2 6
730#define DAATE 7
731
732#define DIDR0 _SFR_MEM8(0x77)
733#define ADC0D 0
734#define ADC1D 1
735#define ADC2D 2
736#define ADC3D 3
737#define ADC4D 4
738#define ADC5D 5
739#define ADC7D 6
740#define ADC8D 7
741
742#define DIDR1 _SFR_MEM8(0x78)
743#define ADC9D 0
744#define ADC10D 1
745#define AMP0PD 2
746#define ACMP1MD 3
747
748#define AMP0CSR _SFR_MEM8(0x79)
749#define AMP0TS0 0
750#define AMP0TS1 1
751#define AMP0GS 3
752#define AMP0G0 4
753#define AMP0G1 5
754#define AMP0IS 6
755#define AMP0EN 7
756
757#define AC1ECON _SFR_MEM8(0x7A)
758#define AC1H0 0
759#define AC1H1 1
760#define AC1H2 2
761#define AC1ICE 3
762#define AC1OE 4
763#define AC1OI 5
764
765#define AC2ECON _SFR_MEM8(0x7B)
766#define AC2H0 0
767#define AC2H1 1
768#define AC2H2 2
769#define AC2OE 4
770#define AC2OI 5
771
772#define AC3ECON _SFR_MEM8(0x7C)
773#define AC3H0 0
774#define AC3H1 1
775#define AC3H2 2
776#define AC3OE 4
777#define AC3OI 5
778
779#define AC1CON _SFR_MEM8(0x7D)
780#define AC1M0 0
781#define AC1M1 1
782#define AC1M2 2
783#define AC1IS0 4
784#define AC1IS1 5
785#define AC1IE 6
786#define AC1EN 7
787
788#define AC2CON _SFR_MEM8(0x7E)
789#define AC2M0 0
790#define AC2M1 1
791#define AC2M2 2
792#define AC2IS0 4
793#define AC2IS1 5
794#define AC2IE 6
795#define AC2EN 7
796
797#define AC3CON _SFR_MEM8(0x7F)
798#define AC3M0 0
799#define AC3M1 1
800#define AC3M2 2
801#define AC3OEA 3
802#define AC3IS0 4
803#define AC3IS1 5
804#define AC3IE 6
805#define AC3EN 7
806
807#define BGCRR _SFR_MEM8(0x80)
808#define BGCR0 0
809#define BGCR1 1
810#define BGCR2 2
811#define BGCR3 3
812
813#define BGCCR _SFR_MEM8(0x81)
814#define BGCC0 0
815#define BGCC1 1
816#define BGCC2 2
817#define BGCC3 3
818
819#define WDTCSR _SFR_MEM8(0x82)
820#define WDP0 0
821#define WDP1 1
822#define WDP2 2
823#define WDE 3
824#define WDCE 4
825#define WDP3 5
826#define WDIE 6
827#define WDIF 7
828
829#define CLKPR _SFR_MEM8(0x83)
830#define CLKPS0 0
831#define CLKPS1 1
832#define CLKPS2 2
833#define CLKPS3 3
834#define CLKPCE 7
835
836#define CLKCSR _SFR_MEM8(0x84)
837#define CLKC0 0
838#define CLKC1 1
839#define CLKC2 2
840#define CLKC3 3
841#define CLKRDY 4
842#define CLKCCE 7
843
844#define CLKSELR _SFR_MEM8(0x85)
845#define CKSEL0 0
846#define CKSEL1 1
847#define CKSEL2 2
848#define CKSEL3 3
849#define CSUT0 4
850#define CSUT1 5
851#define COUT 6
852
853#define PRR _SFR_MEM8(0x86)
854#define PRADC 0
855#define PRSPI 2
856#define PRTIM1 4
857#define PRPSCR 5
858#define PRPSC2 7
859
860#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPSCR)|(1<<PRPSC2))
861#define __AVR_HAVE_PRR_PRADC
862#define __AVR_HAVE_PRR_PRSPI
863#define __AVR_HAVE_PRR_PRTIM1
864#define __AVR_HAVE_PRR_PRPSCR
865#define __AVR_HAVE_PRR_PRPSC2
866
867#define PLLCSR _SFR_MEM8(0x87)
868#define PLOCK 0
869#define PLLE 1
870#define PLLF0 2
871#define PLLF1 3
872#define PLLF2 4
873#define PLLF3 5
874
875#define OSCCAL _SFR_MEM8(0x88)
876#define CAL0 0
877#define CAL1 1
878#define CAL2 2
879#define CAL3 3
880#define CAL4 4
881#define CAL5 5
882#define CAL6 6
883#define CAL7 7
884
885#define EICRA _SFR_MEM8(0x89)
886#define ISC00 0
887#define ISC01 1
888#define ISC10 2
889#define ISC11 3
890#define ISC20 4
891#define ISC21 5
892
893#define TCCR1B _SFR_MEM8(0x8A)
894#define CS10 0
895#define CS11 1
896#define CS12 2
897#define WGM13 4
898#define ICES1 6
899#define ICNC1 7
900
901#define ICR1 _SFR_MEM16(0x8C)
902
903#define ICR1L _SFR_MEM8(0x8C)
904#define ICR1L0 0
905#define ICR1L1 1
906#define ICR1L2 2
907#define ICR1L3 3
908#define ICR1L4 4
909#define ICR1L5 5
910#define ICR1L6 6
911#define ICR1L7 7
912
913#define ICR1H _SFR_MEM8(0x8D)
914#define ICR1H0 0
915#define ICR1H1 1
916#define ICR1H2 2
917#define ICR1H3 3
918#define ICR1H4 4
919#define ICR1H5 5
920#define ICR1H6 6
921#define ICR1H7 7
922
923
924/* Interrupt vectors */
925/* Vector 0 is the reset vector */
926#define PSC2_CAPT_vect_num  1
927#define PSC2_CAPT_vect      _VECTOR(1)  /* PSC2 Capture Event */
928#define PSC2_EC_vect_num  2
929#define PSC2_EC_vect      _VECTOR(2)  /* PSC2 End Cycle */
930#define PSC2_EEC_vect_num  3
931#define PSC2_EEC_vect      _VECTOR(3)  /* PSC2 End Of Enhanced Cycle */
932#define PSC0_CAPT_vect_num  4
933#define PSC0_CAPT_vect      _VECTOR(4)  /* PSC0 Capture Event */
934#define PSC0_EC_vect_num  5
935#define PSC0_EC_vect      _VECTOR(5)  /* PSC0 End Cycle */
936#define PSC0_EEC_vect_num  6
937#define PSC0_EEC_vect      _VECTOR(6)  /* PSC0 End Of Enhanced Cycle */
938#define ANALOG_COMP_1_vect_num  7
939#define ANALOG_COMP_1_vect      _VECTOR(7)  /* Analog Comparator 1 */
940#define ANALOG_COMP_2_vect_num  8
941#define ANALOG_COMP_2_vect      _VECTOR(8)  /* Analog Comparator 2 */
942#define ANALOG_COMP_3_vect_num  9
943#define ANALOG_COMP_3_vect      _VECTOR(9)  /* Analog Comparator 3 */
944#define INT0_vect_num  10
945#define INT0_vect      _VECTOR(10)  /* External Interrupt Request 0 */
946#define TIMER1_CAPT_vect_num  11
947#define TIMER1_CAPT_vect      _VECTOR(11)  /* Timer/Counter1 Capture Event */
948#define TIMER1_OVF_vect_num  12
949#define TIMER1_OVF_vect      _VECTOR(12)  /* Timer/Counter1 Overflow */
950#define ADC_vect_num  13
951#define ADC_vect      _VECTOR(13)  /* ADC Conversion Complete */
952#define INT1_vect_num  14
953#define INT1_vect      _VECTOR(14)  /* External Interrupt Request 1 */
954#define SPI_STC_vect_num  15
955#define SPI_STC_vect      _VECTOR(15)  /* SPI Serial Transfer Complet */
956#define INT2_vect_num  16
957#define INT2_vect      _VECTOR(16)  /* External Interrupt Request 2 */
958#define WDT_vect_num  17
959#define WDT_vect      _VECTOR(17)  /* Watchdog Timeout Interrupt */
960#define EE_READY_vect_num  18
961#define EE_READY_vect      _VECTOR(18)  /* EEPROM Ready */
962#define SPM_READY_vect_num  19
963#define SPM_READY_vect      _VECTOR(19)  /* Store Program Memory Read */
964
965#define _VECTOR_SIZE 2 /* Size of individual vector. */
966#define _VECTORS_SIZE (20 * _VECTOR_SIZE)
967
968
969/* Constants */
970#define SPM_PAGESIZE (64)
971#define RAMSTART     (0x0100)
972#define RAMSIZE      (256)
973#define RAMEND       (RAMSTART + RAMSIZE - 1)
974#define XRAMSTART    (NA)
975#define XRAMSIZE     (0)
976#define XRAMEND      (RAMEND)
977#define E2END        (0x1FF)
978#define E2PAGESIZE   (4)
979#define FLASHEND     (0x1FFF)
980
981
982/* Fuses */
983#define FUSE_MEMORY_SIZE 3
984
985/* Low Fuse Byte */
986#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
987#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
988#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
989#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
990#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
991#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
992#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock Output */
993#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
994#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
995
996/* High Fuse Byte */
997#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
998#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
999#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
1000#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
1001#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
1002#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
1003#define FUSE_DWEN  (unsigned char)~_BV(6)  /* debugWIRE Enable */
1004#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
1005#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
1006
1007/* Extended Fuse Byte */
1008#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
1009#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
1010#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown out detector trigger level */
1011#define FUSE_PSCINRB  (unsigned char)~_BV(3)  /* PSC2 & PSC0 Input Reset Behavior */
1012#define FUSE_PSCRV  (unsigned char)~_BV(4)  /* PSCOUT Reset Value */
1013#define FUSE_PSC0RB  (unsigned char)~_BV(5)  /* PSC0 Reset Behaviour */
1014#define FUSE_PSC2RBA  (unsigned char)~_BV(6)  /* PSC2 Rest Behavior for out OUT22 & 23 */
1015#define FUSE_PSC2RB  (unsigned char)~_BV(7)  /* PSC2 Reset Behaviour */
1016#define EFUSE_DEFAULT (0xFF)
1017
1018
1019/* Lock Bits */
1020#define __LOCK_BITS_EXIST
1021#define __BOOT_LOCK_BITS_0_EXIST
1022#define __BOOT_LOCK_BITS_1_EXIST
1023
1024
1025/* Signature */
1026#define SIGNATURE_0 0x1E
1027#define SIGNATURE_1 0x93
1028#define SIGNATURE_2 0x88
1029
1030
1031#define SLEEP_MODE_IDLE (0x00<<1)
1032#define SLEEP_MODE_ADC (0x01<<1)
1033#define SLEEP_MODE_PWR_DOWN (0x02<<1)
1034#define SLEEP_MODE_STANDBY (0x06<<1)
1035#endif /* _AVR_AT90PWM81_H_ */
1036
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