source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/io90scr100.h @ 46

Last change on this file since 46 was 46, checked in by jrpelegrina, 4 years ago

First release to Xenial

File size: 33.5 KB
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1/* Copyright (c) 2009 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: io90scr100.h 1910 2009-03-04 17:45:30Z arcanum $ */
32
33/* avr/io90scr100.h - definitions for AT90SCR100 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "io90scr100.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_AT90SCR100_H_
49#define _AVR_AT90SCR100_H_ 1
50
51
52/* Registers and associated bit numbers. */
53
54#define PINA _SFR_IO8(0x00)
55#define PINA0 0
56#define PINA1 1
57#define PINA2 2
58#define PINA3 3
59#define PINA4 4
60#define PINA5 5
61#define PINA6 6
62#define PINA7 7
63
64#define DDRA _SFR_IO8(0x01)
65#define DDA0 0
66#define DDA1 1
67#define DDA2 2
68#define DDA3 3
69#define DDA4 4
70#define DDA5 5
71#define DDA6 6
72#define DDA7 7
73
74#define PORTA _SFR_IO8(0x02)
75#define PORTA0 0
76#define PORTA1 1
77#define PORTA2 2
78#define PORTA3 3
79#define PORTA4 4
80#define PORTA5 5
81#define PORTA6 6
82#define PORTA7 7
83
84#define PINB _SFR_IO8(0x03)
85#define PINB0 0
86#define PINB1 1
87#define PINB2 2
88#define PINB3 3
89#define PINB4 4
90#define PINB5 5
91#define PINB6 6
92#define PINB7 7
93
94#define DDRB _SFR_IO8(0x04)
95#define DDB0 0
96#define DDB1 1
97#define DDB2 2
98#define DDB3 3
99#define DDB4 4
100#define DDB5 5
101#define DDB6 6
102#define DDB7 7
103
104#define PORTB _SFR_IO8(0x05)
105#define PORTB0 0
106#define PORTB1 1
107#define PORTB2 2
108#define PORTB3 3
109#define PORTB4 4
110#define PORTB5 5
111#define PORTB6 6
112#define PORTB7 7
113
114#define PINC _SFR_IO8(0x06)
115#define PINC0 0
116#define PINC1 1
117#define PINC2 2
118#define PINC3 3
119#define PINC4 4
120#define PINC5 5
121#define PINC6 6
122#define PINC7 7
123
124#define DDRC _SFR_IO8(0x07)
125#define DDC0 0
126#define DDC1 1
127#define DDC2 2
128#define DDC3 3
129#define DDC4 4
130#define DDC5 5
131#define DDC6 6
132#define DDC7 7
133
134#define PORTC _SFR_IO8(0x08)
135#define PORTC0 0
136#define PORTC1 1
137#define PORTC2 2
138#define PORTC3 3
139#define PORTC4 4
140#define PORTC5 5
141#define PORTC6 6
142#define PORTC7 7
143
144#define PIND _SFR_IO8(0x09)
145#define PIND0 0
146#define PIND1 1
147#define PIND2 2
148#define PIND3 3
149#define PIND4 4
150#define PIND5 5
151#define PIND6 6
152#define PIND7 7
153
154#define DDRD _SFR_IO8(0x0A)
155#define DDD0 0
156#define DDD1 1
157#define DDD2 2
158#define DDD3 3
159#define DDD4 4
160#define DDD5 5
161#define DDD6 6
162#define DDD7 7
163
164#define PORTD _SFR_IO8(0x0B)
165#define PORTD0 0
166#define PORTD1 1
167#define PORTD2 2
168#define PORTD3 3
169#define PORTD4 4
170#define PORTD5 5
171#define PORTD6 6
172#define PORTD7 7
173
174#define PINE _SFR_IO8(0x0C)
175#define PINE0 0
176#define PINE1 1
177#define PINE2 2
178#define PINE3 3
179#define PINE4 4
180#define PINE5 5
181#define PINE6 6
182#define PINE7 7
183
184#define DDRE _SFR_IO8(0x0D)
185#define DDE0 0
186#define DDE1 1
187#define DDE2 2
188#define DDE3 3
189#define DDE4 4
190#define DDE5 5
191#define DDE6 6
192#define DDE7 7
193
194#define PORTE _SFR_IO8(0x0E)
195#define PORTE0 0
196#define PORTE1 1
197#define PORTE2 2
198#define PORTE3 3
199#define PORTE4 4
200#define PORTE5 5
201#define PORTE6 6
202#define PORTE7 7
203
204#define TIFR0 _SFR_IO8(0x15)
205#define TOV0 0
206#define OCF0A 1
207#define OCF0B 2
208
209#define TIFR1 _SFR_IO8(0x16)
210#define TOV1 0
211#define OCF1A 1
212#define OCF1B 2
213#define ICF1 5
214
215#define TIFR2 _SFR_IO8(0x17)
216#define TOV2 0
217#define OCF2A 1
218#define OCF2B 2
219
220#define EIRR _SFR_IO8(0x1A)
221#define INTD2 2
222#define INTD3 3
223
224#define PCIFR _SFR_IO8(0x1B)
225#define PCIF0 0
226#define PCIF1 1
227#define PCIF2 2
228#define PCIF3 3
229
230#define EIFR _SFR_IO8(0x1C)
231#define INTF0 0
232#define INTF1 1
233#define INTF2 2
234#define INTF3 3
235
236#define EIMSK _SFR_IO8(0x1D)
237#define INT0 0
238#define INT1 1
239#define INT2 2
240#define INT3 3
241
242#define GPIOR0 _SFR_IO8(0x1E)
243#define GPIOR00 0
244#define GPIOR01 1
245#define GPIOR02 2
246#define GPIOR03 3
247#define GPIOR04 4
248#define GPIOR05 5
249#define GPIOR06 6
250#define GPIOR07 7
251
252#define EECR _SFR_IO8(0x1F)
253#define EERE 0
254#define EEPE 1
255#define EEMPE 2
256#define EERIE 3
257#define EEPM0 4
258#define EEPM1 5
259
260#define EEDR _SFR_IO8(0x20)
261#define EEDR0 0
262#define EEDR1 1
263#define EEDR2 2
264#define EEDR3 3
265#define EEDR4 4
266#define EEDR5 5
267#define EEDR6 6
268#define EEDR7 7
269
270#define EEAR _SFR_IO16(0x21)
271
272#define EEARL _SFR_IO8(0x21)
273#define EEAR0 0
274#define EEAR1 1
275#define EEAR2 2
276#define EEAR3 3
277#define EEAR4 4
278#define EEAR5 5
279#define EEAR6 6
280#define EEAR7 7
281
282#define EEARH _SFR_IO8(0x22)
283#define EEAR8 0
284#define EEAR9 1
285#define EEAR10 2
286#define EEAR11 3
287
288#define GTCCR _SFR_IO8(0x23)
289#define PSRSYNC 0
290#define PSRASY 1
291#define TSM 7
292
293#define TCCR0A _SFR_IO8(0x24)
294#define WGM00 0
295#define WGM01 1
296#define COM0B0 4
297#define COM0B1 5
298#define COM0A0 6
299#define COM0A1 7
300
301#define TCCR0B _SFR_IO8(0x25)
302#define CS00 0
303#define CS01 1
304#define CS02 2
305#define WGM02 3
306#define FOC0B 6
307#define FOC0A 7
308
309#define TCNT0 _SFR_IO8(0x26)
310#define TCNT0_0 0
311#define TCNT0_1 1
312#define TCNT0_2 2
313#define TCNT0_3 3
314#define TCNT0_4 4
315#define TCNT0_5 5
316#define TCNT0_6 6
317#define TCNT0_7 7
318
319#define OCR0A _SFR_IO8(0x27)
320#define OCR0A_0 0
321#define OCR0A_1 1
322#define OCR0A_2 2
323#define OCR0A_3 3
324#define OCR0A_4 4
325#define OCR0A_5 5
326#define OCR0A_6 6
327#define OCR0A_7 7
328
329#define OCR0B _SFR_IO8(0x28)
330#define OCR0B_0 0
331#define OCR0B_1 1
332#define OCR0B_2 2
333#define OCR0B_3 3
334#define OCR0B_4 4
335#define OCR0B_5 5
336#define OCR0B_6 6
337#define OCR0B_7 7
338
339#define GPIOR1 _SFR_IO8(0x2A)
340#define GPIOR10 0
341#define GPIOR11 1
342#define GPIOR12 2
343#define GPIOR13 3
344#define GPIOR14 4
345#define GPIOR15 5
346#define GPIOR16 6
347#define GPIOR17 7
348
349#define GPIOR2 _SFR_IO8(0x2B)
350#define GPIOR20 0
351#define GPIOR21 1
352#define GPIOR22 2
353#define GPIOR23 3
354#define GPIOR24 4
355#define GPIOR25 5
356#define GPIOR26 6
357#define GPIOR27 7
358
359#define SPCR _SFR_IO8(0x2C)
360#define SPR0 0
361#define SPR1 1
362#define CPHA 2
363#define CPOL 3
364#define MSTR 4
365#define DORD 5
366#define SPE 6
367#define SPIE 7
368
369#define SPSR _SFR_IO8(0x2D)
370#define SPI2X 0
371#define WCOL 6
372#define SPIF 7
373
374#define SPDR _SFR_IO8(0x2E)
375#define SPDR0 0
376#define SPDR1 1
377#define SPDR2 2
378#define SPDR3 3
379#define SPDR4 4
380#define SPDR5 5
381#define SPDR6 6
382#define SPDR7 7
383
384#define OCDR _SFR_IO8(0x31)
385#define OCDR0 0
386#define OCDR1 1
387#define OCDR2 2
388#define OCDR3 3
389#define OCDR4 4
390#define OCDR5 5
391#define OCDR6 6
392#define OCDR7 7
393
394#define SMCR _SFR_IO8(0x33)
395#define SE 0
396#define SM0 1
397#define SM1 2
398#define SM2 3
399
400#define MCUSR _SFR_IO8(0x34)
401#define PORF 0
402#define EXTRF 1
403#define BORF 2
404#define WDRF 3
405#define JTRF 4
406
407#define MCUCR _SFR_IO8(0x35)
408#define IVCE 0
409#define IVSEL 1
410#define PUD 4
411#define BODSE 5
412#define BODS 6
413#define JTD 7
414
415#define SPMCSR _SFR_IO8(0x37)
416#define SPMEN 0
417#define PGERS 1
418#define PGWRT 2
419#define BLBSET 3
420#define RWWSRE 4
421#define SIGRD 5
422#define RWWSB 6
423#define SPMIE 7
424
425#define RAMPZ _SFR_IO8(0x3B)
426#define RAMPZ0 0
427
428#define WDTCSR _SFR_MEM8(0x60)
429#define WDP0 0
430#define WDP1 1
431#define WDP2 2
432#define WDE 3
433#define WDCE 4
434#define WDP3 5
435#define WDIE 6
436#define WDIF 7
437
438#define CLKPR _SFR_MEM8(0x61)
439#define CLKPS0 0
440#define CLKPS1 1
441#define CLKPS2 2
442#define CLKPS3 3
443#define CLKPCE 7
444
445#define PLLCR _SFR_MEM8(0x62)
446#define ON 0
447#define LOCK 1
448#define PLLMUX 7
449
450#define SMONCR _SFR_MEM8(0x63)
451#define SMONEN 0
452#define SMONIE 1
453#define SMONIF 4
454
455#define PRR0 _SFR_MEM8(0x64)
456#define PRUSART0 1
457#define PRSPI 2
458#define PRTIM1 3
459#define PRTIM0 5
460#define PRTIM2 6
461#define PRTWI 7
462
463#define PRR1 _SFR_MEM8(0x65)
464#define PRUSBH 0
465#define PRUSB 1
466#define PRHSSPI 2
467#define PRSCI 3
468#define PRAES 4
469#define PRKB 5
470
471#define OSCCAL _SFR_MEM8(0x66)
472#define CAL0 0
473#define CAL1 1
474#define CAL2 2
475#define CAL3 3
476#define CAL4 4
477#define CAL5 5
478#define CAL6 6
479#define CAL7 7
480
481#define PCICR _SFR_MEM8(0x68)
482#define PCIE0 0
483#define PCIE1 1
484#define PCIE2 2
485#define PCIE3 3
486
487#define EICRA _SFR_MEM8(0x69)
488#define ISC00 0
489#define ISC01 1
490#define ISC10 2
491#define ISC11 3
492#define ISC20 4
493#define ISC21 5
494#define ISC30 6
495#define ISC31 7
496
497#define PCMSK0 _SFR_MEM8(0x6B)
498#define PCINT0 0
499#define PCINT1 1
500#define PCINT2 2
501#define PCINT3 3
502#define PCINT4 4
503#define PCINT5 5
504#define PCINT6 6
505#define PCINT7 7
506
507#define PCMSK1 _SFR_MEM8(0x6C)
508#define PCINT8 0
509#define PCINT9 1
510#define PCINT10 2
511#define PCINT11 3
512#define PCINT12 4
513#define PCINT13 5
514#define PCINT14 6
515#define PCINT15 7
516
517#define PCMSK2 _SFR_MEM8(0x6D)
518#define PCINT16 0
519#define PCINT17 1
520#define PCINT18 2
521#define PCINT19 3
522#define PCINT20 4
523#define PCINT21 5
524#define PCINT22 6
525#define PCINT23 7
526
527#define TIMSK0 _SFR_MEM8(0x6E)
528#define TOIE0 0
529#define OCIE0A 1
530#define OCIE0B 2
531
532#define TIMSK1 _SFR_MEM8(0x6F)
533#define TOIE1 0
534#define OCIE1A 1
535#define OCIE1B 2
536#define ICIE1 5
537
538#define TIMSK2 _SFR_MEM8(0x70)
539#define TOIE2 0
540#define OCIE2A 1
541#define OCIE2B 2
542
543#define PCMSK3 _SFR_MEM8(0x73)
544
545#define LEDCR _SFR_MEM8(0x75)
546#define LED00 0
547#define LED01 1
548#define LED10 2
549#define LED11 3
550#define LED20 4
551#define LED21 5
552#define lED30 6
553#define LED31 7
554
555#define AESCR _SFR_MEM8(0x78)
556#define AESGO 0
557#define ENCRYPT 1
558#define KS 3
559#define KEYGN 4
560#define AUTOKEY 5
561#define AESIF 6
562#define AESIE 7
563
564#define AESACR _SFR_MEM8(0x79)
565#define KD 0
566#define AUTOINC 1
567#define MANINC 2
568#define XOR 3
569
570#define AESADDR _SFR_MEM8(0x7A)
571#define ADDR0 0
572#define ADDR1 1
573#define ADDR2 2
574#define ADDR3 3
575#define ADDR4 4
576#define ADDR5 5
577#define ADDR6 6
578#define ADDR7 7
579
580#define AESDR _SFR_MEM8(0x7B)
581#define DATA0 0
582#define DATA1 1
583#define DATA2 2
584#define DATA3 3
585#define DATA4 4
586#define DATA5 5
587#define DATA6 6
588#define DATA7 7
589
590#define TCCR1A _SFR_MEM8(0x80)
591#define WGM10 0
592#define WGM11 1
593#define COM1B0 4
594#define COM1B1 5
595#define COM1A0 6
596#define COM1A1 7
597
598#define TCCR1B _SFR_MEM8(0x81)
599#define CS10 0
600#define CS11 1
601#define CS12 2
602#define WGM12 3
603#define WGM13 4
604#define ICES1 6
605#define ICNC1 7
606
607#define TCCR1C _SFR_MEM8(0x82)
608#define FOC1B 6
609#define FOC1A 7
610
611#define TCNT1 _SFR_MEM16(0x84)
612
613#define TCNT1L _SFR_MEM8(0x84)
614#define TCNT1L0 0
615#define TCNT1L1 1
616#define TCNT1L2 2
617#define TCNT1L3 3
618#define TCNT1L4 4
619#define TCNT1L5 5
620#define TCNT1L6 6
621#define TCNT1L7 7
622
623#define TCNT1H _SFR_MEM8(0x85)
624#define TCNT1H0 0
625#define TCNT1H1 1
626#define TCNT1H2 2
627#define TCNT1H3 3
628#define TCNT1H4 4
629#define TCNT1H5 5
630#define TCNT1H6 6
631#define TCNT1H7 7
632
633#define ICR1 _SFR_MEM16(0x86)
634
635#define ICR1L _SFR_MEM8(0x86)
636#define ICR1L0 0
637#define ICR1L1 1
638#define ICR1L2 2
639#define ICR1L3 3
640#define ICR1L4 4
641#define ICR1L5 5
642#define ICR1L6 6
643#define ICR1L7 7
644
645#define ICR1H _SFR_MEM8(0x87)
646#define ICR1H0 0
647#define ICR1H1 1
648#define ICR1H2 2
649#define ICR1H3 3
650#define ICR1H4 4
651#define ICR1H5 5
652#define ICR1H6 6
653#define ICR1H7 7
654
655#define OCR1A _SFR_MEM16(0x88)
656
657#define OCR1AL _SFR_MEM8(0x88)
658#define OCR1AL0 0
659#define OCR1AL1 1
660#define OCR1AL2 2
661#define OCR1AL3 3
662#define OCR1AL4 4
663#define OCR1AL5 5
664#define OCR1AL6 6
665#define OCR1AL7 7
666
667#define OCR1AH _SFR_MEM8(0x89)
668#define OCR1AH0 0
669#define OCR1AH1 1
670#define OCR1AH2 2
671#define OCR1AH3 3
672#define OCR1AH4 4
673#define OCR1AH5 5
674#define OCR1AH6 6
675#define OCR1AH7 7
676
677#define OCR1B _SFR_MEM16(0x8A)
678
679#define OCR1BL _SFR_MEM8(0x8A)
680#define OCR1BL0 0
681#define OCR1BL1 1
682#define OCR1BL2 2
683#define OCR1BL3 3
684#define OCR1BL4 4
685#define OCR1BL5 5
686#define OCR1BL6 6
687#define OCR1BL7 7
688
689#define OCR1BH _SFR_MEM8(0x8B)
690#define OCR1BH0 0
691#define OCR1BH1 1
692#define OCR1BH2 2
693#define OCR1BH3 3
694#define OCR1BH4 4
695#define OCR1BH5 5
696#define OCR1BH6 6
697#define OCR1BH7 7
698
699#define KBLSR _SFR_MEM8(0x8D)
700#define KBLS0 0
701#define KBLS1 1
702#define KBLS2 2
703#define KBLS3 3
704#define KBLS4 4
705#define KBLS5 5
706#define KBLS6 6
707#define KBLS7 7
708
709#define KBER _SFR_MEM8(0x8E)
710#define KBE0 0
711#define KBE1 1
712#define KBE2 2
713#define KBE3 3
714#define KBE4 4
715#define KBE5 5
716#define KBE6 6
717#define KBE7 7
718
719#define KBFR _SFR_MEM8(0x8F)
720#define KBF0 0
721#define KBF1 1
722#define KBF2 2
723#define KBF3 3
724#define KBF4 4
725#define KBF5 5
726#define KBF6 6
727#define KBF7 7
728
729#define RDWDR _SFR_MEM8(0x90)
730#define RDD0 0
731#define RDD1 1
732#define RDD2 2
733#define RDD3 3
734#define RDD4 4
735#define RDD5 5
736#define RDD6 6
737#define RDD7 7
738
739#define LFSR0 _SFR_MEM8(0x91)
740#define LFSD0 0
741#define LFSD1 1
742#define LFSD2 2
743#define LFSD3 3
744#define LFSD4 4
745#define LFSD5 5
746#define LFSD6 6
747#define LFSD7 7
748
749#define LFSR1 _SFR_MEM8(0x92)
750#define LFSD8 0
751#define LFSD9 1
752#define LFSD10 2
753#define LFSD11 3
754#define LFSD12 4
755#define LFSD13 5
756#define LFSD14 6
757#define LFSD15 7
758
759#define LFSR2 _SFR_MEM8(0x93)
760#define LFSD16 0
761#define LFSD17 1
762#define LFSD18 2
763#define LFSD19 3
764#define LFSD20 4
765#define LFSD21 5
766#define LFSD22 6
767#define LFSD23 7
768
769#define LFSR3 _SFR_MEM8(0x94)
770#define LFSD24 0
771#define LFSD25 1
772#define LFSD26 2
773#define LFSD27 3
774#define LFSD28 4
775#define LFSD29 5
776#define LFSD30 6
777#define LFSD31 7
778
779#define RNGCR _SFR_MEM8(0x95)
780#define ROSCE 0
781
782#define UHSR _SFR_MEM8(0x99)
783#define SPEED 3
784
785#define UPINT _SFR_MEM8(0x9A)
786#define PINT0 0
787#define PINT1 1
788#define PINT2 2
789#define PINT3 3
790
791#define UPBCX _SFR_MEM16(0x9B)
792
793#define UPBCXL _SFR_MEM8(0x9B)
794#define PBYTCT0 0
795#define PBYTCT1 1
796#define PBYTCT2 2
797#define PBYTCT3 3
798#define PBYTCT4 4
799#define PBYTCT5 5
800#define PBYTCT6 6
801#define PBYTCT7 7
802
803#define UPBCXH _SFR_MEM8(0x9C)
804#define PBYTCT8 0
805#define PBYTCT9 1
806#define PBYTCT10 2
807
808#define UPERRX _SFR_MEM8(0x9D)
809#define DATATGL 0
810#define DATAPID 1
811#define PID 2
812#define PTIMEOUT 3
813#define CRC16 4
814#define COUNTER0 5
815#define COUNTER1 6
816
817#define UHCR _SFR_MEM8(0x9E)
818#define SOFEN 0
819#define RESET 1
820#define RESUME 2
821#define FRZCLK 4
822#define PAD0 5
823#define PAD1 6
824#define UHEN 7
825
826#define UHINT _SFR_MEM8(0x9F)
827#define DCONNI 0
828#define DDISCI 1
829#define RSTI 2
830#define RSMEDI 3
831#define RXRSMI 4
832#define HSOFI 5
833#define HWUPI 6
834
835#define UHIEN _SFR_MEM8(0xA0)
836#define DCONNE 0
837#define DDISCE 1
838#define RSTE 2
839#define RSMEDE 3
840#define RXRSME 4
841#define HSOFE 5
842#define HWUPE 6
843
844#define UHADDR _SFR_MEM8(0xA1)
845#define HADDR0 0
846#define HADDR1 1
847#define HADDR2 2
848#define HADDR3 3
849#define HADDR4 4
850#define HADDR5 5
851#define HADDR6 6
852
853#define UHFNUM _SFR_MEM16(0xA2)
854
855#define UHFNUML _SFR_MEM8(0xA2)
856#define FNUM0 0
857#define FNUM1 1
858#define FNUM2 2
859#define FNUM3 3
860#define FNUM4 4
861#define FNUM5 5
862#define FNUM6 6
863#define FNUM7 7
864
865#define UHFNUMH _SFR_MEM8(0xA3)
866#define FNUM8 0
867#define FNUM9 1
868#define FNUM10 2
869
870#define UHFLEN _SFR_MEM8(0xA4)
871#define FLEN0 0
872#define FLEN1 1
873#define FLEN2 2
874#define FLEN3 3
875#define FLEN4 4
876#define FLEN5 5
877#define FLEN6 6
878#define FLEN7 7
879
880#define UPINRQX _SFR_MEM8(0xA5)
881#define INRQ0 0
882#define INRQ1 1
883#define INRQ2 2
884#define INRQ3 3
885#define INRQ4 4
886#define INRQ5 5
887#define INRQ6 6
888#define INRQ7 7
889
890#define UPINTX _SFR_MEM8(0xA6)
891#define RXINI 0
892#define RXSTALLI 1
893#define TXOUTI 2
894#define TXSTPI 3
895#define PERRI 4
896#define RWAL 5
897#define NAKEDI 6
898#define FIFOCON 7
899
900#define UPNUM _SFR_MEM8(0xA7)
901#define PNUM0 0
902#define PNUM1 1
903
904#define UPRST _SFR_MEM8(0xA8)
905#define P0RST 0
906#define P1RST 1
907#define P2RST 2
908#define P3RST 3
909
910#define UPCRX _SFR_MEM8(0xA9)
911#define PEN 0
912#define RSTDT 3
913#define INMODE 5
914#define PFREEZE 6
915
916#define UPCFG0X _SFR_MEM8(0xAA)
917#define PEPNUM0 0
918#define PEPNUM1 1
919#define PEPNUM2 2
920#define PEPNUM3 3
921#define PTOKEN0 4
922#define PTOKEN1 5
923#define PTYPE0 6
924#define PTYPE1 7
925
926#define UPCFG1X _SFR_MEM8(0xAB)
927#define ALLOC 1
928#define PBK0 2
929#define PBK1 3
930#define PSIZE0 4
931#define PSIZE1 5
932#define PSIZE2 6
933
934#define UPSTAX _SFR_MEM8(0xAC)
935#define NBUSYBK0 0
936#define NBUSYBK1 1
937#define DTSEQ0 2
938#define DTSEQ1 3
939#define UNDERFI 5
940#define OVERFI 6
941#define CFGOK 7
942
943#define UPCFG2X _SFR_MEM8(0xAD)
944#define INTFRQ0 0
945#define INTFRQ1 1
946#define INTFRQ2 2
947#define INTFRQ3 3
948#define INTFRQ4 4
949#define INTFRQ5 5
950#define INTFRQ6 6
951#define INTFRQ7 7
952
953#define UPIENX _SFR_MEM8(0xAE)
954#define RXINE 0
955#define RXSTALLE 1
956#define TXOUTE 2
957#define TXSTPE 3
958#define PERRE 4
959#define NAKEDE 6
960#define FLERRE 7
961
962#define UPDATX _SFR_MEM8(0xAF)
963#define PDAT0 0
964#define PDAT1 1
965#define PDAT2 2
966#define PDAT3 3
967#define PDAT4 4
968#define PDAT5 5
969#define PDAT6 6
970#define PDAT7 7
971
972#define TCCR2A _SFR_MEM8(0xB0)
973#define WGM20 0
974#define WGM21 1
975#define COM2B0 4
976#define COM2B1 5
977#define COM2A0 6
978#define COM2A1 7
979
980#define TCCR2B _SFR_MEM8(0xB1)
981#define CS20 0
982#define CS21 1
983#define CS22 2
984#define WGM22 3
985#define FOC2B 6
986#define FOC2A 7
987
988#define TCNT2 _SFR_MEM8(0xB2)
989#define TCNT2_0 0
990#define TCNT2_1 1
991#define TCNT2_2 2
992#define TCNT2_3 3
993#define TCNT2_4 4
994#define TCNT2_5 5
995#define TCNT2_6 6
996#define TCNT2_7 7
997
998#define OCR2A _SFR_MEM8(0xB3)
999#define OCR2A0 0
1000#define OCR2A1 1
1001#define OCR2A2 2
1002#define OCR2A3 3
1003#define OCR2A4 4
1004#define OCR2A5 5
1005#define OCR2A6 6
1006#define OCR2A7 7
1007
1008#define OCR2B _SFR_MEM8(0xB4)
1009#define OCR2B0 0
1010#define OCR2B1 1
1011#define OCR2B2 2
1012#define OCR2B3 3
1013#define OCR2B4 4
1014#define OCR2B5 5
1015#define OCR2B6 6
1016#define OCR2B7 7
1017
1018#define ASSR _SFR_MEM8(0xB6)
1019#define TCR2BUB 0
1020#define TCR2AUB 1
1021#define OCR2BUB 2
1022#define OCR2AUB 3
1023#define TCN2UB 4
1024#define AS2 5
1025#define EXCLK 6
1026
1027#define TWBR _SFR_MEM8(0xB8)
1028#define TWBR0 0
1029#define TWBR1 1
1030#define TWBR2 2
1031#define TWBR3 3
1032#define TWBR4 4
1033#define TWBR5 5
1034#define TWBR6 6
1035#define TWBR7 7
1036
1037#define TWSR _SFR_MEM8(0xB9)
1038#define TWPS0 0
1039#define TWPS1 1
1040#define TWS3 3
1041#define TWS4 4
1042#define TWS5 5
1043#define TWS6 6
1044#define TWS7 7
1045
1046#define TWAR _SFR_MEM8(0xBA)
1047#define TWGCE 0
1048#define TWA0 1
1049#define TWA1 2
1050#define TWA2 3
1051#define TWA3 4
1052#define TWA4 5
1053#define TWA5 6
1054#define TWA6 7
1055
1056#define TWDR _SFR_MEM8(0xBB)
1057#define TWD0 0
1058#define TWD1 1
1059#define TWD2 2
1060#define TWD3 3
1061#define TWD4 4
1062#define TWD5 5
1063#define TWD6 6
1064#define TWD7 7
1065
1066#define TWCR _SFR_MEM8(0xBC)
1067#define TWIE 0
1068#define TWEN 2
1069#define TWWC 3
1070#define TWSTO 4
1071#define TWSTA 5
1072#define TWEA 6
1073#define TWINT 7
1074
1075#define TWAMR _SFR_MEM8(0xBD)
1076#define TWAM0 1
1077#define TWAM1 2
1078#define TWAM2 3
1079#define TWAM3 4
1080#define TWAM4 5
1081#define TWAM5 6
1082#define TWAM6 7
1083
1084#define UCSR0A _SFR_MEM8(0xC0)
1085#define MPCM0 0
1086#define U2X0 1
1087#define UPE0 2
1088#define DOR0 3
1089#define FE0 4
1090#define UDRE0 5
1091#define TXC0 6
1092#define RXC0 7
1093
1094#define UCSR0B _SFR_MEM8(0xC1)
1095#define TXB80 0
1096#define RXB80 1
1097#define UCSZ02 2
1098#define TXEN0 3
1099#define RXEN0 4
1100#define UDRIE0 5
1101#define TXCIE0 6
1102#define RXCIE0 7
1103
1104#define UCSR0C _SFR_MEM8(0xC2)
1105#define UCPOL0 0
1106#define UCSZ00 1
1107#define UCSZ01 2
1108#define USBS0 3
1109#define UPM00 4
1110#define UPM01 5
1111#define UMSEL00 6
1112#define UMSEL01 7
1113
1114#define UBRR0 _SFR_MEM16(0xC4)
1115
1116#define UBRR0L _SFR_MEM8(0xC4)
1117#define UBRR00 0
1118#define UBRR01 1
1119#define UBRR02 2
1120#define UBRR03 3
1121#define UBRR04 4
1122#define UBRR05 5
1123#define UBRR06 6
1124#define UBRR07 7
1125
1126#define UBRR0H _SFR_MEM8(0xC5)
1127#define UBRR08 0
1128#define UBRR09 1
1129#define UBRR010 2
1130#define UBRR011 3
1131
1132#define UDR0 _SFR_MEM8(0xC6)
1133#define UDR00 0
1134#define UDR01 1
1135#define UDR02 2
1136#define UDR03 3
1137#define UDR04 4
1138#define UDR05 5
1139#define UDR06 6
1140#define UDR07 7
1141
1142#define USBENUM _SFR_MEM8(0xCA)
1143#define USBENUM0 0
1144#define USBENUM1 1
1145#define USBENUM2 2
1146
1147#define USBCSEX _SFR_MEM8(0xCB)
1148#define TXC 0
1149#define RCVD 1
1150#define RXSETUP 2
1151#define STSENT 3
1152#define TXPB 4
1153#define FSTALL 5
1154#define IERR 6
1155
1156#define USBDBCEX _SFR_MEM8(0xCC)
1157#define BCT0 0
1158#define BCT1 1
1159#define BCT2 2
1160#define BCT3 3
1161#define BCT4 4
1162#define BCT5 5
1163#define BCT6 6
1164#define BCT7 7
1165
1166#define USBFCEX _SFR_MEM8(0xCD)
1167#define EPTYP0 0
1168#define EPTYP1 1
1169#define EPDIR 2
1170#define EPE 7
1171
1172#define HSSPITO _SFR_MEM16(0xD1)
1173
1174#define HSSPITOL _SFR_MEM8(0xD1)
1175#define HSSPITOD0 0
1176#define HSSPITOD1 1
1177#define HSSPITOD2 2
1178#define HSSPITOD3 3
1179#define HSSPITOD4 4
1180#define HSSPITOD5 5
1181#define HSSPITOD6 6
1182#define HSSPITOD7 7
1183
1184#define HSSPITOH _SFR_MEM8(0xD2)
1185#define HSSPITOD8 0
1186#define HSSPITOD9 1
1187#define HSSPITOD10 2
1188#define HSSPITOD11 3
1189#define HSSPITOD12 4
1190#define HSSPITOD13 5
1191#define HSSPITOD14 6
1192#define HSSPITOD15 7
1193
1194#define HSSPICNT _SFR_MEM8(0xD3)
1195#define HSSPICNTD0 0
1196#define HSSPICNTD1 1
1197#define HSSPICNTD2 2
1198#define HSSPICNTD3 3
1199#define HSSPICNTD4 4
1200
1201#define HSSPIIER _SFR_MEM8(0xD4)
1202#define NSSIE 4
1203#define RCVOFIE 5
1204#define BTDIE 6
1205#define TIMEOUTIE 7
1206
1207#define HSSPIGTR _SFR_MEM8(0xD5)
1208#define HSSPIGTD0 0
1209#define HSSPIGTD1 1
1210#define HSSPIGTD2 2
1211#define HSSPIGTD3 3
1212#define HSSPIGTD4 4
1213#define HSSPIGTD5 5
1214#define HSSPIGTD6 6
1215#define HSSPIGTD7 7
1216
1217#define HSSPIRDR _SFR_MEM8(0xD6)
1218#define HSSPIRDD0 0
1219#define HSSPIRDD1 1
1220#define HSSPIRDD2 2
1221#define HSSPIRDD3 3
1222#define HSSPIRDD4 4
1223#define HSSPIRDD5 5
1224#define HSSPIRDD6 6
1225#define HSSPIRDD7 7
1226
1227#define HSSPITDR _SFR_MEM8(0xD7)
1228#define HSSPITDD0 0
1229#define HSSPITDD1 1
1230#define HSSPITDD2 2
1231#define HSSPITDD3 3
1232#define HSSPITDD4 4
1233#define HSSPITDD5 5
1234#define HSSPITDD6 6
1235#define HSSPITDD7 7
1236
1237#define HSSPISR _SFR_MEM8(0xD8)
1238#define SPICKRDY 0
1239#define TXBUFE 1
1240#define RXBUFF 2
1241#define NSS 3
1242#define DPRAMRDY 4
1243
1244#define HSSPICFG _SFR_MEM8(0xD9)
1245#define HSSPIEN 0
1246#define HSMSTR 1
1247#define HSCPOL 2
1248#define HSCPHA 3
1249#define DPRAM 4
1250#define SPICKDIV0 5
1251#define SPICKDIV1 6
1252#define SPICKDIV2 7
1253
1254#define HSSPIIR _SFR_MEM8(0xDA)
1255#define NSSFE 3
1256#define NSSRE 4
1257#define RCVOF 5
1258#define BTD 6
1259#define TIMEOUT 7
1260
1261#define HSSPICR _SFR_MEM8(0xDB)
1262#define CS 0
1263#define RETTO 1
1264#define STTTO 2
1265
1266#define HSSPIDMACS _SFR_MEM8(0xDC)
1267#define HSSPIDMAR 0
1268#define HSSPIDMADIR 1
1269#define HSSPIDMAERR 2
1270
1271#define HSSPIDMAD _SFR_MEM16(0xDD)
1272
1273#define HSSPIDMADL _SFR_MEM8(0xDD)
1274#define HSSPIDMAD0 0
1275#define HSSPIDMAD1 1
1276#define HSSPIDMAD2 2
1277#define HSSPIDMAD3 3
1278#define HSSPIDMAD4 4
1279#define HSSPIDMAD5 5
1280#define HSSPIDMAD6 6
1281#define HSSPIDMAD7 7
1282
1283#define HSSPIDMADH _SFR_MEM8(0xDE)
1284#define HSSPIDMAD8 0
1285#define HSSPIDMAD9 1
1286#define HSSPIDMAD10 2
1287#define HSSPIDMAD11 3
1288#define HSSPIDMAD12 4
1289#define HSSPIDMAD13 5
1290
1291#define HSSPIDMAB _SFR_MEM8(0xDF)
1292#define HSSPIDMAB0 0
1293#define HSSPIDMAB1 1
1294#define HSSPIDMAB2 2
1295#define HSSPIDMAB3 3
1296#define HSSPIDMAB4 4
1297
1298#define USBCR _SFR_MEM8(0xE0)
1299#define USBE 1
1300#define UPUC 5
1301#define URMWU 7
1302
1303#define USBPI _SFR_MEM8(0xE1)
1304#define SUSI 0
1305#define RESI 1
1306#define RMWUI 2
1307#define SOFI 3
1308#define FEURI 4
1309
1310#define USBPIM _SFR_MEM8(0xE2)
1311#define SUSIM 0
1312#define RESIM 1
1313#define RMWUIM 2
1314#define SOFIM 3
1315
1316#define USBEI _SFR_MEM8(0xE3)
1317#define EP0I 0
1318#define EP1I 1
1319#define EP2I 2
1320#define EP3I 3
1321#define EP4I 4
1322#define EP5I 5
1323#define EP6I 6
1324#define EP7I 7
1325
1326#define USBEIM _SFR_MEM8(0xE4)
1327#define EP0IM 0
1328#define EP1IM 1
1329#define EP2IM 2
1330#define EP3IM 3
1331#define EP4IM 4
1332#define EP5IM 5
1333#define EP6IM 6
1334#define EP7IM 7
1335
1336#define USBRSTE _SFR_MEM8(0xE5)
1337#define RSTE0 0
1338#define RSTE1 1
1339#define RSTE2 2
1340#define RSTE3 3
1341#define RSTE4 4
1342#define RSTE5 5
1343#define RSTE6 6
1344#define RST7 7
1345
1346#define USBGS _SFR_MEM8(0xE6)
1347#define FAF 0
1348#define FCF 1
1349#define RMWUE 2
1350#define RSMON 3
1351
1352#define USBFA _SFR_MEM8(0xE7)
1353#define FADD0 0
1354#define FADD1 1
1355#define FADD2 2
1356#define FADD3 3
1357#define FADD4 4
1358#define FADD5 5
1359#define FADD6 6
1360
1361#define USBFN _SFR_MEM16(0xE8)
1362
1363#define USBFNL _SFR_MEM8(0xE8)
1364#define FN0 0
1365#define FN1 1
1366#define FN2 2
1367#define FN3 3
1368#define FN4 4
1369#define FN5 5
1370#define FN6 6
1371#define FN7 7
1372
1373#define USBFNH _SFR_MEM8(0xE9)
1374#define FN8 0
1375#define FN9 1
1376#define FN10 2
1377#define FNERR 3
1378#define FNEND 4
1379
1380#define USBDMACS _SFR_MEM8(0xEA)
1381#define USBDMAR 0
1382#define USBDMADIR 1
1383#define USBDMAERR 2
1384#define EPS0 4
1385#define EPS1 5
1386#define EPS2 6
1387
1388#define USBDMAD _SFR_MEM16(0xEB)
1389
1390#define USBDMADL _SFR_MEM8(0xEB)
1391#define USBDMAD0 0
1392#define USBDMAD1 1
1393#define USBDMAD2 2
1394#define USBDMAD3 3
1395#define USBDMAD4 4
1396#define USBDMAD5 5
1397#define USBDMAD6 6
1398#define USBDMAD7 7
1399
1400#define USBDMADH _SFR_MEM8(0xEC)
1401#define USBDMAD8 0
1402#define USBDMAD9 1
1403#define USBDMAD10 2
1404#define USBDMAD11 3
1405#define USBDMAD12 4
1406#define USBDMAD13 5
1407
1408#define USBDMAB _SFR_MEM8(0xED)
1409#define USBDMAB0 0
1410#define USBDMAB1 1
1411#define USBDMAB2 2
1412#define USBDMAB3 3
1413#define USBDMAB4 4
1414#define USBDMAB5 5
1415#define USBDMAB6 6
1416
1417#define DCCR _SFR_MEM8(0xEF)
1418#define DCBUSY 5
1419#define DCRDY 6
1420#define DCON 7
1421
1422#define SCICLK _SFR_MEM8(0xF0)
1423#define SCICLK0 0
1424#define SCICLK1 1
1425#define SCICLK2 2
1426#define SCICLK3 3
1427#define SCICLK4 4
1428#define SCICLK5 5
1429
1430#define SCWT0 _SFR_MEM8(0xF1)
1431#define WT0 0
1432#define WT1 1
1433#define WT2 2
1434#define WT3 3
1435#define WT4 4
1436#define WT5 5
1437#define WT6 6
1438#define WT7 7
1439
1440#define SCWT1 _SFR_MEM8(0xF2)
1441#define WT8 0
1442#define WT9 1
1443#define WT10 2
1444#define WT11 3
1445#define WT12 4
1446#define WT13 5
1447#define WT14 6
1448#define WT15 7
1449
1450#define SCWT2 _SFR_MEM8(0xF3)
1451#define WT16 0
1452#define WT17 1
1453#define WT18 2
1454#define WT19 3
1455#define WT20 4
1456#define WT21 5
1457#define WT22 6
1458#define WT23 7
1459
1460#define SCWT3 _SFR_MEM8(0xF4)
1461#define WT24 0
1462#define WT25 1
1463#define WT26 2
1464#define WT27 3
1465#define WT28 4
1466#define WT29 5
1467#define WT30 6
1468#define WT31 7
1469
1470#define SCGT _SFR_MEM16(0xF5)
1471
1472#define SCGTL _SFR_MEM8(0xF5)
1473#define GT0 0
1474#define GT1 1
1475#define GT2 2
1476#define GT3 3
1477#define GT4 4
1478#define GT5 5
1479#define GT6 6
1480#define GT7 7
1481
1482#define SCGTH _SFR_MEM8(0xF6)
1483#define GT8 0
1484
1485#define SCETU _SFR_MEM16(0xF7)
1486
1487#define SCETUL _SFR_MEM8(0xF7)
1488#define ETU0 0
1489#define ETU1 1
1490#define ETU2 2
1491#define ETU3 3
1492#define ETU4 4
1493#define ETU5 5
1494#define ETU6 6
1495#define ETU7 7
1496
1497#define SCETUH _SFR_MEM8(0xF8)
1498#define ETU8 0
1499#define ETU9 1
1500#define ETU10 2
1501#define COMP 7
1502
1503#define SCIBUF _SFR_MEM8(0xF9)
1504#define SCIBUFD0 0
1505#define SCIBUFD1 1
1506#define SCIBUFD2 2
1507#define SCIBUFD3 3
1508#define SCIBUFD4 4
1509#define SCIBUFD5 5
1510#define SCIBUFD6 6
1511#define SCIBUFD7 7
1512
1513#define SCSR _SFR_MEM8(0xFA)
1514#define CPRESRES 3
1515#define CREPSEL 4
1516#define BGTEN 6
1517
1518#define SCIER _SFR_MEM8(0xFB)
1519#define ESCPI 0
1520#define ESCRI 1
1521#define ESCTI 2
1522#define ESCWTI 3
1523#define EVCARDER 4
1524#define CARDINE 6
1525#define ESCTBI 7
1526
1527#define SCIIR _SFR_MEM8(0xFC)
1528#define SCPI 0
1529#define SCRI 1
1530#define SCTI 2
1531#define SCWTI 3
1532#define VCARDERR 4
1533#define SCTBI 7
1534
1535#define SCISR _SFR_MEM8(0xFD)
1536#define SCPE 0
1537#define SCRC 1
1538#define SCTC 2
1539#define SCWTO 3
1540#define VCARDOK 4
1541#define CARDIN 6
1542#define SCTBE 7
1543
1544#define SCCON _SFR_MEM8(0xFE)
1545#define CARDVCC 0
1546#define CARDRST 1
1547#define CARDCLK 2
1548#define CARDIO 3
1549#define CARDC4 4
1550#define CARDC8 5
1551#define CLK 7
1552
1553#define SCICR _SFR_MEM8(0xFF)
1554#define CONV 0
1555#define CREP 1
1556#define WTEN 2
1557#define UART 3
1558#define VCARD0 4
1559#define VCARD1 5
1560#define CARDDET 6
1561#define SCIRESET 7
1562
1563
1564/* Interrupt vectors */
1565/* Vector 0 is the reset vector */
1566#define INT0_vect_num  1
1567#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
1568#define INT1_vect_num  2
1569#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
1570#define INT2_vect_num  3
1571#define INT2_vect      _VECTOR(3)  /* External Interrupt Request 2 */
1572#define INT3_vect_num  4
1573#define INT3_vect      _VECTOR(4)  /* External Interrupt Request 3 */
1574#define PCINT0_vect_num  5
1575#define PCINT0_vect      _VECTOR(5)  /* Pin Change Interrupt Request 0 */
1576#define PCINT1_vect_num  6
1577#define PCINT1_vect      _VECTOR(6)  /* Pin Change Interrupt Request 1 */
1578#define PCINT2_vect_num  7
1579#define PCINT2_vect      _VECTOR(7)  /* Pin Change Interrupt Request 2 */
1580#define WDT_vect_num  8
1581#define WDT_vect      _VECTOR(8)  /* Watchdog Time-out Interrupt */
1582#define TIMER2_COMPA_vect_num  9
1583#define TIMER2_COMPA_vect      _VECTOR(9)  /* Timer/Counter2 Compare Match A */
1584#define TIMER2_COMPB_vect_num  10
1585#define TIMER2_COMPB_vect      _VECTOR(10)  /* Timer/Counter2 Compare Match B */
1586#define TIMER2_OVF_vect_num  11
1587#define TIMER2_OVF_vect      _VECTOR(11)  /* Timer/Counter2 Overflow */
1588#define TIMER1_CAPT_vect_num  12
1589#define TIMER1_CAPT_vect      _VECTOR(12)  /* Timer/Counter1 Capture Event */
1590#define TIMER1_COMPA_vect_num  13
1591#define TIMER1_COMPA_vect      _VECTOR(13)  /* Timer/Counter1 Compare Match A */
1592#define TIMER1_COMPB_vect_num  14
1593#define TIMER1_COMPB_vect      _VECTOR(14)  /* Timer/Counter1 Compare Match B */
1594#define TIMER1_OVF_vect_num  15
1595#define TIMER1_OVF_vect      _VECTOR(15)  /* Timer/Counter1 Overflow */
1596#define TIMER0_COMPA_vect_num  16
1597#define TIMER0_COMPA_vect      _VECTOR(16)  /* Timer/Counter0 Compare Match A */
1598#define TIMER0_COMPB_vect_num  17
1599#define TIMER0_COMPB_vect      _VECTOR(17)  /* Timer/Counter0 Compare Match B */
1600#define TIMER0_OVF_vect_num  18
1601#define TIMER0_OVF_vect      _VECTOR(18)  /* Timer/Counter0 Overflow */
1602#define SPI_STC_vect_num  19
1603#define SPI_STC_vect      _VECTOR(19)  /* SPI Serial Transfer Complete */
1604#define USART0_RX_vect_num  20
1605#define USART0_RX_vect      _VECTOR(20)  /* USART0, Rx Complete */
1606#define USART0_UDRE_vect_num  21
1607#define USART0_UDRE_vect      _VECTOR(21)  /* USART0 Data register Empty */
1608#define USART0_TX_vect_num  22
1609#define USART0_TX_vect      _VECTOR(22)  /* USART0, Tx Complete */
1610#define SUPPLY_MON_vect_num  23
1611#define SUPPLY_MON_vect      _VECTOR(23)  /* Supply Monitor Interruption */
1612#define RFU_vect_num  24
1613#define RFU_vect      _VECTOR(24)  /* Reserved for Future Use */
1614#define EE_READY_vect_num  25
1615#define EE_READY_vect      _VECTOR(25)  /* EEPROM Ready */
1616#define TWI_vect_num  26
1617#define TWI_vect      _VECTOR(26)  /* 2-wire Serial Interface */
1618#define SPM_READY_vect_num  27
1619#define SPM_READY_vect      _VECTOR(27)  /* Store Program Memory Read */
1620#define KEYBOARD_vect_num  28
1621#define KEYBOARD_vect      _VECTOR(28)  /* Keyboard Input Changed */
1622#define AES_Operation_vect_num  29
1623#define AES_Operation_vect      _VECTOR(29)  /* AES Block Operation Ended */
1624#define HSSPI_vect_num  30
1625#define HSSPI_vect      _VECTOR(30)  /* High-Speed SPI Interruption */
1626#define USB_Endpoint_vect_num  31
1627#define USB_Endpoint_vect      _VECTOR(31)  /* USB Endpoint Related Interruption */
1628#define USB_Protocol_vect_num  32
1629#define USB_Protocol_vect      _VECTOR(32)  /* USB Protocol Related Interruption */
1630#define SCIB_vect_num  33
1631#define SCIB_vect      _VECTOR(33)  /* Smart Card Reader Interface */
1632#define USBHost_Control_vect_num  34
1633#define USBHost_Control_vect      _VECTOR(34)  /* USB Host Controller Interrupt */
1634#define USBHost_Pipe_vect_num  35
1635#define USBHost_Pipe_vect      _VECTOR(35)  /* USB Host Pipe Interrupt */
1636#define CPRES_vect_num  36
1637#define CPRES_vect      _VECTOR(36)  /* Card Presence Detection */
1638#define PCINT3_vect_num  37
1639#define PCINT3_vect      _VECTOR(37)  /* Pin Change Interrupt Request 3 */
1640
1641#define _VECTOR_SIZE 4 /* Size of individual vector. */
1642#define _VECTORS_SIZE (38 * _VECTOR_SIZE)
1643
1644
1645/* Constants */
1646#define SPM_PAGESIZE (256)
1647#define RAMSTART     (0x100)
1648#define RAMSIZE      (4096)
1649#define RAMEND       (RAMSTART + RAMSIZE - 1)
1650#define XRAMSTART    (0x0)
1651#define XRAMSIZE     (0)
1652#define XRAMEND      (RAMEND)
1653#define E2END        (0x7FF)
1654#define E2PAGESIZE   (4)
1655#define FLASHEND     (0xFFFF)
1656
1657
1658/* Fuses */
1659#define FUSE_MEMORY_SIZE 3
1660
1661/* Low Fuse Byte */
1662#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Clock Selection */
1663#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Clock Selection */
1664#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
1665#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
1666#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
1667#define LFUSE_DEFAULT (FUSE_SUT0)
1668
1669/* High Fuse Byte */
1670#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
1671#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
1672#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
1673#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
1674#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
1675#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
1676#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
1677#define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
1678#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
1679
1680/* Extended Fuse Byte */
1681#define FUSE_BODENABLE  (unsigned char)~_BV(0)  /* Brown-out Detector Enable Signal */
1682#define EFUSE_DEFAULT (0xFF)
1683
1684
1685/* Lock Bits */
1686#define __LOCK_BITS_EXIST
1687#define __BOOT_LOCK_BITS_0_EXIST
1688#define __BOOT_LOCK_BITS_1_EXIST
1689
1690
1691/* Signature */
1692#define SIGNATURE_0 0x1E
1693#define SIGNATURE_1 0x96
1694#define SIGNATURE_2 0xC1
1695
1696
1697#endif /* _AVR_AT90SCR100_H_ */
1698
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