source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/io90scr100.h @ 4837

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1/* Copyright (c) 2009 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: io90scr100.h 1910 2009-03-04 17:45:30Z arcanum $ */
32
33/* avr/io90scr100.h - definitions for AT90SCR100 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "io90scr100.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_AT90SCR100_H_
49#define _AVR_AT90SCR100_H_ 1
50
51
52/* Registers and associated bit numbers. */
53
54#define PINA _SFR_IO8(0x00)
55#define PINA0 0
56#define PINA1 1
57#define PINA2 2
58#define PINA3 3
59#define PINA4 4
60#define PINA5 5
61#define PINA6 6
62#define PINA7 7
63
64#define DDRA _SFR_IO8(0x01)
65#define DDA0 0
66#define DDA1 1
67#define DDA2 2
68#define DDA3 3
69#define DDA4 4
70#define DDA5 5
71#define DDA6 6
72#define DDA7 7
73
74#define PORTA _SFR_IO8(0x02)
75#define PORTA0 0
76#define PORTA1 1
77#define PORTA2 2
78#define PORTA3 3
79#define PORTA4 4
80#define PORTA5 5
81#define PORTA6 6
82#define PORTA7 7
83
84#define PINB _SFR_IO8(0x03)
85#define PINB0 0
86#define PINB1 1
87#define PINB2 2
88#define PINB3 3
89#define PINB4 4
90#define PINB5 5
91#define PINB6 6
92#define PINB7 7
93
94#define DDRB _SFR_IO8(0x04)
95#define DDB0 0
96#define DDB1 1
97#define DDB2 2
98#define DDB3 3
99#define DDB4 4
100#define DDB5 5
101#define DDB6 6
102#define DDB7 7
103
104#define PORTB _SFR_IO8(0x05)
105#define PORTB0 0
106#define PORTB1 1
107#define PORTB2 2
108#define PORTB3 3
109#define PORTB4 4
110#define PORTB5 5
111#define PORTB6 6
112#define PORTB7 7
113
114#define PINC _SFR_IO8(0x06)
115#define PINC0 0
116#define PINC1 1
117#define PINC2 2
118#define PINC3 3
119#define PINC4 4
120#define PINC5 5
121#define PINC6 6
122#define PINC7 7
123
124#define DDRC _SFR_IO8(0x07)
125#define DDC0 0
126#define DDC1 1
127#define DDC2 2
128#define DDC3 3
129#define DDC4 4
130#define DDC5 5
131#define DDC6 6
132#define DDC7 7
133
134#define PORTC _SFR_IO8(0x08)
135#define PORTC0 0
136#define PORTC1 1
137#define PORTC2 2
138#define PORTC3 3
139#define PORTC4 4
140#define PORTC5 5
141#define PORTC6 6
142#define PORTC7 7
143
144#define PIND _SFR_IO8(0x09)
145#define PIND0 0
146#define PIND1 1
147#define PIND2 2
148#define PIND3 3
149#define PIND4 4
150#define PIND5 5
151#define PIND6 6
152#define PIND7 7
153
154#define DDRD _SFR_IO8(0x0A)
155#define DDD0 0
156#define DDD1 1
157#define DDD2 2
158#define DDD3 3
159#define DDD4 4
160#define DDD5 5
161#define DDD6 6
162#define DDD7 7
163
164#define PORTD _SFR_IO8(0x0B)
165#define PORTD0 0
166#define PORTD1 1
167#define PORTD2 2
168#define PORTD3 3
169#define PORTD4 4
170#define PORTD5 5
171#define PORTD6 6
172#define PORTD7 7
173
174#define PINE _SFR_IO8(0x0C)
175#define PINE0 0
176#define PINE1 1
177#define PINE2 2
178#define PINE3 3
179#define PINE4 4
180#define PINE5 5
181#define PINE6 6
182#define PINE7 7
183
184#define DDRE _SFR_IO8(0x0D)
185#define DDE0 0
186#define DDE1 1
187#define DDE2 2
188#define DDE3 3
189#define DDE4 4
190#define DDE5 5
191#define DDE6 6
192#define DDE7 7
193
194#define PORTE _SFR_IO8(0x0E)
195#define PORTE0 0
196#define PORTE1 1
197#define PORTE2 2
198#define PORTE3 3
199#define PORTE4 4
200#define PORTE5 5
201#define PORTE6 6
202#define PORTE7 7
203
204#define TIFR0 _SFR_IO8(0x15)
205#define TOV0 0
206#define OCF0A 1
207#define OCF0B 2
208
209#define TIFR1 _SFR_IO8(0x16)
210#define TOV1 0
211#define OCF1A 1
212#define OCF1B 2
213#define ICF1 5
214
215#define TIFR2 _SFR_IO8(0x17)
216#define TOV2 0
217#define OCF2A 1
218#define OCF2B 2
219
220#define EIRR _SFR_IO8(0x1A)
221#define INTD2 2
222#define INTD3 3
223
224#define PCIFR _SFR_IO8(0x1B)
225#define PCIF0 0
226#define PCIF1 1
227#define PCIF2 2
228#define PCIF3 3
229
230#define EIFR _SFR_IO8(0x1C)
231#define INTF0 0
232#define INTF1 1
233#define INTF2 2
234#define INTF3 3
235
236#define EIMSK _SFR_IO8(0x1D)
237#define INT0 0
238#define INT1 1
239#define INT2 2
240#define INT3 3
241
242#define GPIOR0 _SFR_IO8(0x1E)
243#define GPIOR00 0
244#define GPIOR01 1
245#define GPIOR02 2
246#define GPIOR03 3
247#define GPIOR04 4
248#define GPIOR05 5
249#define GPIOR06 6
250#define GPIOR07 7
251
252#define EECR _SFR_IO8(0x1F)
253#define EERE 0
254#define EEPE 1
255#define EEMPE 2
256#define EERIE 3
257#define EEPM0 4
258#define EEPM1 5
259
260#define EEDR _SFR_IO8(0x20)
261#define EEDR0 0
262#define EEDR1 1
263#define EEDR2 2
264#define EEDR3 3
265#define EEDR4 4
266#define EEDR5 5
267#define EEDR6 6
268#define EEDR7 7
269
270#define EEAR _SFR_IO16(0x21)
271
272#define EEARL _SFR_IO8(0x21)
273#define EEAR0 0
274#define EEAR1 1
275#define EEAR2 2
276#define EEAR3 3
277#define EEAR4 4
278#define EEAR5 5
279#define EEAR6 6
280#define EEAR7 7
281
282#define EEARH _SFR_IO8(0x22)
283#define EEAR8 0
284#define EEAR9 1
285#define EEAR10 2
286#define EEAR11 3
287
288#define GTCCR _SFR_IO8(0x23)
289#define PSRSYNC 0
290#define PSRASY 1
291#define TSM 7
292
293#define TCCR0A _SFR_IO8(0x24)
294#define WGM00 0
295#define WGM01 1
296#define COM0B0 4
297#define COM0B1 5
298#define COM0A0 6
299#define COM0A1 7
300
301#define TCCR0B _SFR_IO8(0x25)
302#define CS00 0
303#define CS01 1
304#define CS02 2
305#define WGM02 3
306#define FOC0B 6
307#define FOC0A 7
308
309#define TCNT0 _SFR_IO8(0x26)
310#define TCNT0_0 0
311#define TCNT0_1 1
312#define TCNT0_2 2
313#define TCNT0_3 3
314#define TCNT0_4 4
315#define TCNT0_5 5
316#define TCNT0_6 6
317#define TCNT0_7 7
318
319#define OCR0A _SFR_IO8(0x27)
320#define OCR0A_0 0
321#define OCR0A_1 1
322#define OCR0A_2 2
323#define OCR0A_3 3
324#define OCR0A_4 4
325#define OCR0A_5 5
326#define OCR0A_6 6
327#define OCR0A_7 7
328
329#define OCR0B _SFR_IO8(0x28)
330#define OCR0B_0 0
331#define OCR0B_1 1
332#define OCR0B_2 2
333#define OCR0B_3 3
334#define OCR0B_4 4
335#define OCR0B_5 5
336#define OCR0B_6 6
337#define OCR0B_7 7
338
339#define GPIOR1 _SFR_IO8(0x2A)
340#define GPIOR10 0
341#define GPIOR11 1
342#define GPIOR12 2
343#define GPIOR13 3
344#define GPIOR14 4
345#define GPIOR15 5
346#define GPIOR16 6
347#define GPIOR17 7
348
349#define GPIOR2 _SFR_IO8(0x2B)
350#define GPIOR20 0
351#define GPIOR21 1
352#define GPIOR22 2
353#define GPIOR23 3
354#define GPIOR24 4
355#define GPIOR25 5
356#define GPIOR26 6
357#define GPIOR27 7
358
359#define SPCR _SFR_IO8(0x2C)
360#define SPR0 0
361#define SPR1 1
362#define CPHA 2
363#define CPOL 3
364#define MSTR 4
365#define DORD 5
366#define SPE 6
367#define SPIE 7
368
369#define SPSR _SFR_IO8(0x2D)
370#define SPI2X 0
371#define WCOL 6
372#define SPIF 7
373
374#define SPDR _SFR_IO8(0x2E)
375#define SPDR0 0
376#define SPDR1 1
377#define SPDR2 2
378#define SPDR3 3
379#define SPDR4 4
380#define SPDR5 5
381#define SPDR6 6
382#define SPDR7 7
383
384#define OCDR _SFR_IO8(0x31)
385#define OCDR0 0
386#define OCDR1 1
387#define OCDR2 2
388#define OCDR3 3
389#define OCDR4 4
390#define OCDR5 5
391#define OCDR6 6
392#define OCDR7 7
393
394#define SMCR _SFR_IO8(0x33)
395#define SE 0
396#define SM0 1
397#define SM1 2
398#define SM2 3
399
400#define MCUSR _SFR_IO8(0x34)
401#define PORF 0
402#define EXTRF 1
403#define BORF 2
404#define WDRF 3
405#define JTRF 4
406
407#define MCUCR _SFR_IO8(0x35)
408#define IVCE 0
409#define IVSEL 1
410#define PUD 4
411#define BODSE 5
412#define BODS 6
413#define JTD 7
414
415#define SPMCSR _SFR_IO8(0x37)
416#define SPMEN 0
417#define PGERS 1
418#define PGWRT 2
419#define BLBSET 3
420#define RWWSRE 4
421#define SIGRD 5
422#define RWWSB 6
423#define SPMIE 7
424
425#define RAMPZ _SFR_IO8(0x3B)
426#define RAMPZ0 0
427
428#define WDTCSR _SFR_MEM8(0x60)
429#define WDP0 0
430#define WDP1 1
431#define WDP2 2
432#define WDE 3
433#define WDCE 4
434#define WDP3 5
435#define WDIE 6
436#define WDIF 7
437
438#define CLKPR _SFR_MEM8(0x61)
439#define CLKPS0 0
440#define CLKPS1 1
441#define CLKPS2 2
442#define CLKPS3 3
443#define CLKPCE 7
444
445#define PLLCR _SFR_MEM8(0x62)
446#define ON 0
447#define LOCK 1
448#define PLLMUX 7
449
450#define SMONCR _SFR_MEM8(0x63)
451#define SMONEN 0
452#define SMONIE 1
453#define SMONIF 4
454
455#define PRR0 _SFR_MEM8(0x64)
456#define PRUSART0 1
457#define PRSPI 2
458#define PRTIM1 3
459#define PRTIM0 5
460#define PRTIM2 6
461#define PRTWI 7
462
463#define __AVR_HAVE_PRR0 ((1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
464#define __AVR_HAVE_PRR0_PRUSART0
465#define __AVR_HAVE_PRR0_PRSPI
466#define __AVR_HAVE_PRR0_PRTIM1
467#define __AVR_HAVE_PRR0_PRTIM0
468#define __AVR_HAVE_PRR0_PRTIM2
469#define __AVR_HAVE_PRR0_PRTWI
470
471#define PRR1 _SFR_MEM8(0x65)
472#define PRUSBH 0
473#define PRUSB 1
474#define PRHSSPI 2
475#define PRSCI 3
476#define PRAES 4
477#define PRKB 5
478
479#define __AVR_HAVE_PRR1 ((1<<PRUSBH)|(1<<PRUSB)|(1<<PRHSSPI)|(1<<PRSCI)|(1<<PRAES)|(1<<PRKB))
480#define __AVR_HAVE_PRR1_PRUSBH
481#define __AVR_HAVE_PRR1_PRUSB
482#define __AVR_HAVE_PRR1_PRHSSPI
483#define __AVR_HAVE_PRR1_PRSCI
484#define __AVR_HAVE_PRR1_PRAES
485#define __AVR_HAVE_PRR1_PRKB
486
487#define OSCCAL _SFR_MEM8(0x66)
488#define CAL0 0
489#define CAL1 1
490#define CAL2 2
491#define CAL3 3
492#define CAL4 4
493#define CAL5 5
494#define CAL6 6
495#define CAL7 7
496
497#define PCICR _SFR_MEM8(0x68)
498#define PCIE0 0
499#define PCIE1 1
500#define PCIE2 2
501#define PCIE3 3
502
503#define EICRA _SFR_MEM8(0x69)
504#define ISC00 0
505#define ISC01 1
506#define ISC10 2
507#define ISC11 3
508#define ISC20 4
509#define ISC21 5
510#define ISC30 6
511#define ISC31 7
512
513#define PCMSK0 _SFR_MEM8(0x6B)
514#define PCINT0 0
515#define PCINT1 1
516#define PCINT2 2
517#define PCINT3 3
518#define PCINT4 4
519#define PCINT5 5
520#define PCINT6 6
521#define PCINT7 7
522
523#define PCMSK1 _SFR_MEM8(0x6C)
524#define PCINT8 0
525#define PCINT9 1
526#define PCINT10 2
527#define PCINT11 3
528#define PCINT12 4
529#define PCINT13 5
530#define PCINT14 6
531#define PCINT15 7
532
533#define PCMSK2 _SFR_MEM8(0x6D)
534#define PCINT16 0
535#define PCINT17 1
536#define PCINT18 2
537#define PCINT19 3
538#define PCINT20 4
539#define PCINT21 5
540#define PCINT22 6
541#define PCINT23 7
542
543#define TIMSK0 _SFR_MEM8(0x6E)
544#define TOIE0 0
545#define OCIE0A 1
546#define OCIE0B 2
547
548#define TIMSK1 _SFR_MEM8(0x6F)
549#define TOIE1 0
550#define OCIE1A 1
551#define OCIE1B 2
552#define ICIE1 5
553
554#define TIMSK2 _SFR_MEM8(0x70)
555#define TOIE2 0
556#define OCIE2A 1
557#define OCIE2B 2
558
559#define PCMSK3 _SFR_MEM8(0x73)
560
561#define LEDCR _SFR_MEM8(0x75)
562#define LED00 0
563#define LED01 1
564#define LED10 2
565#define LED11 3
566#define LED20 4
567#define LED21 5
568#define lED30 6
569#define LED31 7
570
571#define AESCR _SFR_MEM8(0x78)
572#define AESGO 0
573#define ENCRYPT 1
574#define KS 3
575#define KEYGN 4
576#define AUTOKEY 5
577#define AESIF 6
578#define AESIE 7
579
580#define AESACR _SFR_MEM8(0x79)
581#define KD 0
582#define AUTOINC 1
583#define MANINC 2
584#define XOR 3
585
586#define AESADDR _SFR_MEM8(0x7A)
587#define ADDR0 0
588#define ADDR1 1
589#define ADDR2 2
590#define ADDR3 3
591#define ADDR4 4
592#define ADDR5 5
593#define ADDR6 6
594#define ADDR7 7
595
596#define AESDR _SFR_MEM8(0x7B)
597#define DATA0 0
598#define DATA1 1
599#define DATA2 2
600#define DATA3 3
601#define DATA4 4
602#define DATA5 5
603#define DATA6 6
604#define DATA7 7
605
606#define TCCR1A _SFR_MEM8(0x80)
607#define WGM10 0
608#define WGM11 1
609#define COM1B0 4
610#define COM1B1 5
611#define COM1A0 6
612#define COM1A1 7
613
614#define TCCR1B _SFR_MEM8(0x81)
615#define CS10 0
616#define CS11 1
617#define CS12 2
618#define WGM12 3
619#define WGM13 4
620#define ICES1 6
621#define ICNC1 7
622
623#define TCCR1C _SFR_MEM8(0x82)
624#define FOC1B 6
625#define FOC1A 7
626
627#define TCNT1 _SFR_MEM16(0x84)
628
629#define TCNT1L _SFR_MEM8(0x84)
630#define TCNT1L0 0
631#define TCNT1L1 1
632#define TCNT1L2 2
633#define TCNT1L3 3
634#define TCNT1L4 4
635#define TCNT1L5 5
636#define TCNT1L6 6
637#define TCNT1L7 7
638
639#define TCNT1H _SFR_MEM8(0x85)
640#define TCNT1H0 0
641#define TCNT1H1 1
642#define TCNT1H2 2
643#define TCNT1H3 3
644#define TCNT1H4 4
645#define TCNT1H5 5
646#define TCNT1H6 6
647#define TCNT1H7 7
648
649#define ICR1 _SFR_MEM16(0x86)
650
651#define ICR1L _SFR_MEM8(0x86)
652#define ICR1L0 0
653#define ICR1L1 1
654#define ICR1L2 2
655#define ICR1L3 3
656#define ICR1L4 4
657#define ICR1L5 5
658#define ICR1L6 6
659#define ICR1L7 7
660
661#define ICR1H _SFR_MEM8(0x87)
662#define ICR1H0 0
663#define ICR1H1 1
664#define ICR1H2 2
665#define ICR1H3 3
666#define ICR1H4 4
667#define ICR1H5 5
668#define ICR1H6 6
669#define ICR1H7 7
670
671#define OCR1A _SFR_MEM16(0x88)
672
673#define OCR1AL _SFR_MEM8(0x88)
674#define OCR1AL0 0
675#define OCR1AL1 1
676#define OCR1AL2 2
677#define OCR1AL3 3
678#define OCR1AL4 4
679#define OCR1AL5 5
680#define OCR1AL6 6
681#define OCR1AL7 7
682
683#define OCR1AH _SFR_MEM8(0x89)
684#define OCR1AH0 0
685#define OCR1AH1 1
686#define OCR1AH2 2
687#define OCR1AH3 3
688#define OCR1AH4 4
689#define OCR1AH5 5
690#define OCR1AH6 6
691#define OCR1AH7 7
692
693#define OCR1B _SFR_MEM16(0x8A)
694
695#define OCR1BL _SFR_MEM8(0x8A)
696#define OCR1BL0 0
697#define OCR1BL1 1
698#define OCR1BL2 2
699#define OCR1BL3 3
700#define OCR1BL4 4
701#define OCR1BL5 5
702#define OCR1BL6 6
703#define OCR1BL7 7
704
705#define OCR1BH _SFR_MEM8(0x8B)
706#define OCR1BH0 0
707#define OCR1BH1 1
708#define OCR1BH2 2
709#define OCR1BH3 3
710#define OCR1BH4 4
711#define OCR1BH5 5
712#define OCR1BH6 6
713#define OCR1BH7 7
714
715#define KBLSR _SFR_MEM8(0x8D)
716#define KBLS0 0
717#define KBLS1 1
718#define KBLS2 2
719#define KBLS3 3
720#define KBLS4 4
721#define KBLS5 5
722#define KBLS6 6
723#define KBLS7 7
724
725#define KBER _SFR_MEM8(0x8E)
726#define KBE0 0
727#define KBE1 1
728#define KBE2 2
729#define KBE3 3
730#define KBE4 4
731#define KBE5 5
732#define KBE6 6
733#define KBE7 7
734
735#define KBFR _SFR_MEM8(0x8F)
736#define KBF0 0
737#define KBF1 1
738#define KBF2 2
739#define KBF3 3
740#define KBF4 4
741#define KBF5 5
742#define KBF6 6
743#define KBF7 7
744
745#define RDWDR _SFR_MEM8(0x90)
746#define RDD0 0
747#define RDD1 1
748#define RDD2 2
749#define RDD3 3
750#define RDD4 4
751#define RDD5 5
752#define RDD6 6
753#define RDD7 7
754
755#define LFSR0 _SFR_MEM8(0x91)
756#define LFSD0 0
757#define LFSD1 1
758#define LFSD2 2
759#define LFSD3 3
760#define LFSD4 4
761#define LFSD5 5
762#define LFSD6 6
763#define LFSD7 7
764
765#define LFSR1 _SFR_MEM8(0x92)
766#define LFSD8 0
767#define LFSD9 1
768#define LFSD10 2
769#define LFSD11 3
770#define LFSD12 4
771#define LFSD13 5
772#define LFSD14 6
773#define LFSD15 7
774
775#define LFSR2 _SFR_MEM8(0x93)
776#define LFSD16 0
777#define LFSD17 1
778#define LFSD18 2
779#define LFSD19 3
780#define LFSD20 4
781#define LFSD21 5
782#define LFSD22 6
783#define LFSD23 7
784
785#define LFSR3 _SFR_MEM8(0x94)
786#define LFSD24 0
787#define LFSD25 1
788#define LFSD26 2
789#define LFSD27 3
790#define LFSD28 4
791#define LFSD29 5
792#define LFSD30 6
793#define LFSD31 7
794
795#define RNGCR _SFR_MEM8(0x95)
796#define ROSCE 0
797
798#define UHSR _SFR_MEM8(0x99)
799#define SPEED 3
800
801#define UPINT _SFR_MEM8(0x9A)
802#define PINT0 0
803#define PINT1 1
804#define PINT2 2
805#define PINT3 3
806
807#define UPBCX _SFR_MEM16(0x9B)
808
809#define UPBCXL _SFR_MEM8(0x9B)
810#define PBYTCT0 0
811#define PBYTCT1 1
812#define PBYTCT2 2
813#define PBYTCT3 3
814#define PBYTCT4 4
815#define PBYTCT5 5
816#define PBYTCT6 6
817#define PBYTCT7 7
818
819#define UPBCXH _SFR_MEM8(0x9C)
820#define PBYTCT8 0
821#define PBYTCT9 1
822#define PBYTCT10 2
823
824#define UPERRX _SFR_MEM8(0x9D)
825#define DATATGL 0
826#define DATAPID 1
827#define PID 2
828#define PTIMEOUT 3
829#define CRC16 4
830#define COUNTER0 5
831#define COUNTER1 6
832
833#define UHCR _SFR_MEM8(0x9E)
834#define SOFEN 0
835#define RESET 1
836#define RESUME 2
837#define FRZCLK 4
838#define PAD0 5
839#define PAD1 6
840#define UHEN 7
841
842#define UHINT _SFR_MEM8(0x9F)
843#define DCONNI 0
844#define DDISCI 1
845#define RSTI 2
846#define RSMEDI 3
847#define RXRSMI 4
848#define HSOFI 5
849#define HWUPI 6
850
851#define UHIEN _SFR_MEM8(0xA0)
852#define DCONNE 0
853#define DDISCE 1
854#define RSTE 2
855#define RSMEDE 3
856#define RXRSME 4
857#define HSOFE 5
858#define HWUPE 6
859
860#define UHADDR _SFR_MEM8(0xA1)
861#define HADDR0 0
862#define HADDR1 1
863#define HADDR2 2
864#define HADDR3 3
865#define HADDR4 4
866#define HADDR5 5
867#define HADDR6 6
868
869#define UHFNUM _SFR_MEM16(0xA2)
870
871#define UHFNUML _SFR_MEM8(0xA2)
872#define FNUM0 0
873#define FNUM1 1
874#define FNUM2 2
875#define FNUM3 3
876#define FNUM4 4
877#define FNUM5 5
878#define FNUM6 6
879#define FNUM7 7
880
881#define UHFNUMH _SFR_MEM8(0xA3)
882#define FNUM8 0
883#define FNUM9 1
884#define FNUM10 2
885
886#define UHFLEN _SFR_MEM8(0xA4)
887#define FLEN0 0
888#define FLEN1 1
889#define FLEN2 2
890#define FLEN3 3
891#define FLEN4 4
892#define FLEN5 5
893#define FLEN6 6
894#define FLEN7 7
895
896#define UPINRQX _SFR_MEM8(0xA5)
897#define INRQ0 0
898#define INRQ1 1
899#define INRQ2 2
900#define INRQ3 3
901#define INRQ4 4
902#define INRQ5 5
903#define INRQ6 6
904#define INRQ7 7
905
906#define UPINTX _SFR_MEM8(0xA6)
907#define RXINI 0
908#define RXSTALLI 1
909#define TXOUTI 2
910#define TXSTPI 3
911#define PERRI 4
912#define RWAL 5
913#define NAKEDI 6
914#define FIFOCON 7
915
916#define UPNUM _SFR_MEM8(0xA7)
917#define PNUM0 0
918#define PNUM1 1
919
920#define UPRST _SFR_MEM8(0xA8)
921#define P0RST 0
922#define P1RST 1
923#define P2RST 2
924#define P3RST 3
925
926#define UPCRX _SFR_MEM8(0xA9)
927#define PEN 0
928#define RSTDT 3
929#define INMODE 5
930#define PFREEZE 6
931
932#define UPCFG0X _SFR_MEM8(0xAA)
933#define PEPNUM0 0
934#define PEPNUM1 1
935#define PEPNUM2 2
936#define PEPNUM3 3
937#define PTOKEN0 4
938#define PTOKEN1 5
939#define PTYPE0 6
940#define PTYPE1 7
941
942#define UPCFG1X _SFR_MEM8(0xAB)
943#define ALLOC 1
944#define PBK0 2
945#define PBK1 3
946#define PSIZE0 4
947#define PSIZE1 5
948#define PSIZE2 6
949
950#define UPSTAX _SFR_MEM8(0xAC)
951#define NBUSYBK0 0
952#define NBUSYBK1 1
953#define DTSEQ0 2
954#define DTSEQ1 3
955#define UNDERFI 5
956#define OVERFI 6
957#define CFGOK 7
958
959#define UPCFG2X _SFR_MEM8(0xAD)
960#define INTFRQ0 0
961#define INTFRQ1 1
962#define INTFRQ2 2
963#define INTFRQ3 3
964#define INTFRQ4 4
965#define INTFRQ5 5
966#define INTFRQ6 6
967#define INTFRQ7 7
968
969#define UPIENX _SFR_MEM8(0xAE)
970#define RXINE 0
971#define RXSTALLE 1
972#define TXOUTE 2
973#define TXSTPE 3
974#define PERRE 4
975#define NAKEDE 6
976#define FLERRE 7
977
978#define UPDATX _SFR_MEM8(0xAF)
979#define PDAT0 0
980#define PDAT1 1
981#define PDAT2 2
982#define PDAT3 3
983#define PDAT4 4
984#define PDAT5 5
985#define PDAT6 6
986#define PDAT7 7
987
988#define TCCR2A _SFR_MEM8(0xB0)
989#define WGM20 0
990#define WGM21 1
991#define COM2B0 4
992#define COM2B1 5
993#define COM2A0 6
994#define COM2A1 7
995
996#define TCCR2B _SFR_MEM8(0xB1)
997#define CS20 0
998#define CS21 1
999#define CS22 2
1000#define WGM22 3
1001#define FOC2B 6
1002#define FOC2A 7
1003
1004#define TCNT2 _SFR_MEM8(0xB2)
1005#define TCNT2_0 0
1006#define TCNT2_1 1
1007#define TCNT2_2 2
1008#define TCNT2_3 3
1009#define TCNT2_4 4
1010#define TCNT2_5 5
1011#define TCNT2_6 6
1012#define TCNT2_7 7
1013
1014#define OCR2A _SFR_MEM8(0xB3)
1015#define OCR2A0 0
1016#define OCR2A1 1
1017#define OCR2A2 2
1018#define OCR2A3 3
1019#define OCR2A4 4
1020#define OCR2A5 5
1021#define OCR2A6 6
1022#define OCR2A7 7
1023
1024#define OCR2B _SFR_MEM8(0xB4)
1025#define OCR2B0 0
1026#define OCR2B1 1
1027#define OCR2B2 2
1028#define OCR2B3 3
1029#define OCR2B4 4
1030#define OCR2B5 5
1031#define OCR2B6 6
1032#define OCR2B7 7
1033
1034#define ASSR _SFR_MEM8(0xB6)
1035#define TCR2BUB 0
1036#define TCR2AUB 1
1037#define OCR2BUB 2
1038#define OCR2AUB 3
1039#define TCN2UB 4
1040#define AS2 5
1041#define EXCLK 6
1042
1043#define TWBR _SFR_MEM8(0xB8)
1044#define TWBR0 0
1045#define TWBR1 1
1046#define TWBR2 2
1047#define TWBR3 3
1048#define TWBR4 4
1049#define TWBR5 5
1050#define TWBR6 6
1051#define TWBR7 7
1052
1053#define TWSR _SFR_MEM8(0xB9)
1054#define TWPS0 0
1055#define TWPS1 1
1056#define TWS3 3
1057#define TWS4 4
1058#define TWS5 5
1059#define TWS6 6
1060#define TWS7 7
1061
1062#define TWAR _SFR_MEM8(0xBA)
1063#define TWGCE 0
1064#define TWA0 1
1065#define TWA1 2
1066#define TWA2 3
1067#define TWA3 4
1068#define TWA4 5
1069#define TWA5 6
1070#define TWA6 7
1071
1072#define TWDR _SFR_MEM8(0xBB)
1073#define TWD0 0
1074#define TWD1 1
1075#define TWD2 2
1076#define TWD3 3
1077#define TWD4 4
1078#define TWD5 5
1079#define TWD6 6
1080#define TWD7 7
1081
1082#define TWCR _SFR_MEM8(0xBC)
1083#define TWIE 0
1084#define TWEN 2
1085#define TWWC 3
1086#define TWSTO 4
1087#define TWSTA 5
1088#define TWEA 6
1089#define TWINT 7
1090
1091#define TWAMR _SFR_MEM8(0xBD)
1092#define TWAM0 1
1093#define TWAM1 2
1094#define TWAM2 3
1095#define TWAM3 4
1096#define TWAM4 5
1097#define TWAM5 6
1098#define TWAM6 7
1099
1100#define UCSR0A _SFR_MEM8(0xC0)
1101#define MPCM0 0
1102#define U2X0 1
1103#define UPE0 2
1104#define DOR0 3
1105#define FE0 4
1106#define UDRE0 5
1107#define TXC0 6
1108#define RXC0 7
1109
1110#define UCSR0B _SFR_MEM8(0xC1)
1111#define TXB80 0
1112#define RXB80 1
1113#define UCSZ02 2
1114#define TXEN0 3
1115#define RXEN0 4
1116#define UDRIE0 5
1117#define TXCIE0 6
1118#define RXCIE0 7
1119
1120#define UCSR0C _SFR_MEM8(0xC2)
1121#define UCPOL0 0
1122#define UCSZ00 1
1123#define UCSZ01 2
1124#define USBS0 3
1125#define UPM00 4
1126#define UPM01 5
1127#define UMSEL00 6
1128#define UMSEL01 7
1129
1130#define UBRR0 _SFR_MEM16(0xC4)
1131
1132#define UBRR0L _SFR_MEM8(0xC4)
1133#define UBRR00 0
1134#define UBRR01 1
1135#define UBRR02 2
1136#define UBRR03 3
1137#define UBRR04 4
1138#define UBRR05 5
1139#define UBRR06 6
1140#define UBRR07 7
1141
1142#define UBRR0H _SFR_MEM8(0xC5)
1143#define UBRR08 0
1144#define UBRR09 1
1145#define UBRR010 2
1146#define UBRR011 3
1147
1148#define UDR0 _SFR_MEM8(0xC6)
1149#define UDR00 0
1150#define UDR01 1
1151#define UDR02 2
1152#define UDR03 3
1153#define UDR04 4
1154#define UDR05 5
1155#define UDR06 6
1156#define UDR07 7
1157
1158#define USBENUM _SFR_MEM8(0xCA)
1159#define USBENUM0 0
1160#define USBENUM1 1
1161#define USBENUM2 2
1162
1163#define USBCSEX _SFR_MEM8(0xCB)
1164#define TXC 0
1165#define RCVD 1
1166#define RXSETUP 2
1167#define STSENT 3
1168#define TXPB 4
1169#define FSTALL 5
1170#define IERR 6
1171
1172#define USBDBCEX _SFR_MEM8(0xCC)
1173#define BCT0 0
1174#define BCT1 1
1175#define BCT2 2
1176#define BCT3 3
1177#define BCT4 4
1178#define BCT5 5
1179#define BCT6 6
1180#define BCT7 7
1181
1182#define USBFCEX _SFR_MEM8(0xCD)
1183#define EPTYP0 0
1184#define EPTYP1 1
1185#define EPDIR 2
1186#define EPE 7
1187
1188#define HSSPITO _SFR_MEM16(0xD1)
1189
1190#define HSSPITOL _SFR_MEM8(0xD1)
1191#define HSSPITOD0 0
1192#define HSSPITOD1 1
1193#define HSSPITOD2 2
1194#define HSSPITOD3 3
1195#define HSSPITOD4 4
1196#define HSSPITOD5 5
1197#define HSSPITOD6 6
1198#define HSSPITOD7 7
1199
1200#define HSSPITOH _SFR_MEM8(0xD2)
1201#define HSSPITOD8 0
1202#define HSSPITOD9 1
1203#define HSSPITOD10 2
1204#define HSSPITOD11 3
1205#define HSSPITOD12 4
1206#define HSSPITOD13 5
1207#define HSSPITOD14 6
1208#define HSSPITOD15 7
1209
1210#define HSSPICNT _SFR_MEM8(0xD3)
1211#define HSSPICNTD0 0
1212#define HSSPICNTD1 1
1213#define HSSPICNTD2 2
1214#define HSSPICNTD3 3
1215#define HSSPICNTD4 4
1216
1217#define HSSPIIER _SFR_MEM8(0xD4)
1218#define NSSIE 4
1219#define RCVOFIE 5
1220#define BTDIE 6
1221#define TIMEOUTIE 7
1222
1223#define HSSPIGTR _SFR_MEM8(0xD5)
1224#define HSSPIGTD0 0
1225#define HSSPIGTD1 1
1226#define HSSPIGTD2 2
1227#define HSSPIGTD3 3
1228#define HSSPIGTD4 4
1229#define HSSPIGTD5 5
1230#define HSSPIGTD6 6
1231#define HSSPIGTD7 7
1232
1233#define HSSPIRDR _SFR_MEM8(0xD6)
1234#define HSSPIRDD0 0
1235#define HSSPIRDD1 1
1236#define HSSPIRDD2 2
1237#define HSSPIRDD3 3
1238#define HSSPIRDD4 4
1239#define HSSPIRDD5 5
1240#define HSSPIRDD6 6
1241#define HSSPIRDD7 7
1242
1243#define HSSPITDR _SFR_MEM8(0xD7)
1244#define HSSPITDD0 0
1245#define HSSPITDD1 1
1246#define HSSPITDD2 2
1247#define HSSPITDD3 3
1248#define HSSPITDD4 4
1249#define HSSPITDD5 5
1250#define HSSPITDD6 6
1251#define HSSPITDD7 7
1252
1253#define HSSPISR _SFR_MEM8(0xD8)
1254#define SPICKRDY 0
1255#define TXBUFE 1
1256#define RXBUFF 2
1257#define NSS 3
1258#define DPRAMRDY 4
1259
1260#define HSSPICFG _SFR_MEM8(0xD9)
1261#define HSSPIEN 0
1262#define HSMSTR 1
1263#define HSCPOL 2
1264#define HSCPHA 3
1265#define DPRAM 4
1266#define SPICKDIV0 5
1267#define SPICKDIV1 6
1268#define SPICKDIV2 7
1269
1270#define HSSPIIR _SFR_MEM8(0xDA)
1271#define NSSFE 3
1272#define NSSRE 4
1273#define RCVOF 5
1274#define BTD 6
1275#define TIMEOUT 7
1276
1277#define HSSPICR _SFR_MEM8(0xDB)
1278#define CS 0
1279#define RETTO 1
1280#define STTTO 2
1281
1282#define HSSPIDMACS _SFR_MEM8(0xDC)
1283#define HSSPIDMAR 0
1284#define HSSPIDMADIR 1
1285#define HSSPIDMAERR 2
1286
1287#define HSSPIDMAD _SFR_MEM16(0xDD)
1288
1289#define HSSPIDMADL _SFR_MEM8(0xDD)
1290#define HSSPIDMAD0 0
1291#define HSSPIDMAD1 1
1292#define HSSPIDMAD2 2
1293#define HSSPIDMAD3 3
1294#define HSSPIDMAD4 4
1295#define HSSPIDMAD5 5
1296#define HSSPIDMAD6 6
1297#define HSSPIDMAD7 7
1298
1299#define HSSPIDMADH _SFR_MEM8(0xDE)
1300#define HSSPIDMAD8 0
1301#define HSSPIDMAD9 1
1302#define HSSPIDMAD10 2
1303#define HSSPIDMAD11 3
1304#define HSSPIDMAD12 4
1305#define HSSPIDMAD13 5
1306
1307#define HSSPIDMAB _SFR_MEM8(0xDF)
1308#define HSSPIDMAB0 0
1309#define HSSPIDMAB1 1
1310#define HSSPIDMAB2 2
1311#define HSSPIDMAB3 3
1312#define HSSPIDMAB4 4
1313
1314#define USBCR _SFR_MEM8(0xE0)
1315#define USBE 1
1316#define UPUC 5
1317#define URMWU 7
1318
1319#define USBPI _SFR_MEM8(0xE1)
1320#define SUSI 0
1321#define RESI 1
1322#define RMWUI 2
1323#define SOFI 3
1324#define FEURI 4
1325
1326#define USBPIM _SFR_MEM8(0xE2)
1327#define SUSIM 0
1328#define RESIM 1
1329#define RMWUIM 2
1330#define SOFIM 3
1331
1332#define USBEI _SFR_MEM8(0xE3)
1333#define EP0I 0
1334#define EP1I 1
1335#define EP2I 2
1336#define EP3I 3
1337#define EP4I 4
1338#define EP5I 5
1339#define EP6I 6
1340#define EP7I 7
1341
1342#define USBEIM _SFR_MEM8(0xE4)
1343#define EP0IM 0
1344#define EP1IM 1
1345#define EP2IM 2
1346#define EP3IM 3
1347#define EP4IM 4
1348#define EP5IM 5
1349#define EP6IM 6
1350#define EP7IM 7
1351
1352#define USBRSTE _SFR_MEM8(0xE5)
1353#define RSTE0 0
1354#define RSTE1 1
1355#define RSTE2 2
1356#define RSTE3 3
1357#define RSTE4 4
1358#define RSTE5 5
1359#define RSTE6 6
1360#define RST7 7
1361
1362#define USBGS _SFR_MEM8(0xE6)
1363#define FAF 0
1364#define FCF 1
1365#define RMWUE 2
1366#define RSMON 3
1367
1368#define USBFA _SFR_MEM8(0xE7)
1369#define FADD0 0
1370#define FADD1 1
1371#define FADD2 2
1372#define FADD3 3
1373#define FADD4 4
1374#define FADD5 5
1375#define FADD6 6
1376
1377#define USBFN _SFR_MEM16(0xE8)
1378
1379#define USBFNL _SFR_MEM8(0xE8)
1380#define FN0 0
1381#define FN1 1
1382#define FN2 2
1383#define FN3 3
1384#define FN4 4
1385#define FN5 5
1386#define FN6 6
1387#define FN7 7
1388
1389#define USBFNH _SFR_MEM8(0xE9)
1390#define FN8 0
1391#define FN9 1
1392#define FN10 2
1393#define FNERR 3
1394#define FNEND 4
1395
1396#define USBDMACS _SFR_MEM8(0xEA)
1397#define USBDMAR 0
1398#define USBDMADIR 1
1399#define USBDMAERR 2
1400#define EPS0 4
1401#define EPS1 5
1402#define EPS2 6
1403
1404#define USBDMAD _SFR_MEM16(0xEB)
1405
1406#define USBDMADL _SFR_MEM8(0xEB)
1407#define USBDMAD0 0
1408#define USBDMAD1 1
1409#define USBDMAD2 2
1410#define USBDMAD3 3
1411#define USBDMAD4 4
1412#define USBDMAD5 5
1413#define USBDMAD6 6
1414#define USBDMAD7 7
1415
1416#define USBDMADH _SFR_MEM8(0xEC)
1417#define USBDMAD8 0
1418#define USBDMAD9 1
1419#define USBDMAD10 2
1420#define USBDMAD11 3
1421#define USBDMAD12 4
1422#define USBDMAD13 5
1423
1424#define USBDMAB _SFR_MEM8(0xED)
1425#define USBDMAB0 0
1426#define USBDMAB1 1
1427#define USBDMAB2 2
1428#define USBDMAB3 3
1429#define USBDMAB4 4
1430#define USBDMAB5 5
1431#define USBDMAB6 6
1432
1433#define DCCR _SFR_MEM8(0xEF)
1434#define DCBUSY 5
1435#define DCRDY 6
1436#define DCON 7
1437
1438#define SCICLK _SFR_MEM8(0xF0)
1439#define SCICLK0 0
1440#define SCICLK1 1
1441#define SCICLK2 2
1442#define SCICLK3 3
1443#define SCICLK4 4
1444#define SCICLK5 5
1445
1446#define SCWT0 _SFR_MEM8(0xF1)
1447#define WT0 0
1448#define WT1 1
1449#define WT2 2
1450#define WT3 3
1451#define WT4 4
1452#define WT5 5
1453#define WT6 6
1454#define WT7 7
1455
1456#define SCWT1 _SFR_MEM8(0xF2)
1457#define WT8 0
1458#define WT9 1
1459#define WT10 2
1460#define WT11 3
1461#define WT12 4
1462#define WT13 5
1463#define WT14 6
1464#define WT15 7
1465
1466#define SCWT2 _SFR_MEM8(0xF3)
1467#define WT16 0
1468#define WT17 1
1469#define WT18 2
1470#define WT19 3
1471#define WT20 4
1472#define WT21 5
1473#define WT22 6
1474#define WT23 7
1475
1476#define SCWT3 _SFR_MEM8(0xF4)
1477#define WT24 0
1478#define WT25 1
1479#define WT26 2
1480#define WT27 3
1481#define WT28 4
1482#define WT29 5
1483#define WT30 6
1484#define WT31 7
1485
1486#define SCGT _SFR_MEM16(0xF5)
1487
1488#define SCGTL _SFR_MEM8(0xF5)
1489#define GT0 0
1490#define GT1 1
1491#define GT2 2
1492#define GT3 3
1493#define GT4 4
1494#define GT5 5
1495#define GT6 6
1496#define GT7 7
1497
1498#define SCGTH _SFR_MEM8(0xF6)
1499#define GT8 0
1500
1501#define SCETU _SFR_MEM16(0xF7)
1502
1503#define SCETUL _SFR_MEM8(0xF7)
1504#define ETU0 0
1505#define ETU1 1
1506#define ETU2 2
1507#define ETU3 3
1508#define ETU4 4
1509#define ETU5 5
1510#define ETU6 6
1511#define ETU7 7
1512
1513#define SCETUH _SFR_MEM8(0xF8)
1514#define ETU8 0
1515#define ETU9 1
1516#define ETU10 2
1517#define COMP 7
1518
1519#define SCIBUF _SFR_MEM8(0xF9)
1520#define SCIBUFD0 0
1521#define SCIBUFD1 1
1522#define SCIBUFD2 2
1523#define SCIBUFD3 3
1524#define SCIBUFD4 4
1525#define SCIBUFD5 5
1526#define SCIBUFD6 6
1527#define SCIBUFD7 7
1528
1529#define SCSR _SFR_MEM8(0xFA)
1530#define CPRESRES 3
1531#define CREPSEL 4
1532#define BGTEN 6
1533
1534#define SCIER _SFR_MEM8(0xFB)
1535#define ESCPI 0
1536#define ESCRI 1
1537#define ESCTI 2
1538#define ESCWTI 3
1539#define EVCARDER 4
1540#define CARDINE 6
1541#define ESCTBI 7
1542
1543#define SCIIR _SFR_MEM8(0xFC)
1544#define SCPI 0
1545#define SCRI 1
1546#define SCTI 2
1547#define SCWTI 3
1548#define VCARDERR 4
1549#define SCTBI 7
1550
1551#define SCISR _SFR_MEM8(0xFD)
1552#define SCPE 0
1553#define SCRC 1
1554#define SCTC 2
1555#define SCWTO 3
1556#define VCARDOK 4
1557#define CARDIN 6
1558#define SCTBE 7
1559
1560#define SCCON _SFR_MEM8(0xFE)
1561#define CARDVCC 0
1562#define CARDRST 1
1563#define CARDCLK 2
1564#define CARDIO 3
1565#define CARDC4 4
1566#define CARDC8 5
1567#define CLK 7
1568
1569#define SCICR _SFR_MEM8(0xFF)
1570#define CONV 0
1571#define CREP 1
1572#define WTEN 2
1573#define UART 3
1574#define VCARD0 4
1575#define VCARD1 5
1576#define CARDDET 6
1577#define SCIRESET 7
1578
1579
1580/* Interrupt vectors */
1581/* Vector 0 is the reset vector */
1582#define INT0_vect_num  1
1583#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
1584#define INT1_vect_num  2
1585#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
1586#define INT2_vect_num  3
1587#define INT2_vect      _VECTOR(3)  /* External Interrupt Request 2 */
1588#define INT3_vect_num  4
1589#define INT3_vect      _VECTOR(4)  /* External Interrupt Request 3 */
1590#define PCINT0_vect_num  5
1591#define PCINT0_vect      _VECTOR(5)  /* Pin Change Interrupt Request 0 */
1592#define PCINT1_vect_num  6
1593#define PCINT1_vect      _VECTOR(6)  /* Pin Change Interrupt Request 1 */
1594#define PCINT2_vect_num  7
1595#define PCINT2_vect      _VECTOR(7)  /* Pin Change Interrupt Request 2 */
1596#define WDT_vect_num  8
1597#define WDT_vect      _VECTOR(8)  /* Watchdog Time-out Interrupt */
1598#define TIMER2_COMPA_vect_num  9
1599#define TIMER2_COMPA_vect      _VECTOR(9)  /* Timer/Counter2 Compare Match A */
1600#define TIMER2_COMPB_vect_num  10
1601#define TIMER2_COMPB_vect      _VECTOR(10)  /* Timer/Counter2 Compare Match B */
1602#define TIMER2_OVF_vect_num  11
1603#define TIMER2_OVF_vect      _VECTOR(11)  /* Timer/Counter2 Overflow */
1604#define TIMER1_CAPT_vect_num  12
1605#define TIMER1_CAPT_vect      _VECTOR(12)  /* Timer/Counter1 Capture Event */
1606#define TIMER1_COMPA_vect_num  13
1607#define TIMER1_COMPA_vect      _VECTOR(13)  /* Timer/Counter1 Compare Match A */
1608#define TIMER1_COMPB_vect_num  14
1609#define TIMER1_COMPB_vect      _VECTOR(14)  /* Timer/Counter1 Compare Match B */
1610#define TIMER1_OVF_vect_num  15
1611#define TIMER1_OVF_vect      _VECTOR(15)  /* Timer/Counter1 Overflow */
1612#define TIMER0_COMPA_vect_num  16
1613#define TIMER0_COMPA_vect      _VECTOR(16)  /* Timer/Counter0 Compare Match A */
1614#define TIMER0_COMPB_vect_num  17
1615#define TIMER0_COMPB_vect      _VECTOR(17)  /* Timer/Counter0 Compare Match B */
1616#define TIMER0_OVF_vect_num  18
1617#define TIMER0_OVF_vect      _VECTOR(18)  /* Timer/Counter0 Overflow */
1618#define SPI_STC_vect_num  19
1619#define SPI_STC_vect      _VECTOR(19)  /* SPI Serial Transfer Complete */
1620#define USART0_RX_vect_num  20
1621#define USART0_RX_vect      _VECTOR(20)  /* USART0, Rx Complete */
1622#define USART0_UDRE_vect_num  21
1623#define USART0_UDRE_vect      _VECTOR(21)  /* USART0 Data register Empty */
1624#define USART0_TX_vect_num  22
1625#define USART0_TX_vect      _VECTOR(22)  /* USART0, Tx Complete */
1626#define SUPPLY_MON_vect_num  23
1627#define SUPPLY_MON_vect      _VECTOR(23)  /* Supply Monitor Interruption */
1628#define RFU_vect_num  24
1629#define RFU_vect      _VECTOR(24)  /* Reserved for Future Use */
1630#define EE_READY_vect_num  25
1631#define EE_READY_vect      _VECTOR(25)  /* EEPROM Ready */
1632#define TWI_vect_num  26
1633#define TWI_vect      _VECTOR(26)  /* 2-wire Serial Interface */
1634#define SPM_READY_vect_num  27
1635#define SPM_READY_vect      _VECTOR(27)  /* Store Program Memory Read */
1636#define KEYBOARD_vect_num  28
1637#define KEYBOARD_vect      _VECTOR(28)  /* Keyboard Input Changed */
1638#define AES_Operation_vect_num  29
1639#define AES_Operation_vect      _VECTOR(29)  /* AES Block Operation Ended */
1640#define HSSPI_vect_num  30
1641#define HSSPI_vect      _VECTOR(30)  /* High-Speed SPI Interruption */
1642#define USB_Endpoint_vect_num  31
1643#define USB_Endpoint_vect      _VECTOR(31)  /* USB Endpoint Related Interruption */
1644#define USB_Protocol_vect_num  32
1645#define USB_Protocol_vect      _VECTOR(32)  /* USB Protocol Related Interruption */
1646#define SCIB_vect_num  33
1647#define SCIB_vect      _VECTOR(33)  /* Smart Card Reader Interface */
1648#define USBHost_Control_vect_num  34
1649#define USBHost_Control_vect      _VECTOR(34)  /* USB Host Controller Interrupt */
1650#define USBHost_Pipe_vect_num  35
1651#define USBHost_Pipe_vect      _VECTOR(35)  /* USB Host Pipe Interrupt */
1652#define CPRES_vect_num  36
1653#define CPRES_vect      _VECTOR(36)  /* Card Presence Detection */
1654#define PCINT3_vect_num  37
1655#define PCINT3_vect      _VECTOR(37)  /* Pin Change Interrupt Request 3 */
1656
1657#define _VECTOR_SIZE 4 /* Size of individual vector. */
1658#define _VECTORS_SIZE (38 * _VECTOR_SIZE)
1659
1660
1661/* Constants */
1662#define SPM_PAGESIZE (256)
1663#define RAMSTART     (0x100)
1664#define RAMSIZE      (4096)
1665#define RAMEND       (RAMSTART + RAMSIZE - 1)
1666#define XRAMSTART    (0x0)
1667#define XRAMSIZE     (0)
1668#define XRAMEND      (RAMEND)
1669#define E2END        (0x7FF)
1670#define E2PAGESIZE   (4)
1671#define FLASHEND     (0xFFFF)
1672
1673
1674/* Fuses */
1675#define FUSE_MEMORY_SIZE 3
1676
1677/* Low Fuse Byte */
1678#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Clock Selection */
1679#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Clock Selection */
1680#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
1681#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
1682#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
1683#define LFUSE_DEFAULT (FUSE_SUT0)
1684
1685/* High Fuse Byte */
1686#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
1687#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
1688#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
1689#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
1690#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
1691#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
1692#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
1693#define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
1694#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
1695
1696/* Extended Fuse Byte */
1697#define FUSE_BODENABLE  (unsigned char)~_BV(0)  /* Brown-out Detector Enable Signal */
1698#define EFUSE_DEFAULT (0xFF)
1699
1700
1701/* Lock Bits */
1702#define __LOCK_BITS_EXIST
1703#define __BOOT_LOCK_BITS_0_EXIST
1704#define __BOOT_LOCK_BITS_1_EXIST
1705
1706
1707/* Signature */
1708#define SIGNATURE_0 0x1E
1709#define SIGNATURE_1 0x96
1710#define SIGNATURE_2 0xC1
1711
1712#define SLEEP_MODE_IDLE         (0)
1713#define SLEEP_MODE_PWR_DOWN     _BV(SM1)
1714#define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
1715#define SLEEP_MODE_STANDBY      (_BV(SM1) | _BV(SM2))
1716#define SLEEP_MODE_EXT_STANDBY  (_BV(SM0) | _BV(SM1) | _BV(SM2))
1717
1718#endif /* _AVR_AT90SCR100_H_ */
1719
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