source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/ioa5272.h @ 46

Last change on this file since 46 was 46, checked in by jrpelegrina, 4 years ago

First release to Xenial

File size: 15.7 KB
Line 
1/*****************************************************************************
2 *
3 * Copyright (C) 2014 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATA5272_H_INCLUDED
36#define _AVR_ATA5272_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "ioa5272.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINA    _SFR_IO8(0x00)
52#define PINA7   7
53#define PINA6   6
54#define PINA5   5
55#define PINA4   4
56#define PINA3   3
57#define PINA2   2
58#define PINA1   1
59#define PINA0   0
60
61#define DDRA    _SFR_IO8(0x01)
62#define DDRA7   7
63#define DDRA6   6
64#define DDRA5   5
65#define DDRA4   4
66#define DDRA3   3
67#define DDRA2   2
68#define DDRA1   1
69#define DDRA0   0
70
71#define PORTA   _SFR_IO8(0x02)
72#define PORTA7  7
73#define PORTA6  6
74#define PORTA5  5
75#define PORTA4  4
76#define PORTA3  3
77#define PORTA2  2
78#define PORTA1  1
79#define PORTA0  0
80
81#define PINB    _SFR_IO8(0x03)
82#define PINB7   7
83#define PINB6   6
84#define PINB5   5
85#define PINB4   4
86#define PINB3   3
87#define PINB2   2
88#define PINB1   1
89#define PINB0   0
90
91#define DDRB    _SFR_IO8(0x04)
92#define DDRB7   7
93#define DDRB6   6
94#define DDRB5   5
95#define DDRB4   4
96#define DDRB3   3
97#define DDRB2   2
98#define DDRB1   1
99#define DDRB0   0
100
101#define PORTB   _SFR_IO8(0x05)
102#define PORTB7  7
103#define PORTB6  6
104#define PORTB5  5
105#define PORTB4  4
106#define PORTB3  3
107#define PORTB2  2
108#define PORTB1  1
109#define PORTB0  0
110
111/* Reserved [0x06..0x11] */
112
113#define PORTCR  _SFR_IO8(0x12)
114
115/* Reserved [0x13..0x14] */
116
117#define TIFR0   _SFR_IO8(0x15)
118#define TOV0    0
119#define OCF0A   1
120
121#define TIFR1   _SFR_IO8(0x16)
122#define TOV1    0
123#define OCF1A   1
124#define OCF1B   2
125#define ICF1    5
126
127/* Reserved [0x17..0x1A] */
128
129#define PCIFR   _SFR_IO8(0x1B)
130#define PCIF0   0
131#define PCIF1   1
132
133#define EIFR    _SFR_IO8(0x1C)
134#define INTF0   0
135#define INTF1   1
136
137#define EIMSK   _SFR_IO8(0x1D)
138#define INT0    0
139#define INT1    1
140
141#define GPIOR0  _SFR_IO8(0x1E)
142
143#define EECR    _SFR_IO8(0x1F)
144#define EERE    0
145#define EEPE    1
146#define EEMPE   2
147#define EERIE   3
148#define EEPM0   4
149#define EEPM1   5
150
151#define EEDR    _SFR_IO8(0x20)
152
153/* Combine EEARL and EEARH */
154#define EEAR    _SFR_IO16(0x21)
155
156#define EEARL   _SFR_IO8(0x21)
157#define EEARH   _SFR_IO8(0x22)
158
159#define GTCCR   _SFR_IO8(0x23)
160#define PSR1    0
161#define PSR0    1
162#define TSM     7
163
164/* Reserved [0x24] */
165
166#define TCCR0A  _SFR_IO8(0x25)
167#define WGM00   0
168#define WGM01   1
169#define COM0A0  6
170#define COM0A1  7
171
172#define TCCR0B  _SFR_IO8(0x26)
173#define CS00    0
174#define CS01    1
175#define CS02    2
176#define FOC0A   7
177
178#define TCNT2   _SFR_IO8(0x27)
179
180#define OCR0A   _SFR_IO8(0x28)
181
182/* Reserved [0x29] */
183
184#define GPIOR1  _SFR_IO8(0x2A)
185
186#define GPIOR2  _SFR_IO8(0x2B)
187
188#define SPCR    _SFR_IO8(0x2C)
189#define SPR0    0
190#define SPR1    1
191#define CPHA    2
192#define CPOL    3
193#define MSTR    4
194#define DORD    5
195#define SPE     6
196#define SPIE    7
197
198#define SPSR    _SFR_IO8(0x2D)
199#define SPI2X   0
200#define WCOL    6
201#define SPIF    7
202
203#define SPDR    _SFR_IO8(0x2E)
204
205/* Reserved [0x2F] */
206
207#define ACSR    _SFR_IO8(0x30)
208#define ACIS0   0
209#define ACIS1   1
210#define ACIC    2
211#define ACIE    3
212#define ACI     4
213#define ACO     5
214#define ACIRS   6
215#define ACD     7
216
217#define DWDR    _SFR_IO8(0x31)
218
219/* Reserved [0x32] */
220
221#define SMCR    _SFR_IO8(0x33)
222#define SE      0
223#define SM0     1
224#define SM1     2
225
226#define MCUSR   _SFR_IO8(0x34)
227#define PORF    0
228#define EXTRF   1
229#define BORF    2
230#define WDRF    3
231
232#define MCUCR   _SFR_IO8(0x35)
233#define PUD     4
234#define BODS    5
235#define BODSE   6
236
237/* Reserved [0x36] */
238
239#define SPMCSR  _SFR_IO8(0x37)
240#define SPMEN   0
241#define PGERS   1
242#define PGWRT   2
243#define RFLB    3
244#define CTPB    4
245#define SIGRD   5
246#define RWWSB   6
247
248/* Reserved [0x38..0x3C] */
249
250/* SP [0x3D..0x3E] */
251
252/* SREG [0x3F] */
253
254#define WDTCR   _SFR_MEM8(0x60)
255#define WDE     3
256#define WDCE    4
257#define WDP0    0
258#define WDP1    1
259#define WDP2    2
260#define WDP3    5
261#define WDIE    6
262#define WDIF    7
263
264#define CLKPR   _SFR_MEM8(0x61)
265#define CLKPS0  0
266#define CLKPS1  1
267#define CLKPS2  2
268#define CLKPS3  3
269#define CLKPCE  7
270
271#define CLKCSR  _SFR_MEM8(0x62)
272#define CLKC0   0
273#define CLKC1   1
274#define CLKC2   2
275#define CLKC3   3
276#define CLKRDY  4
277#define CLKCCE  7
278
279#define CLKSELR _SFR_MEM8(0x63)
280#define CSEL0   0
281#define CSEL1   1
282#define CSEL2   2
283#define CSEL3   3
284#define CSUT0   4
285#define CSUT1   5
286#define COUT    6
287
288#define PRR     _SFR_MEM8(0x64)
289#define PRADC   0
290#define PRUSI   1
291#define PRTIM0  2
292#define PRTIM1  3
293#define PRSPI   4
294#define PRLIN   5
295
296/* Reserved [0x65] */
297
298#define OSCCAL  _SFR_MEM8(0x66)
299#define OSCCAL0 0
300#define OSCCAL1 1
301#define OSCCAL2 2
302#define OSCCAL3 3
303#define OSCCAL4 4
304#define OSCCAL5 5
305#define OSCCAL6 6
306#define OSCCAL7 7
307
308/* Reserved [0x67] */
309
310#define PCICR   _SFR_MEM8(0x68)
311#define PCIE0   0
312#define PCIE1   1
313
314#define EICRA   _SFR_MEM8(0x69)
315#define ISC00   0
316#define ISC01   1
317#define ISC10   2
318#define ISC11   3
319
320/* Reserved [0x6A] */
321
322#define PCMSK0  _SFR_MEM8(0x6B)
323#define PCINT0  0
324#define PCINT1  1
325#define PCINT2  2
326#define PCINT3  3
327#define PCINT4  4
328#define PCINT5  5
329#define PCINT6  6
330#define PCINT7  7
331
332#define PCMSK1  _SFR_MEM8(0x6C)
333#define PCINT8  0
334#define PCINT9  1
335#define PCINT10 2
336#define PCINT11 3
337#define PCINT12 4
338#define PCINT13 5
339#define PCINT14 6
340#define PCINT15 7
341
342/* Reserved [0x6D] */
343
344#define TIMSK0  _SFR_MEM8(0x6E)
345#define TOIE0   0
346#define OCIE0A  1
347
348#define TIMSK1  _SFR_MEM8(0x6F)
349#define TOIE1   0
350#define OCIE1A  1
351#define OCIE1B  2
352#define ICIE1   5
353
354/* Reserved [0x70..0x76] */
355
356#define AMISCR  _SFR_MEM8(0x77)
357#define XREFEN  1
358#define AREFEN  2
359#define ISRCEN  0
360
361/* Combine ADCL and ADCH */
362#ifndef __ASSEMBLER__
363#define ADC     _SFR_MEM16(0x78)
364#endif
365#define ADCW    _SFR_MEM16(0x78)
366
367#define ADCL    _SFR_MEM8(0x78)
368#define ADCH    _SFR_MEM8(0x79)
369
370#define ADCSRA  _SFR_MEM8(0x7A)
371#define ADPS0   0
372#define ADPS1   1
373#define ADPS2   2
374#define ADIE    3
375#define ADIF    4
376#define ADATE   5
377#define ADSC    6
378#define ADEN    7
379
380#define ADCSRB  _SFR_MEM8(0x7B)
381#define ADTS0   0
382#define ADTS1   1
383#define ADTS2   2
384#define BIN     7
385#define ACIR0   4
386#define ACIR1   5
387#define ACME    6
388
389#define ADMUX   _SFR_MEM8(0x7C)
390#define MUX0    0
391#define MUX1    1
392#define MUX2    2
393#define MUX3    3
394#define MUX4    4
395#define ADLAR   5
396#define REFS0   6
397#define REFS1   7
398
399/* Reserved [0x7D] */
400
401#define DIDR0   _SFR_MEM8(0x7E)
402#define ADC0D   0
403#define ADC1D   1
404#define ADC2D   2
405#define ADC3D   3
406#define ADC4D   4
407#define ADC5D   5
408#define ADC6D   6
409#define ADC7D   7
410
411#define DIDR1   _SFR_MEM8(0x7F)
412#define ADC8D   0
413#define ADC9D   1
414#define ADC10D  2
415
416#define TCCR1A  _SFR_MEM8(0x80)
417#define WGM10   0
418#define WGM11   1
419#define COM1B0  4
420#define COM1B1  5
421#define COM1A0  6
422#define COM1A1  7
423
424#define TCCR1B  _SFR_MEM8(0x81)
425#define CS10    0
426#define CS11    1
427#define CS12    2
428#define WGM12   3
429#define WGM13   4
430#define ICES1   6
431#define ICNC1   7
432
433#define TCCR1C  _SFR_MEM8(0x82)
434#define FOC1B   6
435#define FOC1A   7
436
437#define TCCR1D  _SFR_MEM8(0x83)
438#define OC1AU   0
439#define OC1AV   1
440#define OC1AW   2
441#define OC1AX   3
442#define OC1BU   4
443#define OC1BV   5
444#define OC1BW   6
445#define OC1BX   7
446
447/* Combine TCNT1L and TCNT1H */
448#define TCNT1   _SFR_MEM16(0x84)
449
450#define TCNT1L  _SFR_MEM8(0x84)
451#define TCNT1H  _SFR_MEM8(0x85)
452
453/* Combine ICR1L and ICR1H */
454#define ICR1    _SFR_MEM16(0x86)
455
456#define ICR1L   _SFR_MEM8(0x86)
457#define ICR1H   _SFR_MEM8(0x87)
458
459/* Combine OCR1AL and OCR1AH */
460#define OCR1A   _SFR_MEM16(0x88)
461
462#define OCR1AL  _SFR_MEM8(0x88)
463#define OCR1AH  _SFR_MEM8(0x89)
464
465/* Combine OCR1BL and OCR1BH */
466#define OCR1B   _SFR_MEM16(0x8A)
467
468#define OCR1BL  _SFR_MEM8(0x8A)
469#define OCR1BH  _SFR_MEM8(0x8B)
470
471/* Reserved [0x8C..0xB5] */
472
473#define ASSR    _SFR_MEM8(0xB6)
474#define TCR0BUB 0
475#define TCR0AUB 1
476#define OCR0AUB 3
477#define TCN0UB  4
478#define AS0     5
479#define EXCLK   6
480
481/* Reserved [0xB7] */
482
483#define USICR   _SFR_MEM8(0xB8)
484#define USITC   0
485#define USICLK  1
486#define USICS0  2
487#define USICS1  3
488#define USIWM0  4
489#define USIWM1  5
490#define USIOIE  6
491#define USISIE  7
492
493#define USISR   _SFR_MEM8(0xB9)
494#define USICNT0 0
495#define USICNT1 1
496#define USICNT2 2
497#define USICNT3 3
498#define USIDC   4
499#define USIPF   5
500#define USIOIF  6
501#define USISIF  7
502
503#define USIDR   _SFR_MEM8(0xBA)
504
505#define USIBR   _SFR_MEM8(0xBB)
506
507#define USIPP   _SFR_MEM8(0xBC)
508
509/* Reserved [0xBD..0xC7] */
510
511#define LINCR   _SFR_MEM8(0xC8)
512#define LCMD0   0
513#define LCMD1   1
514#define LCMD2   2
515#define LENA    3
516#define LCONF0  4
517#define LCONF1  5
518#define LIN13   6
519#define LSWRES  7
520
521#define LINSIR  _SFR_MEM8(0xC9)
522#define LRXOK   0
523#define LTXOK   1
524#define LIDOK   2
525#define LERR    3
526#define LBUSY   4
527#define LIDST0  5
528#define LIDST1  6
529#define LIDST2  7
530
531#define LINENIR _SFR_MEM8(0xCA)
532#define LENRXOK 0
533#define LENTXOK 1
534#define LENIDOK 2
535#define LENERR  3
536
537#define LINERR  _SFR_MEM8(0xCB)
538#define LBERR   0
539#define LCERR   1
540#define LPERR   2
541#define LSERR   3
542#define LFERR   4
543#define LOVERR  5
544#define LTOERR  6
545#define LABORT  7
546
547#define LINBTR  _SFR_MEM8(0xCC)
548#define LBT0    0
549#define LBT1    1
550#define LBT2    2
551#define LBT3    3
552#define LBT4    4
553#define LBT5    5
554#define LDISR   7
555
556#define LINBRRL _SFR_MEM8(0xCD)
557#define LDIV0   0
558#define LDIV1   1
559#define LDIV2   2
560#define LDIV3   3
561#define LDIV4   4
562#define LDIV5   5
563#define LDIV6   6
564#define LDIV7   7
565
566#define LINBRRH _SFR_MEM8(0xCE)
567#define LDIV8   0
568#define LDIV9   1
569#define LDIV10  2
570#define LDIV11  3
571
572#define LINDLR  _SFR_MEM8(0xCF)
573#define LRXDL0  0
574#define LRXDL1  1
575#define LRXDL2  2
576#define LRXDL3  3
577#define LTXDL0  4
578#define LTXDL1  5
579#define LTXDL2  6
580#define LTXDL3  7
581
582#define LINIDR  _SFR_MEM8(0xD0)
583#define LID0    0
584#define LID1    1
585#define LID2    2
586#define LID3    3
587#define LID4    4
588#define LID5    5
589#define LP0     6
590#define LP1     7
591
592#define LINSEL  _SFR_MEM8(0xD1)
593#define LINDX0  0
594#define LINDX1  1
595#define LINDX2  2
596#define LAINC   3
597
598#define LINDAT  _SFR_MEM8(0xD2)
599#define LDATA0  0
600#define LDATA1  1
601#define LDATA2  2
602#define LDATA3  3
603#define LDATA4  4
604#define LDATA5  5
605#define LDATA6  6
606#define LDATA7  7
607
608
609
610/* Interrupt vectors */
611/* Vector 0 is the reset vector */
612/* External Interrupt Request 0 */
613#define INT0_vect            _VECTOR(1)
614#define INT0_vect_num        1
615
616/* External Interrupt Request 1 */
617#define INT1_vect            _VECTOR(2)
618#define INT1_vect_num        2
619
620/* Pin Change Interrupt Request 0 */
621#define PCINT0_vect            _VECTOR(3)
622#define PCINT0_vect_num        3
623
624/* Pin Change Interrupt Request 1 */
625#define PCINT1_vect            _VECTOR(4)
626#define PCINT1_vect_num        4
627
628/* Watchdog Time-Out Interrupt */
629#define WDT_vect            _VECTOR(5)
630#define WDT_vect_num        5
631
632/* Timer/Counter1 Capture Event */
633#define TIMER1_CAPT_vect            _VECTOR(6)
634#define TIMER1_CAPT_vect_num        6
635
636/* Timer/Counter1 Compare Match 1A */
637#define TIMER1_COMPA_vect            _VECTOR(7)
638#define TIMER1_COMPA_vect_num        7
639
640/* Timer/Counter1 Compare Match 1B */
641#define TIMER1_COMPB_vect            _VECTOR(8)
642#define TIMER1_COMPB_vect_num        8
643
644/* Timer/Counter1 Overflow */
645#define TIMER1_OVF_vect            _VECTOR(9)
646#define TIMER1_OVF_vect_num        9
647
648/* Timer/Counter0 Compare Match 0A */
649#define TIMER0_COMPA_vect            _VECTOR(10)
650#define TIMER0_COMPA_vect_num        10
651
652/* Timer/Counter0 Overflow */
653#define TIMER0_OVF_vect            _VECTOR(11)
654#define TIMER0_OVF_vect_num        11
655
656/* LIN Transfer Complete */
657#define LIN_TC_vect            _VECTOR(12)
658#define LIN_TC_vect_num        12
659
660/* LIN Error */
661#define LIN_ERR_vect            _VECTOR(13)
662#define LIN_ERR_vect_num        13
663
664/* SPI Serial Transfer Complete */
665#define SPI_STC_vect            _VECTOR(14)
666#define SPI_STC_vect_num        14
667
668/* ADC Conversion Complete */
669#define ADC_vect            _VECTOR(15)
670#define ADC_vect_num        15
671
672/* EEPROM Ready */
673#define EE_RDY_vect            _VECTOR(16)
674#define EE_RDY_vect_num        16
675
676/* USI Overflow */
677#define USI_OVF_vect            _VECTOR(19)
678#define USI_OVF_vect_num        19
679
680/* Analog Comparator */
681#define ANA_COMP_vect            _VECTOR(34)
682#define ANA_COMP_vect_num        34
683
684/* USI Start */
685#define USI_START_vect            _VECTOR(36)
686#define USI_START_vect_num        36
687
688#define _VECTORS_SIZE 74
689
690
691/* Constants */
692
693#define SPM_PAGESIZE 128
694#define FLASHSTART   0x0000
695#define FLASHEND     0x1FFF
696#define RAMSTART     0x0100
697#define RAMSIZE      512
698#define RAMEND       0x02FF
699#define E2START     0
700#define E2SIZE      512
701#define E2PAGESIZE  4
702#define E2END       0x01FF
703#define XRAMEND      RAMEND
704
705
706/* Fuses */
707
708#define FUSE_MEMORY_SIZE 3
709
710/* Low Fuse Byte */
711#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
712#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
713#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
714#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
715#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
716#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
717#define FUSE_CKOUT       (unsigned char)~_BV(6)
718#define FUSE_CKDIV8      (unsigned char)~_BV(7)
719
720/* High Fuse Byte */
721#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
722#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
723#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
724#define FUSE_EESAVE      (unsigned char)~_BV(3)
725#define FUSE_WDTON       (unsigned char)~_BV(4)
726#define FUSE_SPIEN       (unsigned char)~_BV(5)
727#define FUSE_DWEN        (unsigned char)~_BV(6)
728#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
729
730/* Extended Fuse Byte */
731#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
732
733
734/* Lock Bits */
735#define __LOCK_BITS_EXIST
736
737
738/* Signature */
739#define SIGNATURE_0 0x1E
740#define SIGNATURE_1 0x93
741#define SIGNATURE_2 0x87
742
743
744#endif /* #ifdef _AVR_ATA5272_H_INCLUDED */
745
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