source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/ioa5505.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

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1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATA5505_H_INCLUDED
36#define _AVR_ATA5505_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "ioa5505.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINA    _SFR_IO8(0x00)
52#define PINA7   7
53#define PINA6   6
54#define PINA5   5
55#define PINA4   4
56#define PINA3   3
57#define PINA2   2
58#define PINA1   1
59#define PINA0   0
60
61#define DDRA    _SFR_IO8(0x01)
62#define DDRA7   7
63// Inserted "DDA7" from "DDRA7" due to compatibility
64#define DDA7    7
65#define DDRA6   6
66// Inserted "DDA6" from "DDRA6" due to compatibility
67#define DDA6    6
68#define DDRA5   5
69// Inserted "DDA5" from "DDRA5" due to compatibility
70#define DDA5    5
71#define DDRA4   4
72// Inserted "DDA4" from "DDRA4" due to compatibility
73#define DDA4    4
74#define DDRA3   3
75// Inserted "DDA3" from "DDRA3" due to compatibility
76#define DDA3    3
77#define DDRA2   2
78// Inserted "DDA2" from "DDRA2" due to compatibility
79#define DDA2    2
80#define DDRA1   1
81// Inserted "DDA1" from "DDRA1" due to compatibility
82#define DDA1    1
83#define DDRA0   0
84// Inserted "DDA0" from "DDRA0" due to compatibility
85#define DDA0    0
86
87#define PORTA   _SFR_IO8(0x02)
88#define PORTA7  7
89#define PORTA6  6
90#define PORTA5  5
91#define PORTA4  4
92#define PORTA3  3
93#define PORTA2  2
94#define PORTA1  1
95#define PORTA0  0
96
97#define PINB    _SFR_IO8(0x03)
98#define PINB7   7
99#define PINB6   6
100#define PINB5   5
101#define PINB4   4
102#define PINB3   3
103#define PINB2   2
104#define PINB1   1
105#define PINB0   0
106
107#define DDRB    _SFR_IO8(0x04)
108#define DDRB7   7
109// Inserted "DDB7" from "DDRB7" due to compatibility
110#define DDB7    7
111#define DDRB6   6
112// Inserted "DDB6" from "DDRB6" due to compatibility
113#define DDB6    6
114#define DDRB5   5
115// Inserted "DDB5" from "DDRB5" due to compatibility
116#define DDB5    5
117#define DDRB4   4
118// Inserted "DDB4" from "DDRB4" due to compatibility
119#define DDB4    4
120#define DDRB3   3
121// Inserted "DDB3" from "DDRB3" due to compatibility
122#define DDB3    3
123#define DDRB2   2
124// Inserted "DDB2" from "DDRB2" due to compatibility
125#define DDB2    2
126#define DDRB1   1
127// Inserted "DDB1" from "DDRB1" due to compatibility
128#define DDB1    1
129#define DDRB0   0
130// Inserted "DDB0" from "DDRB0" due to compatibility
131#define DDB0    0
132
133#define PORTB   _SFR_IO8(0x05)
134#define PORTB7  7
135#define PORTB6  6
136#define PORTB5  5
137#define PORTB4  4
138#define PORTB3  3
139#define PORTB2  2
140#define PORTB1  1
141#define PORTB0  0
142
143/* Reserved [0x06..0x11] */
144
145#define PORTCR  _SFR_IO8(0x12)
146#define PUDA    0
147#define PUDB    1
148#define BBMA    4
149#define BBMB    5
150
151/* Reserved [0x13..0x14] */
152
153#define TIFR0   _SFR_IO8(0x15)
154#define TOV0    0
155#define OCF0A   1
156
157#define TIFR1   _SFR_IO8(0x16)
158#define TOV1    0
159#define OCF1A   1
160#define OCF1B   2
161#define ICF1    5
162
163/* Reserved [0x17..0x1A] */
164
165#define PCIFR   _SFR_IO8(0x1B)
166#define PCIF0   0
167#define PCIF1   1
168
169#define EIFR    _SFR_IO8(0x1C)
170#define INTF0   0
171#define INTF1   1
172
173#define EIMSK   _SFR_IO8(0x1D)
174#define INT0    0
175#define INT1    1
176
177#define GPIOR0  _SFR_IO8(0x1E)
178
179#define EECR    _SFR_IO8(0x1F)
180#define EERE    0
181#define EEPE    1
182#define EEMPE   2
183#define EERIE   3
184#define EEPM0   4
185#define EEPM1   5
186
187#define EEDR    _SFR_IO8(0x20)
188
189/* Combine EEARL and EEARH */
190#define EEAR    _SFR_IO16(0x21)
191
192#define EEARL   _SFR_IO8(0x21)
193#define EEARH   _SFR_IO8(0x22)
194
195#define GTCCR   _SFR_IO8(0x23)
196#define PSR1    0
197#define PSR0    1
198#define TSM     7
199
200/* Reserved [0x24] */
201
202#define TCCR0A  _SFR_IO8(0x25)
203#define WGM00   0
204#define WGM01   1
205#define COM0A0  6
206#define COM0A1  7
207
208#define TCCR0B  _SFR_IO8(0x26)
209#define CS00    0
210#define CS01    1
211#define CS02    2
212#define FOC0A   7
213
214#define TCNT2   _SFR_IO8(0x27)
215
216#define OCR0A   _SFR_IO8(0x28)
217
218/* Reserved [0x29] */
219
220#define GPIOR1  _SFR_IO8(0x2A)
221
222#define GPIOR2  _SFR_IO8(0x2B)
223
224#define SPCR    _SFR_IO8(0x2C)
225#define SPR0    0
226#define SPR1    1
227#define CPHA    2
228#define CPOL    3
229#define MSTR    4
230#define DORD    5
231#define SPE     6
232#define SPIE    7
233
234#define SPSR    _SFR_IO8(0x2D)
235#define SPI2X   0
236#define WCOL    6
237#define SPIF    7
238
239#define SPDR    _SFR_IO8(0x2E)
240
241/* Reserved [0x2F] */
242
243#define ACSR    _SFR_IO8(0x30)
244#define ACIS0   0
245#define ACIS1   1
246#define ACIC    2
247#define ACIE    3
248#define ACI     4
249#define ACO     5
250#define ACIRS   6
251#define ACD     7
252
253#define DWDR    _SFR_IO8(0x31)
254
255/* Reserved [0x32] */
256
257#define SMCR    _SFR_IO8(0x33)
258#define SE      0
259#define SM0     1
260#define SM1     2
261
262#define MCUSR   _SFR_IO8(0x34)
263#define PORF    0
264#define EXTRF   1
265#define BORF    2
266#define WDRF    3
267
268#define MCUCR   _SFR_IO8(0x35)
269#define PUD     4
270#define BODSE   5
271#define BODS    6
272
273/* Reserved [0x36] */
274
275#define SPMCSR  _SFR_IO8(0x37)
276#define SPMEN   0
277#define PGERS   1
278#define PGWRT   2
279#define RFLB    3
280#define CTPB    4
281#define SIGRD   5
282#define RWWSB   6
283
284/* Reserved [0x38..0x3C] */
285
286/* SP [0x3D..0x3E] */
287
288/* SREG [0x3F] */
289
290#define WDTCR   _SFR_MEM8(0x60)
291#define WDE     3
292#define WDCE    4
293#define WDP0    0
294#define WDP1    1
295#define WDP2    2
296#define WDP3    5
297#define WDIE    6
298#define WDIF    7
299
300#define CLKPR   _SFR_MEM8(0x61)
301#define CLKPS0  0
302#define CLKPS1  1
303#define CLKPS2  2
304#define CLKPS3  3
305#define CLKPCE  7
306
307#define CLKCSR  _SFR_MEM8(0x62)
308#define CLKC0   0
309#define CLKC1   1
310#define CLKC2   2
311#define CLKC3   3
312#define CLKRDY  4
313#define CLKCCE  7
314
315#define CLKSELR _SFR_MEM8(0x63)
316#define CSEL0   0
317#define CSEL1   1
318#define CSEL2   2
319#define CSEL3   3
320#define CSUT0   4
321#define CSUT1   5
322#define COUT    6
323
324#define PRR     _SFR_MEM8(0x64)
325#define PRADC   0
326#define PRUSI   1
327#define PRTIM0  2
328#define PRTIM1  3
329#define PRSPI   4
330#define PRLIN   5
331
332#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
333#define __AVR_HAVE_PRR_PRADC
334#define __AVR_HAVE_PRR_PRUSI
335#define __AVR_HAVE_PRR_PRTIM0
336#define __AVR_HAVE_PRR_PRTIM1
337#define __AVR_HAVE_PRR_PRSPI
338#define __AVR_HAVE_PRR_PRLIN
339
340/* Reserved [0x65] */
341
342#define OSCCAL  _SFR_MEM8(0x66)
343#define OSCCAL0 0
344#define OSCCAL1 1
345#define OSCCAL2 2
346#define OSCCAL3 3
347#define OSCCAL4 4
348#define OSCCAL5 5
349#define OSCCAL6 6
350#define OSCCAL7 7
351
352/* Reserved [0x67] */
353
354#define PCICR   _SFR_MEM8(0x68)
355#define PCIE0   0
356#define PCIE1   1
357
358#define EICRA   _SFR_MEM8(0x69)
359#define ISC00   0
360#define ISC01   1
361#define ISC10   2
362#define ISC11   3
363
364/* Reserved [0x6A] */
365
366#define PCMSK0  _SFR_MEM8(0x6B)
367#define PCINT0  0
368#define PCINT1  1
369#define PCINT2  2
370#define PCINT3  3
371#define PCINT4  4
372#define PCINT5  5
373#define PCINT6  6
374#define PCINT7  7
375
376#define PCMSK1  _SFR_MEM8(0x6C)
377#define PCINT8  0
378#define PCINT9  1
379#define PCINT10 2
380#define PCINT11 3
381#define PCINT12 4
382#define PCINT13 5
383#define PCINT14 6
384#define PCINT15 7
385
386/* Reserved [0x6D] */
387
388#define TIMSK0  _SFR_MEM8(0x6E)
389#define TOIE0   0
390#define OCIE0A  1
391
392#define TIMSK1  _SFR_MEM8(0x6F)
393#define TOIE1   0
394#define OCIE1A  1
395#define OCIE1B  2
396#define ICIE1   5
397
398/* Reserved [0x70..0x76] */
399
400#define AMISCR  _SFR_MEM8(0x77)
401#define XREFEN  1
402#define AREFEN  2
403#define ISRCEN  0
404
405/* Combine ADCL and ADCH */
406#ifndef __ASSEMBLER__
407#define ADC     _SFR_MEM16(0x78)
408#endif
409#define ADCW    _SFR_MEM16(0x78)
410
411#define ADCL    _SFR_MEM8(0x78)
412#define ADCH    _SFR_MEM8(0x79)
413
414#define ADCSRA  _SFR_MEM8(0x7A)
415#define ADPS0   0
416#define ADPS1   1
417#define ADPS2   2
418#define ADIE    3
419#define ADIF    4
420#define ADATE   5
421#define ADSC    6
422#define ADEN    7
423
424#define ADCSRB  _SFR_MEM8(0x7B)
425#define ADTS0   0
426#define ADTS1   1
427#define ADTS2   2
428#define BIN     7
429#define ACIR0   4
430#define ACIR1   5
431#define ACME    6
432
433#define ADMUX   _SFR_MEM8(0x7C)
434#define MUX0    0
435#define MUX1    1
436#define MUX2    2
437#define MUX3    3
438#define MUX4    4
439#define ADLAR   5
440#define REFS0   6
441#define REFS1   7
442
443/* Reserved [0x7D] */
444
445#define DIDR0   _SFR_MEM8(0x7E)
446#define ADC0D   0
447#define ADC1D   1
448#define ADC2D   2
449#define ADC3D   3
450#define ADC4D   4
451#define ADC5D   5
452#define ADC6D   6
453#define ADC7D   7
454
455#define DIDR1   _SFR_MEM8(0x7F)
456#define ADC8D   0
457#define ADC9D   1
458#define ADC10D  2
459
460#define TCCR1A  _SFR_MEM8(0x80)
461#define WGM10   0
462#define WGM11   1
463#define COM1B0  4
464#define COM1B1  5
465#define COM1A0  6
466#define COM1A1  7
467
468#define TCCR1B  _SFR_MEM8(0x81)
469#define CS10    0
470#define CS11    1
471#define CS12    2
472#define WGM12   3
473#define WGM13   4
474#define ICES1   6
475#define ICNC1   7
476
477#define TCCR1C  _SFR_MEM8(0x82)
478#define FOC1B   6
479#define FOC1A   7
480
481#define TCCR1D  _SFR_MEM8(0x83)
482#define OC1AU   0
483#define OC1AV   1
484#define OC1AW   2
485#define OC1AX   3
486#define OC1BU   4
487#define OC1BV   5
488#define OC1BW   6
489#define OC1BX   7
490
491/* Combine TCNT1L and TCNT1H */
492#define TCNT1   _SFR_MEM16(0x84)
493
494#define TCNT1L  _SFR_MEM8(0x84)
495#define TCNT1H  _SFR_MEM8(0x85)
496
497/* Combine ICR1L and ICR1H */
498#define ICR1    _SFR_MEM16(0x86)
499
500#define ICR1L   _SFR_MEM8(0x86)
501#define ICR1H   _SFR_MEM8(0x87)
502
503/* Combine OCR1AL and OCR1AH */
504#define OCR1A   _SFR_MEM16(0x88)
505
506#define OCR1AL  _SFR_MEM8(0x88)
507#define OCR1AH  _SFR_MEM8(0x89)
508
509/* Combine OCR1BL and OCR1BH */
510#define OCR1B   _SFR_MEM16(0x8A)
511
512#define OCR1BL  _SFR_MEM8(0x8A)
513#define OCR1BH  _SFR_MEM8(0x8B)
514
515/* Reserved [0x8C..0xB5] */
516
517#define ASSR    _SFR_MEM8(0xB6)
518#define TCR0BUB 0
519#define TCR0AUB 1
520#define OCR0AUB 3
521#define TCN0UB  4
522#define AS0     5
523#define EXCLK   6
524
525/* Reserved [0xB7] */
526
527#define USICR   _SFR_MEM8(0xB8)
528#define USITC   0
529#define USICLK  1
530#define USICS0  2
531#define USICS1  3
532#define USIWM0  4
533#define USIWM1  5
534#define USIOIE  6
535#define USISIE  7
536
537#define USISR   _SFR_MEM8(0xB9)
538#define USICNT0 0
539#define USICNT1 1
540#define USICNT2 2
541#define USICNT3 3
542#define USIDC   4
543#define USIPF   5
544#define USIOIF  6
545#define USISIF  7
546
547#define USIDR   _SFR_MEM8(0xBA)
548
549#define USIBR   _SFR_MEM8(0xBB)
550
551#define USIPP   _SFR_MEM8(0xBC)
552
553/* Reserved [0xBD..0xC7] */
554
555#define LINCR   _SFR_MEM8(0xC8)
556#define LCMD0   0
557#define LCMD1   1
558#define LCMD2   2
559#define LENA    3
560#define LCONF0  4
561#define LCONF1  5
562#define LIN13   6
563#define LSWRES  7
564
565#define LINSIR  _SFR_MEM8(0xC9)
566#define LRXOK   0
567#define LTXOK   1
568#define LIDOK   2
569#define LERR    3
570#define LBUSY   4
571#define LIDST0  5
572#define LIDST1  6
573#define LIDST2  7
574
575#define LINENIR _SFR_MEM8(0xCA)
576#define LENRXOK 0
577#define LENTXOK 1
578#define LENIDOK 2
579#define LENERR  3
580
581#define LINERR  _SFR_MEM8(0xCB)
582#define LBERR   0
583#define LCERR   1
584#define LPERR   2
585#define LSERR   3
586#define LFERR   4
587#define LOVERR  5
588#define LTOERR  6
589#define LABORT  7
590
591#define LINBTR  _SFR_MEM8(0xCC)
592#define LBT0    0
593#define LBT1    1
594#define LBT2    2
595#define LBT3    3
596#define LBT4    4
597#define LBT5    5
598#define LDISR   7
599
600#define LINBRRL _SFR_MEM8(0xCD)
601#define LDIV0   0
602#define LDIV1   1
603#define LDIV2   2
604#define LDIV3   3
605#define LDIV4   4
606#define LDIV5   5
607#define LDIV6   6
608#define LDIV7   7
609
610#define LINBRRH _SFR_MEM8(0xCE)
611#define LDIV8   0
612#define LDIV9   1
613#define LDIV10  2
614#define LDIV11  3
615
616#define LINDLR  _SFR_MEM8(0xCF)
617#define LRXDL0  0
618#define LRXDL1  1
619#define LRXDL2  2
620#define LRXDL3  3
621#define LTXDL0  4
622#define LTXDL1  5
623#define LTXDL2  6
624#define LTXDL3  7
625
626#define LINIDR  _SFR_MEM8(0xD0)
627#define LID0    0
628#define LID1    1
629#define LID2    2
630#define LID3    3
631#define LID4    4
632#define LID5    5
633#define LP0     6
634#define LP1     7
635
636#define LINSEL  _SFR_MEM8(0xD1)
637#define LINDX0  0
638#define LINDX1  1
639#define LINDX2  2
640#define LAINC   3
641
642#define LINDAT  _SFR_MEM8(0xD2)
643#define LDATA0  0
644#define LDATA1  1
645#define LDATA2  2
646#define LDATA3  3
647#define LDATA4  4
648#define LDATA5  5
649#define LDATA6  6
650#define LDATA7  7
651
652
653
654/* Values and associated defines */
655
656
657#define SLEEP_MODE_IDLE (0x00<<1)
658#define SLEEP_MODE_ADC (0x01<<1)
659#define SLEEP_MODE_PWR_DOWN (0x02<<1)
660#define SLEEP_MODE_PWR_SAVE (0x03<<1)
661
662/* Interrupt vectors */
663/* Vector 0 is the reset vector */
664/* External Interrupt Request 0 */
665#define INT0_vect            _VECTOR(1)
666#define INT0_vect_num        1
667
668/* External Interrupt Request 1 */
669#define INT1_vect            _VECTOR(2)
670#define INT1_vect_num        2
671
672/* Pin Change Interrupt Request 0 */
673#define PCINT0_vect            _VECTOR(3)
674#define PCINT0_vect_num        3
675
676/* Pin Change Interrupt Request 1 */
677#define PCINT1_vect            _VECTOR(4)
678#define PCINT1_vect_num        4
679
680/* Watchdog Time-Out Interrupt */
681#define WDT_vect            _VECTOR(5)
682#define WDT_vect_num        5
683
684/* Timer/Counter1 Capture Event */
685#define TIMER1_CAPT_vect            _VECTOR(6)
686#define TIMER1_CAPT_vect_num        6
687
688/* Timer/Counter1 Compare Match 1A */
689#define TIMER1_COMPA_vect            _VECTOR(7)
690#define TIMER1_COMPA_vect_num        7
691
692/* Timer/Counter1 Compare Match 1B */
693#define TIMER1_COMPB_vect            _VECTOR(8)
694#define TIMER1_COMPB_vect_num        8
695
696/* Timer/Counter1 Overflow */
697#define TIMER1_OVF_vect            _VECTOR(9)
698#define TIMER1_OVF_vect_num        9
699
700/* Timer/Counter0 Compare Match 0A */
701#define TIMER0_COMPA_vect            _VECTOR(10)
702#define TIMER0_COMPA_vect_num        10
703
704/* Timer/Counter0 Overflow */
705#define TIMER0_OVF_vect            _VECTOR(11)
706#define TIMER0_OVF_vect_num        11
707
708/* LIN Transfer Complete */
709#define LIN_TC_vect            _VECTOR(12)
710#define LIN_TC_vect_num        12
711
712/* LIN Error */
713#define LIN_ERR_vect            _VECTOR(13)
714#define LIN_ERR_vect_num        13
715
716/* SPI Serial Transfer Complete */
717#define SPI_STC_vect            _VECTOR(14)
718#define SPI_STC_vect_num        14
719
720/* ADC Conversion Complete */
721#define ADC_vect            _VECTOR(15)
722#define ADC_vect_num        15
723
724/* EEPROM Ready */
725#define EE_RDY_vect            _VECTOR(16)
726#define EE_RDY_vect_num        16
727
728/* Analog Comparator */
729#define ANA_COMP_vect            _VECTOR(17)
730#define ANA_COMP_vect_num        17
731
732/* USI Start */
733#define USI_START_vect            _VECTOR(18)
734#define USI_START_vect_num        18
735
736/* USI Overflow */
737#define USI_OVF_vect            _VECTOR(19)
738#define USI_OVF_vect_num        19
739
740#define _VECTORS_SIZE 80
741
742
743/* Constants */
744
745#define SPM_PAGESIZE 128
746#define FLASHSTART   0x0000
747#define FLASHEND     0x3FFF
748#define RAMSTART     0x0100
749#define RAMSIZE      512
750#define RAMEND       0x02FF
751#define E2START     0
752#define E2SIZE      512
753#define E2PAGESIZE  4
754#define E2END       0x01FF
755#define XRAMEND      RAMEND
756
757
758/* Fuses */
759
760#define FUSE_MEMORY_SIZE 3
761
762/* Low Fuse Byte */
763#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
764#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
765#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
766#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
767#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
768#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
769#define FUSE_CKOUT       (unsigned char)~_BV(6)
770#define FUSE_CKDIV8      (unsigned char)~_BV(7)
771#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
772
773
774/* High Fuse Byte */
775#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
776#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
777#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
778#define FUSE_EESAVE      (unsigned char)~_BV(3)
779#define FUSE_WDTON       (unsigned char)~_BV(4)
780#define FUSE_SPIEN       (unsigned char)~_BV(5)
781#define FUSE_DWEN        (unsigned char)~_BV(6)
782#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
783#define HFUSE_DEFAULT    (FUSE_SPIEN)
784
785
786/* Extended Fuse Byte */
787#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
788#define EFUSE_DEFAULT    (0xFF)
789
790
791
792/* Lock Bits */
793#define __LOCK_BITS_EXIST
794
795
796/* Signature */
797#define SIGNATURE_0 0x1E
798#define SIGNATURE_1 0x94
799#define SIGNATURE_2 0x87
800
801
802#endif /* #ifdef _AVR_ATA5505_H_INCLUDED */
803
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