source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/ioa5702m322.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 3 years ago

Adding new version

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1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATA5702M322_H_INCLUDED
36#define _AVR_ATA5702M322_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "ioa5702m322.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define GPIOR0  _SFR_IO8(0x00)
52
53#define PRR1    _SFR_IO8(0x01)
54#define PRT1    0
55#define PRT2    1
56#define PRT3    2
57#define PRT4    3
58#define PRT5    4
59#define PRLFR   5
60#define PRLFTP  6
61#define PRLFPH  7
62
63#define __AVR_HAVE_PRR1 ((1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRT4)|(1<<PRT5)|(1<<PRLFR)|(1<<PRLFTP)|(1<<PRLFPH))
64#define __AVR_HAVE_PRR1_PRT1
65#define __AVR_HAVE_PRR1_PRT2
66#define __AVR_HAVE_PRR1_PRT3
67#define __AVR_HAVE_PRR1_PRT4
68#define __AVR_HAVE_PRR1_PRT5
69#define __AVR_HAVE_PRR1_PRLFR
70#define __AVR_HAVE_PRR1_PRLFTP
71#define __AVR_HAVE_PRR1_PRLFPH
72
73#define PRR2    _SFR_IO8(0x02)
74#define PRSPI2  0
75#define PRTWI2  1
76#define PRSF    2
77#define PRDF    3
78#define PRTM    6
79#define PRSSM   7
80
81#define __AVR_HAVE_PRR2 ((1<<PRSPI2)|(1<<PRTWI2)|(1<<PRSF)|(1<<PRDF)|(1<<PRTM)|(1<<PRSSM))
82#define __AVR_HAVE_PRR2_PRSPI2
83#define __AVR_HAVE_PRR2_PRTWI2
84#define __AVR_HAVE_PRR2_PRSF
85#define __AVR_HAVE_PRR2_PRDF
86#define __AVR_HAVE_PRR2_PRTM
87#define __AVR_HAVE_PRR2_PRSSM
88
89#define PINB    _SFR_IO8(0x03)
90#define PINB7   7
91#define PINB6   6
92#define PINB5   5
93#define PINB4   4
94#define PINB3   3
95#define PINB2   2
96#define PINB1   1
97#define PINB0   0
98
99#define DDRB    _SFR_IO8(0x04)
100#define DDRB7   7
101// Inserted "DDB7" from "DDRB7" due to compatibility
102#define DDB7    7
103#define DDRB6   6
104// Inserted "DDB6" from "DDRB6" due to compatibility
105#define DDB6    6
106#define DDRB5   5
107// Inserted "DDB5" from "DDRB5" due to compatibility
108#define DDB5    5
109#define DDRB4   4
110// Inserted "DDB4" from "DDRB4" due to compatibility
111#define DDB4    4
112#define DDRB3   3
113// Inserted "DDB3" from "DDRB3" due to compatibility
114#define DDB3    3
115#define DDRB2   2
116// Inserted "DDB2" from "DDRB2" due to compatibility
117#define DDB2    2
118#define DDRB1   1
119// Inserted "DDB1" from "DDRB1" due to compatibility
120#define DDB1    1
121#define DDRB0   0
122// Inserted "DDB0" from "DDRB0" due to compatibility
123#define DDB0    0
124
125#define PORTB   _SFR_IO8(0x05)
126#define PORTB7  7
127#define PORTB6  6
128#define PORTB5  5
129#define PORTB4  4
130#define PORTB3  3
131#define PORTB2  2
132#define PORTB1  1
133#define PORTB0  0
134
135#define PINC    _SFR_IO8(0x06)
136#define PINC2   2
137#define PINC1   1
138#define PINC0   0
139
140#define DDRC    _SFR_IO8(0x07)
141#define DDRC2   2
142// Inserted "DDC2" from "DDRC2" due to compatibility
143#define DDC2    2
144#define DDRC1   1
145// Inserted "DDC1" from "DDRC1" due to compatibility
146#define DDC1    1
147#define DDRC0   0
148// Inserted "DDC0" from "DDRC0" due to compatibility
149#define DDC0    0
150
151#define PORTC   _SFR_IO8(0x08)
152#define PORTC2  2
153#define PORTC1  1
154#define PORTC0  0
155
156#define PIND    _SFR_IO8(0x09)
157#define PIND7   7
158#define PIND6   6
159#define PIND5   5
160#define PIND4   4
161#define PIND3   3
162#define PIND2   2
163#define PIND1   1
164#define PIND0   0
165
166#define DDRD    _SFR_IO8(0x0A)
167#define DDRD7   7
168// Inserted "DDD7" from "DDRD7" due to compatibility
169#define DDD7    7
170#define DDRD6   6
171// Inserted "DDD6" from "DDRD6" due to compatibility
172#define DDD6    6
173#define DDRD5   5
174// Inserted "DDD5" from "DDRD5" due to compatibility
175#define DDD5    5
176#define DDRD4   4
177// Inserted "DDD4" from "DDRD4" due to compatibility
178#define DDD4    4
179#define DDRD3   3
180// Inserted "DDD3" from "DDRD3" due to compatibility
181#define DDD3    3
182#define DDRD2   2
183// Inserted "DDD2" from "DDRD2" due to compatibility
184#define DDD2    2
185#define DDRD1   1
186// Inserted "DDD1" from "DDRD1" due to compatibility
187#define DDD1    1
188#define DDRD0   0
189// Inserted "DDD0" from "DDRD0" due to compatibility
190#define DDD0    0
191
192#define PORTD   _SFR_IO8(0x0B)
193#define PORTD7  7
194#define PORTD6  6
195#define PORTD5  5
196#define PORTD4  4
197#define PORTD3  3
198#define PORTD2  2
199#define PORTD1  1
200#define PORTD0  0
201
202#define TPCR2   _SFR_IO8(0x0C)
203#define TPMA    0
204#define TPMOD   1
205#define TPPSD   2
206#define TPD     3
207#define TPNFTO  4
208#define TPWDLV0 5
209#define TPWDLV1 6
210
211#define TPFR    _SFR_IO8(0x0D)
212#define TPF     0
213#define TPFTF   1
214#define TPNFTF  2
215#define TPBERF  3
216
217#define MCUCR   _SFR_IO8(0x0E)
218#define IVL0    0
219#define IVL1    1
220#define SPIIO   2
221#define ENPS    3
222#define PUD     4
223#define TRCCE   5
224#define TRCEN   6
225#define IVSEL   7
226
227#define FSCR    _SFR_IO8(0x0F)
228#define TXMOD   0
229#define SFM     1
230#define TXMS0   2
231#define TXMS1   3
232#define PAOER   4
233#define PAON    7
234
235/* Reserved [0x10] */
236
237#define T1CR    _SFR_IO8(0x11)
238#define T1OTM   0
239#define T1CTM   1
240#define T1CRM   2
241#define T1TOP   4
242#define T1RES   5
243#define T1TOS   6
244#define T1ENA   7
245
246#define T2CR    _SFR_IO8(0x12)
247#define T2OTM   0
248#define T2CTM   1
249#define T2CRM   2
250#define T2TOP   4
251#define T2RES   5
252#define T2TOS   6
253#define T2ENA   7
254
255#define T3CR    _SFR_IO8(0x13)
256#define T3OTM   0
257#define T3CTM   1
258#define T3CRM   2
259#define T3CPRM  3
260#define T3TOP   4
261#define T3RES   5
262#define T3TOS   6
263#define T3ENA   7
264
265#define T4CR    _SFR_IO8(0x14)
266#define T4OTM   0
267#define T4CTM   1
268#define T4CRM   2
269#define T4CPRM  3
270#define T4TOP   4
271#define T4RES   5
272#define T4TOS   6
273#define T4ENA   7
274
275#define LTCMR   _SFR_IO8(0x15)
276#define LTPS0   0
277#define LTPS1   1
278#define LTPS2   2
279#define LTCRM   3
280#define LTCIM   4
281#define LTCM    5
282#define LTSM    6
283#define LTENA   7
284
285#define EECR2   _SFR_IO8(0x16)
286#define EEBRE   0
287#define E2CIM   1
288#define E2AVF   5
289#define E2FF    6
290#define E2CF    7
291
292#define PHTCR   _SFR_IO8(0x17)
293#define FRFIFO  5
294#define CPM     6
295#define CSM     7
296
297#define LDFFL   _SFR_IO8(0x18)
298#define LDFFL0  0
299#define LDFFL1  1
300#define LDFFL2  2
301#define LDFFL3  3
302#define LDFFL4  4
303#define LDFFL5  5
304#define LDFCLR  7
305
306#define LDFD    _SFR_IO8(0x19)
307
308#define PRR0    _SFR_IO8(0x1A)
309#define PRSPI   0
310#define PRLFRS  1
311#define PRTXDC  2
312#define PRCRC   3
313#define PRVM    4
314#define PRCO    5
315#define PRCU    6
316#define PRTWI1  7
317
318#define __AVR_HAVE_PRR0 ((1<<PRSPI)|(1<<PRLFRS)|(1<<PRTXDC)|(1<<PRCRC)|(1<<PRVM)|(1<<PRCO)|(1<<PRCU)|(1<<PRTWI1))
319#define __AVR_HAVE_PRR0_PRSPI
320#define __AVR_HAVE_PRR0_PRLFRS
321#define __AVR_HAVE_PRR0_PRTXDC
322#define __AVR_HAVE_PRR0_PRCRC
323#define __AVR_HAVE_PRR0_PRVM
324#define __AVR_HAVE_PRR0_PRCO
325#define __AVR_HAVE_PRR0_PRCU
326#define __AVR_HAVE_PRR0_PRTWI1
327
328#define PHFR    _SFR_IO8(0x1B)
329#define CRCEF   0
330#define PHTBLF  1
331#define PHDFF   2
332#define PHIDFF  3
333#define PHID0F  4
334#define PHID1F  5
335
336#define LFFR    _SFR_IO8(0x1C)
337#define LFSYDF  0
338#define LFDEF   1
339#define LFEOF   2
340#define LFTOF   3
341#define LFSD    6
342#define LFES    7
343
344#define AESCR   _SFR_IO8(0x1D)
345#define AESWK   0
346#define AESWD   1
347#define AESIM   2
348#define AESD    3
349#define AESXOR  4
350#define AESRES  5
351#define AESLKM  6
352#define AESE    7
353
354#define AESSR   _SFR_IO8(0x1E)
355#define AESRF   0
356#define AESERF  7
357
358#define EECR    _SFR_IO8(0x1F)
359#define EERE    0
360#define EEWE    1
361#define EEMWE   2
362#define EERIE   3
363#define EEPM0   4
364#define EEPM1   5
365#define EEPAGE  6
366#define NVMBSY  7
367
368#define EEDR    _SFR_IO8(0x20)
369
370/* Combine EEARL and EEARH */
371#define EEAR    _SFR_IO16(0x21)
372
373#define EEARL   _SFR_IO8(0x21)
374#define EEARH   _SFR_IO8(0x22)
375
376#define EEPR    _SFR_IO8(0x23)
377#define EEAP0   0
378#define EEAP1   1
379#define EEAP2   2
380#define EEAP3   3
381
382#define GPIOR1  _SFR_IO8(0x24)
383
384#define GPIOR2  _SFR_IO8(0x25)
385
386#define PCICR   _SFR_IO8(0x26)
387#define PCIE0   0
388#define PCIE1   1
389
390#define EIMSK   _SFR_IO8(0x27)
391#define INT0    0
392#define INT1    1
393
394#define EIFR    _SFR_IO8(0x28)
395#define INTF0   0
396#define INTF1   1
397
398#define LDFCKSW _SFR_IO8(0x29)
399#define LDFSCSW 0
400#define LDFSCKS 1
401
402#define VMSCR   _SFR_IO8(0x2A)
403#define VMF     0
404#define VMDIH   1
405
406#define MCUSR   _SFR_IO8(0x2B)
407#define PORF    0
408#define EXTRF   1
409#define WDRF    3
410#define DWRF    4
411#define TPRF    5
412
413#define SPCR    _SFR_IO8(0x2C)
414#define SPR0    0
415#define SPR1    1
416#define CPHA    2
417#define CPOL    3
418#define MSTR    4
419#define DORD    5
420#define SPE     6
421#define SPIE    7
422
423#define SPSR    _SFR_IO8(0x2D)
424#define SPI2X   0
425#define RXIF    4
426#define TXIF    5
427#define SPIF    7
428
429#define SPDR    _SFR_IO8(0x2E)
430
431#define LFCR0   _SFR_IO8(0x2F)
432#define LFCE1   0
433#define LFCE2   1
434#define LFCE3   2
435#define LFBR0   3
436#define LFBR1   4
437#define LFMG    5
438#define LFRRT0  6
439#define LFRRT1  7
440
441#define LFCR1   _SFR_IO8(0x30)
442#define RSST0   0
443#define RSST1   1
444#define LFFM1   2
445#define ARMDE   3
446#define FLLEN   4
447#define ADTHEN  5
448#define LFPEEN  6
449#define LFRE    7
450
451#define DWDR    _SFR_IO8(0x31)
452
453#define T0IFR   _SFR_IO8(0x32)
454#define T0F     0
455
456/* Reserved [0x33..0x36] */
457
458#define SPMCSR  _SFR_IO8(0x37)
459#define SELFPRGEN 0
460#define PGERS   1
461#define PGWRT   2
462#define FLSEL0  3
463#define FLSEL1  4
464#define FLSEL2  5
465#define RWWSB   6
466#define SPMIE   7
467
468#define SMCR    _SFR_IO8(0x38)
469#define SE      0
470#define SM0     1
471#define SM1     2
472#define SM2     3
473
474#define TPSR    _SFR_IO8(0x39)
475#define TPA     0
476#define TPGAP   1
477#define TPPSW   2
478#define TPBCOK  3
479
480#define LFCR2   _SFR_IO8(0x3A)
481#define LFSEN0  0
482#define LFSEN1  1
483#define LFDAMP  2
484#define LFVC0   5
485#define LFVC1   6
486#define LFVC2   7
487
488#define LFCR3   _SFR_IO8(0x3B)
489#define LFRCTEN 0
490#define LFRCPCEN 1
491#define LFRCPM  2
492#define LFTON   3
493#define LFTS0   4
494#define LFTS1   5
495#define LFTS2   6
496#define LFSBEN  7
497
498/* Reserved [0x3C] */
499
500/* SP [0x3D..0x3E] */
501
502/* SREG [0x3F] */
503
504#define FSEN    _SFR_MEM8(0x60)
505#define SDPU    0
506#define SDEN    1
507#define GAEN    2
508#define PEEN    3
509#define ASEN    4
510#define ANTT    5
511
512#define FSFCR   _SFR_MEM8(0x61)
513#define BTSEL0  0
514#define BTSEL1  1
515#define ASDIV0  4
516#define ASDIV1  5
517#define ASDIV2  6
518#define ASDIV3  7
519
520/* Combine GACDIVL and GACDIVH */
521#define GACDIV  _SFR_MEM16(0x62)
522
523#define GACDIVL _SFR_MEM8(0x62)
524#define GACDIVH _SFR_MEM8(0x63)
525
526#define FFREQ1L _SFR_MEM8(0x64)
527
528#define FFREQ1M _SFR_MEM8(0x65)
529
530#define FFREQ1H _SFR_MEM8(0x66)
531
532#define FFREQ2L _SFR_MEM8(0x67)
533
534#define FFREQ2M _SFR_MEM8(0x68)
535
536#define FFREQ2H _SFR_MEM8(0x69)
537
538#define BBTE2   _SFR_MEM8(0x6A)
539#define TDEPO   0
540#define DITDIS  1
541
542#define EICRA   _SFR_MEM8(0x6B)
543#define ISC00   0
544#define ISC01   1
545#define ISC10   2
546#define ISC11   3
547
548#define PCMSK0  _SFR_MEM8(0x6C)
549#define PCINT0  0
550#define PCINT1  1
551#define PCINT2  2
552#define PCINT3  3
553#define PCINT4  4
554#define PCINT5  5
555#define PCINT6  6
556#define PCINT7  7
557
558#define PCMSK1  _SFR_MEM8(0x6D)
559#define PCINT8  0
560#define PCINT9  1
561#define PCINT10 2
562#define PCINT11 3
563#define PCINT12 4
564#define PCINT13 5
565#define PCINT14 6
566#define PCINT15 7
567
568#define WDTCR   _SFR_MEM8(0x6E)
569#define WDPS0   0
570#define WDPS1   1
571#define WDPS2   2
572#define WDE     3
573#define WDCE    4
574
575#define T1CNT   _SFR_MEM8(0x6F)
576
577#define T1COR   _SFR_MEM8(0x70)
578
579#define T1MR    _SFR_MEM8(0x71)
580#define T1CS0   0
581#define T1CS1   1
582#define T1PS0   2
583#define T1PS1   3
584#define T1PS2   4
585#define T1PS3   5
586#define T1DC0   6
587#define T1DC1   7
588
589#define T1IMR   _SFR_MEM8(0x72)
590#define T1OIM   0
591#define T1CIM   1
592
593#define T2CNT   _SFR_MEM8(0x73)
594
595#define T2COR   _SFR_MEM8(0x74)
596
597#define T2MR    _SFR_MEM8(0x75)
598#define T2CS0   0
599#define T2CS1   1
600#define T2PS0   2
601#define T2PS1   3
602#define T2PS2   4
603#define T2PS3   5
604#define T2DC0   6
605#define T2DC1   7
606
607#define T2IMR   _SFR_MEM8(0x76)
608#define T2OIM   0
609#define T2CIM   1
610
611/* Combine T3CNTL and T3CNTH */
612#define T3CNT   _SFR_MEM16(0x77)
613
614#define T3CNTL  _SFR_MEM8(0x77)
615#define T3CNTH  _SFR_MEM8(0x78)
616
617/* Combine T3CORL and T3CORH */
618#define T3COR   _SFR_MEM16(0x79)
619
620#define T3CORL  _SFR_MEM8(0x79)
621#define T3CORH  _SFR_MEM8(0x7A)
622
623/* Combine T3ICRL and T3ICRH */
624#define T3ICR   _SFR_MEM16(0x7B)
625
626#define T3ICRL  _SFR_MEM8(0x7B)
627#define T3ICRH  _SFR_MEM8(0x7C)
628
629#define T3MRA   _SFR_MEM8(0x7D)
630#define T3CS0   0
631#define T3CS1   1
632#define T3PS0   2
633#define T3PS1   3
634#define T3PS2   4
635
636#define T3MRB   _SFR_MEM8(0x7E)
637#define T3SCE   1
638#define T3CNC   2
639#define T3CE0   3
640#define T3CE1   4
641#define T3ICS0  5
642#define T3ICS1  6
643#define T3ICS2  7
644
645#define T3IMR   _SFR_MEM8(0x7F)
646#define T3OIM   0
647#define T3CIM   1
648#define T3CPIM  2
649
650/* Combine T4CNTL and T4CNTH */
651#define T4CNT   _SFR_MEM16(0x80)
652
653#define T4CNTL  _SFR_MEM8(0x80)
654#define T4CNTH  _SFR_MEM8(0x81)
655
656/* Combine T4CORL and T4CORH */
657#define T4COR   _SFR_MEM16(0x82)
658
659#define T4CORL  _SFR_MEM8(0x82)
660#define T4CORH  _SFR_MEM8(0x83)
661
662/* Combine T4ICRL and T4ICRH */
663#define T4ICR   _SFR_MEM16(0x84)
664
665#define T4ICRL  _SFR_MEM8(0x84)
666#define T4ICRH  _SFR_MEM8(0x85)
667
668#define T4MRA   _SFR_MEM8(0x86)
669#define T4CS0   0
670#define T4CS1   1
671#define T4PS0   2
672#define T4PS1   3
673#define T4PS2   4
674
675#define T4MRB   _SFR_MEM8(0x87)
676#define T4SCE   1
677#define T4CNC   2
678#define T4CE0   3
679#define T4CE1   4
680#define T4ICS0  5
681#define T4ICS1  6
682#define T4ICS2  7
683
684#define T4IMR   _SFR_MEM8(0x88)
685#define T4OIM   0
686#define T4CIM   1
687#define T4CPIM  2
688
689#define T5TEMP  _SFR_MEM8(0x89)
690
691/* Combine T5OCRL and T5OCRH */
692#define T5OCR   _SFR_MEM16(0x8A)
693
694#define T5OCRL  _SFR_MEM8(0x8A)
695#define T5OCRH  _SFR_MEM8(0x8B)
696
697#define T5CCR   _SFR_MEM8(0x8C)
698#define T5CS0   0
699#define T5CS1   1
700#define T5CS2   2
701#define T5CTC   3
702
703/* Combine T5CNTL and T5CNTH */
704#define T5CNT   _SFR_MEM16(0x8D)
705
706#define T5CNTL  _SFR_MEM8(0x8D)
707#define T5CNTH  _SFR_MEM8(0x8E)
708
709#define T5IMR   _SFR_MEM8(0x8F)
710#define T5OIM   0
711#define T5CIM   1
712
713#define LFCALR1 _SFR_MEM8(0x90)
714#define LFSTC0  0
715#define LFSTC1  1
716#define LFSTC2  2
717#define ICOMPRT0 3
718#define ICOMPRT1 4
719#define SEL150M0 5
720#define SEL150M1 6
721#define SEL150M2 7
722
723#define LFCALR2 _SFR_MEM8(0x91)
724#define LFSTRES0 0
725#define LFSTRES1 1
726#define LFSTRES2 2
727#define LFSTRES3 3
728#define LFSTRES4 4
729#define LFSTRES5 5
730#define LFSRM   6
731#define TIKOMPD 7
732
733#define LFCALR3 _SFR_MEM8(0x92)
734#define TCGAIN10 0
735#define TCGAIN11 1
736#define TCGAIN12 2
737#define TCGAIN13 3
738#define TCGAIN14 4
739#define TCGAIN15 5
740#define TCGAIN16 6
741#define TCGAIN17 7
742
743#define LFCALR4 _SFR_MEM8(0x93)
744#define TCGAIN20 0
745#define TCGAIN21 1
746#define TCGAIN22 2
747#define TCGAIN23 3
748#define TCGAIN24 4
749#define TCGAIN25 5
750#define TCGAIN26 6
751#define TCGAIN27 7
752
753#define LFCALR5 _SFR_MEM8(0x94)
754#define TCGAIN30 0
755#define TCGAIN31 1
756#define TCGAIN32 2
757#define TCGAIN34 4
758#define TCGAIN35 5
759#define TCGAIN36 6
760#define TCGAIN37 7
761
762#define LFCALR6 _SFR_MEM8(0x95)
763#define TCGAIN40 0
764#define TCGAIN41 1
765#define TCGAIN42 2
766#define TCGAIN43 3
767#define TCGAIN44 4
768
769#define LFCALR7 _SFR_MEM8(0x96)
770
771#define LFCALR8 _SFR_MEM8(0x97)
772
773#define LFCALR9 _SFR_MEM8(0x98)
774
775#define LFCALR10 _SFR_MEM8(0x99)
776
777#define LFCALR11 _SFR_MEM8(0x9A)
778
779#define LFCALR12 _SFR_MEM8(0x9B)
780
781#define LFCALR13 _SFR_MEM8(0x9C)
782
783#define LFCALR14 _SFR_MEM8(0x9D)
784
785#define LFCALR15 _SFR_MEM8(0x9E)
786
787#define LFCALR16 _SFR_MEM8(0x9F)
788
789#define LFCALR17 _SFR_MEM8(0xA0)
790
791#define LFCALR18 _SFR_MEM8(0xA1)
792
793#define LFCALR19 _SFR_MEM8(0xA2)
794
795#define LFCALR20 _SFR_MEM8(0xA3)
796
797#define LFCALR21 _SFR_MEM8(0xA4)
798
799#define LFCALR22 _SFR_MEM8(0xA5)
800
801#define LFCALR23 _SFR_MEM8(0xA6)
802
803#define LFCALR24 _SFR_MEM8(0xA7)
804
805#define LFCALR25 _SFR_MEM8(0xA8)
806
807#define LFCALR26 _SFR_MEM8(0xA9)
808
809#define LFCALR27 _SFR_MEM8(0xAA)
810
811#define LFCALR28 _SFR_MEM8(0xAB)
812
813#define LFCALR29 _SFR_MEM8(0xAC)
814
815#define LFCALR30 _SFR_MEM8(0xAD)
816
817#define LFCALR31 _SFR_MEM8(0xAE)
818
819#define LFCALR32 _SFR_MEM8(0xAF)
820
821#define LFCALR33 _SFR_MEM8(0xB0)
822
823#define LFCALR34 _SFR_MEM8(0xB1)
824
825#define LFCALR35 _SFR_MEM8(0xB2)
826
827#define LFCALR36 _SFR_MEM8(0xB3)
828
829#define LFCALR37 _SFR_MEM8(0xB4)
830
831#define LFCALR38 _SFR_MEM8(0xB5)
832
833#define LFCALR39 _SFR_MEM8(0xB6)
834
835#define LFCALR40 _SFR_MEM8(0xB7)
836
837#define LFCALR41 _SFR_MEM8(0xB8)
838
839#define LFCALR42 _SFR_MEM8(0xB9)
840
841#define LFCALR43 _SFR_MEM8(0xBA)
842
843#define LFCALR44 _SFR_MEM8(0xBB)
844
845#define LFCALR45 _SFR_MEM8(0xBC)
846
847#define LFCALR46 _SFR_MEM8(0xBD)
848
849#define LFCALR47 _SFR_MEM8(0xBE)
850
851#define LFCALR48 _SFR_MEM8(0xBF)
852
853#define LFCALR49 _SFR_MEM8(0xC0)
854
855#define LFCALR50 _SFR_MEM8(0xC1)
856
857#define LFCALR51 _SFR_MEM8(0xC2)
858
859#define LFCALR52 _SFR_MEM8(0xC3)
860
861#define LFCALR53 _SFR_MEM8(0xC4)
862
863#define XFUSE   _SFR_MEM8(0xC5)
864
865#define MRCCAL  _SFR_MEM8(0xC6)
866
867#define FRCCAL  _SFR_MEM8(0xC7)
868
869#define RCTCAL  _SFR_MEM8(0xC8)
870#define FRCTC   0
871#define MRCTC0  1
872#define MRCTC1  2
873#define MRCTC2  3
874#define DI_MRCBG 4
875
876#define CMSR    _SFR_MEM8(0xC9)
877#define ECF     0
878
879#define CMOCR   _SFR_MEM8(0xCA)
880#define FRCAO   0
881#define MRCAO   1
882#define FRCACT  2
883
884#define SUPFR   _SFR_MEM8(0xCB)
885#define AVCCRF  0
886#define AVCCLF  1
887
888#define SUPCR   _SFR_MEM8(0xCC)
889#define AVCCRM  0
890#define AVCCLM  1
891#define PVEN    2
892#define AVDIC   3
893#define AVEN    4
894#define DVHEN   5
895#define VMRESM  6
896#define VMEMEN  7
897
898#define SUPCA1  _SFR_MEM8(0xCD)
899#define PV22    2
900#define PVDIC   3
901#define PVCAL0  4
902#define PVCAL1  5
903#define PVCAL2  6
904#define PVCAL3  7
905
906#define SUPCA2  _SFR_MEM8(0xCE)
907#define BGCAL0  0
908#define BGCAL1  1
909#define BGCAL2  2
910#define BGCAL3  3
911
912#define SUPCA3  _SFR_MEM8(0xCF)
913#define ACAL0   0
914#define ACAL1   1
915#define ACAL2   2
916#define ACAL3   3
917#define ACAL4   4
918#define ACAL5   5
919#define ACAL6   6
920#define ACAL7   7
921
922#define SUPCA4  _SFR_MEM8(0xD0)
923#define ICONST0 0
924#define ICONST1 1
925#define ICONST2 2
926#define ICONST3 3
927#define ICONST4 4
928#define ICONST5 5
929
930#define CALRDY  _SFR_MEM8(0xD1)
931
932#define DFS     _SFR_MEM8(0xD2)
933#define DFFLRF  0
934#define DFUFL   1
935#define DFOFL   2
936
937/* Reserved [0xD3..0xD4] */
938
939#define DFL     _SFR_MEM8(0xD5)
940#define DFFLS0  0
941#define DFFLS1  1
942#define DFFLS2  2
943#define DFFLS3  3
944#define DFFLS4  4
945#define DFFLS5  5
946#define DFCLR   7
947
948#define DFWP    _SFR_MEM8(0xD6)
949
950#define DFRP    _SFR_MEM8(0xD7)
951
952#define DFD     _SFR_MEM8(0xD8)
953
954#define DFI     _SFR_MEM8(0xD9)
955#define DFFLIM  0
956#define DFERIM  1
957
958#define DFC     _SFR_MEM8(0xDA)
959#define DFFLC0  0
960#define DFFLC1  1
961#define DFFLC2  2
962#define DFFLC3  3
963#define DFFLC4  4
964#define DFFLC5  5
965#define DFDRA   7
966
967#define SFS     _SFR_MEM8(0xDB)
968#define SFFLRF  0
969#define SFUFL   1
970#define SFOFL   2
971
972#define SFL     _SFR_MEM8(0xDC)
973#define SFFLS0  0
974#define SFFLS1  1
975#define SFFLS2  2
976#define SFFLS3  3
977#define SFFLS4  4
978#define SFCLR   7
979
980#define SFWP    _SFR_MEM8(0xDD)
981
982#define SFRP    _SFR_MEM8(0xDE)
983
984#define SFD     _SFR_MEM8(0xDF)
985
986#define SFI     _SFR_MEM8(0xE0)
987#define SFFLIM  0
988#define SFERIM  1
989
990#define SFC     _SFR_MEM8(0xE1)
991#define SFFLC0  0
992#define SFFLC1  1
993#define SFFLC2  2
994#define SFFLC3  3
995#define SFFLC4  4
996#define SFDRA   7
997
998#define SSMCR   _SFR_MEM8(0xE2)
999#define SSMTGE  2
1000#define SSMTPE  3
1001#define SSMPVE  4
1002#define SSMTAE  5
1003
1004#define GTCCR   _SFR_MEM8(0xE3)
1005#define PSR10   0
1006#define TSM     7
1007
1008#define SSMFBR  _SFR_MEM8(0xE4)
1009#define SSMPLDT 5
1010
1011#define SSMRR   _SFR_MEM8(0xE5)
1012#define SSMR    0
1013#define SSMST   1
1014
1015#define SSMSR   _SFR_MEM8(0xE6)
1016#define SSMESM0 0
1017#define SSMESM1 1
1018#define SSMESM2 2
1019#define SSMESM3 3
1020#define SSMERR  7
1021
1022#define SSMIFR  _SFR_MEM8(0xE7)
1023#define SSMIF   0
1024
1025#define SSMIMR  _SFR_MEM8(0xE8)
1026#define SSMIM   0
1027
1028#define MSMSTR  _SFR_MEM8(0xE9)
1029#define SSMMST0 0
1030#define SSMMST1 1
1031#define SSMMST2 2
1032#define SSMMST3 3
1033#define SSMMST4 4
1034
1035#define SSMSTR  _SFR_MEM8(0xEA)
1036#define SSMSTA0 0
1037#define SSMSTA1 1
1038#define SSMSTA2 2
1039#define SSMSTA3 3
1040#define SSMSTA4 4
1041#define SSMSTA5 5
1042
1043#define VXMCTRL _SFR_MEM8(0xEB)
1044#define VX_SEL0 0
1045#define VX_SEL1 1
1046#define EN_VX   2
1047#define EN_VX_OUT 3
1048#define EN_VX_IN 4
1049
1050#define MSMCR1  _SFR_MEM8(0xEC)
1051#define MSMSM00 0
1052#define MSMSM01 1
1053#define MSMSM02 2
1054#define MSMSM03 3
1055#define MSMSM10 4
1056#define MSMSM11 5
1057#define MSMSM12 6
1058#define MSMSM13 7
1059
1060#define MSMCR2  _SFR_MEM8(0xED)
1061#define MSMSM20 0
1062#define MSMSM21 1
1063#define MSMSM22 2
1064#define MSMSM23 3
1065#define MSMSM30 4
1066#define MSMSM31 5
1067#define MSMSM32 6
1068#define MSMSM33 7
1069
1070#define MSMCR3  _SFR_MEM8(0xEE)
1071#define MSMSM40 0
1072#define MSMSM41 1
1073#define MSMSM42 2
1074#define MSMSM43 3
1075#define MSMSM50 4
1076#define MSMSM51 5
1077#define MSMSM52 6
1078#define MSMSM53 7
1079
1080#define MSMCR4  _SFR_MEM8(0xEF)
1081#define MSMSM60 0
1082#define MSMSM61 1
1083#define MSMSM62 2
1084#define MSMSM63 3
1085#define MSMSM70 4
1086#define MSMSM71 5
1087#define MSMSM72 6
1088#define MSMSM73 7
1089
1090/* Reserved [0xF0..0xF6] */
1091
1092#define SP2CR   _SFR_MEM8(0xF7)
1093#define SP2R0   0
1094#define SP2R1   1
1095#define CPHA2   2
1096#define CPOL2   3
1097#define MSTR2   4
1098#define DORD2   5
1099#define SP2E    6
1100#define SP2IE   7
1101
1102#define SP2DR   _SFR_MEM8(0xF8)
1103
1104#define SP2SR   _SFR_MEM8(0xF9)
1105#define SPI22X  0
1106#define WCOL2   6
1107#define SP2IF   7
1108
1109/* Reserved [0xFA..0xFB] */
1110
1111/* Combine TRCIDL and TRCIDH */
1112#define TRCID   _SFR_MEM16(0xFC)
1113
1114#define TRCIDL  _SFR_MEM8(0xFC)
1115#define TRCIDH  _SFR_MEM8(0xFD)
1116
1117/* Reserved [0xFE] */
1118
1119#define TRCDR   _SFR_MEM8(0xFF)
1120
1121#define FESR    _SFR_MEM8(0x100)
1122#define XRDY    2
1123#define PLCK    3
1124#define ANTS    4
1125
1126#define FEEN1   _SFR_MEM8(0x101)
1127#define PLEN    0
1128#define PLCAL   1
1129#define XTOEN   2
1130#define PLSP1   6
1131#define ATEN    7
1132
1133#define FEEN2   _SFR_MEM8(0x102)
1134#define PAEN    2
1135#define PLPEN   4
1136#define CPBIA   6
1137
1138#define FELNA   _SFR_MEM8(0x103)
1139
1140#define FEAT    _SFR_MEM8(0x104)
1141#define ANTN0   0
1142#define ANTN1   1
1143#define ANTN2   2
1144#define ANTN3   3
1145
1146#define FEPAC   _SFR_MEM8(0x105)
1147#define PACR0   0
1148#define PACR1   1
1149#define PACR2   2
1150#define PACR3   3
1151#define PACR4   4
1152#define PACR5   5
1153#define PACR6   6
1154#define PACR7   7
1155
1156#define FEVCT   _SFR_MEM8(0x106)
1157
1158#define FEBT    _SFR_MEM8(0x107)
1159#define CTN20   0
1160#define CTN21   1
1161#define RTN20   2
1162#define RTN21   3
1163
1164#define FEMS    _SFR_MEM8(0x108)
1165#define PLLS0   0
1166#define PLLS1   1
1167#define PLLS2   2
1168#define PLLS3   3
1169#define PLLM0   4
1170#define PLLM1   5
1171#define PLLM2   6
1172#define PLLM3   7
1173
1174#define FETN4   _SFR_MEM8(0x109)
1175#define CTN40   0
1176#define CTN41   1
1177#define CTN42   2
1178#define CTN43   3
1179#define RTN40   4
1180#define RTN41   5
1181#define RTN42   6
1182#define RTN43   7
1183
1184#define FECR    _SFR_MEM8(0x10A)
1185#define LBNHB   0
1186#define S4N3    1
1187#define PLCKG   4
1188#define ANPS    5
1189
1190#define FEVCO   _SFR_MEM8(0x10B)
1191#define CPCC0   0
1192#define CPCC1   1
1193#define CPCC2   2
1194#define CPCC3   3
1195#define VCOB0   4
1196#define VCOB1   5
1197#define VCOB2   6
1198#define VCOB3   7
1199
1200#define FEALR   _SFR_MEM8(0x10C)
1201#define RNGE0   0
1202#define RNGE1   1
1203
1204#define FEANT   _SFR_MEM8(0x10D)
1205#define LVLC0   0
1206#define LVLC1   1
1207#define LVLC2   2
1208#define LVLC3   3
1209
1210#define FEBIA   _SFR_MEM8(0x10E)
1211
1212/* Reserved [0x10F..0x114] */
1213
1214#define CLKOD   _SFR_MEM8(0x115)
1215
1216#define CLKOCR  _SFR_MEM8(0x116)
1217#define CLKOS0  0
1218#define CLKOS1  1
1219#define CLKOEN  2
1220
1221/* Reserved [0x117..0x11B] */
1222
1223#define FETE1   _SFR_MEM8(0x11C)
1224#define ADCT    0
1225#define XTOT    1
1226#define LNLT    2
1227#define LNHT    3
1228#define PATE    4
1229#define AMPT    5
1230#define VCOT    6
1231#define ANTN    7
1232
1233#define FETE2   _SFR_MEM8(0x11D)
1234#define RCCT    0
1235#define PPFT    1
1236#define LFT     2
1237#define CPT     3
1238#define PFDT    4
1239#define DADCT   5
1240#define PRET    6
1241#define SWALT   7
1242
1243#define FETE3   _SFR_MEM8(0x11E)
1244#define BIOUT   0
1245#define RMPTST  1
1246
1247#define FETD    _SFR_MEM8(0x11F)
1248
1249#define TMFSM   _SFR_MEM8(0x120)
1250#define TMSSM0  0
1251#define TMSSM1  1
1252#define TMSSM2  2
1253#define TMSSM3  3
1254#define TMMSM0  4
1255#define TMMSM1  5
1256#define TMMSM2  6
1257
1258/* Combine TMCRCL and TMCRCH */
1259#define TMCRC   _SFR_MEM16(0x121)
1260
1261#define TMCRCL  _SFR_MEM8(0x121)
1262#define TMCRCH  _SFR_MEM8(0x122)
1263
1264#define TMCSB   _SFR_MEM8(0x123)
1265
1266/* Combine TMCIL and TMCIH */
1267#define TMCI    _SFR_MEM16(0x124)
1268
1269#define TMCIL   _SFR_MEM8(0x124)
1270#define TMCIH   _SFR_MEM8(0x125)
1271
1272/* Combine TMCPL and TMCPH */
1273#define TMCP    _SFR_MEM16(0x126)
1274
1275#define TMCPL   _SFR_MEM8(0x126)
1276#define TMCPH   _SFR_MEM8(0x127)
1277
1278#define TMSHR   _SFR_MEM8(0x128)
1279
1280/* Combine TMTLLL and TMTLLH */
1281#define TMTLL   _SFR_MEM16(0x129)
1282
1283#define TMTLLL  _SFR_MEM8(0x129)
1284#define TMTLLH  _SFR_MEM8(0x12A)
1285
1286#define TMSSC   _SFR_MEM8(0x12B)
1287#define TMSSP0  0
1288#define TMSSP1  1
1289#define TMSSP2  2
1290#define TMSSP3  3
1291#define TMSSL0  4
1292#define TMSSL1  5
1293#define TMSSL2  6
1294#define TMSSH   7
1295
1296#define TMSR    _SFR_MEM8(0x12C)
1297#define TMTCF   0
1298
1299#define TMCR2   _SFR_MEM8(0x12D)
1300#define TMCRCE  0
1301#define TMCRCSE0 1
1302#define TMCRCSE1 2
1303#define TMNRZE  3
1304#define TMPOL   4
1305#define TMSSE   5
1306#define TMLSB   6
1307
1308#define TMCR1   _SFR_MEM8(0x12E)
1309#define TMPIS0  0
1310#define TMPIS1  1
1311#define TMPIS2  2
1312#define TMSCS   3
1313#define TMCIM   4
1314
1315/* Reserved [0x12F] */
1316
1317#define LFDSR1  _SFR_MEM8(0x130)
1318#define LOTHA0  0
1319#define LOTHA1  1
1320#define HITHA0  2
1321#define HITHA1  3
1322#define CTTHA0  4
1323#define CTTHA1  5
1324
1325#define LFDSR2  _SFR_MEM8(0x131)
1326#define LOTHB0  0
1327#define LOTHB1  1
1328#define HITHB0  2
1329#define HITHB1  3
1330#define CTTHB0  4
1331#define CTTHB1  5
1332
1333#define LFDSR3  _SFR_MEM8(0x132)
1334#define PBDTH0  0
1335#define PBDTH1  1
1336#define QCTH0   3
1337#define QCTH1   4
1338#define QCTH2   5
1339
1340#define LFDSR4  _SFR_MEM8(0x133)
1341#define SDTHA0  0
1342#define SDTHA1  1
1343#define SDTHA2  2
1344#define SCTHA0  3
1345#define SCTHA1  4
1346#define SCTHA2  5
1347#define SRSTC0  6
1348#define SRSTC1  7
1349
1350#define LFDSR5  _SFR_MEM8(0x134)
1351#define SDTHB0  0
1352#define SDTHB1  1
1353#define SDTHB2  2
1354#define SCTHB0  3
1355#define SCTHB1  4
1356#define SCTHB2  5
1357#define SSUTA   6
1358#define SSUTB   7
1359
1360#define LFDSR6  _SFR_MEM8(0x135)
1361#define TODU0   0
1362#define TODU1   1
1363#define TODU2   2
1364#define TODS0   3
1365#define TODS1   4
1366#define TODS2   5
1367
1368#define LFDSR7  _SFR_MEM8(0x136)
1369#define PBSP0   0
1370#define PBSP1   1
1371#define PBG0    2
1372#define PBG1    3
1373#define MDSP0   4
1374#define MDSP1   5
1375#define MDG0    6
1376#define MDG1    7
1377
1378#define LFDSR8  _SFR_MEM8(0x137)
1379#define CLD0    0
1380#define CLD1    1
1381#define CLD2    2
1382#define LGFE    3
1383#define ASWTH0  4
1384#define ASWTH1  5
1385#define ASWTH2  6
1386
1387#define LFDSR9  _SFR_MEM8(0x138)
1388#define STW0    0
1389#define STW1    1
1390#define STW2    2
1391#define STW3    3
1392#define STW4    4
1393
1394#define LFDSR10 _SFR_MEM8(0x139)
1395#define FCL0    0
1396#define FCL1    1
1397#define FCL2    2
1398#define FCL3    3
1399#define FCL4    4
1400#define FCL5    5
1401#define STBTH0  6
1402#define STBTH1  7
1403
1404#define LFDSR11 _SFR_MEM8(0x13A)
1405#define TINITA0 0
1406#define TINITA1 1
1407#define TINITA2 2
1408#define TINITA3 3
1409#define TINITB0 4
1410#define TINITB1 5
1411#define TINITB2 6
1412#define TINITB3 7
1413
1414#define EEPR1   _SFR_MEM8(0x13B)
1415#define EEPS4WD 0
1416#define EEPS4RD 1
1417#define EEPS5WD 2
1418#define EEPS5RD 3
1419#define EEPS6WD 4
1420#define EEPS6RD 5
1421#define EEPS7WD 6
1422#define EEPS7RD 7
1423
1424#define EEPR2   _SFR_MEM8(0x13C)
1425#define EEPS8WD 0
1426#define EEPS8RD 1
1427#define EEPS9WD 2
1428#define EEPS9RD 3
1429#define EEPS10WD 4
1430#define EEPS10RD 5
1431#define EEPS11WD 6
1432#define EEPS11RD 7
1433
1434#define EEPR3   _SFR_MEM8(0x13D)
1435#define EEPS12WD 0
1436#define EEPS12RD 1
1437
1438/* Reserved [0x13E..0x144] */
1439
1440#define CRCCR   _SFR_MEM8(0x145)
1441#define CRCRS   0
1442#define REFLI   1
1443#define REFLO   2
1444
1445#define CRCDOR  _SFR_MEM8(0x146)
1446
1447/* Reserved [0x147..0x150] */
1448
1449#define LFSRCTM _SFR_MEM8(0x151)
1450#define LFSRCT1 0
1451#define LFSRCT2 1
1452#define LFSRCT3 2
1453#define LFSRCT4 3
1454#define LFSRCT5 4
1455#define LFSRCT6 5
1456#define LFSRCT7 6
1457#define LFSRCT8 7
1458
1459#define DBCR    _SFR_MEM8(0x152)
1460#define DBMD    0
1461#define DBCS    1
1462#define DBTMS   2
1463#define DBHA    3
1464
1465#define DBTC    _SFR_MEM8(0x153)
1466
1467#define DBENB   _SFR_MEM8(0x154)
1468
1469#define DBENC   _SFR_MEM8(0x155)
1470
1471#define DBGSW   _SFR_MEM8(0x156)
1472#define DBGGS0  0
1473#define DBGGS1  1
1474#define DBGGS2  2
1475#define DBGGS3  3
1476#define CPBFOS0 4
1477#define CPBFOS1 5
1478#define CPBF    6
1479#define ATEST   7
1480
1481#define SFFR    _SFR_MEM8(0x157)
1482#define RFL0    0
1483#define RFL1    1
1484#define RFL2    2
1485#define RFC     3
1486#define TFL0    4
1487#define TFL1    5
1488#define TFL2    6
1489#define TFC     7
1490
1491#define SFIR    _SFR_MEM8(0x158)
1492#define RIL0    0
1493#define RIL1    1
1494#define RIL2    2
1495#define SRIE    3
1496#define TIL0    4
1497#define TIL1    5
1498#define TIL2    6
1499#define STIE    7
1500
1501#define T2IFR   _SFR_MEM8(0x159)
1502#define T2OFF   0
1503#define T2COF   1
1504
1505#define PGMST   _SFR_MEM8(0x15A)
1506#define PGMSYN0 0
1507#define PGMSYN1 1
1508#define PGMSYN2 2
1509#define PGMSYN3 3
1510#define PGMSYN4 4
1511
1512#define EEST    _SFR_MEM8(0x15B)
1513#define EESYN0  0
1514#define EESYN1  1
1515#define EESYN2  2
1516#define EESYN3  3
1517
1518#define LFSRCTL _SFR_MEM8(0x15C)
1519#define LFSRCT0 0
1520
1521/* Reserved [0x15D..0x160] */
1522
1523#define PCIFR   _SFR_MEM8(0x161)
1524#define PCIF0   0
1525#define PCIF1   1
1526
1527#define T0CR    _SFR_MEM8(0x162)
1528#define T0PS0   0
1529#define T0PS1   1
1530#define T0PS2   2
1531#define T0IE    3
1532#define T0PR    4
1533
1534/* Reserved [0x163] */
1535
1536#define DBEND   _SFR_MEM8(0x164)
1537
1538#define TPCR1   _SFR_MEM8(0x165)
1539#define TPQPLM  2
1540#define TPBR    4
1541#define TPDFCP0 5
1542#define TPDFCP1 6
1543#define TPMODE  7
1544
1545#define TPIMR   _SFR_MEM8(0x166)
1546#define TPIM    0
1547#define TPFTIM  1
1548#define TPNFTIM 2
1549#define TPBERIM 3
1550
1551#define TPDCR1  _SFR_MEM8(0x167)
1552#define TPDCL10 0
1553#define TPDCL11 1
1554#define TPDCL12 2
1555#define TPDCL13 3
1556#define TPDCL14 4
1557#define TPDCL15 5
1558
1559#define TPDCR2  _SFR_MEM8(0x168)
1560#define TPDCL20 0
1561#define TPDCL21 1
1562#define TPDCL22 2
1563#define TPDCL23 3
1564#define TPDCL24 4
1565#define TPDCL25 5
1566
1567#define TPDCR3  _SFR_MEM8(0x169)
1568#define TPDCL30 0
1569#define TPDCL31 1
1570#define TPDCL32 2
1571#define TPDCL33 3
1572#define TPDCL34 4
1573#define TPDCL35 5
1574
1575#define TPDCR4  _SFR_MEM8(0x16A)
1576#define TPDCL40 0
1577#define TPDCL41 1
1578#define TPDCL42 2
1579#define TPDCL43 3
1580#define TPDCL44 4
1581#define TPDCL45 5
1582
1583#define TPDCR5  _SFR_MEM8(0x16B)
1584#define TPDCL50 0
1585#define TPDCL51 1
1586#define TPDCL52 2
1587#define TPDCL53 3
1588#define TPDCL54 4
1589#define TPDCL55 5
1590
1591#define TPECR1  _SFR_MEM8(0x16C)
1592#define TPECL10 0
1593#define TPECL11 1
1594#define TPECL12 2
1595#define TPECL13 3
1596#define TPECL14 4
1597#define TPECL15 5
1598#define TPECL16 6
1599#define TPECL17 7
1600
1601#define TPECR2  _SFR_MEM8(0x16D)
1602#define TPECL20 0
1603#define TPECL21 1
1604#define TPECL22 2
1605#define TPECL23 3
1606#define TPECL24 4
1607#define TPECL25 5
1608#define TPECL26 6
1609#define TPECL27 7
1610
1611#define TPECR3  _SFR_MEM8(0x16E)
1612#define TPECL30 0
1613#define TPECL31 1
1614#define TPECL32 2
1615#define TPECL33 3
1616#define TPECL34 4
1617#define TPECL35 5
1618#define TPECL36 6
1619#define TPECL37 7
1620
1621#define TPECR4  _SFR_MEM8(0x16F)
1622#define TPECL40 0
1623#define TPECL41 1
1624#define TPECL42 2
1625#define TPECL43 3
1626#define TPECL44 4
1627#define TPECL45 5
1628#define TPECL46 6
1629#define TPECL47 7
1630
1631#define TPECMR  _SFR_MEM8(0x170)
1632#define TPECM10 0
1633#define TPECM11 1
1634#define TPECM20 2
1635#define TPECM21 3
1636#define TPECM30 4
1637#define TPECM31 5
1638#define TPECM40 6
1639#define TPECM41 7
1640
1641#define TPCR3   _SFR_MEM8(0x171)
1642#define TPTD    0
1643#define TPRD    1
1644#define TPTLIW  2
1645#define TPRCD   5
1646
1647#define TPCR4   _SFR_MEM8(0x172)
1648#define TPBCCS0 0
1649#define TPBCCS1 1
1650#define TPBCCS2 2
1651#define TPBCCS3 3
1652#define TPBCM   4
1653
1654#define TPCR5   _SFR_MEM8(0x173)
1655#define TPMUD0  0
1656#define TPMUD1  1
1657#define TPMUD2  2
1658#define TPMD0   4
1659#define TPMD1   5
1660#define TPMD2   6
1661
1662/* Reserved [0x174] */
1663
1664#define TPCALR1 _SFR_MEM8(0x175)
1665#define TPBG_IREF0 0
1666#define TPBG_IREF1 1
1667#define TPBG_IREF2 2
1668#define TPBG_IREF3 3
1669#define TPBG_IREF4 4
1670#define TPBG_IREF5 5
1671
1672#define TPCALR2 _SFR_MEM8(0x176)
1673#define TPBG_UREF0 0
1674#define TPBG_UREF1 1
1675#define TPBG_UREF2 2
1676#define TPBG_UREF3 3
1677#define TPBG_UREF4 4
1678#define TPBG_UREF5 5
1679#define TPBG_UREF6 6
1680
1681#define TPCALR3 _SFR_MEM8(0x177)
1682#define LFVCC_TPCAL0 0
1683#define LFVCC_TPCAL1 1
1684#define LFVCC_TPCAL2 2
1685#define TPORTH0 3
1686#define TPORTH1 4
1687
1688#define TPCALR4 _SFR_MEM8(0x178)
1689#define TPINIT_CAL0 0
1690#define TPINIT_CAL1 1
1691#define TPINIT_CAL2 2
1692#define COMPVC_CAL0 3
1693#define COMPVC_CAL1 4
1694
1695#define TPCALR5 _SFR_MEM8(0x179)
1696
1697#define TPCALR6 _SFR_MEM8(0x17A)
1698
1699#define TPCALR7 _SFR_MEM8(0x17B)
1700
1701#define TPCALR8 _SFR_MEM8(0x17C)
1702
1703#define TPCALR9 _SFR_MEM8(0x17D)
1704
1705#define TPCALR10 _SFR_MEM8(0x17E)
1706
1707#define AESDPR  _SFR_MEM8(0x17F)
1708
1709#define AESKR   _SFR_MEM8(0x180)
1710
1711#define AESDR   _SFR_MEM8(0x181)
1712
1713#define GPIOR3  _SFR_MEM8(0x182)
1714
1715#define GPIOR4  _SFR_MEM8(0x183)
1716
1717#define GPIOR5  _SFR_MEM8(0x184)
1718
1719#define GPIOR6  _SFR_MEM8(0x185)
1720
1721#define GPIOR7  _SFR_MEM8(0x186)
1722
1723#define GPIOR8  _SFR_MEM8(0x187)
1724
1725#define PHBCRR  _SFR_MEM8(0x188)
1726
1727/* Reserved [0x189..0x18D] */
1728
1729#define LFCPR   _SFR_MEM8(0x18E)
1730#define LFCALP  0
1731#define LFCALRY 1
1732#define TPCD    6
1733#define LFCPCE  7
1734
1735#define LFIMR   _SFR_MEM8(0x18F)
1736#define LFSYDIM 0
1737#define LFDEIM  1
1738#define LFEOIM  2
1739
1740#define PHID0   _SFR_MEM16(0x190)
1741
1742#define PHID0L  _SFR_MEM8(0x194)
1743
1744#define PHID1   _SFR_MEM16(0x195)
1745
1746#define PHID1L  _SFR_MEM8(0x199)
1747
1748#define PHIDFR  _SFR_MEM8(0x19A)
1749
1750#define LFSYSY  _SFR_MEM16(0x19B)
1751
1752#define LFSYLE  _SFR_MEM8(0x19F)
1753#define LFSYLE0 0
1754#define LFSYLE1 1
1755#define LFSYLE2 2
1756#define LFSYLE3 3
1757#define LFSYLE4 4
1758#define LFSYLE5 5
1759
1760#define LFSTOP  _SFR_MEM8(0x1A0)
1761#define LFSTSY0 0
1762#define LFSTSY1 1
1763#define LFSTSY2 2
1764#define LFSTSY3 3
1765#define LFSTL0  4
1766#define LFSTL1  5
1767#define LFSTL2  6
1768
1769#define LTCOR   _SFR_MEM8(0x1A1)
1770
1771#define T1IFR   _SFR_MEM8(0x1A2)
1772#define T1OFF   0
1773#define T1COF   1
1774
1775/* Reserved [0x1A3] */
1776
1777#define PHTBLR  _SFR_MEM8(0x1A4)
1778
1779#define PHDFR   _SFR_MEM8(0x1A5)
1780
1781#define LTEMR   _SFR_MEM8(0x1A6)
1782#define ID0EM   0
1783#define ID1EM   1
1784#define IDFEM   2
1785#define DFEM    3
1786#define TBLEM   4
1787#define FLEM    5
1788#define EOFEM   6
1789#define LTCOF   7
1790
1791#define LFQC3   _SFR_MEM8(0x1A7)
1792#define LFQS30  0
1793#define LFQS31  1
1794#define LFQS32  2
1795#define LFQS33  3
1796#define LFCS30  4
1797#define LFCS31  5
1798#define LFCS32  6
1799#define LFCS33  7
1800
1801#define LFQC2   _SFR_MEM8(0x1A8)
1802#define LFQS20  0
1803#define LFQS21  1
1804#define LFQS22  2
1805#define LFQS23  3
1806#define LFCS20  4
1807#define LFCS21  5
1808#define LFCS22  6
1809#define LFCS23  7
1810
1811#define LFQC1   _SFR_MEM8(0x1A9)
1812#define LFQS10  0
1813#define LFQS11  1
1814#define LFQS12  2
1815#define LFQS13  3
1816#define LFCS10  4
1817#define LFCS11  5
1818#define LFCS12  6
1819#define LFCS13  7
1820
1821#define TW2BR   _SFR_MEM8(0x1AA)
1822
1823#define TW2CR   _SFR_MEM8(0x1AB)
1824#define TW2IE   0
1825#define TW2EN   2
1826#define TW2WC   3
1827#define TW2STO  4
1828#define TW2STA  5
1829#define TW2EA   6
1830#define TW2INT  7
1831
1832#define TW2SR   _SFR_MEM8(0x1AC)
1833#define TW2PS0  0
1834#define TW2PS1  1
1835#define TW2S0   3
1836#define TW2S1   4
1837#define TW2S2   5
1838#define TW2S3   6
1839#define TW2S4   7
1840
1841#define TW2DR   _SFR_MEM8(0x1AD)
1842
1843#define TW2AR   _SFR_MEM8(0x1AE)
1844#define TW2GCE  0
1845#define TW2A0   1
1846#define TW2A1   2
1847#define TW2A2   3
1848#define TW2A3   4
1849#define TW2A4   5
1850#define TW2A5   6
1851#define TW2A6   7
1852
1853#define TW2AMR  _SFR_MEM8(0x1AF)
1854#define TW2AM0  1
1855#define TW2AM1  2
1856#define TW2AM2  3
1857#define TW2AM3  4
1858#define TW2AM4  5
1859#define TW2AM5  6
1860#define TW2AM6  7
1861
1862#define RSCR    _SFR_MEM8(0x1B0)
1863#define RSSDEN  0
1864#define RSOS    1
1865#define RSEOR   2
1866#define RSOFM   3
1867#define RSMODE0 4
1868#define RSMODE1 5
1869#define RSRES   7
1870
1871#define RSSR    _SFR_MEM8(0x1B1)
1872#define RSRDY   0
1873#define RSSVLD  1
1874
1875#define RSMS1R  _SFR_MEM8(0x1B2)
1876#define RSCH1E  0
1877#define RSCH2E  1
1878#define RSCH3E  2
1879#define RSINTM  3
1880#define RSSTIM  4
1881#define RSCMS   5
1882#define RSSSV   6
1883#define RSSCAL  7
1884
1885#define RSMS2R  _SFR_MEM8(0x1B3)
1886#define RSSADR0 0
1887#define RSSADR1 1
1888#define RSSADR2 2
1889#define RSSADR3 3
1890#define RSAVGS0 4
1891#define RSAVGS1 5
1892#define RSAVGS2 6
1893#define RSAVGS3 7
1894
1895#define RSFR    _SFR_MEM8(0x1B4)
1896#define RSOOR1  0
1897#define RSOOR2  1
1898#define RSOOR3  2
1899#define RSOFF   3
1900#define RSAOOR1 5
1901#define RSAOOR2 6
1902#define RSAOOR3 7
1903
1904/* Reserved [0x1B5] */
1905
1906#define RSCALIB _SFR_MEM8(0x1B6)
1907#define RSCALIB0 0
1908#define RSCALIB1 1
1909#define RSCALIB2 2
1910#define RSCALIB3 3
1911#define RSCALIB4 4
1912#define RSCALIB5 5
1913#define RSCALIB6 6
1914#define RSCALIB7 7
1915
1916#define RSDLYR  _SFR_MEM8(0x1B7)
1917#define RSTRD0  0
1918#define RSTRD1  1
1919#define RSTRD2  2
1920#define RSTRD3  3
1921#define RSTRD4  4
1922#define RSTRD5  5
1923#define RSRD0   6
1924#define RSRD1   7
1925
1926#define RSRES1L _SFR_MEM8(0x1B8)
1927#define RSRES1L0 0
1928#define RSRES1L1 1
1929#define RSRES1L2 2
1930#define RSRES1L3 3
1931#define RSRES1L4 4
1932#define RSRES1L5 5
1933#define RSRES1L6 6
1934#define RSRES1L7 7
1935
1936#define RSRES1H _SFR_MEM8(0x1B9)
1937#define RSRES1H0 0
1938#define RSRES1H1 1
1939#define RSRES1H2 2
1940#define RSRES1H3 3
1941#define RSRES1H4 4
1942#define RSRES1H5 5
1943#define RSRES1H6 6
1944#define RSRES1H7 7
1945
1946#define RSRES2L _SFR_MEM8(0x1BA)
1947#define RSRES2L0 0
1948#define RSRES2L1 1
1949#define RSRES2L2 2
1950#define RSRES2L3 3
1951#define RSRES2L4 4
1952#define RSRES2L5 5
1953#define RSRES2L6 6
1954#define RSRES2L7 7
1955
1956#define RSRES2H _SFR_MEM8(0x1BB)
1957#define RSRES2H0 0
1958#define RSRES2H1 1
1959#define RSRES2H2 2
1960#define RSRES2H3 3
1961#define RSRES2H4 4
1962#define RSRES2H5 5
1963#define RSRES2H6 6
1964#define RSRES2H7 7
1965
1966#define RSRES3L _SFR_MEM8(0x1BC)
1967#define RSRES3L0 0
1968#define RSRES3L1 1
1969#define RSRES3L2 2
1970#define RSRES3L3 3
1971#define RSRES3L4 4
1972#define RSRES3L5 5
1973#define RSRES3L6 6
1974#define RSRES3L7 7
1975
1976#define RSRES3H _SFR_MEM8(0x1BD)
1977#define RSRES3H0 0
1978#define RSRES3H1 1
1979#define RSRES3H2 2
1980#define RSRES3H3 3
1981#define RSRES3H4 4
1982#define RSRES3H5 5
1983#define RSRES3H6 6
1984#define RSRES3H7 7
1985
1986#define RSRES4L _SFR_MEM8(0x1BE)
1987#define RSRES4L0 0
1988#define RSRES4L1 1
1989#define RSRES4L2 2
1990#define RSRES4L3 3
1991#define RSRES4L4 4
1992#define RSRES4L5 5
1993#define RSRES4L6 6
1994#define RSRES4L7 7
1995
1996#define RSRES4H _SFR_MEM8(0x1BF)
1997#define RSRES4H0 0
1998#define RSRES4H1 1
1999#define RSRES4H2 2
2000#define RSRES4H3 3
2001#define RSRES4H4 4
2002#define RSRES4H5 5
2003#define RSRES4H6 6
2004#define RSRES4H7 7
2005
2006#define RSSRCR  _SFR_MEM8(0x1C0)
2007#define SRCMODE0 0
2008#define SRCMODE1 1
2009#define SRCMIN0 2
2010#define SRCMIN1 3
2011#define SRCCLR  4
2012#define SRCSTEP0 6
2013#define SRCSTEP1 7
2014
2015#define SD12RR  _SFR_MEM8(0x1C1)
2016#define SD12RR0 0
2017#define SD12RR1 1
2018#define SD12RR2 2
2019#define SD12RR3 3
2020#define SD12RR4 4
2021#define SD12RR5 5
2022#define SD12RR6 6
2023#define SD12RR7 7
2024
2025#define SD13RR  _SFR_MEM8(0x1C2)
2026#define SD13RR0 0
2027#define SD13RR1 1
2028#define SD13RR2 2
2029#define SD13RR3 3
2030#define SD13RR4 4
2031#define SD13RR5 5
2032#define SD13RR6 6
2033#define SD13RR7 7
2034
2035#define SD23RR  _SFR_MEM8(0x1C3)
2036#define SD23RR0 0
2037#define SD23RR1 1
2038#define SD23RR2 2
2039#define SD23RR3 3
2040#define SD23RR4 4
2041#define SD23RR5 5
2042#define SD23RR6 6
2043#define SD23RR7 7
2044
2045#define SD360R  _SFR_MEM8(0x1C4)
2046#define SD360R0 0
2047#define SD360R1 1
2048#define SD360R2 2
2049#define SD360R3 3
2050#define SD360R4 4
2051#define SD360R5 5
2052#define SD360R6 6
2053#define SD360R7 7
2054
2055#define RSDBGR  _SFR_MEM8(0x1C5)
2056#define RSSANA  0
2057#define RSINFM  2
2058#define RSFPD   3
2059#define RSHOME  4
2060#define RSDBGS0 5
2061#define RSDBGS1 6
2062#define RSDBGEN 7
2063
2064/* Reserved [0x1C6..0x1D0] */
2065
2066#define LDFS    _SFR_MEM8(0x1D1)
2067#define LDFFLR  0
2068#define LDFUF   1
2069#define LDFOF   2
2070
2071#define T4IFR   _SFR_MEM8(0x1D2)
2072#define T4OFF   0
2073#define T4COF   1
2074#define T4ICF   2
2075
2076#define LDFWP   _SFR_MEM8(0x1D3)
2077#define LDFWP0  0
2078#define LDFWP1  1
2079#define LDFWP2  2
2080#define LDFWP3  3
2081#define LDFWP4  4
2082#define LDFWP5  5
2083
2084#define LDFRP   _SFR_MEM8(0x1D4)
2085#define LDFRP0  0
2086#define LDFRP1  1
2087#define LDFRP2  2
2088#define LDFRP3  3
2089#define LDFRP4  4
2090#define LDFRP5  5
2091
2092#define T5IFR   _SFR_MEM8(0x1D5)
2093#define T5OFF   0
2094#define T5COF   1
2095
2096#define LDFIM   _SFR_MEM8(0x1D6)
2097#define LDFFLIM 0
2098#define LDFEIM  1
2099
2100#define LDFC    _SFR_MEM8(0x1D7)
2101#define LDFFLC0 0
2102#define LDFFLC1 1
2103#define LDFFLC2 2
2104#define LDFFLC3 3
2105#define LDFFLC4 4
2106#define LDFFLC5 5
2107#define LDFMSB  6
2108
2109#define PHIMR   _SFR_MEM8(0x1D8)
2110#define PHTBLIM 1
2111#define PHDFIM  2
2112#define PHIDFIM 3
2113#define PHID0IM 4
2114#define PHID1IM 5
2115
2116#define PHCRCR  _SFR_MEM8(0x1D9)
2117#define CRCFR   2
2118#define CRCSE0  4
2119#define CRCSE1  5
2120#define CRCEN   7
2121
2122#define PHCST   _SFR_MEM8(0x1DA)
2123
2124/* Reserved [0x1DB] */
2125
2126/* Combine PHCRPL and PHCRPH */
2127#define PHCRP   _SFR_MEM16(0x1DC)
2128
2129#define PHCRPL  _SFR_MEM8(0x1DC)
2130#define PHCRPH  _SFR_MEM8(0x1DD)
2131
2132#define PHCSR   _SFR_MEM8(0x1DE)
2133
2134/* Reserved [0x1DF] */
2135
2136#define CRCDIR  _SFR_MEM8(0x1E0)
2137
2138#define T3IFR   _SFR_MEM8(0x1E1)
2139#define T3OFF   0
2140#define T3COF   1
2141#define T3ICF   2
2142
2143/* Reserved [0x1E2] */
2144
2145#define CMCR    _SFR_MEM8(0x1E3)
2146#define CMM0    0
2147#define CMM1    1
2148#define CMM2    2
2149#define CCS     3
2150#define CMONEN  6
2151#define CMCCE   7
2152
2153#define CMIMR   _SFR_MEM8(0x1E4)
2154#define ECIE    0
2155
2156#define CLPR    _SFR_MEM8(0x1E5)
2157#define CLKPS0  0
2158#define CLKPS1  1
2159#define CLKPS2  2
2160#define CLTPS0  3
2161#define CLTPS1  4
2162#define CLTPS2  5
2163#define CLPCE   7
2164
2165#define VMCR    _SFR_MEM8(0x1E6)
2166#define VMLS0   0
2167#define VMLS1   1
2168#define VMLS2   2
2169#define VMLS3   3
2170#define VMIM    4
2171#define VMPS0   5
2172#define VMPS1   6
2173#define VMRS    7
2174
2175#define DBONDR  _SFR_MEM8(0x1E7)
2176#define BBESD   0
2177#define AGND_BB 1
2178#define ISO_GND 2
2179#define AGND_LF 3
2180#define BTEST4  4
2181#define BTEST5  5
2182#define BTEST6  6
2183
2184#define CALRDYLF _SFR_MEM8(0x1E8)
2185
2186#define TW1BR   _SFR_MEM8(0x1E9)
2187
2188#define TW1CR   _SFR_MEM8(0x1EA)
2189#define TW1IE   0
2190#define TW1EN   2
2191#define TW1WC   3
2192#define TW1STO  4
2193#define TW1STA  5
2194#define TW1EA   6
2195#define TW1INT  7
2196
2197#define TW1SR   _SFR_MEM8(0x1EB)
2198#define TW1PS0  0
2199#define TW1PS1  1
2200#define TW1S0   3
2201#define TW1S1   4
2202#define TW1S2   5
2203#define TW1S3   6
2204#define TW1S4   7
2205
2206#define TW1DR   _SFR_MEM8(0x1EC)
2207
2208#define TW1AR   _SFR_MEM8(0x1ED)
2209#define TW1GCE  0
2210#define TW1A0   1
2211#define TW1A1   2
2212#define TW1A2   3
2213#define TW1A3   4
2214#define TW1A4   5
2215#define TW1A5   6
2216#define TW1A6   7
2217
2218#define TW1AMR  _SFR_MEM8(0x1EE)
2219#define TW1AM0  1
2220#define TW1AM1  2
2221#define TW1AM2  3
2222#define TW1AM3  4
2223#define TW1AM4  5
2224#define TW1AM5  6
2225#define TW1AM6  7
2226
2227#define PDSCR   _SFR_MEM8(0x1EF)
2228#define PDSC0   0
2229#define PDSC1   1
2230#define PDSC2   2
2231#define PDSC3   3
2232#define PDSC4   4
2233#define STBTEST 5
2234#define RSSISEL 6
2235#define ATBSEL  7
2236
2237#define TMOCR   _SFR_MEM8(0x1F0)
2238#define TO1PIS0 0
2239#define TO1PIS1 1
2240#define TO2PIS0 2
2241#define TO2PIS1 3
2242#define TO3PIS0 4
2243#define TO3PIS1 5
2244#define TO4PIS0 6
2245#define TO4PIS1 7
2246
2247#define SRCCAL  _SFR_MEM8(0x1F1)
2248#define SRCCAL1 0
2249#define SRCCAL2 1
2250#define SRCCAL3 2
2251#define SRCCAL4 3
2252#define SRCCAL5 4
2253#define SRCCAL6 5
2254#define SRCCAL7 6
2255#define SRCCAL8 7
2256
2257#define SRCTCAL _SFR_MEM8(0x1F2)
2258#define SRCTC0  0
2259#define SRCTC1  1
2260#define SRCTC2  2
2261#define SRCS0   3
2262#define SRCS1   4
2263#define DIS_SRC 6
2264#define HOLD_SRC 7
2265
2266#define SUPCA5  _SFR_MEM8(0x1F3)
2267#define IPTAT0  0
2268#define IPTAT1  1
2269#define IPTAT2  2
2270#define IPTAT3  3
2271#define IPTAT4  4
2272#define IPTAT5  5
2273
2274#define SUPCA6  _SFR_MEM8(0x1F4)
2275#define VBGTR0  0
2276#define VBGTR1  1
2277#define VBGTR2  2
2278#define VBGTR3  3
2279#define VBGTR4  4
2280#define VBGTR5  5
2281#define VBGTR6  6
2282#define VBGTR7  7
2283
2284#define SUPCA7  _SFR_MEM8(0x1F5)
2285#define VCCCAL0 0
2286#define VCCCAL1 1
2287#define VCCCAL2 2
2288#define LFVCCBD0 3
2289#define LFVCCBD1 4
2290#define LFVCCBD2 5
2291
2292#define SUPCA8  _SFR_MEM8(0x1F6)
2293#define VSWBD0  0
2294#define VSWBD1  1
2295#define VSWBD2  2
2296#define DVCCBD0 3
2297#define DVCCBD1 4
2298#define DVCCBD2 5
2299
2300#define SUPCA9  _SFR_MEM8(0x1F7)
2301#define VMEM0   0
2302#define VMEM1   1
2303#define VMEM2   2
2304#define VMEM3   3
2305#define VMEM4   4
2306#define VMEM5   5
2307#define VMEM6   6
2308#define VMEM7   7
2309
2310#define SUPCA10 _SFR_MEM8(0x1F8)
2311
2312#define TPCALR11 _SFR_MEM8(0x1F9)
2313#define MTBTR0  0
2314#define MTBTR1  1
2315#define ENDVBD  2
2316#define ENLFBD  3
2317#define ENVSWBD 4
2318#define TPCALR115 5
2319#define TPCALR116 6
2320#define TPCALR117 7
2321
2322#define TPCALR12 _SFR_MEM8(0x1FA)
2323#define TPDMOD  0
2324#define TPCALR121 1
2325#define TPCALR122 2
2326#define TPCALR123 3
2327#define TPCALR124 4
2328#define TPCALR125 5
2329#define TPCALR126 6
2330#define TPCALR127 7
2331
2332#define TPCALR13 _SFR_MEM8(0x1FB)
2333
2334/* Reserved [0x1FC..0x1FD] */
2335
2336#define PMTER   _SFR_MEM8(0x1FE)
2337
2338#define SRCCALL _SFR_MEM8(0x1FF)
2339#define SRCCAL0 0
2340
2341
2342
2343/* Interrupt vectors */
2344/* Vector 0 is the reset vector */
2345/* External Interrupt Request 0 */
2346#define INT0_vect            _VECTOR(1)
2347#define INT0_vect_num        1
2348
2349/* External Interrupt Request 1 */
2350#define INT1_vect            _VECTOR(2)
2351#define INT1_vect_num        2
2352
2353/* Pin Change Interrupt Request 0 */
2354#define PCI0_vect            _VECTOR(3)
2355#define PCI0_vect_num        3
2356
2357/* Pin Change Interrupt Request 1 */
2358#define PCI1_vect            _VECTOR(4)
2359#define PCI1_vect_num        4
2360
2361/* Voltage Monitoring Interrupt */
2362#define VMON_vect            _VECTOR(5)
2363#define VMON_vect_num        5
2364
2365/* AVCC Reset Interrupt */
2366#define AVCCR_vect            _VECTOR(6)
2367#define AVCCR_vect_num        6
2368
2369/* AVCC Low Interrupt */
2370#define AVCCL_vect            _VECTOR(7)
2371#define AVCCL_vect_num        7
2372
2373/* Timer0 Interval Interrupt */
2374#define T0INT_vect            _VECTOR(8)
2375#define T0INT_vect_num        8
2376
2377/* Timer/Counter1 Compare Match Interrupt */
2378#define T1COMP_vect            _VECTOR(9)
2379#define T1COMP_vect_num        9
2380
2381/* Timer/Counter1 Overflow Interrupt */
2382#define T1OVF_vect            _VECTOR(10)
2383#define T1OVF_vect_num        10
2384
2385/* Timer/Counter2 Compare Match Interrupt */
2386#define T2COMP_vect            _VECTOR(11)
2387#define T2COMP_vect_num        11
2388
2389/* Timer/Counter2 Overflow Interrupt */
2390#define T2OVF_vect            _VECTOR(12)
2391#define T2OVF_vect_num        12
2392
2393/* Timer/Counter3 Capture Event Interrupt */
2394#define T3CAP_vect            _VECTOR(13)
2395#define T3CAP_vect_num        13
2396
2397/* Timer/Counter3 Compare Match Interrupt */
2398#define T3COMP_vect            _VECTOR(14)
2399#define T3COMP_vect_num        14
2400
2401/* Timer/Counter3 Overflow Interrupt */
2402#define T3OVF_vect            _VECTOR(15)
2403#define T3OVF_vect_num        15
2404
2405/* Timer/Counter4 Capture Event Interrupt */
2406#define T4CAP_vect            _VECTOR(16)
2407#define T4CAP_vect_num        16
2408
2409/* Timer/Counter4 Compare Match Interrupt */
2410#define T4COMP_vect            _VECTOR(17)
2411#define T4COMP_vect_num        17
2412
2413/* Timer/Counter4 Overflow Interrupt */
2414#define T4OVF_vect            _VECTOR(18)
2415#define T4OVF_vect_num        18
2416
2417/* Timer/Counter5 Compare Match Interrupt */
2418#define T5COMP_vect            _VECTOR(19)
2419#define T5COMP_vect_num        19
2420
2421/* Timer/Counter5 Overflow Interrupt */
2422#define T5OVF_vect            _VECTOR(20)
2423#define T5OVF_vect_num        20
2424
2425/* SPI Serial Transfer Complete Interrupt */
2426#define SPI_vect            _VECTOR(21)
2427#define SPI_vect_num        21
2428
2429/* SPI Rx Buffer Interrupt */
2430#define SRX_FIFO_vect            _VECTOR(22)
2431#define SRX_FIFO_vect_num        22
2432
2433/* SPI Tx Buffer Interrupt */
2434#define STX_FIFO_vect            _VECTOR(23)
2435#define STX_FIFO_vect_num        23
2436
2437/* Sequencer State Machine Interrupt */
2438#define SSM_vect            _VECTOR(24)
2439#define SSM_vect_num        24
2440
2441/* Data FIFO fill level reached Interrupt */
2442#define DFFLR_vect            _VECTOR(25)
2443#define DFFLR_vect_num        25
2444
2445/* Data FIFO overflow or underflow error Interrupt */
2446#define DFOUE_vect            _VECTOR(26)
2447#define DFOUE_vect_num        26
2448
2449/* RSSI/Preamble FIFO fill level reached Interrupt */
2450#define SFFLR_vect            _VECTOR(27)
2451#define SFFLR_vect_num        27
2452
2453/* RSSI/Preamble FIFO overflow or underflow error Interrupt */
2454#define SFOUE_vect            _VECTOR(28)
2455#define SFOUE_vect_num        28
2456
2457/* Tx Modulator Telegram Finish Interrupt */
2458#define TMTCF_vect            _VECTOR(29)
2459#define TMTCF_vect_num        29
2460
2461/* AES Krypto Unit Interrupt */
2462#define AES_vect            _VECTOR(30)
2463#define AES_vect_num        30
2464
2465/* Transponder Mode Interrupt */
2466#define TPINT_vect            _VECTOR(31)
2467#define TPINT_vect_num        31
2468
2469/* Transponder Timeout Error Interrupt */
2470#define TPTOERR_vect            _VECTOR(32)
2471#define TPTOERR_vect_num        32
2472
2473/* LF receiver Identifier 0 Interrupt */
2474#define LFID0INT_vect            _VECTOR(33)
2475#define LFID0INT_vect_num        33
2476
2477/* LF receiver Identifier 1 Interrupt */
2478#define LFID1INT_vect            _VECTOR(34)
2479#define LFID1INT_vect_num        34
2480
2481/* LF receiver Frame End Interrupt */
2482#define LFFEINT_vect            _VECTOR(35)
2483#define LFFEINT_vect_num        35
2484
2485/* LF receiver Bit Count Reached Interrupt */
2486#define LFBCR_vect            _VECTOR(36)
2487#define LFBCR_vect_num        36
2488
2489/* LF receiver PreBurst Detected Interrupt */
2490#define LFPBD_vect            _VECTOR(37)
2491#define LFPBD_vect_num        37
2492
2493/* LF receiver Decoder Error Interrupt */
2494#define LFDE_vect            _VECTOR(38)
2495#define LFDE_vect_num        38
2496
2497/* LF receiver End of Telegram Interrupt */
2498#define LFEOT_vect            _VECTOR(39)
2499#define LFEOT_vect_num        39
2500
2501/* LF receiver Timer Compare Match Interrupt */
2502#define LFTCOR_vect            _VECTOR(40)
2503#define LFTCOR_vect_num        40
2504
2505/* LF receiver RSSI measurement Interrupt */
2506#define LFRSCO_vect            _VECTOR(41)
2507#define LFRSCO_vect_num        41
2508
2509/* LF Data FIFO Fill Level Reached Interrupt */
2510#define LDFFLR_vect            _VECTOR(42)
2511#define LDFFLR_vect_num        42
2512
2513/* LF Data FIFO Overflow or Underflow Error Interrupt */
2514#define LDFOUE_vect            _VECTOR(43)
2515#define LDFOUE_vect_num        43
2516
2517/* External input Clock monitoring Interrupt */
2518#define EXCM_vect            _VECTOR(44)
2519#define EXCM_vect_num        44
2520
2521/* EEPROM Error Correction Interrupt */
2522#define E2CINT_vect            _VECTOR(45)
2523#define E2CINT_vect_num        45
2524
2525/* EEPROM Ready Interrupt */
2526#define ERDY_vect            _VECTOR(46)
2527#define ERDY_vect_num        46
2528
2529/* Store Program Memory Ready */
2530#define SPMR_vect            _VECTOR(47)
2531#define SPMR_vect_num        47
2532
2533/* TWI1 Interrupt */
2534#define TWI1_vect            _VECTOR(48)
2535#define TWI1_vect_num        48
2536
2537/* SPI2 Interrupt */
2538#define SPI2_vect            _VECTOR(49)
2539#define SPI2_vect_num        49
2540
2541/* TWI2 Interrupt */
2542#define TWI2_vect            _VECTOR(50)
2543#define TWI2_vect_num        50
2544
2545#define _VECTORS_SIZE 204
2546
2547
2548/* Constants */
2549
2550#define SPM_PAGESIZE 64
2551#define FLASHSTART   0x8000
2552#define FLASHEND     0xFFFF
2553#define RAMSTART     0x0200
2554#define RAMSIZE      1024
2555#define RAMEND       0x05FF
2556#define E2START     0
2557#define E2SIZE      2176
2558#define E2PAGESIZE  16
2559#define E2END       0x087F
2560#define XRAMEND      RAMEND
2561
2562
2563/* Fuses */
2564
2565#define FUSE_MEMORY_SIZE 1
2566
2567/* Fuse Byte */
2568#define FUSE_PCEE1       (unsigned char)~_BV(0)
2569#define FUSE_EEACC       (unsigned char)~_BV(1)
2570#define FUSE_BOOTRST     (unsigned char)~_BV(2)
2571#define FUSE_EESAVE      (unsigned char)~_BV(3)
2572#define FUSE_WDTON       (unsigned char)~_BV(4)
2573#define FUSE_SPIEN       (unsigned char)~_BV(5)
2574#define FUSE_DWEN        (unsigned char)~_BV(6)
2575#define FUSE_CKDIV8      (unsigned char)~_BV(7)
2576#define LFUSE_DEFAULT    (FUSE_SPIEN)
2577
2578
2579
2580/* Lock Bits */
2581#define __LOCK_BITS_EXIST
2582
2583
2584/* Signature */
2585#define SIGNATURE_0 0x1E
2586#define SIGNATURE_1 0x95
2587#define SIGNATURE_2 0x69
2588
2589
2590#endif /* #ifdef _AVR_ATA5702M322_H_INCLUDED */
2591
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