| 1 | /***************************************************************************** |
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| 2 | * |
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| 3 | * Copyright (C) 2016 Atmel Corporation |
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| 4 | * All rights reserved. |
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| 5 | * |
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| 6 | * Redistribution and use in source and binary forms, with or without |
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| 7 | * modification, are permitted provided that the following conditions are met: |
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| 8 | * |
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| 9 | * * Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * |
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| 12 | * * Redistributions in binary form must reproduce the above copyright |
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| 13 | * notice, this list of conditions and the following disclaimer in |
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| 14 | * the documentation and/or other materials provided with the |
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| 15 | * distribution. |
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| 16 | * |
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| 17 | * * Neither the name of the copyright holders nor the names of |
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| 18 | * contributors may be used to endorse or promote products derived |
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| 19 | * from this software without specific prior written permission. |
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| 20 | * |
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| 21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 22 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 24 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 25 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 31 | * POSSIBILITY OF SUCH DAMAGE. |
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| 32 | ****************************************************************************/ |
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| 33 | |
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| 34 | |
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| 35 | #ifndef _AVR_ATA5782_H_INCLUDED |
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| 36 | #define _AVR_ATA5782_H_INCLUDED |
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| 37 | |
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| 38 | |
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| 39 | #ifndef _AVR_IO_H_ |
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| 40 | # error "Include <avr/io.h> instead of this file." |
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| 41 | #endif |
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| 42 | |
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| 43 | #ifndef _AVR_IOXXX_H_ |
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| 44 | # define _AVR_IOXXX_H_ "ioa5782.h" |
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| 45 | #else |
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| 46 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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| 47 | #endif |
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| 48 | |
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| 49 | /* Registers and associated bit numbers */ |
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| 50 | |
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| 51 | #define PRR0 _SFR_IO8(0x01) |
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| 52 | #define PRSPI 0 |
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| 53 | #define PRRXDC 1 |
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| 54 | #define PRTXDC 2 |
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| 55 | #define PRCRC 3 |
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| 56 | #define PRVM 4 |
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| 57 | #define PRCO 5 |
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| 58 | |
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| 59 | #define __AVR_HAVE_PRR0 ((1<<PRSPI)|(1<<PRRXDC)|(1<<PRTXDC)|(1<<PRCRC)|(1<<PRVM)|(1<<PRCO)) |
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| 60 | #define __AVR_HAVE_PRR0_PRSPI |
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| 61 | #define __AVR_HAVE_PRR0_PRRXDC |
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| 62 | #define __AVR_HAVE_PRR0_PRTXDC |
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| 63 | #define __AVR_HAVE_PRR0_PRCRC |
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| 64 | #define __AVR_HAVE_PRR0_PRVM |
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| 65 | #define __AVR_HAVE_PRR0_PRCO |
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| 66 | |
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| 67 | #define PRR1 _SFR_IO8(0x02) |
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| 68 | #define PRT1 0 |
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| 69 | #define PRT2 1 |
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| 70 | #define PRT3 2 |
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| 71 | #define PRT4 3 |
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| 72 | #define PRT5 4 |
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| 73 | |
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| 74 | #define __AVR_HAVE_PRR1 ((1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRT4)|(1<<PRT5)) |
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| 75 | #define __AVR_HAVE_PRR1_PRT1 |
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| 76 | #define __AVR_HAVE_PRR1_PRT2 |
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| 77 | #define __AVR_HAVE_PRR1_PRT3 |
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| 78 | #define __AVR_HAVE_PRR1_PRT4 |
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| 79 | #define __AVR_HAVE_PRR1_PRT5 |
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| 80 | |
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| 81 | #define PRR2 _SFR_IO8(0x03) |
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| 82 | #define PRXB 0 |
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| 83 | #define PRXA 1 |
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| 84 | #define PRSF 2 |
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| 85 | #define PRDF 3 |
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| 86 | #define PRIDS 4 |
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| 87 | #define PRRS 5 |
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| 88 | #define PRSSM 7 |
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| 89 | |
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| 90 | #define __AVR_HAVE_PRR2 ((1<<PRXB)|(1<<PRXA)|(1<<PRSF)|(1<<PRDF)|(1<<PRIDS)|(1<<PRRS)|(1<<PRSSM)) |
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| 91 | #define __AVR_HAVE_PRR2_PRXB |
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| 92 | #define __AVR_HAVE_PRR2_PRXA |
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| 93 | #define __AVR_HAVE_PRR2_PRSF |
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| 94 | #define __AVR_HAVE_PRR2_PRDF |
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| 95 | #define __AVR_HAVE_PRR2_PRIDS |
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| 96 | #define __AVR_HAVE_PRR2_PRRS |
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| 97 | #define __AVR_HAVE_PRR2_PRSSM |
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| 98 | |
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| 99 | #define RDPR _SFR_IO8(0x04) |
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| 100 | #define PRPTB 0 |
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| 101 | #define PRPTA 1 |
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| 102 | #define PRFLT 2 |
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| 103 | #define PRTMP 3 |
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| 104 | #define APRPTB 4 |
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| 105 | #define APRPTA 5 |
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| 106 | #define ARDPRF 6 |
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| 107 | #define RDPRF 7 |
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| 108 | |
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| 109 | #define PINB _SFR_IO8(0x05) |
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| 110 | #define PINB7 7 |
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| 111 | #define PINB6 6 |
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| 112 | #define PINB5 5 |
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| 113 | #define PINB4 4 |
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| 114 | #define PINB3 3 |
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| 115 | #define PINB2 2 |
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| 116 | #define PINB1 1 |
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| 117 | #define PINB0 0 |
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| 118 | |
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| 119 | #define DDRB _SFR_IO8(0x06) |
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| 120 | #define DDRB7 7 |
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| 121 | // Inserted "DDB7" from "DDRB7" due to compatibility |
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| 122 | #define DDB7 7 |
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| 123 | #define DDRB6 6 |
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| 124 | // Inserted "DDB6" from "DDRB6" due to compatibility |
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| 125 | #define DDB6 6 |
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| 126 | #define DDRB5 5 |
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| 127 | // Inserted "DDB5" from "DDRB5" due to compatibility |
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| 128 | #define DDB5 5 |
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| 129 | #define DDRB4 4 |
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| 130 | // Inserted "DDB4" from "DDRB4" due to compatibility |
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| 131 | #define DDB4 4 |
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| 132 | #define DDRB3 3 |
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| 133 | // Inserted "DDB3" from "DDRB3" due to compatibility |
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| 134 | #define DDB3 3 |
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| 135 | #define DDRB2 2 |
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| 136 | // Inserted "DDB2" from "DDRB2" due to compatibility |
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| 137 | #define DDB2 2 |
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| 138 | #define DDRB1 1 |
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| 139 | // Inserted "DDB1" from "DDRB1" due to compatibility |
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| 140 | #define DDB1 1 |
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| 141 | #define DDRB0 0 |
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| 142 | // Inserted "DDB0" from "DDRB0" due to compatibility |
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| 143 | #define DDB0 0 |
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| 144 | |
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| 145 | #define PORTB _SFR_IO8(0x07) |
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| 146 | #define PORTB7 7 |
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| 147 | #define PORTB6 6 |
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| 148 | #define PORTB5 5 |
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| 149 | #define PORTB4 4 |
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| 150 | #define PORTB3 3 |
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| 151 | #define PORTB2 2 |
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| 152 | #define PORTB1 1 |
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| 153 | #define PORTB0 0 |
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| 154 | |
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| 155 | #define PINC _SFR_IO8(0x08) |
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| 156 | #define PINC5 5 |
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| 157 | #define PINC4 4 |
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| 158 | #define PINC3 3 |
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| 159 | #define PINC2 2 |
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| 160 | #define PINC1 1 |
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| 161 | #define PINC0 0 |
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| 162 | |
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| 163 | #define DDRC _SFR_IO8(0x09) |
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| 164 | #define DDRC5 5 |
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| 165 | // Inserted "DDC5" from "DDRC5" due to compatibility |
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| 166 | #define DDC5 5 |
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| 167 | #define DDRC4 4 |
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| 168 | // Inserted "DDC4" from "DDRC4" due to compatibility |
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| 169 | #define DDC4 4 |
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| 170 | #define DDRC3 3 |
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| 171 | // Inserted "DDC3" from "DDRC3" due to compatibility |
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| 172 | #define DDC3 3 |
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| 173 | #define DDRC2 2 |
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| 174 | // Inserted "DDC2" from "DDRC2" due to compatibility |
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| 175 | #define DDC2 2 |
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| 176 | #define DDRC1 1 |
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| 177 | // Inserted "DDC1" from "DDRC1" due to compatibility |
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| 178 | #define DDC1 1 |
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| 179 | #define DDRC0 0 |
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| 180 | // Inserted "DDC0" from "DDRC0" due to compatibility |
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| 181 | #define DDC0 0 |
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| 182 | |
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| 183 | #define PORTC _SFR_IO8(0x0A) |
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| 184 | #define PORTC5 5 |
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| 185 | #define PORTC4 4 |
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| 186 | #define PORTC3 3 |
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| 187 | #define PORTC2 2 |
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| 188 | #define PORTC1 1 |
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| 189 | #define PORTC0 0 |
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| 190 | |
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| 191 | /* Reserved [0x0B..0x0C] */ |
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| 192 | |
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| 193 | #define RDSIFR _SFR_IO8(0x0D) |
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| 194 | #define NBITA 0 |
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| 195 | #define NBITB 1 |
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| 196 | #define EOTA 2 |
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| 197 | #define EOTB 3 |
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| 198 | #define SOTA 4 |
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| 199 | #define SOTB 5 |
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| 200 | #define WCOA 6 |
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| 201 | #define WCOB 7 |
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| 202 | |
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| 203 | #define MCUCR _SFR_IO8(0x0E) |
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| 204 | #define IVCE 0 |
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| 205 | #define IVSEL 1 |
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| 206 | #define SPIIO 2 |
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| 207 | #define ENPS 3 |
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| 208 | #define PUD 4 |
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| 209 | #define PB4HS 5 |
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| 210 | #define PB7LS 6 |
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| 211 | #define PB7HS 7 |
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| 212 | |
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| 213 | #define PCIFR _SFR_IO8(0x0F) |
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| 214 | #define PCIF0 0 |
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| 215 | #define PCIF1 1 |
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| 216 | |
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| 217 | #define T0CR _SFR_IO8(0x10) |
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| 218 | #define T0PS0 0 |
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| 219 | #define T0PS1 1 |
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| 220 | #define T0PS2 2 |
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| 221 | #define T0IE 3 |
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| 222 | #define T0PR 4 |
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| 223 | |
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| 224 | #define T1CR _SFR_IO8(0x11) |
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| 225 | #define T1OTM 0 |
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| 226 | #define T1CTM 1 |
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| 227 | #define T1CRM 2 |
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| 228 | #define T1TOP 4 |
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| 229 | #define T1RES 5 |
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| 230 | #define T1TOS 6 |
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| 231 | #define T1ENA 7 |
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| 232 | |
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| 233 | #define T2CR _SFR_IO8(0x12) |
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| 234 | #define T2OTM 0 |
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| 235 | #define T2CTM 1 |
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| 236 | #define T2CRM 2 |
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| 237 | #define T2TOP 4 |
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| 238 | #define T2RES 5 |
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| 239 | #define T2TOS 6 |
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| 240 | #define T2ENA 7 |
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| 241 | |
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| 242 | #define T3CR _SFR_IO8(0x13) |
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| 243 | #define T3OTM 0 |
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| 244 | #define T3CTM 1 |
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| 245 | #define T3CRM 2 |
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| 246 | #define T3CPRM 3 |
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| 247 | #define T3TOP 4 |
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| 248 | #define T3RES 5 |
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| 249 | #define T3TOS 6 |
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| 250 | #define T3ENA 7 |
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| 251 | |
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| 252 | #define T4CR _SFR_IO8(0x14) |
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| 253 | #define T4OTM 0 |
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| 254 | #define T4CTM 1 |
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| 255 | #define T4CRM 2 |
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| 256 | #define T4CPRM 3 |
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| 257 | #define T4TOP 4 |
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| 258 | #define T4RES 5 |
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| 259 | #define T4TOS 6 |
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| 260 | #define T4ENA 7 |
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| 261 | |
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| 262 | #define T1IFR _SFR_IO8(0x15) |
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| 263 | #define T1OFF 0 |
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| 264 | #define T1COF 1 |
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| 265 | |
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| 266 | #define T2IFR _SFR_IO8(0x16) |
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| 267 | #define T2OFF 0 |
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| 268 | #define T2COF 1 |
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| 269 | |
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| 270 | #define T3IFR _SFR_IO8(0x17) |
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| 271 | #define T3OFF 0 |
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| 272 | #define T3COF 1 |
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| 273 | #define T3ICF 2 |
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| 274 | |
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| 275 | #define T4IFR _SFR_IO8(0x18) |
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| 276 | #define T4OFF 0 |
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| 277 | #define T4COF 1 |
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| 278 | #define T4ICF 2 |
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| 279 | |
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| 280 | #define T5IFR _SFR_IO8(0x19) |
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| 281 | #define T5OFF 0 |
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| 282 | #define T5COF 1 |
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| 283 | |
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| 284 | #define GPIOR0 _SFR_IO8(0x1A) |
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| 285 | |
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| 286 | #define GPIOR3 _SFR_IO8(0x1B) |
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| 287 | |
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| 288 | #define GPIOR4 _SFR_IO8(0x1C) |
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| 289 | |
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| 290 | #define GPIOR5 _SFR_IO8(0x1D) |
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| 291 | |
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| 292 | #define GPIOR6 _SFR_IO8(0x1E) |
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| 293 | |
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| 294 | #define EECR _SFR_IO8(0x1F) |
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| 295 | #define EERE 0 |
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| 296 | #define EEWE 1 |
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| 297 | #define EEMWE 2 |
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| 298 | #define EERIE 3 |
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| 299 | #define EEPM0 4 |
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| 300 | #define EEPM1 5 |
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| 301 | #define EEPAGE 6 |
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| 302 | #define NVMBSY 7 |
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| 303 | |
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| 304 | #define EEDR _SFR_IO8(0x20) |
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| 305 | |
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| 306 | /* Combine EEARL and EEARH */ |
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| 307 | #define EEAR _SFR_IO16(0x21) |
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| 308 | |
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| 309 | #define EEARL _SFR_IO8(0x21) |
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| 310 | #define EEARH _SFR_IO8(0x22) |
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| 311 | |
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| 312 | #define EEPR _SFR_IO8(0x23) |
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| 313 | #define EEAP0 0 |
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| 314 | #define EEAP1 1 |
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| 315 | #define EEAP2 2 |
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| 316 | #define EEAP3 3 |
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| 317 | |
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| 318 | #define GPIOR1 _SFR_IO8(0x24) |
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| 319 | |
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| 320 | #define GPIOR2 _SFR_IO8(0x25) |
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| 321 | |
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| 322 | #define PCICR _SFR_IO8(0x26) |
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| 323 | #define PCIE0 0 |
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| 324 | #define PCIE1 1 |
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| 325 | |
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| 326 | #define EIMSK _SFR_IO8(0x27) |
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| 327 | #define INT0 0 |
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| 328 | #define INT1 1 |
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| 329 | |
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| 330 | #define EIFR _SFR_IO8(0x28) |
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| 331 | #define INTF0 0 |
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| 332 | #define INTF1 1 |
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| 333 | |
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| 334 | #define CRCDIR _SFR_IO8(0x29) |
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| 335 | |
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| 336 | #define VMCSR _SFR_IO8(0x2A) |
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| 337 | #define VMLS0 0 |
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| 338 | #define VMLS1 1 |
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| 339 | #define VMLS2 2 |
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| 340 | #define VMLS3 3 |
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| 341 | #define VMIM 4 |
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| 342 | #define VMF 5 |
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| 343 | |
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| 344 | #define MCUSR _SFR_IO8(0x2B) |
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| 345 | #define PORF 0 |
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| 346 | #define EXTRF 1 |
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| 347 | #define WDRF 3 |
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| 348 | |
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| 349 | #define SPCR _SFR_IO8(0x2C) |
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| 350 | #define SPR0 0 |
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| 351 | #define SPR1 1 |
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| 352 | #define CPHA 2 |
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| 353 | #define CPOL 3 |
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| 354 | #define MSTR 4 |
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| 355 | #define DORD 5 |
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| 356 | #define SPE 6 |
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| 357 | #define SPIE 7 |
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| 358 | |
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| 359 | #define SPSR _SFR_IO8(0x2D) |
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| 360 | #define SPI2X 0 |
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| 361 | #define RXIF 4 |
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| 362 | #define TXIF 5 |
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| 363 | #define SPIF 7 |
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| 364 | |
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| 365 | #define SPDR _SFR_IO8(0x2E) |
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| 366 | |
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| 367 | #define T0IFR _SFR_IO8(0x2F) |
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| 368 | #define T0F 0 |
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| 369 | |
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| 370 | /* Reserved [0x30] */ |
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| 371 | |
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| 372 | #define DWDR _SFR_IO8(0x31) |
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| 373 | |
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| 374 | /* Reserved [0x32] */ |
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| 375 | |
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| 376 | #define RDCR _SFR_IO8(0x33) |
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| 377 | #define RDPU 0 |
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| 378 | #define ADIVEN 1 |
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| 379 | #define RDEN 2 |
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| 380 | |
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| 381 | #define EOTSA _SFR_IO8(0x34) |
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| 382 | #define CARFA 0 |
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| 383 | #define AMPFA 1 |
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| 384 | #define SYTFA 2 |
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| 385 | #define MANFA 3 |
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| 386 | #define TMOFA 4 |
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| 387 | #define TELRA 5 |
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| 388 | #define RRFA 6 |
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| 389 | #define EOTBF 7 |
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| 390 | |
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| 391 | #define EOTCA _SFR_IO8(0x35) |
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| 392 | #define CARFEA 0 |
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| 393 | #define AMPFEA 1 |
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| 394 | #define SYTFEA 2 |
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| 395 | #define MANFEA 3 |
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| 396 | #define TMOFEA 4 |
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| 397 | #define TELREA 5 |
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| 398 | #define RRFEA 6 |
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| 399 | #define EOTBFE 7 |
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| 400 | |
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| 401 | #define EOTSB _SFR_IO8(0x36) |
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| 402 | #define CARFB 0 |
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| 403 | #define AMPFB 1 |
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| 404 | #define SYTFB 2 |
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| 405 | #define MANFB 3 |
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| 406 | #define TMOFB 4 |
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| 407 | #define TELRB 5 |
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| 408 | #define RRFB 6 |
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| 409 | #define EOTAF 7 |
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| 410 | |
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| 411 | #define EOTCB _SFR_IO8(0x37) |
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| 412 | #define CARFEB 0 |
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| 413 | #define AMPFEB 1 |
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| 414 | #define SYTFEB 2 |
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| 415 | #define MANFEB 3 |
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| 416 | #define TMOFEB 4 |
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| 417 | #define TELREB 5 |
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| 418 | #define RRFEB 6 |
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| 419 | #define EOTAFE 7 |
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| 420 | |
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| 421 | #define SMCR _SFR_IO8(0x38) |
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| 422 | #define SE 0 |
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| 423 | #define SM0 1 |
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| 424 | #define SM1 2 |
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| 425 | #define SM2 3 |
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| 426 | |
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| 427 | #define CMCR _SFR_IO8(0x39) |
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| 428 | #define CMM0 0 |
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| 429 | #define CMM1 1 |
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| 430 | #define CMM2 2 |
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| 431 | #define CCS 3 |
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| 432 | #define SRCD 4 |
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| 433 | #define CMONEN 6 |
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| 434 | #define CMCCE 7 |
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| 435 | |
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| 436 | #define CMIMR _SFR_IO8(0x3A) |
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| 437 | #define ECIE 0 |
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| 438 | |
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| 439 | #define CLPR _SFR_IO8(0x3B) |
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| 440 | #define CLKPS0 0 |
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| 441 | #define CLKPS1 1 |
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| 442 | #define CLKPS2 2 |
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| 443 | #define CLTPS0 3 |
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| 444 | #define CLTPS1 4 |
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| 445 | #define CLTPS2 5 |
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| 446 | #define CLPCE 7 |
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| 447 | |
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| 448 | #define SPMCSR _SFR_IO8(0x3C) |
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| 449 | #define SELFPRGEN 0 |
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| 450 | #define PGERS 1 |
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| 451 | #define PGWRT 2 |
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| 452 | #define BLBSET 3 |
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| 453 | #define SPMIE 7 |
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| 454 | |
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| 455 | /* SP [0x3D..0x3E] */ |
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| 456 | |
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| 457 | /* SREG [0x3F] */ |
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| 458 | |
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| 459 | #define FSEN _SFR_MEM8(0x60) |
|---|
| 460 | #define SDPU 0 |
|---|
| 461 | #define SDEN 1 |
|---|
| 462 | |
|---|
| 463 | /* Reserved [0x61..0x63] */ |
|---|
| 464 | |
|---|
| 465 | #define FFREQ1L _SFR_MEM8(0x64) |
|---|
| 466 | |
|---|
| 467 | #define FFREQ1M _SFR_MEM8(0x65) |
|---|
| 468 | |
|---|
| 469 | #define FFREQ1H _SFR_MEM8(0x66) |
|---|
| 470 | |
|---|
| 471 | #define FFREQ2L _SFR_MEM8(0x67) |
|---|
| 472 | |
|---|
| 473 | #define FFREQ2M _SFR_MEM8(0x68) |
|---|
| 474 | |
|---|
| 475 | #define FFREQ2H _SFR_MEM8(0x69) |
|---|
| 476 | |
|---|
| 477 | /* Reserved [0x6A] */ |
|---|
| 478 | |
|---|
| 479 | #define EICRA _SFR_MEM8(0x6B) |
|---|
| 480 | #define ISC00 0 |
|---|
| 481 | #define ISC01 1 |
|---|
| 482 | #define ISC10 2 |
|---|
| 483 | #define ISC11 3 |
|---|
| 484 | |
|---|
| 485 | #define PCMSK0 _SFR_MEM8(0x6C) |
|---|
| 486 | #define PCINT0 0 |
|---|
| 487 | #define PCINT1 1 |
|---|
| 488 | #define PCINT2 2 |
|---|
| 489 | #define PCINT3 3 |
|---|
| 490 | #define PCINT4 4 |
|---|
| 491 | #define PCINT5 5 |
|---|
| 492 | #define PCINT6 6 |
|---|
| 493 | #define PCINT7 7 |
|---|
| 494 | |
|---|
| 495 | #define PCMSK1 _SFR_MEM8(0x6D) |
|---|
| 496 | #define PCINT8 0 |
|---|
| 497 | #define PCINT9 1 |
|---|
| 498 | #define PCINT10 2 |
|---|
| 499 | #define PCINT11 3 |
|---|
| 500 | #define PCINT12 4 |
|---|
| 501 | #define PCINT13 5 |
|---|
| 502 | |
|---|
| 503 | #define WDTCR _SFR_MEM8(0x6E) |
|---|
| 504 | #define WDPS0 0 |
|---|
| 505 | #define WDPS1 1 |
|---|
| 506 | #define WDPS2 2 |
|---|
| 507 | #define WDE 3 |
|---|
| 508 | #define WDCE 4 |
|---|
| 509 | |
|---|
| 510 | #define T1CNT _SFR_MEM8(0x6F) |
|---|
| 511 | |
|---|
| 512 | #define T1COR _SFR_MEM8(0x70) |
|---|
| 513 | |
|---|
| 514 | #define T1MR _SFR_MEM8(0x71) |
|---|
| 515 | #define T1CS0 0 |
|---|
| 516 | #define T1CS1 1 |
|---|
| 517 | #define T1PS0 2 |
|---|
| 518 | #define T1PS1 3 |
|---|
| 519 | #define T1PS2 4 |
|---|
| 520 | #define T1PS3 5 |
|---|
| 521 | #define T1DC0 6 |
|---|
| 522 | #define T1DC1 7 |
|---|
| 523 | |
|---|
| 524 | #define T1IMR _SFR_MEM8(0x72) |
|---|
| 525 | #define T1OIM 0 |
|---|
| 526 | #define T1CIM 1 |
|---|
| 527 | |
|---|
| 528 | #define T2CNT _SFR_MEM8(0x73) |
|---|
| 529 | |
|---|
| 530 | #define T2COR _SFR_MEM8(0x74) |
|---|
| 531 | |
|---|
| 532 | #define T2MR _SFR_MEM8(0x75) |
|---|
| 533 | #define T2CS0 0 |
|---|
| 534 | #define T2CS1 1 |
|---|
| 535 | #define T2PS0 2 |
|---|
| 536 | #define T2PS1 3 |
|---|
| 537 | #define T2PS2 4 |
|---|
| 538 | #define T2PS3 5 |
|---|
| 539 | #define T2DC0 6 |
|---|
| 540 | #define T2DC1 7 |
|---|
| 541 | |
|---|
| 542 | #define T2IMR _SFR_MEM8(0x76) |
|---|
| 543 | #define T2OIM 0 |
|---|
| 544 | #define T2CIM 1 |
|---|
| 545 | |
|---|
| 546 | /* Combine T3CNTL and T3CNTH */ |
|---|
| 547 | #define T3CNT _SFR_MEM16(0x77) |
|---|
| 548 | |
|---|
| 549 | #define T3CNTL _SFR_MEM8(0x77) |
|---|
| 550 | #define T3CNTH _SFR_MEM8(0x78) |
|---|
| 551 | |
|---|
| 552 | /* Combine T3CORL and T3CORH */ |
|---|
| 553 | #define T3COR _SFR_MEM16(0x79) |
|---|
| 554 | |
|---|
| 555 | #define T3CORL _SFR_MEM8(0x79) |
|---|
| 556 | #define T3CORH _SFR_MEM8(0x7A) |
|---|
| 557 | |
|---|
| 558 | /* Combine T3ICRL and T3ICRH */ |
|---|
| 559 | #define T3ICR _SFR_MEM16(0x7B) |
|---|
| 560 | |
|---|
| 561 | #define T3ICRL _SFR_MEM8(0x7B) |
|---|
| 562 | #define T3ICRH _SFR_MEM8(0x7C) |
|---|
| 563 | |
|---|
| 564 | #define T3MRA _SFR_MEM8(0x7D) |
|---|
| 565 | #define T3CS0 0 |
|---|
| 566 | #define T3CS1 1 |
|---|
| 567 | #define T3PS0 2 |
|---|
| 568 | #define T3PS1 3 |
|---|
| 569 | #define T3PS2 4 |
|---|
| 570 | |
|---|
| 571 | #define T3MRB _SFR_MEM8(0x7E) |
|---|
| 572 | #define T3SCE 1 |
|---|
| 573 | #define T3CNC 2 |
|---|
| 574 | #define T3CE0 3 |
|---|
| 575 | #define T3CE1 4 |
|---|
| 576 | #define T3ICS0 5 |
|---|
| 577 | #define T3ICS1 6 |
|---|
| 578 | #define T3ICS2 7 |
|---|
| 579 | |
|---|
| 580 | #define T3IMR _SFR_MEM8(0x7F) |
|---|
| 581 | #define T3OIM 0 |
|---|
| 582 | #define T3CIM 1 |
|---|
| 583 | #define T3CPIM 2 |
|---|
| 584 | |
|---|
| 585 | /* Combine T4CNTL and T4CNTH */ |
|---|
| 586 | #define T4CNT _SFR_MEM16(0x80) |
|---|
| 587 | |
|---|
| 588 | #define T4CNTL _SFR_MEM8(0x80) |
|---|
| 589 | #define T4CNTH _SFR_MEM8(0x81) |
|---|
| 590 | |
|---|
| 591 | /* Combine T4CORL and T4CORH */ |
|---|
| 592 | #define T4COR _SFR_MEM16(0x82) |
|---|
| 593 | |
|---|
| 594 | #define T4CORL _SFR_MEM8(0x82) |
|---|
| 595 | #define T4CORH _SFR_MEM8(0x83) |
|---|
| 596 | |
|---|
| 597 | /* Combine T4ICRL and T4ICRH */ |
|---|
| 598 | #define T4ICR _SFR_MEM16(0x84) |
|---|
| 599 | |
|---|
| 600 | #define T4ICRL _SFR_MEM8(0x84) |
|---|
| 601 | #define T4ICRH _SFR_MEM8(0x85) |
|---|
| 602 | |
|---|
| 603 | #define T4MRA _SFR_MEM8(0x86) |
|---|
| 604 | #define T4CS0 0 |
|---|
| 605 | #define T4CS1 1 |
|---|
| 606 | #define T4PS0 2 |
|---|
| 607 | #define T4PS1 3 |
|---|
| 608 | #define T4PS2 4 |
|---|
| 609 | |
|---|
| 610 | #define T4MRB _SFR_MEM8(0x87) |
|---|
| 611 | #define T4SCE 1 |
|---|
| 612 | #define T4CNC 2 |
|---|
| 613 | #define T4CE0 3 |
|---|
| 614 | #define T4CE1 4 |
|---|
| 615 | #define T4ICS0 5 |
|---|
| 616 | #define T4ICS1 6 |
|---|
| 617 | #define T4ICS2 7 |
|---|
| 618 | |
|---|
| 619 | #define T4IMR _SFR_MEM8(0x88) |
|---|
| 620 | #define T4OIM 0 |
|---|
| 621 | #define T4CIM 1 |
|---|
| 622 | #define T4CPIM 2 |
|---|
| 623 | |
|---|
| 624 | /* Reserved [0x89] */ |
|---|
| 625 | |
|---|
| 626 | /* Combine T5OCRL and T5OCRH */ |
|---|
| 627 | #define T5OCR _SFR_MEM16(0x8A) |
|---|
| 628 | |
|---|
| 629 | #define T5OCRL _SFR_MEM8(0x8A) |
|---|
| 630 | #define T5OCRH _SFR_MEM8(0x8B) |
|---|
| 631 | |
|---|
| 632 | #define T5CCR _SFR_MEM8(0x8C) |
|---|
| 633 | #define T5CS0 0 |
|---|
| 634 | #define T5CS1 1 |
|---|
| 635 | #define T5CS2 2 |
|---|
| 636 | #define T5CTC 3 |
|---|
| 637 | |
|---|
| 638 | /* Combine T5CNTL and T5CNTH */ |
|---|
| 639 | #define T5CNT _SFR_MEM16(0x8D) |
|---|
| 640 | |
|---|
| 641 | #define T5CNTL _SFR_MEM8(0x8D) |
|---|
| 642 | #define T5CNTH _SFR_MEM8(0x8E) |
|---|
| 643 | |
|---|
| 644 | #define T5IMR _SFR_MEM8(0x8F) |
|---|
| 645 | #define T5OIM 0 |
|---|
| 646 | #define T5CIM 1 |
|---|
| 647 | |
|---|
| 648 | #define GTCCR _SFR_MEM8(0x90) |
|---|
| 649 | #define PSR10 0 |
|---|
| 650 | #define TSM 7 |
|---|
| 651 | |
|---|
| 652 | #define SOTSB _SFR_MEM8(0x91) |
|---|
| 653 | #define CAROB 0 |
|---|
| 654 | #define AMPOB 1 |
|---|
| 655 | #define SYTOB 2 |
|---|
| 656 | #define MANOB 3 |
|---|
| 657 | #define WUPOB 4 |
|---|
| 658 | #define SFIDOB 5 |
|---|
| 659 | #define RROB 6 |
|---|
| 660 | #define WCOAO 7 |
|---|
| 661 | |
|---|
| 662 | #define SOTSA _SFR_MEM8(0x92) |
|---|
| 663 | #define CAROA 0 |
|---|
| 664 | #define AMPOA 1 |
|---|
| 665 | #define SYTOA 2 |
|---|
| 666 | #define MANOA 3 |
|---|
| 667 | #define WUPOA 4 |
|---|
| 668 | #define SFIDOA 5 |
|---|
| 669 | #define RROA 6 |
|---|
| 670 | #define WCOBO 7 |
|---|
| 671 | |
|---|
| 672 | #define SOTCB _SFR_MEM8(0x93) |
|---|
| 673 | #define CAROEB 0 |
|---|
| 674 | #define AMPOEB 1 |
|---|
| 675 | #define SYTOEB 2 |
|---|
| 676 | #define MANOEB 3 |
|---|
| 677 | #define WUPEB 4 |
|---|
| 678 | #define SFIDEB 5 |
|---|
| 679 | #define RROEB 6 |
|---|
| 680 | #define WCOAOE 7 |
|---|
| 681 | |
|---|
| 682 | #define SOTCA _SFR_MEM8(0x94) |
|---|
| 683 | #define CAROEA 0 |
|---|
| 684 | #define AMPOEA 1 |
|---|
| 685 | #define SYTOEA 2 |
|---|
| 686 | #define MANOEA 3 |
|---|
| 687 | #define WUPEA 4 |
|---|
| 688 | #define SFIDEA 5 |
|---|
| 689 | #define RROEA 6 |
|---|
| 690 | #define WCOBOE 7 |
|---|
| 691 | |
|---|
| 692 | #define TESRB _SFR_MEM8(0x95) |
|---|
| 693 | #define CRCOB 0 |
|---|
| 694 | #define EOTLB0 1 |
|---|
| 695 | #define EOTLB1 2 |
|---|
| 696 | |
|---|
| 697 | #define TESRA _SFR_MEM8(0x96) |
|---|
| 698 | #define CRCOA 0 |
|---|
| 699 | #define EOTLA0 1 |
|---|
| 700 | #define EOTLA1 2 |
|---|
| 701 | |
|---|
| 702 | /* Reserved [0x97] */ |
|---|
| 703 | |
|---|
| 704 | #define RDSIMR _SFR_MEM8(0x98) |
|---|
| 705 | #define NBITAM 0 |
|---|
| 706 | #define NBITBM 1 |
|---|
| 707 | #define EOTAM 2 |
|---|
| 708 | #define EOTBM 3 |
|---|
| 709 | #define SOTAM 4 |
|---|
| 710 | #define SOTBM 5 |
|---|
| 711 | #define WCOAM 6 |
|---|
| 712 | #define WCOBM 7 |
|---|
| 713 | |
|---|
| 714 | #define RDOCR _SFR_MEM8(0x99) |
|---|
| 715 | #define TMDS0 1 |
|---|
| 716 | #define TMDS1 2 |
|---|
| 717 | #define ETRPA 3 |
|---|
| 718 | #define ETRPB 4 |
|---|
| 719 | #define RDSIDA 5 |
|---|
| 720 | #define RDSIDB 6 |
|---|
| 721 | |
|---|
| 722 | /* Reserved [0x9A] */ |
|---|
| 723 | |
|---|
| 724 | #define TEMPL _SFR_MEM8(0x9B) |
|---|
| 725 | |
|---|
| 726 | #define TEMPH _SFR_MEM8(0x9C) |
|---|
| 727 | |
|---|
| 728 | #define SYCB _SFR_MEM8(0x9D) |
|---|
| 729 | #define SYCSB0 0 |
|---|
| 730 | #define SYCSB1 1 |
|---|
| 731 | #define SYCSB2 2 |
|---|
| 732 | #define SYCSB3 3 |
|---|
| 733 | #define SYTLB0 4 |
|---|
| 734 | #define SYTLB1 5 |
|---|
| 735 | #define SYTLB2 6 |
|---|
| 736 | #define SYTLB3 7 |
|---|
| 737 | |
|---|
| 738 | #define SYCA _SFR_MEM8(0x9E) |
|---|
| 739 | #define SYCSA0 0 |
|---|
| 740 | #define SYCSA1 1 |
|---|
| 741 | #define SYCSA2 2 |
|---|
| 742 | #define SYCSA3 3 |
|---|
| 743 | #define SYTLA0 4 |
|---|
| 744 | #define SYTLA1 5 |
|---|
| 745 | #define SYTLA2 6 |
|---|
| 746 | #define SYTLA3 7 |
|---|
| 747 | |
|---|
| 748 | #define RXFOB _SFR_MEM8(0x9F) |
|---|
| 749 | |
|---|
| 750 | #define RXFOA _SFR_MEM8(0xA0) |
|---|
| 751 | |
|---|
| 752 | #define DMMB _SFR_MEM8(0xA1) |
|---|
| 753 | #define DMATB0 0 |
|---|
| 754 | #define DMATB1 1 |
|---|
| 755 | #define DMATB2 2 |
|---|
| 756 | #define DMATB3 3 |
|---|
| 757 | #define DMATB4 4 |
|---|
| 758 | #define DMPB 5 |
|---|
| 759 | #define DMHB 6 |
|---|
| 760 | #define DMNEB 7 |
|---|
| 761 | |
|---|
| 762 | #define DMMA _SFR_MEM8(0xA2) |
|---|
| 763 | #define DMATA0 0 |
|---|
| 764 | #define DMATA1 1 |
|---|
| 765 | #define DMATA2 2 |
|---|
| 766 | #define DMATA3 3 |
|---|
| 767 | #define DMATA4 4 |
|---|
| 768 | #define DMPA 5 |
|---|
| 769 | #define DMHA 6 |
|---|
| 770 | #define DMNEA 7 |
|---|
| 771 | |
|---|
| 772 | #define DMCDB _SFR_MEM8(0xA3) |
|---|
| 773 | #define DMCLB0 0 |
|---|
| 774 | #define DMCLB1 1 |
|---|
| 775 | #define DMCLB2 2 |
|---|
| 776 | #define DMCLB3 3 |
|---|
| 777 | #define DMCLB4 4 |
|---|
| 778 | #define DMCTB0 5 |
|---|
| 779 | #define DMCTB1 6 |
|---|
| 780 | #define DMCTB2 7 |
|---|
| 781 | |
|---|
| 782 | #define DMCDA _SFR_MEM8(0xA4) |
|---|
| 783 | #define DMCLA0 0 |
|---|
| 784 | #define DMCLA1 1 |
|---|
| 785 | #define DMCLA2 2 |
|---|
| 786 | #define DMCLA3 3 |
|---|
| 787 | #define DMCLA4 4 |
|---|
| 788 | #define DMCTA0 5 |
|---|
| 789 | #define DMCTA1 6 |
|---|
| 790 | #define DMCTA2 7 |
|---|
| 791 | |
|---|
| 792 | #define DMCRB _SFR_MEM8(0xA5) |
|---|
| 793 | #define DMPGB0 0 |
|---|
| 794 | #define DMPGB1 1 |
|---|
| 795 | #define DMPGB2 2 |
|---|
| 796 | #define DMPGB3 3 |
|---|
| 797 | #define DMPGB4 4 |
|---|
| 798 | #define SASKB 5 |
|---|
| 799 | #define SY1TB 6 |
|---|
| 800 | #define DMARB 7 |
|---|
| 801 | |
|---|
| 802 | #define DMCRA _SFR_MEM8(0xA6) |
|---|
| 803 | #define DMPGA0 0 |
|---|
| 804 | #define DMPGA1 1 |
|---|
| 805 | #define DMPGA2 2 |
|---|
| 806 | #define DMPGA3 3 |
|---|
| 807 | #define DMPGA4 4 |
|---|
| 808 | #define SASKA 5 |
|---|
| 809 | #define SY1TA 6 |
|---|
| 810 | #define DMARA 7 |
|---|
| 811 | |
|---|
| 812 | #define DMDRB _SFR_MEM8(0xA7) |
|---|
| 813 | #define DMAB0 0 |
|---|
| 814 | #define DMAB1 1 |
|---|
| 815 | #define DMAB2 2 |
|---|
| 816 | #define DMAB3 3 |
|---|
| 817 | #define DMDNB0 4 |
|---|
| 818 | #define DMDNB1 5 |
|---|
| 819 | #define DMDNB2 6 |
|---|
| 820 | #define DMDNB3 7 |
|---|
| 821 | |
|---|
| 822 | #define DMDRA _SFR_MEM8(0xA8) |
|---|
| 823 | #define DMAA0 0 |
|---|
| 824 | #define DMAA1 1 |
|---|
| 825 | #define DMAA2 2 |
|---|
| 826 | #define DMAA3 3 |
|---|
| 827 | #define DMDNA0 4 |
|---|
| 828 | #define DMDNA1 5 |
|---|
| 829 | #define DMDNA2 6 |
|---|
| 830 | #define DMDNA3 7 |
|---|
| 831 | |
|---|
| 832 | #define CHCR _SFR_MEM8(0xA9) |
|---|
| 833 | #define BWM0 0 |
|---|
| 834 | #define BWM1 1 |
|---|
| 835 | #define BWM2 2 |
|---|
| 836 | #define BWM3 3 |
|---|
| 837 | |
|---|
| 838 | #define CHDN _SFR_MEM8(0xAA) |
|---|
| 839 | #define BBDN0 0 |
|---|
| 840 | #define BBDN1 1 |
|---|
| 841 | #define BBDN2 2 |
|---|
| 842 | #define BBDN3 3 |
|---|
| 843 | #define BBDN4 4 |
|---|
| 844 | #define ADCDN 5 |
|---|
| 845 | |
|---|
| 846 | #define SFIDCB _SFR_MEM8(0xAB) |
|---|
| 847 | #define SFIDTB0 0 |
|---|
| 848 | #define SFIDTB1 1 |
|---|
| 849 | #define SFIDTB2 2 |
|---|
| 850 | #define SFIDTB3 3 |
|---|
| 851 | #define SFIDTB4 4 |
|---|
| 852 | #define SEMEB 7 |
|---|
| 853 | |
|---|
| 854 | #define SFIDLB _SFR_MEM8(0xAC) |
|---|
| 855 | #define SFIDLB0 0 |
|---|
| 856 | #define SFIDLB1 1 |
|---|
| 857 | #define SFIDLB2 2 |
|---|
| 858 | #define SFIDLB3 3 |
|---|
| 859 | #define SFIDLB4 4 |
|---|
| 860 | #define SFIDLB5 5 |
|---|
| 861 | |
|---|
| 862 | #define WUPTB _SFR_MEM8(0xAD) |
|---|
| 863 | #define WUPTB0 0 |
|---|
| 864 | #define WUPTB1 1 |
|---|
| 865 | #define WUPTB2 2 |
|---|
| 866 | #define WUPTB3 3 |
|---|
| 867 | #define WUPTB4 4 |
|---|
| 868 | |
|---|
| 869 | #define WUPLB _SFR_MEM8(0xAE) |
|---|
| 870 | #define WUPLB0 0 |
|---|
| 871 | #define WUPLB1 1 |
|---|
| 872 | #define WUPLB2 2 |
|---|
| 873 | #define WUPLB3 3 |
|---|
| 874 | #define WUPLB4 4 |
|---|
| 875 | #define WUPLB5 5 |
|---|
| 876 | |
|---|
| 877 | #define SFID1B _SFR_MEM8(0xAF) |
|---|
| 878 | |
|---|
| 879 | #define SFID2B _SFR_MEM8(0xB0) |
|---|
| 880 | |
|---|
| 881 | #define SFID3B _SFR_MEM8(0xB1) |
|---|
| 882 | |
|---|
| 883 | #define SFID4B _SFR_MEM8(0xB2) |
|---|
| 884 | |
|---|
| 885 | #define WUP1B _SFR_MEM8(0xB3) |
|---|
| 886 | |
|---|
| 887 | #define WUP2B _SFR_MEM8(0xB4) |
|---|
| 888 | |
|---|
| 889 | #define WUP3B _SFR_MEM8(0xB5) |
|---|
| 890 | |
|---|
| 891 | #define WUP4B _SFR_MEM8(0xB6) |
|---|
| 892 | |
|---|
| 893 | #define SFIDCA _SFR_MEM8(0xB7) |
|---|
| 894 | #define SFIDTA0 0 |
|---|
| 895 | #define SFIDTA1 1 |
|---|
| 896 | #define SFIDTA2 2 |
|---|
| 897 | #define SFIDTA3 3 |
|---|
| 898 | #define SFIDTA4 4 |
|---|
| 899 | #define SEMEA 7 |
|---|
| 900 | |
|---|
| 901 | #define SFIDLA _SFR_MEM8(0xB8) |
|---|
| 902 | #define SFIDLA0 0 |
|---|
| 903 | #define SFIDLA1 1 |
|---|
| 904 | #define SFIDLA2 2 |
|---|
| 905 | #define SFIDLA3 3 |
|---|
| 906 | #define SFIDLA4 4 |
|---|
| 907 | #define SFIDLA5 5 |
|---|
| 908 | |
|---|
| 909 | #define WUPTA _SFR_MEM8(0xB9) |
|---|
| 910 | #define WUPTA0 0 |
|---|
| 911 | #define WUPTA1 1 |
|---|
| 912 | #define WUPTA2 2 |
|---|
| 913 | #define WUPTA3 3 |
|---|
| 914 | #define WUPTA4 4 |
|---|
| 915 | |
|---|
| 916 | #define WUPLA _SFR_MEM8(0xBA) |
|---|
| 917 | #define WUPLA0 0 |
|---|
| 918 | #define WUPLA1 1 |
|---|
| 919 | #define WUPLA2 2 |
|---|
| 920 | #define WUPLA3 3 |
|---|
| 921 | #define WUPLA4 4 |
|---|
| 922 | #define WUPLA5 5 |
|---|
| 923 | |
|---|
| 924 | #define SFID1A _SFR_MEM8(0xBB) |
|---|
| 925 | |
|---|
| 926 | #define SFID2A _SFR_MEM8(0xBC) |
|---|
| 927 | |
|---|
| 928 | #define SFID3A _SFR_MEM8(0xBD) |
|---|
| 929 | |
|---|
| 930 | #define SFID4A _SFR_MEM8(0xBE) |
|---|
| 931 | |
|---|
| 932 | #define WUP1A _SFR_MEM8(0xBF) |
|---|
| 933 | |
|---|
| 934 | #define WUP2A _SFR_MEM8(0xC0) |
|---|
| 935 | |
|---|
| 936 | #define WUP3A _SFR_MEM8(0xC1) |
|---|
| 937 | |
|---|
| 938 | #define WUP4A _SFR_MEM8(0xC2) |
|---|
| 939 | |
|---|
| 940 | #define CLKOD _SFR_MEM8(0xC3) |
|---|
| 941 | |
|---|
| 942 | #define CLKOCR _SFR_MEM8(0xC4) |
|---|
| 943 | #define CLKOS0 0 |
|---|
| 944 | #define CLKOS1 1 |
|---|
| 945 | #define CLKOEN 2 |
|---|
| 946 | |
|---|
| 947 | #define XFUSE _SFR_MEM8(0xC5) |
|---|
| 948 | |
|---|
| 949 | #define SRCCAL _SFR_MEM8(0xC6) |
|---|
| 950 | #define SRCCAL0 0 |
|---|
| 951 | #define SRCCAL1 1 |
|---|
| 952 | #define SRCCAL2 2 |
|---|
| 953 | #define SRCCAL3 3 |
|---|
| 954 | #define SRCCAL4 4 |
|---|
| 955 | #define SRCCAL5 5 |
|---|
| 956 | #define SRCTC0 6 |
|---|
| 957 | #define SRCTC1 7 |
|---|
| 958 | |
|---|
| 959 | #define FRCCAL _SFR_MEM8(0xC7) |
|---|
| 960 | #define FRCCAL0 0 |
|---|
| 961 | #define FRCCAL1 1 |
|---|
| 962 | #define FRCCAL2 2 |
|---|
| 963 | #define FRCCAL3 3 |
|---|
| 964 | #define FRCCAL4 4 |
|---|
| 965 | #define FRCTC 5 |
|---|
| 966 | |
|---|
| 967 | #define CMSR _SFR_MEM8(0xC8) |
|---|
| 968 | #define ECF 0 |
|---|
| 969 | |
|---|
| 970 | #define CMOCR _SFR_MEM8(0xC9) |
|---|
| 971 | #define FRCAO 0 |
|---|
| 972 | #define SRCAO 1 |
|---|
| 973 | #define FRCACT 2 |
|---|
| 974 | #define SRCACT 3 |
|---|
| 975 | |
|---|
| 976 | #define SUPFR _SFR_MEM8(0xCA) |
|---|
| 977 | #define AVCCRF 0 |
|---|
| 978 | #define AVCCLF 1 |
|---|
| 979 | |
|---|
| 980 | #define SUPCR _SFR_MEM8(0xCB) |
|---|
| 981 | #define AVCCRM 0 |
|---|
| 982 | #define AVCCLM 1 |
|---|
| 983 | #define PVEN 2 |
|---|
| 984 | #define DVDIS 4 |
|---|
| 985 | #define AVEN 5 |
|---|
| 986 | #define AVDIC 6 |
|---|
| 987 | |
|---|
| 988 | /* Reserved [0xCC] */ |
|---|
| 989 | |
|---|
| 990 | #define SUPCA2 _SFR_MEM8(0xCD) |
|---|
| 991 | #define BGCAL0 0 |
|---|
| 992 | #define BGCAL1 1 |
|---|
| 993 | #define BGCAL2 2 |
|---|
| 994 | #define BGCAL3 3 |
|---|
| 995 | |
|---|
| 996 | #define SUPCA3 _SFR_MEM8(0xCE) |
|---|
| 997 | #define ACAL4 0 |
|---|
| 998 | #define ACAL5 1 |
|---|
| 999 | #define ACAL6 2 |
|---|
| 1000 | #define ACAL7 3 |
|---|
| 1001 | #define DCAL4 4 |
|---|
| 1002 | #define DCAL5 5 |
|---|
| 1003 | #define DCAL6 6 |
|---|
| 1004 | |
|---|
| 1005 | #define SUPCA4 _SFR_MEM8(0xCF) |
|---|
| 1006 | #define ACAL0 0 |
|---|
| 1007 | #define ACAL1 1 |
|---|
| 1008 | #define ACAL2 2 |
|---|
| 1009 | #define ACAL3 3 |
|---|
| 1010 | #define DCAL0 4 |
|---|
| 1011 | #define DCAL1 5 |
|---|
| 1012 | #define DCAL2 6 |
|---|
| 1013 | #define DCAL3 7 |
|---|
| 1014 | |
|---|
| 1015 | #define CALRDY _SFR_MEM8(0xD0) |
|---|
| 1016 | |
|---|
| 1017 | #define VMCAL _SFR_MEM8(0xD1) |
|---|
| 1018 | #define VMCAL0 0 |
|---|
| 1019 | #define VMCAL1 1 |
|---|
| 1020 | #define VMCAL2 2 |
|---|
| 1021 | |
|---|
| 1022 | #define DFS _SFR_MEM8(0xD2) |
|---|
| 1023 | #define DFFLRF 0 |
|---|
| 1024 | #define DFUFL 1 |
|---|
| 1025 | #define DFOFL 2 |
|---|
| 1026 | |
|---|
| 1027 | /* Combine DFTLL and DFTLH */ |
|---|
| 1028 | #define DFTL _SFR_MEM16(0xD3) |
|---|
| 1029 | |
|---|
| 1030 | #define DFTLL _SFR_MEM8(0xD3) |
|---|
| 1031 | #define DFTLH _SFR_MEM8(0xD4) |
|---|
| 1032 | |
|---|
| 1033 | #define DFL _SFR_MEM8(0xD5) |
|---|
| 1034 | #define DFFLS0 0 |
|---|
| 1035 | #define DFFLS1 1 |
|---|
| 1036 | #define DFFLS2 2 |
|---|
| 1037 | #define DFFLS3 3 |
|---|
| 1038 | #define DFFLS4 4 |
|---|
| 1039 | #define DFFLS5 5 |
|---|
| 1040 | #define DFCLR 7 |
|---|
| 1041 | |
|---|
| 1042 | #define DFWP _SFR_MEM8(0xD6) |
|---|
| 1043 | #define DFWP0 0 |
|---|
| 1044 | #define DFWP1 1 |
|---|
| 1045 | #define DFWP2 2 |
|---|
| 1046 | #define DFWP3 3 |
|---|
| 1047 | #define DFWP4 4 |
|---|
| 1048 | #define DFWP5 5 |
|---|
| 1049 | |
|---|
| 1050 | #define DFRP _SFR_MEM8(0xD7) |
|---|
| 1051 | #define DFRP0 0 |
|---|
| 1052 | #define DFRP1 1 |
|---|
| 1053 | #define DFRP2 2 |
|---|
| 1054 | #define DFRP3 3 |
|---|
| 1055 | #define DFRP4 4 |
|---|
| 1056 | #define DFRP5 5 |
|---|
| 1057 | |
|---|
| 1058 | #define DFD _SFR_MEM8(0xD8) |
|---|
| 1059 | |
|---|
| 1060 | #define DFI _SFR_MEM8(0xD9) |
|---|
| 1061 | #define DFFLIM 0 |
|---|
| 1062 | #define DFERIM 1 |
|---|
| 1063 | |
|---|
| 1064 | #define DFC _SFR_MEM8(0xDA) |
|---|
| 1065 | #define DFFLC0 0 |
|---|
| 1066 | #define DFFLC1 1 |
|---|
| 1067 | #define DFFLC2 2 |
|---|
| 1068 | #define DFFLC3 3 |
|---|
| 1069 | #define DFFLC4 4 |
|---|
| 1070 | #define DFFLC5 5 |
|---|
| 1071 | #define DFDRA 7 |
|---|
| 1072 | |
|---|
| 1073 | #define SFS _SFR_MEM8(0xDB) |
|---|
| 1074 | #define SFFLRF 0 |
|---|
| 1075 | #define SFUFL 1 |
|---|
| 1076 | #define SFOFL 2 |
|---|
| 1077 | |
|---|
| 1078 | #define SFL _SFR_MEM8(0xDC) |
|---|
| 1079 | #define SFFLS0 0 |
|---|
| 1080 | #define SFFLS1 1 |
|---|
| 1081 | #define SFFLS2 2 |
|---|
| 1082 | #define SFFLS3 3 |
|---|
| 1083 | #define SFFLS4 4 |
|---|
| 1084 | #define SFCLR 7 |
|---|
| 1085 | |
|---|
| 1086 | #define SFWP _SFR_MEM8(0xDD) |
|---|
| 1087 | #define SFWP0 0 |
|---|
| 1088 | #define SFWP1 1 |
|---|
| 1089 | #define SFWP2 2 |
|---|
| 1090 | #define SFWP3 3 |
|---|
| 1091 | #define SFWP4 4 |
|---|
| 1092 | |
|---|
| 1093 | #define SFRP _SFR_MEM8(0xDE) |
|---|
| 1094 | #define SFRP0 0 |
|---|
| 1095 | #define SFRP1 1 |
|---|
| 1096 | #define SFRP2 2 |
|---|
| 1097 | #define SFRP3 3 |
|---|
| 1098 | #define SFRP4 4 |
|---|
| 1099 | |
|---|
| 1100 | #define SFD _SFR_MEM8(0xDF) |
|---|
| 1101 | |
|---|
| 1102 | #define SFI _SFR_MEM8(0xE0) |
|---|
| 1103 | #define SFFLIM 0 |
|---|
| 1104 | #define SFERIM 1 |
|---|
| 1105 | |
|---|
| 1106 | #define SFC _SFR_MEM8(0xE1) |
|---|
| 1107 | #define SFFLC0 0 |
|---|
| 1108 | #define SFFLC1 1 |
|---|
| 1109 | #define SFFLC2 2 |
|---|
| 1110 | #define SFFLC3 3 |
|---|
| 1111 | #define SFFLC4 4 |
|---|
| 1112 | #define SFDRA 7 |
|---|
| 1113 | |
|---|
| 1114 | #define SSMCR _SFR_MEM8(0xE2) |
|---|
| 1115 | #define SSMTX 0 |
|---|
| 1116 | #define SSMTM 1 |
|---|
| 1117 | #define SSMTGE 2 |
|---|
| 1118 | #define SSMTPE 3 |
|---|
| 1119 | #define SSMPVE 4 |
|---|
| 1120 | #define SSMTAE 5 |
|---|
| 1121 | #define SETRPA 6 |
|---|
| 1122 | #define SETRPB 7 |
|---|
| 1123 | |
|---|
| 1124 | #define SSMRCR _SFR_MEM8(0xE3) |
|---|
| 1125 | #define SSMPA 0 |
|---|
| 1126 | #define SSMPB 1 |
|---|
| 1127 | #define SSMADA 2 |
|---|
| 1128 | #define SSMADB 3 |
|---|
| 1129 | #define SSMPVS 4 |
|---|
| 1130 | #define SSMIFA 5 |
|---|
| 1131 | #define SSMIDSE 6 |
|---|
| 1132 | #define SSMTMOE 7 |
|---|
| 1133 | |
|---|
| 1134 | #define SSMFBR _SFR_MEM8(0xE4) |
|---|
| 1135 | #define SSMFID0 0 |
|---|
| 1136 | #define SSMFID1 1 |
|---|
| 1137 | #define SSMFID2 2 |
|---|
| 1138 | #define SSMDFDT 3 |
|---|
| 1139 | #define SSMHADT 4 |
|---|
| 1140 | #define SSMPLDT 5 |
|---|
| 1141 | |
|---|
| 1142 | #define SSMRR _SFR_MEM8(0xE5) |
|---|
| 1143 | #define SSMR 0 |
|---|
| 1144 | #define SSMST 1 |
|---|
| 1145 | |
|---|
| 1146 | #define SSMSR _SFR_MEM8(0xE6) |
|---|
| 1147 | #define SSMESM0 0 |
|---|
| 1148 | #define SSMESM1 1 |
|---|
| 1149 | #define SSMESM2 2 |
|---|
| 1150 | #define SSMESM3 3 |
|---|
| 1151 | #define SSMERR 7 |
|---|
| 1152 | |
|---|
| 1153 | #define SSMIFR _SFR_MEM8(0xE7) |
|---|
| 1154 | #define SSMIF 0 |
|---|
| 1155 | |
|---|
| 1156 | #define SSMIMR _SFR_MEM8(0xE8) |
|---|
| 1157 | #define SSMIM 0 |
|---|
| 1158 | |
|---|
| 1159 | #define MSMSTR _SFR_MEM8(0xE9) |
|---|
| 1160 | #define SSMMST0 0 |
|---|
| 1161 | #define SSMMST1 1 |
|---|
| 1162 | #define SSMMST2 2 |
|---|
| 1163 | #define SSMMST3 3 |
|---|
| 1164 | #define SSMMST4 4 |
|---|
| 1165 | |
|---|
| 1166 | #define SSMSTR _SFR_MEM8(0xEA) |
|---|
| 1167 | #define SSMSTA0 0 |
|---|
| 1168 | #define SSMSTA1 1 |
|---|
| 1169 | #define SSMSTA2 2 |
|---|
| 1170 | #define SSMSTA3 3 |
|---|
| 1171 | #define SSMSTA4 4 |
|---|
| 1172 | #define SSMSTA5 5 |
|---|
| 1173 | |
|---|
| 1174 | #define SSMXSR _SFR_MEM8(0xEB) |
|---|
| 1175 | #define SSMSTB0 0 |
|---|
| 1176 | #define SSMSTB1 1 |
|---|
| 1177 | #define SSMSTB2 2 |
|---|
| 1178 | #define SSMSTB3 3 |
|---|
| 1179 | #define SSMSTB4 4 |
|---|
| 1180 | #define SSMSTB5 5 |
|---|
| 1181 | |
|---|
| 1182 | #define MSMCR1 _SFR_MEM8(0xEC) |
|---|
| 1183 | #define MSMSM00 0 |
|---|
| 1184 | #define MSMSM01 1 |
|---|
| 1185 | #define MSMSM02 2 |
|---|
| 1186 | #define MSMSM03 3 |
|---|
| 1187 | #define MSMSM10 4 |
|---|
| 1188 | #define MSMSM11 5 |
|---|
| 1189 | #define MSMSM12 6 |
|---|
| 1190 | #define MSMSM13 7 |
|---|
| 1191 | |
|---|
| 1192 | #define MSMCR2 _SFR_MEM8(0xED) |
|---|
| 1193 | #define MSMSM20 0 |
|---|
| 1194 | #define MSMSM21 1 |
|---|
| 1195 | #define MSMSM22 2 |
|---|
| 1196 | #define MSMSM23 3 |
|---|
| 1197 | #define MSMSM30 4 |
|---|
| 1198 | #define MSMSM31 5 |
|---|
| 1199 | #define MSMSM32 6 |
|---|
| 1200 | #define MSMSM33 7 |
|---|
| 1201 | |
|---|
| 1202 | #define MSMCR3 _SFR_MEM8(0xEE) |
|---|
| 1203 | #define MSMSM40 0 |
|---|
| 1204 | #define MSMSM41 1 |
|---|
| 1205 | #define MSMSM42 2 |
|---|
| 1206 | #define MSMSM43 3 |
|---|
| 1207 | #define MSMSM50 4 |
|---|
| 1208 | #define MSMSM51 5 |
|---|
| 1209 | #define MSMSM52 6 |
|---|
| 1210 | #define MSMSM53 7 |
|---|
| 1211 | |
|---|
| 1212 | #define MSMCR4 _SFR_MEM8(0xEF) |
|---|
| 1213 | #define MSMSM60 0 |
|---|
| 1214 | #define MSMSM61 1 |
|---|
| 1215 | #define MSMSM62 2 |
|---|
| 1216 | #define MSMSM63 3 |
|---|
| 1217 | #define MSMSM70 4 |
|---|
| 1218 | #define MSMSM71 5 |
|---|
| 1219 | #define MSMSM72 6 |
|---|
| 1220 | #define MSMSM73 7 |
|---|
| 1221 | |
|---|
| 1222 | #define GTCR _SFR_MEM8(0xF0) |
|---|
| 1223 | #define RXTEHA 0 |
|---|
| 1224 | #define GAPMA 1 |
|---|
| 1225 | #define DARA 2 |
|---|
| 1226 | #define IWUPA 3 |
|---|
| 1227 | #define RXTEHB 4 |
|---|
| 1228 | #define GAPMB 5 |
|---|
| 1229 | #define DARB 6 |
|---|
| 1230 | #define IWUPB 7 |
|---|
| 1231 | |
|---|
| 1232 | #define SOTC1A _SFR_MEM8(0xF1) |
|---|
| 1233 | #define CAROEA1 0 |
|---|
| 1234 | #define AMPOEA1 1 |
|---|
| 1235 | #define SYTOEA1 2 |
|---|
| 1236 | #define MANOEA1 3 |
|---|
| 1237 | #define WUPEA1 4 |
|---|
| 1238 | #define SFIDEA1 5 |
|---|
| 1239 | #define RROEA1 6 |
|---|
| 1240 | #define WCOBOE1 7 |
|---|
| 1241 | |
|---|
| 1242 | #define SOTC2A _SFR_MEM8(0xF2) |
|---|
| 1243 | #define CAROEA2 0 |
|---|
| 1244 | #define AMPOEA2 1 |
|---|
| 1245 | #define SYTOEA2 2 |
|---|
| 1246 | #define MANOEA2 3 |
|---|
| 1247 | #define WUPEA2 4 |
|---|
| 1248 | #define SFIDEA2 5 |
|---|
| 1249 | #define RROEA2 6 |
|---|
| 1250 | #define WCOBOE2 7 |
|---|
| 1251 | |
|---|
| 1252 | #define SOTC1B _SFR_MEM8(0xF3) |
|---|
| 1253 | #define CAROEB1 0 |
|---|
| 1254 | #define AMPOEB1 1 |
|---|
| 1255 | #define SYTOEB1 2 |
|---|
| 1256 | #define MANOEB1 3 |
|---|
| 1257 | #define WUPEB1 4 |
|---|
| 1258 | #define SFIDEB1 5 |
|---|
| 1259 | #define RROEB1 6 |
|---|
| 1260 | #define WCOAOE1 7 |
|---|
| 1261 | |
|---|
| 1262 | #define SOTC2B _SFR_MEM8(0xF4) |
|---|
| 1263 | #define CAROEB2 0 |
|---|
| 1264 | #define AMPOEB2 1 |
|---|
| 1265 | #define SYTOEB2 2 |
|---|
| 1266 | #define MANOEB2 3 |
|---|
| 1267 | #define WUPEB2 4 |
|---|
| 1268 | #define SFIDEB2 5 |
|---|
| 1269 | #define RROEB2 6 |
|---|
| 1270 | #define WCOAOE2 7 |
|---|
| 1271 | |
|---|
| 1272 | #define EOTC1A _SFR_MEM8(0xF5) |
|---|
| 1273 | #define CARFEA1 0 |
|---|
| 1274 | #define AMPFEA1 1 |
|---|
| 1275 | #define SYTFEA1 2 |
|---|
| 1276 | #define MANFEA1 3 |
|---|
| 1277 | #define TMOFEA1 4 |
|---|
| 1278 | #define TELREA1 5 |
|---|
| 1279 | #define RRFEA1 6 |
|---|
| 1280 | #define EOTBFE1 7 |
|---|
| 1281 | |
|---|
| 1282 | #define EOTC2A _SFR_MEM8(0xF6) |
|---|
| 1283 | #define CARFEA2 0 |
|---|
| 1284 | #define AMPFEA2 1 |
|---|
| 1285 | #define SYTFEA2 2 |
|---|
| 1286 | #define MANFEA2 3 |
|---|
| 1287 | #define TMOFEA2 4 |
|---|
| 1288 | #define TELREA2 5 |
|---|
| 1289 | #define RRFEA2 6 |
|---|
| 1290 | #define EOTBFE2 7 |
|---|
| 1291 | |
|---|
| 1292 | #define EOTC3A _SFR_MEM8(0xF7) |
|---|
| 1293 | #define CARFEA3 0 |
|---|
| 1294 | #define AMPFEA3 1 |
|---|
| 1295 | #define SYTFEA3 2 |
|---|
| 1296 | #define MANFEA3 3 |
|---|
| 1297 | #define TMOFEA3 4 |
|---|
| 1298 | #define TELREA3 5 |
|---|
| 1299 | #define RRFEA3 6 |
|---|
| 1300 | #define EOTBFE3 7 |
|---|
| 1301 | |
|---|
| 1302 | #define EOTC1B _SFR_MEM8(0xF8) |
|---|
| 1303 | #define CARFEB1 0 |
|---|
| 1304 | #define AMPFEB1 1 |
|---|
| 1305 | #define SYTFEB1 2 |
|---|
| 1306 | #define MANFEB1 3 |
|---|
| 1307 | #define TMOFEB1 4 |
|---|
| 1308 | #define TELREB1 5 |
|---|
| 1309 | #define RRFEB1 6 |
|---|
| 1310 | #define EOTAFE1 7 |
|---|
| 1311 | |
|---|
| 1312 | #define EOTC2B _SFR_MEM8(0xF9) |
|---|
| 1313 | #define CARFEB2 0 |
|---|
| 1314 | #define AMPFEB2 1 |
|---|
| 1315 | #define SYTFEB2 2 |
|---|
| 1316 | #define MANFEB2 3 |
|---|
| 1317 | #define TMOFEB2 4 |
|---|
| 1318 | #define TELREB2 5 |
|---|
| 1319 | #define RRFEB2 6 |
|---|
| 1320 | #define EOTAFE2 7 |
|---|
| 1321 | |
|---|
| 1322 | #define EOTC3B _SFR_MEM8(0xFA) |
|---|
| 1323 | #define CARFEB3 0 |
|---|
| 1324 | #define AMPFEB3 1 |
|---|
| 1325 | #define SYTFEB3 2 |
|---|
| 1326 | #define MANFEB3 3 |
|---|
| 1327 | #define TMOFEB3 4 |
|---|
| 1328 | #define TELREB3 5 |
|---|
| 1329 | #define RRFEB3 6 |
|---|
| 1330 | #define EOTAFE3 7 |
|---|
| 1331 | |
|---|
| 1332 | #define WCOTOA _SFR_MEM8(0xFB) |
|---|
| 1333 | |
|---|
| 1334 | #define WCOTOB _SFR_MEM8(0xFC) |
|---|
| 1335 | |
|---|
| 1336 | #define SOTTOA _SFR_MEM8(0xFD) |
|---|
| 1337 | |
|---|
| 1338 | #define SOTTOB _SFR_MEM8(0xFE) |
|---|
| 1339 | |
|---|
| 1340 | #define SSMFCR _SFR_MEM8(0xFF) |
|---|
| 1341 | #define SSMIDSO 0 |
|---|
| 1342 | #define SSMIDSF 1 |
|---|
| 1343 | |
|---|
| 1344 | #define FESR _SFR_MEM8(0x100) |
|---|
| 1345 | #define LBSAT 0 |
|---|
| 1346 | #define HBSAT 1 |
|---|
| 1347 | #define XRDY 2 |
|---|
| 1348 | #define PLCK 3 |
|---|
| 1349 | |
|---|
| 1350 | #define FEEN1 _SFR_MEM8(0x101) |
|---|
| 1351 | #define PLEN 0 |
|---|
| 1352 | #define PLCAL 1 |
|---|
| 1353 | #define XTOEN 2 |
|---|
| 1354 | #define LNAEN 3 |
|---|
| 1355 | #define ADEN 4 |
|---|
| 1356 | #define ADCLK 5 |
|---|
| 1357 | #define PLSP1 6 |
|---|
| 1358 | #define ATEN 7 |
|---|
| 1359 | |
|---|
| 1360 | #define FEEN2 _SFR_MEM8(0x102) |
|---|
| 1361 | #define SDRX 0 |
|---|
| 1362 | #define SDRX2 1 |
|---|
| 1363 | #define PAEN 2 |
|---|
| 1364 | #define TMPM 3 |
|---|
| 1365 | #define PLPEN 4 |
|---|
| 1366 | #define XTPEN 5 |
|---|
| 1367 | |
|---|
| 1368 | #define FELNA _SFR_MEM8(0x103) |
|---|
| 1369 | #define LBH0 0 |
|---|
| 1370 | #define LBH1 1 |
|---|
| 1371 | #define LBH2 2 |
|---|
| 1372 | #define LBH3 3 |
|---|
| 1373 | #define LBL0 4 |
|---|
| 1374 | #define LBL1 5 |
|---|
| 1375 | #define LBL2 6 |
|---|
| 1376 | #define LBL3 7 |
|---|
| 1377 | |
|---|
| 1378 | /* Reserved [0x104..0x105] */ |
|---|
| 1379 | |
|---|
| 1380 | #define FEVCT _SFR_MEM8(0x106) |
|---|
| 1381 | #define FEVCT0 0 |
|---|
| 1382 | #define FEVCT1 1 |
|---|
| 1383 | #define FEVCT2 2 |
|---|
| 1384 | #define FEVCT3 3 |
|---|
| 1385 | |
|---|
| 1386 | #define FEBT _SFR_MEM8(0x107) |
|---|
| 1387 | #define CTN20 0 |
|---|
| 1388 | #define CTN21 1 |
|---|
| 1389 | #define RTN20 2 |
|---|
| 1390 | #define RTN21 3 |
|---|
| 1391 | |
|---|
| 1392 | #define FEMS _SFR_MEM8(0x108) |
|---|
| 1393 | #define PLLS0 0 |
|---|
| 1394 | #define PLLS1 1 |
|---|
| 1395 | #define PLLS2 2 |
|---|
| 1396 | #define PLLS3 3 |
|---|
| 1397 | #define PLLM0 4 |
|---|
| 1398 | #define PLLM1 5 |
|---|
| 1399 | #define PLLM2 6 |
|---|
| 1400 | #define PLLM3 7 |
|---|
| 1401 | |
|---|
| 1402 | #define FETN4 _SFR_MEM8(0x109) |
|---|
| 1403 | #define CTN40 0 |
|---|
| 1404 | #define CTN41 1 |
|---|
| 1405 | #define CTN42 2 |
|---|
| 1406 | #define CTN43 3 |
|---|
| 1407 | #define RTN40 4 |
|---|
| 1408 | #define RTN41 5 |
|---|
| 1409 | #define RTN42 6 |
|---|
| 1410 | #define RTN43 7 |
|---|
| 1411 | |
|---|
| 1412 | #define FECR _SFR_MEM8(0x10A) |
|---|
| 1413 | #define LBNHB 0 |
|---|
| 1414 | #define S4N3 1 |
|---|
| 1415 | #define ANDP 2 |
|---|
| 1416 | #define ADHS 3 |
|---|
| 1417 | #define PLCKG 4 |
|---|
| 1418 | #define ANPS 5 |
|---|
| 1419 | |
|---|
| 1420 | #define FEVCO _SFR_MEM8(0x10B) |
|---|
| 1421 | #define CPCC0 0 |
|---|
| 1422 | #define CPCC1 1 |
|---|
| 1423 | #define CPCC2 2 |
|---|
| 1424 | #define CPCC3 3 |
|---|
| 1425 | #define VCOB0 4 |
|---|
| 1426 | #define VCOB1 5 |
|---|
| 1427 | #define VCOB2 6 |
|---|
| 1428 | #define VCOB3 7 |
|---|
| 1429 | |
|---|
| 1430 | #define FEALR _SFR_MEM8(0x10C) |
|---|
| 1431 | #define RNGE0 0 |
|---|
| 1432 | #define RNGE1 1 |
|---|
| 1433 | |
|---|
| 1434 | #define FEANT _SFR_MEM8(0x10D) |
|---|
| 1435 | #define LVLC0 0 |
|---|
| 1436 | #define LVLC1 1 |
|---|
| 1437 | #define LVLC2 2 |
|---|
| 1438 | #define LVLC3 3 |
|---|
| 1439 | |
|---|
| 1440 | #define FEBIA _SFR_MEM8(0x10E) |
|---|
| 1441 | #define IFAEN 7 |
|---|
| 1442 | |
|---|
| 1443 | /* Reserved [0x10F..0x12E] */ |
|---|
| 1444 | |
|---|
| 1445 | #define RXBC1 _SFR_MEM8(0x12F) |
|---|
| 1446 | #define RXCEA 0 |
|---|
| 1447 | #define RXCBLA0 1 |
|---|
| 1448 | #define RXCBLA1 2 |
|---|
| 1449 | #define RXMSBA 3 |
|---|
| 1450 | #define RXCEB 4 |
|---|
| 1451 | #define RXCBLB0 5 |
|---|
| 1452 | #define RXCBLB1 6 |
|---|
| 1453 | #define RXMSBB 7 |
|---|
| 1454 | |
|---|
| 1455 | #define RXBC2 _SFR_MEM8(0x130) |
|---|
| 1456 | #define RXBPB 0 |
|---|
| 1457 | #define RXBF 1 |
|---|
| 1458 | #define RXBCLR 2 |
|---|
| 1459 | |
|---|
| 1460 | #define RXTLLB _SFR_MEM8(0x131) |
|---|
| 1461 | |
|---|
| 1462 | #define RXTLHB _SFR_MEM8(0x132) |
|---|
| 1463 | #define RXTLHB0 0 |
|---|
| 1464 | #define RXTLHB1 1 |
|---|
| 1465 | #define RXTLHB2 2 |
|---|
| 1466 | #define RXTLHB3 3 |
|---|
| 1467 | |
|---|
| 1468 | #define RXCRLB _SFR_MEM8(0x133) |
|---|
| 1469 | |
|---|
| 1470 | #define RXCRHB _SFR_MEM8(0x134) |
|---|
| 1471 | |
|---|
| 1472 | #define RXCSBB _SFR_MEM8(0x135) |
|---|
| 1473 | |
|---|
| 1474 | #define RXCILB _SFR_MEM8(0x136) |
|---|
| 1475 | |
|---|
| 1476 | #define RXCIHB _SFR_MEM8(0x137) |
|---|
| 1477 | |
|---|
| 1478 | #define RXCPLB _SFR_MEM8(0x138) |
|---|
| 1479 | |
|---|
| 1480 | #define RXCPHB _SFR_MEM8(0x139) |
|---|
| 1481 | |
|---|
| 1482 | #define RXDSB _SFR_MEM8(0x13A) |
|---|
| 1483 | |
|---|
| 1484 | #define RXTLLA _SFR_MEM8(0x13B) |
|---|
| 1485 | |
|---|
| 1486 | #define RXTLHA _SFR_MEM8(0x13C) |
|---|
| 1487 | #define RXTLHA0 0 |
|---|
| 1488 | #define RXTLHA1 1 |
|---|
| 1489 | #define RXTLHA2 2 |
|---|
| 1490 | #define RXTLHA3 3 |
|---|
| 1491 | |
|---|
| 1492 | #define RXCRLA _SFR_MEM8(0x13D) |
|---|
| 1493 | |
|---|
| 1494 | #define RXCRHA _SFR_MEM8(0x13E) |
|---|
| 1495 | |
|---|
| 1496 | #define RXCSBA _SFR_MEM8(0x13F) |
|---|
| 1497 | |
|---|
| 1498 | #define RXCILA _SFR_MEM8(0x140) |
|---|
| 1499 | |
|---|
| 1500 | #define RXCIHA _SFR_MEM8(0x141) |
|---|
| 1501 | |
|---|
| 1502 | #define RXCPLA _SFR_MEM8(0x142) |
|---|
| 1503 | |
|---|
| 1504 | #define RXCPHA _SFR_MEM8(0x143) |
|---|
| 1505 | |
|---|
| 1506 | #define RXDSA _SFR_MEM8(0x144) |
|---|
| 1507 | |
|---|
| 1508 | #define CRCCR _SFR_MEM8(0x145) |
|---|
| 1509 | #define CRCRS 0 |
|---|
| 1510 | #define REFLI 1 |
|---|
| 1511 | #define REFLO 2 |
|---|
| 1512 | |
|---|
| 1513 | #define CRCDOR _SFR_MEM8(0x146) |
|---|
| 1514 | |
|---|
| 1515 | #define IDB0 _SFR_MEM8(0x147) |
|---|
| 1516 | |
|---|
| 1517 | #define IDB1 _SFR_MEM8(0x148) |
|---|
| 1518 | |
|---|
| 1519 | #define IDB2 _SFR_MEM8(0x149) |
|---|
| 1520 | |
|---|
| 1521 | #define IDB3 _SFR_MEM8(0x14A) |
|---|
| 1522 | |
|---|
| 1523 | #define IDC _SFR_MEM8(0x14B) |
|---|
| 1524 | #define IDL0 0 |
|---|
| 1525 | #define IDL1 1 |
|---|
| 1526 | #define IDBO0 2 |
|---|
| 1527 | #define IDBO1 3 |
|---|
| 1528 | #define IDFIM 5 |
|---|
| 1529 | #define IDCLR 6 |
|---|
| 1530 | #define IDCE 7 |
|---|
| 1531 | |
|---|
| 1532 | #define IDS _SFR_MEM8(0x14C) |
|---|
| 1533 | #define IDOK 0 |
|---|
| 1534 | #define IDFULL 1 |
|---|
| 1535 | |
|---|
| 1536 | #define RSSAV _SFR_MEM8(0x14D) |
|---|
| 1537 | |
|---|
| 1538 | #define RSSPK _SFR_MEM8(0x14E) |
|---|
| 1539 | |
|---|
| 1540 | #define RSSL _SFR_MEM8(0x14F) |
|---|
| 1541 | |
|---|
| 1542 | #define RSSH _SFR_MEM8(0x150) |
|---|
| 1543 | |
|---|
| 1544 | #define RSSC _SFR_MEM8(0x151) |
|---|
| 1545 | #define RSUP0 0 |
|---|
| 1546 | #define RSUP1 1 |
|---|
| 1547 | #define RSUP2 2 |
|---|
| 1548 | #define RSUP3 3 |
|---|
| 1549 | #define RSWLH 4 |
|---|
| 1550 | #define RSHRX 5 |
|---|
| 1551 | #define RSPKF 6 |
|---|
| 1552 | |
|---|
| 1553 | #define DBCR _SFR_MEM8(0x152) |
|---|
| 1554 | #define DBMD 0 |
|---|
| 1555 | #define DBCS 1 |
|---|
| 1556 | #define DBTMS 2 |
|---|
| 1557 | #define DBHA 3 |
|---|
| 1558 | |
|---|
| 1559 | #define DBTC _SFR_MEM8(0x153) |
|---|
| 1560 | |
|---|
| 1561 | #define DBENB _SFR_MEM8(0x154) |
|---|
| 1562 | |
|---|
| 1563 | #define DBENC _SFR_MEM8(0x155) |
|---|
| 1564 | |
|---|
| 1565 | #define DBGSW _SFR_MEM8(0x156) |
|---|
| 1566 | #define DBGGS0 0 |
|---|
| 1567 | #define DBGGS1 1 |
|---|
| 1568 | #define DBGGS2 2 |
|---|
| 1569 | #define DBGGS3 3 |
|---|
| 1570 | #define CPBFOS0 4 |
|---|
| 1571 | #define CPBFOS1 5 |
|---|
| 1572 | #define CPBF 6 |
|---|
| 1573 | #define DBGSE 7 |
|---|
| 1574 | |
|---|
| 1575 | #define SFFR _SFR_MEM8(0x157) |
|---|
| 1576 | #define RFL0 0 |
|---|
| 1577 | #define RFL1 1 |
|---|
| 1578 | #define RFL2 2 |
|---|
| 1579 | #define RFC 3 |
|---|
| 1580 | #define TFL0 4 |
|---|
| 1581 | #define TFL1 5 |
|---|
| 1582 | #define TFL2 6 |
|---|
| 1583 | #define TFC 7 |
|---|
| 1584 | |
|---|
| 1585 | #define SFIR _SFR_MEM8(0x158) |
|---|
| 1586 | #define RIL0 0 |
|---|
| 1587 | #define RIL1 1 |
|---|
| 1588 | #define RIL2 2 |
|---|
| 1589 | #define SRIE 3 |
|---|
| 1590 | #define TIL0 4 |
|---|
| 1591 | #define TIL1 5 |
|---|
| 1592 | #define TIL2 6 |
|---|
| 1593 | #define STIE 7 |
|---|
| 1594 | |
|---|
| 1595 | #define EECR2 _SFR_MEM8(0x159) |
|---|
| 1596 | #define EEBRE 0 |
|---|
| 1597 | |
|---|
| 1598 | #define PGMST _SFR_MEM8(0x15A) |
|---|
| 1599 | #define PGMSYN0 0 |
|---|
| 1600 | #define PGMSYN1 1 |
|---|
| 1601 | #define PGMSYN2 2 |
|---|
| 1602 | #define PGMSYN3 3 |
|---|
| 1603 | #define PGMSYN4 4 |
|---|
| 1604 | |
|---|
| 1605 | #define EEST _SFR_MEM8(0x15B) |
|---|
| 1606 | #define EESYN0 0 |
|---|
| 1607 | #define EESYN1 1 |
|---|
| 1608 | #define EESYN2 2 |
|---|
| 1609 | #define EESYN3 3 |
|---|
| 1610 | |
|---|
| 1611 | #define RSIFG _SFR_MEM8(0x15C) |
|---|
| 1612 | |
|---|
| 1613 | #define RSLDV _SFR_MEM8(0x15D) |
|---|
| 1614 | |
|---|
| 1615 | #define RSHDV _SFR_MEM8(0x15E) |
|---|
| 1616 | |
|---|
| 1617 | #define RSCOM _SFR_MEM8(0x15F) |
|---|
| 1618 | #define RSDC 0 |
|---|
| 1619 | #define RSIFC 1 |
|---|
| 1620 | |
|---|
| 1621 | |
|---|
| 1622 | |
|---|
| 1623 | /* Values and associated defines */ |
|---|
| 1624 | |
|---|
| 1625 | |
|---|
| 1626 | #define SLEEP_MODE_IDLE (0x00<<1) |
|---|
| 1627 | #define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1) |
|---|
| 1628 | #define SLEEP_MODE_PWR_DOWN (0x02<<1) |
|---|
| 1629 | #define SLEEP_MODE_PWR_SAVE (0x03<<1) |
|---|
| 1630 | |
|---|
| 1631 | /* Interrupt vectors */ |
|---|
| 1632 | /* Vector 0 is the reset vector */ |
|---|
| 1633 | /* External Interrupt Request 0 */ |
|---|
| 1634 | #define INT0_vect _VECTOR(1) |
|---|
| 1635 | #define INT0_vect_num 1 |
|---|
| 1636 | |
|---|
| 1637 | /* External Interrupt Request 1 */ |
|---|
| 1638 | #define INT1_vect _VECTOR(2) |
|---|
| 1639 | #define INT1_vect_num 2 |
|---|
| 1640 | |
|---|
| 1641 | /* Pin Change Interrupt Request 0 */ |
|---|
| 1642 | #define PCI0_vect _VECTOR(3) |
|---|
| 1643 | #define PCI0_vect_num 3 |
|---|
| 1644 | |
|---|
| 1645 | /* Pin Change Interrupt Request 1 */ |
|---|
| 1646 | #define PCI1_vect _VECTOR(4) |
|---|
| 1647 | #define PCI1_vect_num 4 |
|---|
| 1648 | |
|---|
| 1649 | /* Voltage Monitoring Interrupt */ |
|---|
| 1650 | #define VMON_vect _VECTOR(5) |
|---|
| 1651 | #define VMON_vect_num 5 |
|---|
| 1652 | |
|---|
| 1653 | /* AVCC Reset Interrupt */ |
|---|
| 1654 | #define AVCCR_vect _VECTOR(6) |
|---|
| 1655 | #define AVCCR_vect_num 6 |
|---|
| 1656 | |
|---|
| 1657 | /* AVCC Low Interrupt */ |
|---|
| 1658 | #define AVCCL_vect _VECTOR(7) |
|---|
| 1659 | #define AVCCL_vect_num 7 |
|---|
| 1660 | |
|---|
| 1661 | /* Timer 0 Interval Interrupt */ |
|---|
| 1662 | #define T0INT_vect _VECTOR(8) |
|---|
| 1663 | #define T0INT_vect_num 8 |
|---|
| 1664 | |
|---|
| 1665 | /* Timer/Counter1 Compare Match Interrupt */ |
|---|
| 1666 | #define T1COMP_vect _VECTOR(9) |
|---|
| 1667 | #define T1COMP_vect_num 9 |
|---|
| 1668 | |
|---|
| 1669 | /* Timer/Counter1 Overflow Interrupt */ |
|---|
| 1670 | #define T1OVF_vect _VECTOR(10) |
|---|
| 1671 | #define T1OVF_vect_num 10 |
|---|
| 1672 | |
|---|
| 1673 | /* Timer/Counter2 Compare Match Interrupt */ |
|---|
| 1674 | #define T2COMP_vect _VECTOR(11) |
|---|
| 1675 | #define T2COMP_vect_num 11 |
|---|
| 1676 | |
|---|
| 1677 | /* Timer/Counter2 Overflow Interrupt */ |
|---|
| 1678 | #define T2OVF_vect _VECTOR(12) |
|---|
| 1679 | #define T2OVF_vect_num 12 |
|---|
| 1680 | |
|---|
| 1681 | /* Timer/Counter3 Capture Event Interrupt */ |
|---|
| 1682 | #define T3CAP_vect _VECTOR(13) |
|---|
| 1683 | #define T3CAP_vect_num 13 |
|---|
| 1684 | |
|---|
| 1685 | /* Timer/Counter3 Compare Match Interrupt */ |
|---|
| 1686 | #define T3COMP_vect _VECTOR(14) |
|---|
| 1687 | #define T3COMP_vect_num 14 |
|---|
| 1688 | |
|---|
| 1689 | /* Timer/Counter3 Overflow Interrupt */ |
|---|
| 1690 | #define T3OVF_vect _VECTOR(15) |
|---|
| 1691 | #define T3OVF_vect_num 15 |
|---|
| 1692 | |
|---|
| 1693 | /* Timer/Counter4 Capture Event Interrupt */ |
|---|
| 1694 | #define T4CAP_vect _VECTOR(16) |
|---|
| 1695 | #define T4CAP_vect_num 16 |
|---|
| 1696 | |
|---|
| 1697 | /* Timer/Counter4 Compare Match Interrupt */ |
|---|
| 1698 | #define T4COMP_vect _VECTOR(17) |
|---|
| 1699 | #define T4COMP_vect_num 17 |
|---|
| 1700 | |
|---|
| 1701 | /* Timer/Counter4 Overflow Interrupt */ |
|---|
| 1702 | #define T4OVF_vect _VECTOR(18) |
|---|
| 1703 | #define T4OVF_vect_num 18 |
|---|
| 1704 | |
|---|
| 1705 | /* Timer/Counter5 Compare Match Interrupt */ |
|---|
| 1706 | #define T5COMP_vect _VECTOR(19) |
|---|
| 1707 | #define T5COMP_vect_num 19 |
|---|
| 1708 | |
|---|
| 1709 | /* Timer/Counter5 Overflow Interrupt */ |
|---|
| 1710 | #define T5OVF_vect _VECTOR(20) |
|---|
| 1711 | #define T5OVF_vect_num 20 |
|---|
| 1712 | |
|---|
| 1713 | /* SPI Serial Transfer Complete Interrupt */ |
|---|
| 1714 | #define SPI_vect _VECTOR(21) |
|---|
| 1715 | #define SPI_vect_num 21 |
|---|
| 1716 | |
|---|
| 1717 | /* SPI Rx Buffer Interrupt */ |
|---|
| 1718 | #define SRX_FIFO_vect _VECTOR(22) |
|---|
| 1719 | #define SRX_FIFO_vect_num 22 |
|---|
| 1720 | |
|---|
| 1721 | /* SPI Tx Buffer Interrupt */ |
|---|
| 1722 | #define STX_FIFO_vect _VECTOR(23) |
|---|
| 1723 | #define STX_FIFO_vect_num 23 |
|---|
| 1724 | |
|---|
| 1725 | /* Sequencer State Machine Interrupt */ |
|---|
| 1726 | #define SSM_vect _VECTOR(24) |
|---|
| 1727 | #define SSM_vect_num 24 |
|---|
| 1728 | |
|---|
| 1729 | /* Data FIFO fill level reached Interrupt */ |
|---|
| 1730 | #define DFFLR_vect _VECTOR(25) |
|---|
| 1731 | #define DFFLR_vect_num 25 |
|---|
| 1732 | |
|---|
| 1733 | /* Data FIFO overflow or underflow error Interrupt */ |
|---|
| 1734 | #define DFOUE_vect _VECTOR(26) |
|---|
| 1735 | #define DFOUE_vect_num 26 |
|---|
| 1736 | |
|---|
| 1737 | /* RSSI/Preamble FIFO fill level reached Interrupt */ |
|---|
| 1738 | #define SFFLR_vect _VECTOR(27) |
|---|
| 1739 | #define SFFLR_vect_num 27 |
|---|
| 1740 | |
|---|
| 1741 | /* RSSI/Preamble FIFO overflow or underflow error Interrupt */ |
|---|
| 1742 | #define SFOUE_vect _VECTOR(28) |
|---|
| 1743 | #define SFOUE_vect_num 28 |
|---|
| 1744 | |
|---|
| 1745 | /* Tx Modulator Telegram Finish Interrupt */ |
|---|
| 1746 | #define TMTCF_vect _VECTOR(29) |
|---|
| 1747 | #define TMTCF_vect_num 29 |
|---|
| 1748 | |
|---|
| 1749 | /* UHF receiver wake up ok on Rx path B */ |
|---|
| 1750 | #define UHF_WCOB_vect _VECTOR(30) |
|---|
| 1751 | #define UHF_WCOB_vect_num 30 |
|---|
| 1752 | |
|---|
| 1753 | /* UHF receiver wake up ok on Rx path A */ |
|---|
| 1754 | #define UHF_WCOA_vect _VECTOR(31) |
|---|
| 1755 | #define UHF_WCOA_vect_num 31 |
|---|
| 1756 | |
|---|
| 1757 | /* UHF receiver start of telegram ok on Rx path B */ |
|---|
| 1758 | #define UHF_SOTB_vect _VECTOR(32) |
|---|
| 1759 | #define UHF_SOTB_vect_num 32 |
|---|
| 1760 | |
|---|
| 1761 | /* UHF receiver start of telegram ok on Rx path A */ |
|---|
| 1762 | #define UHF_SOTA_vect _VECTOR(33) |
|---|
| 1763 | #define UHF_SOTA_vect_num 33 |
|---|
| 1764 | |
|---|
| 1765 | /* UHF receiver end of telegram on Rx path B */ |
|---|
| 1766 | #define UHF_EOTB_vect _VECTOR(34) |
|---|
| 1767 | #define UHF_EOTB_vect_num 34 |
|---|
| 1768 | |
|---|
| 1769 | /* UHF receiver end of telegram on Rx path A */ |
|---|
| 1770 | #define UHF_EOTA_vect _VECTOR(35) |
|---|
| 1771 | #define UHF_EOTA_vect_num 35 |
|---|
| 1772 | |
|---|
| 1773 | /* UHF receiver new bit on Rx path B */ |
|---|
| 1774 | #define UHF_NBITB_vect _VECTOR(36) |
|---|
| 1775 | #define UHF_NBITB_vect_num 36 |
|---|
| 1776 | |
|---|
| 1777 | /* UHF receiver new bit on Rx path A */ |
|---|
| 1778 | #define UHF_NBITA_vect _VECTOR(37) |
|---|
| 1779 | #define UHF_NBITA_vect_num 37 |
|---|
| 1780 | |
|---|
| 1781 | /* External input Clock monitoring Interrupt */ |
|---|
| 1782 | #define EXCM_vect _VECTOR(38) |
|---|
| 1783 | #define EXCM_vect_num 38 |
|---|
| 1784 | |
|---|
| 1785 | /* EEPROM Ready Interrupt */ |
|---|
| 1786 | #define ERDY_vect _VECTOR(39) |
|---|
| 1787 | #define ERDY_vect_num 39 |
|---|
| 1788 | |
|---|
| 1789 | /* Store Program Memory Ready */ |
|---|
| 1790 | #define SPMR_vect _VECTOR(40) |
|---|
| 1791 | #define SPMR_vect_num 40 |
|---|
| 1792 | |
|---|
| 1793 | /* IDSCAN Full Interrupt */ |
|---|
| 1794 | #define IDFULL_vect _VECTOR(41) |
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| 1795 | #define IDFULL_vect_num 41 |
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| 1796 | |
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| 1797 | #define _VECTORS_SIZE 168 |
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| 1798 | |
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| 1799 | |
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| 1800 | /* Constants */ |
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| 1801 | |
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| 1802 | #define SPM_PAGESIZE 64 |
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| 1803 | #define FLASHSTART 0x8000 |
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| 1804 | #define FLASHEND 0xCFFF |
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| 1805 | #define RAMSTART 0x0200 |
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| 1806 | #define RAMSIZE 1024 |
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| 1807 | #define RAMEND 0x05FF |
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| 1808 | #define E2START 0 |
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| 1809 | #define E2SIZE 1024 |
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| 1810 | #define E2PAGESIZE 16 |
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| 1811 | #define E2END 0x03FF |
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| 1812 | #define XRAMEND RAMEND |
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| 1813 | |
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| 1814 | |
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| 1815 | /* Fuses */ |
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| 1816 | |
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| 1817 | #define FUSE_MEMORY_SIZE 1 |
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| 1818 | |
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| 1819 | /* Fuse Byte */ |
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| 1820 | #define FUSE_EXTCLKEN (unsigned char)~_BV(0) |
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| 1821 | #define FUSE_RSTDISBL (unsigned char)~_BV(1) |
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| 1822 | #define FUSE_BOOTRST (unsigned char)~_BV(2) |
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| 1823 | #define FUSE_EESAVE (unsigned char)~_BV(3) |
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| 1824 | #define FUSE_WDTON (unsigned char)~_BV(4) |
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| 1825 | #define FUSE_SPIEN (unsigned char)~_BV(5) |
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| 1826 | #define FUSE_DWEN (unsigned char)~_BV(6) |
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| 1827 | #define FUSE_CKDIV8 (unsigned char)~_BV(7) |
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| 1828 | #define LFUSE_DEFAULT (FUSE_SPIEN) |
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| 1829 | |
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| 1830 | |
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| 1831 | |
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| 1832 | /* Lock Bits */ |
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| 1833 | #define __LOCK_BITS_EXIST |
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| 1834 | |
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| 1835 | |
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| 1836 | /* Signature */ |
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| 1837 | #define SIGNATURE_0 0x1E |
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| 1838 | #define SIGNATURE_1 0x95 |
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| 1839 | #define SIGNATURE_2 0x65 |
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| 1840 | |
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| 1841 | |
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| 1842 | #endif /* #ifdef _AVR_ATA5782_H_INCLUDED */ |
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| 1843 | |
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