source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/ioa5790.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

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1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATA5790_H_INCLUDED
36#define _AVR_ATA5790_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "ioa5790.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINB    _SFR_IO8(0x03)
52#define PINB7   7
53#define PINB6   6
54#define PINB5   5
55#define PINB4   4
56#define PINB3   3
57#define PINB2   2
58#define PINB1   1
59#define PINB0   0
60
61#define DDRB    _SFR_IO8(0x04)
62#define DDRB7   7
63// Inserted "DDB7" from "DDRB7" due to compatibility
64#define DDB7    7
65#define DDRB6   6
66// Inserted "DDB6" from "DDRB6" due to compatibility
67#define DDB6    6
68#define DDRB5   5
69// Inserted "DDB5" from "DDRB5" due to compatibility
70#define DDB5    5
71#define DDRB4   4
72// Inserted "DDB4" from "DDRB4" due to compatibility
73#define DDB4    4
74#define DDRB3   3
75// Inserted "DDB3" from "DDRB3" due to compatibility
76#define DDB3    3
77#define DDRB2   2
78// Inserted "DDB2" from "DDRB2" due to compatibility
79#define DDB2    2
80#define DDRB1   1
81// Inserted "DDB1" from "DDRB1" due to compatibility
82#define DDB1    1
83#define DDRB0   0
84// Inserted "DDB0" from "DDRB0" due to compatibility
85#define DDB0    0
86
87#define PORTB   _SFR_IO8(0x05)
88#define PORTB7  7
89#define PORTB6  6
90#define PORTB5  5
91#define PORTB4  4
92#define PORTB3  3
93#define PORTB2  2
94#define PORTB1  1
95#define PORTB0  0
96
97#define PINC    _SFR_IO8(0x06)
98#define PINC7   7
99#define PINC6   6
100#define PINC5   5
101#define PINC4   4
102#define PINC3   3
103#define PINC2   2
104#define PINC1   1
105#define PINC0   0
106
107#define DDRC    _SFR_IO8(0x07)
108#define DDRC7   7
109// Inserted "DDC7" from "DDRC7" due to compatibility
110#define DDC7    7
111#define DDRC6   6
112// Inserted "DDC6" from "DDRC6" due to compatibility
113#define DDC6    6
114#define DDRC5   5
115// Inserted "DDC5" from "DDRC5" due to compatibility
116#define DDC5    5
117#define DDRC4   4
118// Inserted "DDC4" from "DDRC4" due to compatibility
119#define DDC4    4
120#define DDRC3   3
121// Inserted "DDC3" from "DDRC3" due to compatibility
122#define DDC3    3
123#define DDRC2   2
124// Inserted "DDC2" from "DDRC2" due to compatibility
125#define DDC2    2
126#define DDRC1   1
127// Inserted "DDC1" from "DDRC1" due to compatibility
128#define DDC1    1
129#define DDRC0   0
130// Inserted "DDC0" from "DDRC0" due to compatibility
131#define DDC0    0
132
133#define PORTC   _SFR_IO8(0x08)
134#define PORTC7  7
135#define PORTC6  6
136#define PORTC5  5
137#define PORTC4  4
138#define PORTC3  3
139#define PORTC2  2
140#define PORTC1  1
141#define PORTC0  0
142
143#define PIND    _SFR_IO8(0x09)
144#define PIND7   7
145#define PIND6   6
146#define PIND5   5
147#define PIND4   4
148#define PIND3   3
149#define PIND2   2
150#define PIND1   1
151#define PIND0   0
152
153#define DDRD    _SFR_IO8(0x0A)
154#define DDRD7   7
155// Inserted "DDD7" from "DDRD7" due to compatibility
156#define DDD7    7
157#define DDRD6   6
158// Inserted "DDD6" from "DDRD6" due to compatibility
159#define DDD6    6
160#define DDRD5   5
161// Inserted "DDD5" from "DDRD5" due to compatibility
162#define DDD5    5
163#define DDRD4   4
164// Inserted "DDD4" from "DDRD4" due to compatibility
165#define DDD4    4
166#define DDRD3   3
167// Inserted "DDD3" from "DDRD3" due to compatibility
168#define DDD3    3
169#define DDRD2   2
170// Inserted "DDD2" from "DDRD2" due to compatibility
171#define DDD2    2
172#define DDRD1   1
173// Inserted "DDD1" from "DDRD1" due to compatibility
174#define DDD1    1
175#define DDRD0   0
176// Inserted "DDD0" from "DDRD0" due to compatibility
177#define DDD0    0
178
179#define PORTD   _SFR_IO8(0x0B)
180#define PORTD7  7
181#define PORTD6  6
182#define PORTD5  5
183#define PORTD4  4
184#define PORTD3  3
185#define PORTD2  2
186#define PORTD1  1
187#define PORTD0  0
188
189/* Reserved [0x0C] */
190
191#define TPCR    _SFR_IO8(0x0D)
192#define TPMA    0
193#define TPMOD   1
194#define TPMS0   2
195#define TPMS1   3
196#define TPMD0   4
197#define TPMD1   5
198#define TPPSD   6
199#define TPD     7
200
201#define TPFR    _SFR_IO8(0x0E)
202#define TPF     0
203#define TPA     1
204#define TPGAP   2
205#define TPPSW   3
206
207#define CMCR    _SFR_IO8(0x0F)
208#define CMM0    0
209#define CMM1    1
210#define SRCD    2
211#define CO32D   3
212#define CCS     4
213#define ECINS   5
214#define CMONEN  6
215#define CMCCE   7
216
217#define CMSR    _SFR_IO8(0x10)
218#define ECF     0
219#define SXF     1
220#define RTCF    2
221
222#define T2CR    _SFR_IO8(0x11)
223#define T2OTM   0
224#define T2CTM   1
225#define T2CRM   2
226#define T2GRM   3
227#define T2TOP   4
228#define T2RES   5
229#define T2TS    6
230#define T2E     7
231
232#define T3CR    _SFR_IO8(0x12)
233#define T3OTM   0
234#define T3CTM   1
235#define T3CRM   2
236#define T3CPRM  3
237#define T3TOP   4
238#define T3RES   5
239#define T3CPTM  6
240#define T3E     7
241
242#define AESCR   _SFR_IO8(0x13)
243#define AESWK   0
244#define AESWD   1
245#define AESIM   2
246#define AESD    3
247#define AESXOR  4
248#define AESRES  5
249#define AESE    7
250
251#define AESSR   _SFR_IO8(0x14)
252#define AESRF   0
253#define AESERF  7
254
255#define TMIFR   _SFR_IO8(0x15)
256#define TMRXF   0
257#define TMTXF   1
258#define TMTCF   2
259#define TMRXS   3
260#define TMTXS   4
261
262#define VMSR    _SFR_IO8(0x16)
263#define VMF     0
264
265#define PCIFR   _SFR_IO8(0x17)
266#define PCIF0   0
267#define PCIF1   1
268
269#define LFFR    _SFR_IO8(0x18)
270#define LFID0F  0
271#define LFID1F  1
272#define LFFEF   2
273#define LFDBF   3
274#define LFRSF   4
275#define LFSDF   5
276#define LFMDF   6
277#define LFCAF   7
278
279#define T0IFR   _SFR_IO8(0x19)
280#define T0F     0
281
282#define T1IFR   _SFR_IO8(0x1A)
283#define T1F     0
284
285#define T2IFR   _SFR_IO8(0x1B)
286#define T2OFF   0
287#define T2COF   1
288
289#define T3IFR   _SFR_IO8(0x1C)
290#define T3OFF   0
291#define T3COF   1
292#define T3ICF   2
293
294#define EIFR    _SFR_IO8(0x1D)
295#define INTF0   0
296
297#define GPIOR   _SFR_IO8(0x1E)
298
299#define EECR    _SFR_IO8(0x1F)
300#define EERE    0
301#define EEWE    1
302#define EEMWE   2
303#define EERIE   3
304#define EEPM0   4
305#define EEPM1   5
306#define EELP    6
307
308#define EEDR    _SFR_IO8(0x20)
309
310/* Combine EEARL and EEARH */
311#define EEAR    _SFR_IO16(0x21)
312
313#define EEARL   _SFR_IO8(0x21)
314#define EEARH   _SFR_IO8(0x22)
315
316#define EEPR    _SFR_IO8(0x23)
317#define EEAP0   0
318#define EEAP1   1
319#define EEAP2   2
320#define EEAP3   3
321
322#define EECCR   _SFR_IO8(0x24)
323#define EEL0    0
324#define EEL1    1
325#define EEL2    2
326#define EEL3    3
327
328/* Reserved [0x25] */
329
330#define PCICR   _SFR_IO8(0x26)
331#define PCIE0   0
332#define PCIE1   1
333
334#define EIMSK   _SFR_IO8(0x27)
335#define INT0    0
336
337#define TMDR    _SFR_IO8(0x28)
338
339#define AESDR   _SFR_IO8(0x29)
340
341#define AESKR   _SFR_IO8(0x2A)
342#define AESKR0  0
343#define AESKR1  1
344#define AESKR2  2
345#define AESKR3  3
346#define AESKR4  4
347#define AESKR5  5
348#define AESKR6  6
349#define AESKR7  7
350
351#define VMCR    _SFR_IO8(0x2B)
352#define VMLS0   0
353#define VMLS1   1
354#define VMLS2   2
355#define VMLS3   3
356#define VMIM    4
357#define VMPS    5
358#define BODPD   6
359#define BODLS   7
360
361#define SPCR    _SFR_IO8(0x2C)
362#define SPR0    0
363#define SPR1    1
364#define CPHA    2
365#define CPOL    3
366#define MSTR    4
367#define DORD    5
368#define SPE     6
369#define SPIE    7
370
371#define SPSR    _SFR_IO8(0x2D)
372#define SPI2X   0
373#define WCOL    6
374#define SPIF    7
375
376#define SPDR    _SFR_IO8(0x2E)
377
378#define LFCR0   _SFR_IO8(0x2F)
379#define LFCE1   0
380#define LFCE2   1
381#define LFCE3   2
382#define LFBRS   3
383#define LFRBS   4
384#define LFMG    5
385#define LFVC0   6
386#define LFVC1   7
387
388#define LFCR1   _SFR_IO8(0x30)
389#define LFM0    0
390#define LFM1    1
391#define LFFM0   2
392#define LFFM1   3
393#define LFRMS   4
394#define LFRMSA  5
395#define LFQCE   6
396#define LFRE    7
397
398/* Reserved [0x31] */
399
400#define LFRDB   _SFR_IO8(0x32)
401
402#define SMCR    _SFR_IO8(0x33)
403#define SE      0
404#define SM0     1
405#define SM1     2
406#define SM2     3
407
408#define MCUSR   _SFR_IO8(0x34)
409#define PORF    0
410#define EXTRF   1
411#define BORF    2
412#define WDRF    3
413#define TPRF    5
414
415#define MCUCR   _SFR_IO8(0x35)
416#define IVCE    0
417#define IVSEL   1
418#define PUD     4
419
420#define LFSR    _SFR_IO8(0x36)
421#define LFES    0
422#define LFSD    1
423
424#define SPMCSR  _SFR_IO8(0x37)
425#define SPMEN   0
426#define PGERS   1
427#define PGWRT   2
428#define BLBSET  3
429#define RWWSRE  4
430#define SIGRD   5
431#define RWWSB   6
432#define SPMIE   7
433
434#define T1CR    _SFR_IO8(0x38)
435#define T1PS0   0
436#define T1PS1   1
437#define T1IE    2
438#define T1CS0   3
439#define T1CS1   4
440#define T1E     7
441
442#define T0CR    _SFR_IO8(0x39)
443#define T0PS0   0
444#define T0PS1   1
445#define T0PS2   2
446#define T0IE    3
447#define T0PR    4
448
449/* Reserved [0x3A] */
450
451#define CMIMR   _SFR_IO8(0x3B)
452#define ECIE    0
453#define SXIE    1
454#define RTCIE   2
455
456#define CLKPR   _SFR_IO8(0x3C)
457#define CLKPS0  0
458#define CLKPS1  1
459#define CLKPS2  2
460#define CLTPS0  3
461#define CLTPS1  4
462#define CLTPS2  5
463#define CLKPCE  7
464
465/* SP [0x3D..0x3E] */
466
467/* SREG [0x3F] */
468
469#define WDTCR   _SFR_MEM8(0x60)
470#define WDPS0   0
471#define WDPS1   1
472#define WDPS2   2
473#define WDE     3
474#define WDCE    4
475
476/* Reserved [0x61..0x62] */
477
478#define PRR0    _SFR_MEM8(0x63)
479#define PRLFR   0
480#define PRT1    1
481#define PRT2    2
482#define PRT3    3
483#define PRTM    4
484#define PRCU    5
485#define PRDS    6
486#define PRVM    7
487
488#define __AVR_HAVE_PRR0 ((1<<PRLFR)|(1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRTM)|(1<<PRCU)|(1<<PRDS)|(1<<PRVM))
489#define __AVR_HAVE_PRR0_PRLFR
490#define __AVR_HAVE_PRR0_PRT1
491#define __AVR_HAVE_PRR0_PRT2
492#define __AVR_HAVE_PRR0_PRT3
493#define __AVR_HAVE_PRR0_PRTM
494#define __AVR_HAVE_PRR0_PRCU
495#define __AVR_HAVE_PRR0_PRDS
496#define __AVR_HAVE_PRR0_PRVM
497
498#define PRR1    _SFR_MEM8(0x64)
499#define PRCI    0
500#define PRSPI   1
501
502#define __AVR_HAVE_PRR1 ((1<<PRCI)|(1<<PRSPI))
503#define __AVR_HAVE_PRR1_PRCI
504#define __AVR_HAVE_PRR1_PRSPI
505
506#define SRCCAL  _SFR_MEM8(0x65)
507
508#define FRCCAL  _SFR_MEM8(0x66)
509
510/* Reserved [0x67..0x68] */
511
512#define EICRA   _SFR_MEM8(0x69)
513#define ISC00   0
514#define ISC01   1
515
516#define PCMSK0  _SFR_MEM8(0x6A)
517#define PCINT0  0
518#define PCINT1  1
519#define PCINT2  2
520#define PCINT3  3
521#define PCINT4  4
522#define PCINT5  5
523#define PCINT6  6
524#define PCINT7  7
525
526#define PCMSK1  _SFR_MEM8(0x6B)
527#define PCINT8  0
528#define PCINT9  1
529#define PCINT10 2
530#define PCINT11 3
531#define PCINT12 4
532#define PCINT13 5
533#define PCINT14 6
534#define PCINT15 7
535
536/* Reserved [0x6C] */
537
538#define LDCR    _SFR_MEM8(0x6D)
539#define LDE     0
540#define LDCS0   1
541#define LDCS1   2
542
543/* Reserved [0x6E..0x6F] */
544
545#define T2CNT   _SFR_MEM8(0x70)
546
547#define T2COR   _SFR_MEM8(0x71)
548
549/* Reserved [0x72] */
550
551#define T2MR    _SFR_MEM8(0x73)
552#define T2CS0   0
553#define T2CS1   1
554#define T2CS2   2
555#define T2PS0   3
556#define T2PS1   4
557#define T2PS2   5
558#define T2D0    6
559#define T2D1    7
560
561#define T2IMR   _SFR_MEM8(0x74)
562#define T2OIM   0
563#define T2CIM   1
564
565/* Reserved [0x75] */
566
567#define T3CNT   _SFR_MEM8(0x76)
568
569#define T3COR   _SFR_MEM8(0x77)
570
571#define T3ICR   _SFR_MEM8(0x78)
572
573#define T3MRA   _SFR_MEM8(0x79)
574#define T3CS0   0
575#define T3CS1   1
576#define T3SCE   2
577#define T3CE0   3
578#define T3CE1   4
579#define T3CNC   5
580#define T3ICS0  6
581#define T3ICS1  7
582
583#define T3MRB   _SFR_MEM8(0x7A)
584#define T3PS0   0
585#define T3PS1   1
586#define T3PS2   2
587
588#define T3IMR   _SFR_MEM8(0x7B)
589#define T3OIM   0
590#define T3CIM   1
591#define T3CPIM  2
592
593/* Reserved [0x7C] */
594
595#define TMCR    _SFR_MEM8(0x7D)
596#define MI1S0   0
597#define MI1S1   1
598#define MI2S0   2
599#define MI2S1   3
600#define MI4S0   4
601#define MI4S1   5
602#define TMCPOL  6
603#define TMSSIE  7
604
605#define TMMR    _SFR_MEM8(0x7E)
606#define MOS0    0
607#define MOS1    1
608#define MSCS0   2
609#define MSCS1   3
610#define MOUTC   4
611#define TMMS0   5
612#define TMMS1   6
613#define TM12S   7
614
615#define TMIMR   _SFR_MEM8(0x7F)
616#define TMRXIM  0
617#define TMTXIM  1
618#define TMTCIM  2
619
620/* Reserved [0x80..0x81] */
621
622#define LFIMR   _SFR_MEM8(0x82)
623#define LFID0IM 0
624#define LFID1IM 1
625#define LFFEIM  2
626#define LFDBIM  3
627#define LFRSIM  4
628#define LFSDIM  5
629#define LFMDIM  6
630
631#define LFCAD   _SFR_MEM8(0x83)
632
633#define LFID00  _SFR_MEM8(0x84)
634
635#define LFID01  _SFR_MEM8(0x85)
636
637#define LFID02  _SFR_MEM8(0x86)
638
639#define LFID03  _SFR_MEM8(0x87)
640
641#define LFID10  _SFR_MEM8(0x88)
642
643#define LFID11  _SFR_MEM8(0x89)
644
645#define LFID12  _SFR_MEM8(0x8A)
646
647#define LFID13  _SFR_MEM8(0x8B)
648
649#define LFRD0   _SFR_MEM8(0x8C)
650
651#define LFRD1   _SFR_MEM8(0x8D)
652
653#define LFRD2   _SFR_MEM8(0x8E)
654
655#define LFRD3   _SFR_MEM8(0x8F)
656
657#define LFID0M  _SFR_MEM8(0x90)
658#define ID0FS0  0
659#define ID0FS1  1
660#define ID0FS2  2
661#define ID0FS3  3
662#define ID0FS4  4
663#define ID0E    7
664
665#define LFID1M  _SFR_MEM8(0x91)
666#define ID1FS0  0
667#define ID1FS1  1
668#define ID1FS2  2
669#define ID1FS3  3
670#define ID1FS4  4
671#define ID1E    7
672
673#define LFRDF   _SFR_MEM8(0x92)
674#define RDFS0   0
675#define RDFS1   1
676#define RDFS2   2
677#define RDFS3   3
678#define RDFS4   4
679#define RDFE    7
680
681#define LFRSD1  _SFR_MEM8(0x93)
682
683#define LFRSD2  _SFR_MEM8(0x94)
684
685#define LFRSD3  _SFR_MEM8(0x95)
686
687#define LFCC1   _SFR_MEM8(0x96)
688
689#define LFCC2   _SFR_MEM8(0x97)
690
691#define LFCC3   _SFR_MEM8(0x98)
692
693/* Reserved [0x99..0x9B] */
694
695#define TPIMR   _SFR_MEM8(0x9C)
696#define TPIM    0
697
698/* Reserved [0x9D] */
699
700#define RTCCR   _SFR_MEM8(0x9E)
701#define RTCR    0
702
703#define RTCDR   _SFR_MEM8(0x9F)
704
705/* Reserved [0xA0..0xA7] */
706
707#define TMMDR   _SFR_MEM8(0xA8)
708
709#define TMBDR   _SFR_MEM8(0xA9)
710
711#define TMTDR   _SFR_MEM8(0xAA)
712
713#define TMSR    _SFR_MEM8(0xAB)
714
715/* Reserved [0xAC] */
716
717#define CRCDR   _SFR_MEM8(0xAD)
718
719#define CRCCR   _SFR_MEM8(0xAE)
720#define CRCN0   0
721#define CRCN1   1
722#define CRCN2   2
723#define CRCSEL  3
724#define REFLI   4
725#define REFLO   5
726#define CRCRS   7
727
728#define CRCSR   _SFR_MEM8(0xAF)
729#define CRCBF   0
730
731
732
733/* Values and associated defines */
734
735
736#define SLEEP_MODE_IDLE (0x00<<1)
737#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
738#define SLEEP_MODE_PWR_DOWN (0x02<<1)
739#define SLEEP_MODE_PWR_SAVE (0x03<<1)
740
741/* Interrupt vectors */
742/* Vector 0 is the reset vector */
743/* Transponder Mode Interrupt */
744#define TPINT_vect            _VECTOR(1)
745#define TPINT_vect_num        1
746
747/* External Interrupt Request 0 */
748#define INT0_vect            _VECTOR(2)
749#define INT0_vect_num        2
750
751/* Pin Change Interrupt Request 0 */
752#define PCINT0_vect            _VECTOR(3)
753#define PCINT0_vect_num        3
754
755/* Pin Change Interrupt Request 1 */
756#define PCINT1_vect            _VECTOR(4)
757#define PCINT1_vect_num        4
758
759/* Voltage Monitoring Interrupt */
760#define VMINT_vect            _VECTOR(5)
761#define VMINT_vect_num        5
762
763/* Timer0 Interval Interrupt */
764#define T0INT_vect            _VECTOR(6)
765#define T0INT_vect_num        6
766
767/* LF-Receiver Identifier 0 Interrupt */
768#define LFID0INT_vect            _VECTOR(7)
769#define LFID0INT_vect_num        7
770
771/* LF-Receiver Identifier 1 Interrupt */
772#define LFID1INT_vect            _VECTOR(8)
773#define LFID1INT_vect_num        8
774
775/* LF-Receiver Frame End Interrupt */
776#define LFFEINT_vect            _VECTOR(9)
777#define LFFEINT_vect_num        9
778
779/* LF-Receiver Data Buffer full Interrupt */
780#define LFDBINT_vect            _VECTOR(10)
781#define LFDBINT_vect_num        10
782
783/* Timer/Counter3 Capture Event Interrupt */
784#define T3CAPINT_vect            _VECTOR(11)
785#define T3CAPINT_vect_num        11
786
787/* Timer/Counter3 Compare Match Interrupt */
788#define T3COMINT_vect            _VECTOR(12)
789#define T3COMINT_vect_num        12
790
791/* Timer/Counter3 Overflow Interrupt */
792#define T3OVFINT_vect            _VECTOR(13)
793#define T3OVFINT_vect_num        13
794
795/* Timer/Counter2 Compare Match Interrupt */
796#define T2COMINT_vect            _VECTOR(14)
797#define T2COMINT_vect_num        14
798
799/* Timer/Counter2 Overflow Interrupt */
800#define T2OVFINT_vect            _VECTOR(15)
801#define T2OVFINT_vect_num        15
802
803/* Timer 1 Interval Interrupt */
804#define T1INT_vect            _VECTOR(16)
805#define T1INT_vect_num        16
806
807/* SPI Serial Transfer Complete Interrupt */
808#define SPISTC_vect            _VECTOR(17)
809#define SPISTC_vect_num        17
810
811/* Timer Modulator SSI Receive Buffer Interrupt */
812#define TMRXBINT_vect            _VECTOR(18)
813#define TMRXBINT_vect_num        18
814
815/* Timer Modulator SSI Transmit Buffer Interrupt */
816#define TMTXBINT_vect            _VECTOR(19)
817#define TMTXBINT_vect_num        19
818
819/* Timer Modulator Transmit Complete Interrupt */
820#define TMTXCINT_vect            _VECTOR(20)
821#define TMTXCINT_vect_num        20
822
823/* AES Interrupt */
824#define AESINT_vect            _VECTOR(21)
825#define AESINT_vect_num        21
826
827/* LF-Receiver RSSi measurement Interrupt */
828#define LFRSSINT_vect            _VECTOR(22)
829#define LFRSSINT_vect_num        22
830
831/* LF-Receiver Signal Detect Interrupt */
832#define LFSDINT_vect            _VECTOR(23)
833#define LFSDINT_vect_num        23
834
835/* LF-Receiver Manchester Decoder error Interrupt  */
836#define LFMDINT_vect            _VECTOR(24)
837#define LFMDINT_vect_num        24
838
839/* External Input Clock Monitoring Interrupt */
840#define EXCMINT_vect            _VECTOR(25)
841#define EXCMINT_vect_num        25
842
843/* External XTAL Oscillator Break Down Interrupt */
844#define EXXMINT_vect            _VECTOR(26)
845#define EXXMINT_vect_num        26
846
847/* Real Time Clock Interrupt */
848#define RTCINT_vect            _VECTOR(27)
849#define RTCINT_vect_num        27
850
851/* EEPROM Ready Interrupt */
852#define EEREADY_vect            _VECTOR(28)
853#define EEREADY_vect_num        28
854
855/* Store Program Memory Ready  */
856#define SPMREADY_vect            _VECTOR(29)
857#define SPMREADY_vect_num        29
858
859#define _VECTORS_SIZE 120
860
861
862/* Constants */
863
864#define SPM_PAGESIZE 128
865#define FLASHSTART   0x0000
866#define FLASHEND     0x3FFF
867#define RAMSTART     0x0100
868#define RAMSIZE      512
869#define RAMEND       0x02FF
870#define E2START     0
871#define E2SIZE      2048
872#define E2PAGESIZE  16
873#define E2END       0x07FF
874#define XRAMEND      RAMEND
875
876
877/* Fuses */
878
879#define FUSE_MEMORY_SIZE 1
880
881/* Fuse Byte */
882#define FUSE_EXTCLKEN    (unsigned char)~_BV(0)
883#define FUSE__32OEN      (unsigned char)~_BV(1)
884#define FUSE_Reserved    (unsigned char)~_BV(2)
885#define FUSE_EESAVE      (unsigned char)~_BV(3)
886#define FUSE_WDTON       (unsigned char)~_BV(4)
887#define FUSE_SPIEN       (unsigned char)~_BV(5)
888#define FUSE_DWEN        (unsigned char)~_BV(6)
889#define FUSE_CKDIV8      (unsigned char)~_BV(7)
890#define LFUSE_DEFAULT    (FUSE__32OEN & FUSE_Reserved & FUSE_WDTON & FUSE_SPIEN & FUSE_CKDIV8)
891
892
893
894/* Lock Bits */
895#define __LOCK_BITS_EXIST
896#define __BOOT_LOCK_BITS_0_EXIST
897#define __BOOT_LOCK_BITS_1_EXIST
898
899
900/* Signature */
901#define SIGNATURE_0 0x1E
902#define SIGNATURE_1 0x94
903#define SIGNATURE_2 0x61
904
905
906#endif /* #ifdef _AVR_ATA5790_H_INCLUDED */
907
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