source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/ioa5790n.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

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1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATA5790N_H_INCLUDED
36#define _AVR_ATA5790N_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "ioa5790n.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINB    _SFR_IO8(0x03)
52#define PINB7   7
53#define PINB6   6
54#define PINB5   5
55#define PINB4   4
56#define PINB3   3
57#define PINB2   2
58#define PINB1   1
59#define PINB0   0
60
61#define DDRB    _SFR_IO8(0x04)
62#define DDRB7   7
63// Inserted "DDB7" from "DDRB7" due to compatibility
64#define DDB7    7
65#define DDRB6   6
66// Inserted "DDB6" from "DDRB6" due to compatibility
67#define DDB6    6
68#define DDRB5   5
69// Inserted "DDB5" from "DDRB5" due to compatibility
70#define DDB5    5
71#define DDRB4   4
72// Inserted "DDB4" from "DDRB4" due to compatibility
73#define DDB4    4
74#define DDRB3   3
75// Inserted "DDB3" from "DDRB3" due to compatibility
76#define DDB3    3
77#define DDRB2   2
78// Inserted "DDB2" from "DDRB2" due to compatibility
79#define DDB2    2
80#define DDRB1   1
81// Inserted "DDB1" from "DDRB1" due to compatibility
82#define DDB1    1
83#define DDRB0   0
84// Inserted "DDB0" from "DDRB0" due to compatibility
85#define DDB0    0
86
87#define PORTB   _SFR_IO8(0x05)
88#define PORTB7  7
89#define PORTB6  6
90#define PORTB5  5
91#define PORTB4  4
92#define PORTB3  3
93#define PORTB2  2
94#define PORTB1  1
95#define PORTB0  0
96
97#define PINC    _SFR_IO8(0x06)
98#define PINC7   7
99#define PINC6   6
100#define PINC5   5
101#define PINC4   4
102#define PINC3   3
103#define PINC2   2
104#define PINC1   1
105#define PINC0   0
106
107#define DDRC    _SFR_IO8(0x07)
108#define DDRC7   7
109// Inserted "DDC7" from "DDRC7" due to compatibility
110#define DDC7    7
111#define DDRC6   6
112// Inserted "DDC6" from "DDRC6" due to compatibility
113#define DDC6    6
114#define DDRC5   5
115// Inserted "DDC5" from "DDRC5" due to compatibility
116#define DDC5    5
117#define DDRC4   4
118// Inserted "DDC4" from "DDRC4" due to compatibility
119#define DDC4    4
120#define DDRC3   3
121// Inserted "DDC3" from "DDRC3" due to compatibility
122#define DDC3    3
123#define DDRC2   2
124// Inserted "DDC2" from "DDRC2" due to compatibility
125#define DDC2    2
126#define DDRC1   1
127// Inserted "DDC1" from "DDRC1" due to compatibility
128#define DDC1    1
129#define DDRC0   0
130// Inserted "DDC0" from "DDRC0" due to compatibility
131#define DDC0    0
132
133#define PORTC   _SFR_IO8(0x08)
134#define PORTC7  7
135#define PORTC6  6
136#define PORTC5  5
137#define PORTC4  4
138#define PORTC3  3
139#define PORTC2  2
140#define PORTC1  1
141#define PORTC0  0
142
143#define PIND    _SFR_IO8(0x09)
144#define PIND7   7
145#define PIND6   6
146#define PIND5   5
147#define PIND4   4
148#define PIND3   3
149#define PIND2   2
150#define PIND1   1
151#define PIND0   0
152
153#define DDRD    _SFR_IO8(0x0A)
154#define DDRD7   7
155// Inserted "DDD7" from "DDRD7" due to compatibility
156#define DDD7    7
157#define DDRD6   6
158// Inserted "DDD6" from "DDRD6" due to compatibility
159#define DDD6    6
160#define DDRD5   5
161// Inserted "DDD5" from "DDRD5" due to compatibility
162#define DDD5    5
163#define DDRD4   4
164// Inserted "DDD4" from "DDRD4" due to compatibility
165#define DDD4    4
166#define DDRD3   3
167// Inserted "DDD3" from "DDRD3" due to compatibility
168#define DDD3    3
169#define DDRD2   2
170// Inserted "DDD2" from "DDRD2" due to compatibility
171#define DDD2    2
172#define DDRD1   1
173// Inserted "DDD1" from "DDRD1" due to compatibility
174#define DDD1    1
175#define DDRD0   0
176// Inserted "DDD0" from "DDRD0" due to compatibility
177#define DDD0    0
178
179#define PORTD   _SFR_IO8(0x0B)
180#define PORTD7  7
181#define PORTD6  6
182#define PORTD5  5
183#define PORTD4  4
184#define PORTD3  3
185#define PORTD2  2
186#define PORTD1  1
187#define PORTD0  0
188
189#define T3CR2   _SFR_IO8(0x0C)
190#define T3GRES  0
191#define T3C2TM  1
192#define T3C2RM  2
193
194#define TPCR    _SFR_IO8(0x0D)
195#define TPMA    0
196#define TPMOD   1
197#define TPMS0   2
198#define TPMS1   3
199#define TPMD0   4
200#define TPMD1   5
201#define TPPSD   6
202#define TPD     7
203
204#define TPFR    _SFR_IO8(0x0E)
205#define TPF     0
206#define TPA     1
207#define TPGAP   2
208#define TPPSW   3
209
210#define CMCR    _SFR_IO8(0x0F)
211#define CMM0    0
212#define CMM1    1
213#define SRCD    2
214#define CO32D   3
215#define CCS     4
216#define ECINS   5
217#define CMONEN  6
218#define CMCCE   7
219
220#define CMSR    _SFR_IO8(0x10)
221#define ECF     0
222#define SXF     1
223#define RTCF    2
224
225#define T2CR    _SFR_IO8(0x11)
226#define T2OTM   0
227#define T2CTM   1
228#define T2CRM   2
229#define T2GRM   3
230#define T2TOP   4
231#define T2RES   5
232#define T2TS    6
233#define T2E     7
234
235#define T3CR    _SFR_IO8(0x12)
236#define T3OTM   0
237#define T3CTM   1
238#define T3CRM   2
239#define T3CPRM  3
240#define T3TOP   4
241#define T3RES   5
242#define T3CPTM  6
243#define T3E     7
244
245#define AESCR   _SFR_IO8(0x13)
246#define AESWK   0
247#define AESWD   1
248#define AESIM   2
249#define AESD    3
250#define AESXOR  4
251#define AESRES  5
252#define AESE    7
253
254#define AESSR   _SFR_IO8(0x14)
255#define AESRF   0
256#define AESERF  7
257
258#define TMIFR   _SFR_IO8(0x15)
259#define TMRXF   0
260#define TMTXF   1
261#define TMTCF   2
262#define TMRXS   3
263#define TMTXS   4
264
265#define VMSR    _SFR_IO8(0x16)
266#define VMF     0
267
268#define PCIFR   _SFR_IO8(0x17)
269#define PCIF0   0
270#define PCIF1   1
271
272#define LFFR    _SFR_IO8(0x18)
273#define LFID0F  0
274#define LFID1F  1
275#define LFFEF   2
276#define LFDBF   3
277#define LFRSF   4
278#define LFSDF   5
279#define LFMDF   6
280#define LFCAF   7
281
282#define T0IFR   _SFR_IO8(0x19)
283#define T0F     0
284
285#define T1IFR   _SFR_IO8(0x1A)
286#define T1F     0
287
288#define T2IFR   _SFR_IO8(0x1B)
289#define T2OFF   0
290#define T2COF   1
291
292#define T3IFR   _SFR_IO8(0x1C)
293#define T3OFF   0
294#define T3COF   1
295#define T3ICF   2
296#define T3CO2F  3
297
298#define EIFR    _SFR_IO8(0x1D)
299#define INTF0   0
300
301#define GPIOR   _SFR_IO8(0x1E)
302
303#define EECR    _SFR_IO8(0x1F)
304#define EERE    0
305#define EEWE    1
306#define EEMWE   2
307#define EERIE   3
308#define EEPM0   4
309#define EEPM1   5
310#define EELP    6
311#define NVMBSY  7
312
313#define EEDR    _SFR_IO8(0x20)
314
315/* Combine EEARL and EEARH */
316#define EEAR    _SFR_IO16(0x21)
317
318#define EEARL   _SFR_IO8(0x21)
319#define EEARH   _SFR_IO8(0x22)
320
321#define EEPR    _SFR_IO8(0x23)
322#define EEAP0   0
323#define EEAP1   1
324#define EEAP2   2
325#define EEAP3   3
326
327#define EECCR   _SFR_IO8(0x24)
328#define EEL0    0
329#define EEL1    1
330#define EEL2    2
331#define EEL3    3
332
333#define EECR2   _SFR_IO8(0x25)
334#define EEBRE   0
335#define EEPAGE  1
336
337#define PCICR   _SFR_IO8(0x26)
338#define PCIE0   0
339#define PCIE1   1
340
341#define EIMSK   _SFR_IO8(0x27)
342#define INT0    0
343
344#define TMDR    _SFR_IO8(0x28)
345
346#define AESDR   _SFR_IO8(0x29)
347
348#define AESKR   _SFR_IO8(0x2A)
349#define AESKR0  0
350#define AESKR1  1
351#define AESKR2  2
352#define AESKR3  3
353#define AESKR4  4
354#define AESKR5  5
355#define AESKR6  6
356#define AESKR7  7
357
358#define VMCR    _SFR_IO8(0x2B)
359#define VMLS0   0
360#define VMLS1   1
361#define VMLS2   2
362#define VMLS3   3
363#define VMIM    4
364#define VMPS    5
365#define BODPD   6
366#define BODLS   7
367
368#define SPCR    _SFR_IO8(0x2C)
369#define SPR0    0
370#define SPR1    1
371#define CPHA    2
372#define CPOL    3
373#define MSTR    4
374#define DORD    5
375#define SPE     6
376#define SPIE    7
377
378#define SPSR    _SFR_IO8(0x2D)
379#define SPI2X   0
380#define WCOL    6
381#define SPIF    7
382
383#define SPDR    _SFR_IO8(0x2E)
384
385#define LFCR0   _SFR_IO8(0x2F)
386#define LFCE1   0
387#define LFCE2   1
388#define LFCE3   2
389#define LFBRS   3
390#define LFRBS   4
391#define LFMG    5
392#define LFVC0   6
393#define LFVC1   7
394
395#define LFCR1   _SFR_IO8(0x30)
396#define LFM0    0
397#define LFM1    1
398#define LFFM0   2
399#define LFFM1   3
400#define LFRMS   4
401#define LFRMSA  5
402#define LFQCE   6
403#define LFRE    7
404
405/* Reserved [0x31] */
406
407#define LFRDB   _SFR_IO8(0x32)
408
409#define SMCR    _SFR_IO8(0x33)
410#define SE      0
411#define SM0     1
412#define SM1     2
413#define SM2     3
414
415#define MCUSR   _SFR_IO8(0x34)
416#define PORF    0
417#define EXTRF   1
418#define BORF    2
419#define WDRF    3
420#define TPRF    5
421
422#define MCUCR   _SFR_IO8(0x35)
423#define IVCE    0
424#define IVSEL   1
425#define PUD     4
426
427#define LFSR    _SFR_IO8(0x36)
428#define LFES    0
429#define LFSD    1
430
431#define SPMCSR  _SFR_IO8(0x37)
432#define SPMEN   0
433#define PGERS   1
434#define PGWRT   2
435#define BLBSET  3
436#define RWWSRE  4
437#define SIGRD   5
438#define RWWSB   6
439#define SPMIE   7
440
441#define T1CR    _SFR_IO8(0x38)
442#define T1PS0   0
443#define T1PS1   1
444#define T1IE    2
445#define T1CS0   3
446#define T1CS1   4
447#define T1E     7
448
449#define T0CR    _SFR_IO8(0x39)
450#define T0PS0   0
451#define T0PS1   1
452#define T0PS2   2
453#define T0IE    3
454#define T0PR    4
455
456/* Reserved [0x3A] */
457
458#define CMIMR   _SFR_IO8(0x3B)
459#define ECIE    0
460#define SXIE    1
461#define RTCIE   2
462
463#define CLKPR   _SFR_IO8(0x3C)
464#define CLKPS0  0
465#define CLKPS1  1
466#define CLKPS2  2
467#define CLTPS0  3
468#define CLTPS1  4
469#define CLTPS2  5
470#define CLKPCE  7
471
472/* SP [0x3D..0x3E] */
473
474/* SREG [0x3F] */
475
476#define WDTCR   _SFR_MEM8(0x60)
477#define WDPS0   0
478#define WDPS1   1
479#define WDPS2   2
480#define WDE     3
481#define WDCE    4
482
483/* Reserved [0x61..0x62] */
484
485#define PRR0    _SFR_MEM8(0x63)
486#define PRLFR   0
487#define PRT1    1
488#define PRT2    2
489#define PRT3    3
490#define PRTM    4
491#define PRCU    5
492#define PRDS    6
493#define PRVM    7
494
495#define __AVR_HAVE_PRR0 ((1<<PRLFR)|(1<<PRT1)|(1<<PRT2)|(1<<PRT3)|(1<<PRTM)|(1<<PRCU)|(1<<PRDS)|(1<<PRVM))
496#define __AVR_HAVE_PRR0_PRLFR
497#define __AVR_HAVE_PRR0_PRT1
498#define __AVR_HAVE_PRR0_PRT2
499#define __AVR_HAVE_PRR0_PRT3
500#define __AVR_HAVE_PRR0_PRTM
501#define __AVR_HAVE_PRR0_PRCU
502#define __AVR_HAVE_PRR0_PRDS
503#define __AVR_HAVE_PRR0_PRVM
504
505#define PRR1    _SFR_MEM8(0x64)
506#define PRCI    0
507#define PRSPI   1
508
509#define __AVR_HAVE_PRR1 ((1<<PRCI)|(1<<PRSPI))
510#define __AVR_HAVE_PRR1_PRCI
511#define __AVR_HAVE_PRR1_PRSPI
512
513#define SRCCAL  _SFR_MEM8(0x65)
514
515#define FRCCAL  _SFR_MEM8(0x66)
516
517/* Reserved [0x67..0x68] */
518
519#define EICRA   _SFR_MEM8(0x69)
520#define ISC00   0
521#define ISC01   1
522
523#define PCMSK0  _SFR_MEM8(0x6A)
524#define PCINT0  0
525#define PCINT1  1
526#define PCINT2  2
527#define PCINT3  3
528#define PCINT4  4
529#define PCINT5  5
530#define PCINT6  6
531#define PCINT7  7
532
533#define PCMSK1  _SFR_MEM8(0x6B)
534#define PCINT8  0
535#define PCINT9  1
536#define PCINT10 2
537#define PCINT11 3
538#define PCINT12 4
539#define PCINT13 5
540#define PCINT14 6
541#define PCINT15 7
542
543/* Reserved [0x6C] */
544
545#define LDCR    _SFR_MEM8(0x6D)
546#define LDE     0
547#define LDCS0   1
548#define LDCS1   2
549
550/* Reserved [0x6E..0x6F] */
551
552#define T2CNT   _SFR_MEM8(0x70)
553
554#define T2COR   _SFR_MEM8(0x71)
555
556/* Reserved [0x72] */
557
558#define T2MR    _SFR_MEM8(0x73)
559#define T2CS0   0
560#define T2CS1   1
561#define T2CS2   2
562#define T2PS0   3
563#define T2PS1   4
564#define T2PS2   5
565#define T2D0    6
566#define T2D1    7
567
568#define T2IMR   _SFR_MEM8(0x74)
569#define T2OIM   0
570#define T2CIM   1
571
572#define T3CO2R  _SFR_MEM8(0x75)
573
574#define T3CNT   _SFR_MEM8(0x76)
575
576#define T3COR   _SFR_MEM8(0x77)
577
578#define T3ICR   _SFR_MEM8(0x78)
579
580#define T3MRA   _SFR_MEM8(0x79)
581#define T3CS0   0
582#define T3CS1   1
583#define T3SCE   2
584#define T3CE0   3
585#define T3CE1   4
586#define T3CNC   5
587#define T3ICS0  6
588#define T3ICS1  7
589
590#define T3MRB   _SFR_MEM8(0x7A)
591#define T3PS0   0
592#define T3PS1   1
593#define T3PS2   2
594
595#define T3IMR   _SFR_MEM8(0x7B)
596#define T3OIM   0
597#define T3CIM   1
598#define T3CPIM  2
599#define T3C2IM  3
600
601/* Reserved [0x7C] */
602
603#define TMCR    _SFR_MEM8(0x7D)
604#define MI1S0   0
605#define MI1S1   1
606#define MI2S0   2
607#define MI2S1   3
608#define MI4S0   4
609#define MI4S1   5
610#define TMCPOL  6
611#define TMSSIE  7
612
613#define TMMR    _SFR_MEM8(0x7E)
614#define MOS0    0
615#define MOS1    1
616#define MSCS0   2
617#define MSCS1   3
618#define MOUTC   4
619#define TMMS0   5
620#define TMMS1   6
621#define TM12S   7
622
623#define TMIMR   _SFR_MEM8(0x7F)
624#define TMRXIM  0
625#define TMTXIM  1
626#define TMTCIM  2
627
628/* Reserved [0x80..0x81] */
629
630#define LFIMR   _SFR_MEM8(0x82)
631#define LFID0IM 0
632#define LFID1IM 1
633#define LFFEIM  2
634#define LFDBIM  3
635#define LFRSIM  4
636#define LFSDIM  5
637#define LFMDIM  6
638
639#define LFCAD   _SFR_MEM8(0x83)
640
641#define LFID00  _SFR_MEM8(0x84)
642
643#define LFID01  _SFR_MEM8(0x85)
644
645#define LFID02  _SFR_MEM8(0x86)
646
647#define LFID03  _SFR_MEM8(0x87)
648
649#define LFID10  _SFR_MEM8(0x88)
650
651#define LFID11  _SFR_MEM8(0x89)
652
653#define LFID12  _SFR_MEM8(0x8A)
654
655#define LFID13  _SFR_MEM8(0x8B)
656
657#define LFRD0   _SFR_MEM8(0x8C)
658
659#define LFRD1   _SFR_MEM8(0x8D)
660
661#define LFRD2   _SFR_MEM8(0x8E)
662
663#define LFRD3   _SFR_MEM8(0x8F)
664
665#define LFID0M  _SFR_MEM8(0x90)
666#define ID0FS0  0
667#define ID0FS1  1
668#define ID0FS2  2
669#define ID0FS3  3
670#define ID0FS4  4
671#define ID0E    7
672
673#define LFID1M  _SFR_MEM8(0x91)
674#define ID1FS0  0
675#define ID1FS1  1
676#define ID1FS2  2
677#define ID1FS3  3
678#define ID1FS4  4
679#define ID1E    7
680
681#define LFRDF   _SFR_MEM8(0x92)
682#define RDFS0   0
683#define RDFS1   1
684#define RDFS2   2
685#define RDFS3   3
686#define RDFS4   4
687#define RDFE    7
688
689#define LFRSD1  _SFR_MEM8(0x93)
690
691#define LFRSD2  _SFR_MEM8(0x94)
692
693#define LFRSD3  _SFR_MEM8(0x95)
694
695#define LFCC1   _SFR_MEM8(0x96)
696
697#define LFCC2   _SFR_MEM8(0x97)
698
699#define LFCC3   _SFR_MEM8(0x98)
700
701#define LFQCR   _SFR_MEM8(0x99)
702#define LFQCLL  0
703
704/* Reserved [0x9A..0x9B] */
705
706#define TPIMR   _SFR_MEM8(0x9C)
707#define TPIM    0
708
709/* Reserved [0x9D] */
710
711#define RTCCR   _SFR_MEM8(0x9E)
712#define RTCR    0
713
714#define RTCDR   _SFR_MEM8(0x9F)
715
716/* Reserved [0xA0..0xA7] */
717
718#define TMMDR   _SFR_MEM8(0xA8)
719
720#define TMBDR   _SFR_MEM8(0xA9)
721
722#define TMTDR   _SFR_MEM8(0xAA)
723
724#define TMSR    _SFR_MEM8(0xAB)
725
726#define CRCPOL  _SFR_MEM8(0xAC)
727
728#define CRCDR   _SFR_MEM8(0xAD)
729
730#define CRCCR   _SFR_MEM8(0xAE)
731#define CRCN0   0
732#define CRCN1   1
733#define CRCN2   2
734#define CRCSEL  3
735#define REFLI   4
736#define REFLO   5
737#define STVAL   6
738#define CRCRS   7
739
740#define CRCSR   _SFR_MEM8(0xAF)
741#define CRCBF   0
742
743
744
745/* Values and associated defines */
746
747
748#define SLEEP_MODE_IDLE (0x00<<1)
749#define SLEEP_MODE_EXT_PWR_SAVE (0x01<<1)
750#define SLEEP_MODE_PWR_DOWN (0x02<<1)
751#define SLEEP_MODE_PWR_SAVE (0x03<<1)
752
753/* Interrupt vectors */
754/* Vector 0 is the reset vector */
755/* Transponder Mode Interrupt */
756#define TPINT_vect            _VECTOR(1)
757#define TPINT_vect_num        1
758
759/* External Interrupt Request 0 */
760#define INT0_vect            _VECTOR(2)
761#define INT0_vect_num        2
762
763/* Pin Change Interrupt Request 0 */
764#define PCINT0_vect            _VECTOR(3)
765#define PCINT0_vect_num        3
766
767/* Pin Change Interrupt Request 1 */
768#define PCINT1_vect            _VECTOR(4)
769#define PCINT1_vect_num        4
770
771/* Voltage Monitoring Interrupt */
772#define VMINT_vect            _VECTOR(5)
773#define VMINT_vect_num        5
774
775/* Timer0 Interval Interrupt */
776#define T0INT_vect            _VECTOR(6)
777#define T0INT_vect_num        6
778
779/* LF-Receiver Identifier 0 Interrupt */
780#define LFID0INT_vect            _VECTOR(7)
781#define LFID0INT_vect_num        7
782
783/* LF-Receiver Identifier 1 Interrupt */
784#define LFID1INT_vect            _VECTOR(8)
785#define LFID1INT_vect_num        8
786
787/* LF-Receiver Frame End Interrupt */
788#define LFFEINT_vect            _VECTOR(9)
789#define LFFEINT_vect_num        9
790
791/* LF-Receiver Data Buffer full Interrupt */
792#define LFDBINT_vect            _VECTOR(10)
793#define LFDBINT_vect_num        10
794
795/* Timer/Counter3 Capture Event Interrupt */
796#define T3CAPINT_vect            _VECTOR(11)
797#define T3CAPINT_vect_num        11
798
799/* Timer/Counter3 Compare Match Interrupt */
800#define T3COMINT_vect            _VECTOR(12)
801#define T3COMINT_vect_num        12
802
803/* Timer/Counter3 Overflow Interrupt */
804#define T3OVFINT_vect            _VECTOR(13)
805#define T3OVFINT_vect_num        13
806
807/* Timer/Counter3 Compare Match 2 Interrupt */
808#define T3COM2INT_vect            _VECTOR(14)
809#define T3COM2INT_vect_num        14
810
811/* Timer/Counter2 Compare Match Interrupt */
812#define T2COMINT_vect            _VECTOR(15)
813#define T2COMINT_vect_num        15
814
815/* Timer/Counter2 Overflow Interrupt */
816#define T2OVFINT_vect            _VECTOR(16)
817#define T2OVFINT_vect_num        16
818
819/* Timer 1 Interval Interrupt */
820#define T1INT_vect            _VECTOR(17)
821#define T1INT_vect_num        17
822
823/* SPI Serial Transfer Complete Interrupt */
824#define SPISTC_vect            _VECTOR(18)
825#define SPISTC_vect_num        18
826
827/* Timer Modulator SSI Receive Buffer Interrupt */
828#define TMRXBINT_vect            _VECTOR(19)
829#define TMRXBINT_vect_num        19
830
831/* Timer Modulator SSI Transmit Buffer Interrupt */
832#define TMTXBINT_vect            _VECTOR(20)
833#define TMTXBINT_vect_num        20
834
835/* Timer Modulator Transmit Complete Interrupt */
836#define TMTXCINT_vect            _VECTOR(21)
837#define TMTXCINT_vect_num        21
838
839/* AES Interrupt */
840#define AESINT_vect            _VECTOR(22)
841#define AESINT_vect_num        22
842
843/* LF-Receiver RSSi measurement Interrupt */
844#define LFRSSINT_vect            _VECTOR(23)
845#define LFRSSINT_vect_num        23
846
847/* LF-Receiver Signal Detect Interrupt */
848#define LFSDINT_vect            _VECTOR(24)
849#define LFSDINT_vect_num        24
850
851/* LF-Receiver Manchester Decoder error Interrupt  */
852#define LFMDINT_vect            _VECTOR(25)
853#define LFMDINT_vect_num        25
854
855/* External Input Clock Monitoring Interrupt */
856#define EXCMINT_vect            _VECTOR(26)
857#define EXCMINT_vect_num        26
858
859/* External XTAL Oscillator Break Down Interrupt */
860#define EXXMINT_vect            _VECTOR(27)
861#define EXXMINT_vect_num        27
862
863/* Real Time Clock Interrupt */
864#define RTCINT_vect            _VECTOR(28)
865#define RTCINT_vect_num        28
866
867/* EEPROM Ready Interrupt */
868#define EEREADY_vect            _VECTOR(29)
869#define EEREADY_vect_num        29
870
871/* Store Program Memory Ready  */
872#define SPMREADY_vect            _VECTOR(30)
873#define SPMREADY_vect_num        30
874
875#define _VECTORS_SIZE 124
876
877
878/* Constants */
879
880#define SPM_PAGESIZE 128
881#define FLASHSTART   0x0000
882#define FLASHEND     0x3FFF
883#define RAMSTART     0x0100
884#define RAMSIZE      512
885#define RAMEND       0x02FF
886#define E2START     0
887#define E2SIZE      2048
888#define E2PAGESIZE  16
889#define E2END       0x07FF
890#define XRAMEND      RAMEND
891
892
893/* Fuses */
894
895#define FUSE_MEMORY_SIZE 1
896
897/* Fuse Byte */
898#define FUSE__32OEN      (unsigned char)~_BV(1)
899#define FUSE_Reserved    (unsigned char)~_BV(2)
900#define FUSE_EESAVE      (unsigned char)~_BV(3)
901#define FUSE_WDTON       (unsigned char)~_BV(4)
902#define FUSE_SPIEN       (unsigned char)~_BV(5)
903#define FUSE_DWEN        (unsigned char)~_BV(6)
904#define FUSE_CKDIV8      (unsigned char)~_BV(7)
905#define LFUSE_DEFAULT    (FUSE__32OEN & FUSE_Reserved & FUSE_WDTON & FUSE_SPIEN & FUSE_CKDIV8)
906
907
908
909/* Lock Bits */
910#define __LOCK_BITS_EXIST
911#define __BOOT_LOCK_BITS_0_EXIST
912#define __BOOT_LOCK_BITS_1_EXIST
913
914
915/* Signature */
916#define SIGNATURE_0 0x1E
917#define SIGNATURE_1 0x94
918#define SIGNATURE_2 0x62
919
920
921#endif /* #ifdef _AVR_ATA5790N_H_INCLUDED */
922
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