source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/ioa6286.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 3 years ago

Adding new version

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1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATA6286_H_INCLUDED
36#define _AVR_ATA6286_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "ioa6286.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINB    _SFR_IO8(0x03)
52#define PINB7   7
53#define PINB6   6
54#define PINB5   5
55#define PINB4   4
56#define PINB3   3
57#define PINB2   2
58#define PINB1   1
59#define PINB0   0
60
61#define DDRB    _SFR_IO8(0x04)
62#define DDRB7   7
63// Inserted "DDB7" from "DDRB7" due to compatibility
64#define DDB7    7
65#define DDRB6   6
66// Inserted "DDB6" from "DDRB6" due to compatibility
67#define DDB6    6
68#define DDRB5   5
69// Inserted "DDB5" from "DDRB5" due to compatibility
70#define DDB5    5
71#define DDRB4   4
72// Inserted "DDB4" from "DDRB4" due to compatibility
73#define DDB4    4
74#define DDRB3   3
75// Inserted "DDB3" from "DDRB3" due to compatibility
76#define DDB3    3
77#define DDRB2   2
78// Inserted "DDB2" from "DDRB2" due to compatibility
79#define DDB2    2
80#define DDRB1   1
81// Inserted "DDB1" from "DDRB1" due to compatibility
82#define DDB1    1
83#define DDRB0   0
84// Inserted "DDB0" from "DDRB0" due to compatibility
85#define DDB0    0
86
87#define PORTB   _SFR_IO8(0x05)
88#define PORTB7  7
89#define PORTB6  6
90#define PORTB5  5
91#define PORTB4  4
92#define PORTB3  3
93#define PORTB2  2
94#define PORTB1  1
95#define PORTB0  0
96
97#define PINC    _SFR_IO8(0x06)
98#define PINC2   2
99#define PINC1   1
100#define PINC0   0
101
102#define DDRC    _SFR_IO8(0x07)
103#define DDRC2   2
104// Inserted "DDC2" from "DDRC2" due to compatibility
105#define DDC2    2
106#define DDRC1   1
107// Inserted "DDC1" from "DDRC1" due to compatibility
108#define DDC1    1
109#define DDRC0   0
110// Inserted "DDC0" from "DDRC0" due to compatibility
111#define DDC0    0
112
113#define PORTC   _SFR_IO8(0x08)
114#define PORTC2  2
115#define PORTC1  1
116#define PORTC0  0
117
118#define PIND    _SFR_IO8(0x09)
119#define PIND7   7
120#define PIND6   6
121#define PIND5   5
122#define PIND4   4
123#define PIND3   3
124#define PIND2   2
125#define PIND1   1
126#define PIND0   0
127
128#define DDRD    _SFR_IO8(0x0A)
129#define DDRD7   7
130// Inserted "DDD7" from "DDRD7" due to compatibility
131#define DDD7    7
132#define DDRD6   6
133// Inserted "DDD6" from "DDRD6" due to compatibility
134#define DDD6    6
135#define DDRD5   5
136// Inserted "DDD5" from "DDRD5" due to compatibility
137#define DDD5    5
138#define DDRD4   4
139// Inserted "DDD4" from "DDRD4" due to compatibility
140#define DDD4    4
141#define DDRD3   3
142// Inserted "DDD3" from "DDRD3" due to compatibility
143#define DDD3    3
144#define DDRD2   2
145// Inserted "DDD2" from "DDRD2" due to compatibility
146#define DDD2    2
147#define DDRD1   1
148// Inserted "DDD1" from "DDRD1" due to compatibility
149#define DDD1    1
150#define DDRD0   0
151// Inserted "DDD0" from "DDRD0" due to compatibility
152#define DDD0    0
153
154#define PORTD   _SFR_IO8(0x0B)
155#define PORTD7  7
156#define PORTD6  6
157#define PORTD5  5
158#define PORTD4  4
159#define PORTD3  3
160#define PORTD2  2
161#define PORTD1  1
162#define PORTD0  0
163
164/* Reserved [0x0C..0x0E] */
165
166#define CMCR    _SFR_IO8(0x0F)
167#define CMM0    0
168#define CMM1    1
169#define SRCD    2
170#define CMONEN  3
171#define CCS     4
172#define ECINS   5
173#define CMCCE   7
174
175#define CMSR    _SFR_IO8(0x10)
176#define ECF     0
177
178#define T2CRA   _SFR_IO8(0x11)
179#define T2OTM   0
180#define T2CTM   1
181#define T2CR    2
182#define T2CRM   3
183#define T2ICS   5
184#define T2TS    6
185#define T2E     7
186
187#define T2CRB   _SFR_IO8(0x12)
188#define T2SCE   0
189
190/* Reserved [0x13] */
191
192#define T3CRA   _SFR_IO8(0x14)
193#define T3AC    0
194#define T3SCE   1
195#define T3CR    2
196#define T3TS    6
197#define T3E     7
198
199/* Reserved [0x15] */
200
201#define VMCSR   _SFR_IO8(0x16)
202#define VMEN    0
203#define VMLS0   1
204#define VMLS1   2
205#define VMLS2   3
206#define VMIM    4
207#define VMF     5
208#define BODPD   6
209#define BODLS   7
210
211#define PCIFR   _SFR_IO8(0x17)
212#define PCIF0   0
213#define PCIF1   1
214#define PCIF2   2
215
216#define LFFR    _SFR_IO8(0x18)
217#define LFWPF   0
218#define LFBF    1
219#define LFEDF   2
220#define LFRF    3
221
222#define SSFR    _SFR_IO8(0x19)
223#define MSENF   0
224#define MSENO   1
225
226#define T10IFR  _SFR_IO8(0x1A)
227#define T0F     0
228#define T1F     1
229
230#define T2IFR   _SFR_IO8(0x1B)
231#define T2OFF   0
232#define T2COF   1
233#define T2ICF   2
234#define T2RXF   3
235#define T2TXF   4
236#define T2TCF   5
237
238#define T3IFR   _SFR_IO8(0x1C)
239#define T3OFF   0
240#define T3COAF  1
241#define T3COBF  2
242#define T3ICF   3
243
244#define EIFR    _SFR_IO8(0x1D)
245#define INTF0   0
246#define INTF1   1
247
248#define GPIOR0  _SFR_IO8(0x1E)
249
250#define EECR    _SFR_IO8(0x1F)
251#define EERE    0
252#define EEWE    1
253#define EEMWE   2
254#define EERIE   3
255#define EEPM0   4
256#define EEPM1   5
257
258#define EEDR    _SFR_IO8(0x20)
259
260/* Combine EEARL and EEARH */
261#define EEAR    _SFR_IO16(0x21)
262
263#define EEARL   _SFR_IO8(0x21)
264#define EEARH   _SFR_IO8(0x22)
265
266#define PCICR   _SFR_IO8(0x23)
267#define PCIE0   0
268#define PCIE1   1
269#define PCIE2   2
270
271#define EIMSK   _SFR_IO8(0x24)
272#define INT0    0
273#define INT1    1
274
275/* Reserved [0x25..0x26] */
276
277#define SVCR    _SFR_IO8(0x27)
278
279#define SCR     _SFR_IO8(0x28)
280#define SMS     0
281#define SEN0    1
282#define SEN1    2
283#define SMEN    3
284
285#define SCCR    _SFR_IO8(0x29)
286#define SRCC0   0
287#define SRCC1   1
288#define SCCS0   2
289#define SCCS1   3
290#define SCCS2   4
291
292#define GPIOR1  _SFR_IO8(0x2A)
293
294#define GPIOR2  _SFR_IO8(0x2B)
295
296#define SPCR    _SFR_IO8(0x2C)
297#define SPR0    0
298#define SPR1    1
299#define CPHA    2
300#define CPOL    3
301#define MSTR    4
302#define DORD    5
303#define SPE     6
304#define SPIE    7
305
306#define SPSR    _SFR_IO8(0x2D)
307#define SPI2X   0
308#define WCOL    6
309#define SPIF    7
310
311#define SPDR    _SFR_IO8(0x2E)
312
313#define T2MDR   _SFR_IO8(0x2F)
314
315#define LFRR    _SFR_IO8(0x30)
316
317/* Reserved [0x31] */
318
319#define LFCDR   _SFR_IO8(0x32)
320#define LFDO    0
321#define LFRST   6
322#define LFSCE   7
323
324#define SMCR    _SFR_IO8(0x33)
325#define SE      0
326#define SM0     1
327#define SM1     2
328#define SM2     3
329
330#define MCUSR   _SFR_IO8(0x34)
331#define PORF    0
332#define EXTRF   1
333#define BORF    2
334#define WDRF    3
335#define TSRF    5
336
337#define MCUCR   _SFR_IO8(0x35)
338#define IVCE    0
339#define IVSEL   1
340#define PUD     4
341
342#define LFRB    _SFR_IO8(0x36)
343
344#define SPMCSR  _SFR_IO8(0x37)
345#define SELFPRGEN 0
346#define PGERS   1
347#define PGWRT   2
348#define BLBSET  3
349#define RWWSRE  4
350#define RWWSB   6
351#define SPMIE   7
352
353#define T1CR    _SFR_IO8(0x38)
354#define T1PS0   0
355#define T1PS1   1
356#define T1PS2   2
357#define T1CS0   3
358#define T1CS1   4
359#define T1CS2   5
360#define T1IE    7
361
362#define T0CR    _SFR_IO8(0x39)
363#define T0PAS0  0
364#define T0PAS1  1
365#define T0PAS2  2
366#define T0IE    3
367#define T0PR    4
368#define T0PBS0  5
369#define T0PBS1  6
370#define T0PBS2  7
371
372/* Reserved [0x3A] */
373
374#define CMIMR   _SFR_IO8(0x3B)
375#define ECIE    0
376
377#define CLKPR   _SFR_IO8(0x3C)
378#define CLKPS0  0
379#define CLKPS1  1
380#define CLKPS2  2
381#define CLTPS0  3
382#define CLTPS1  4
383#define CLTPS2  5
384#define CLPCE   7
385
386/* SP [0x3D..0x3E] */
387
388/* SREG [0x3F] */
389
390#define WDTCR   _SFR_MEM8(0x60)
391#define WDPS0   0
392#define WDPS1   1
393#define WDPS2   2
394#define WDE     3
395#define WDCE    4
396
397#define SIMSK   _SFR_MEM8(0x61)
398#define MSIE    0
399
400/* Reserved [0x62..0x63] */
401
402#define TSCR    _SFR_MEM8(0x64)
403#define TSSD    0
404
405#define SRCCAL  _SFR_MEM8(0x65)
406
407#define FRCCAL  _SFR_MEM8(0x66)
408
409#define MSVCAL  _SFR_MEM8(0x67)
410
411/* Reserved [0x68] */
412
413#define EICRA   _SFR_MEM8(0x69)
414#define ISC00   0
415#define ISC01   1
416#define ISC10   2
417#define ISC11   3
418
419#define PCMSK0  _SFR_MEM8(0x6A)
420#define PCINT0  0
421#define PCINT1  1
422#define PCINT2  2
423#define PCINT3  3
424#define PCINT4  4
425#define PCINT5  5
426#define PCINT6  6
427#define PCINT7  7
428
429#define PCMSK1  _SFR_MEM8(0x6B)
430#define PCINT8  0
431#define PCINT9  1
432#define PCINT10 2
433
434#define PCMSK2  _SFR_MEM8(0x6C)
435#define PCINT16 0
436#define PCINT17 1
437#define PCINT18 2
438#define PCINT19 3
439#define PCINT20 4
440#define PCINT21 5
441#define PCINT22 6
442#define PCINT23 7
443
444/* Reserved [0x6D] */
445
446#define T2ICRL  _SFR_MEM8(0x6E)
447
448#define T2ICR   _SFR_MEM8(0x6F)
449
450/* Combine T2CORL and T2CORH */
451#define T2COR   _SFR_MEM16(0x70)
452
453#define T2CORL  _SFR_MEM8(0x70)
454#define T2CORH  _SFR_MEM8(0x71)
455
456#define T2MRA   _SFR_MEM8(0x72)
457#define T2CS0   0
458#define T2CS1   1
459#define T2CS2   2
460#define T2CE0   3
461#define T2CE1   4
462#define T2CNC   5
463#define T2TP0   6
464#define T2TP1   7
465
466#define T2MRB   _SFR_MEM8(0x73)
467#define T2M0    0
468#define T2M1    1
469#define T2M2    2
470#define T2M3    3
471#define T2TOP   4
472#define T2CPOL  6
473#define T2SSIE  7
474
475#define T2IMR   _SFR_MEM8(0x74)
476#define T2OIM   0
477#define T2CIM   1
478#define T2CPIM  2
479#define T2RXIM  3
480#define T2TXIM  4
481#define T2TCIM  5
482
483/* Reserved [0x75] */
484
485/* Combine T3ICRL and T3ICRH */
486#define T3ICR   _SFR_MEM16(0x76)
487
488#define T3ICRL  _SFR_MEM8(0x76)
489#define T3ICRH  _SFR_MEM8(0x77)
490
491/* Combine T3CORAL and T3CORAH */
492#define T3CORA  _SFR_MEM16(0x78)
493
494#define T3CORAL _SFR_MEM8(0x78)
495#define T3CORAH _SFR_MEM8(0x79)
496
497/* Combine T3CORBL and T3CORBH */
498#define T3CORB  _SFR_MEM16(0x7A)
499
500#define T3CORBL _SFR_MEM8(0x7A)
501#define T3CORBH _SFR_MEM8(0x7B)
502
503#define T3MRA   _SFR_MEM8(0x7C)
504#define T3CS0   0
505#define T3CS1   1
506#define T3CS2   2
507#define T3CE0   3
508#define T3CE1   4
509#define T3CNC   5
510#define T3ICS0  6
511#define T3ICS1  7
512
513#define T3MRB   _SFR_MEM8(0x7D)
514#define T3M0    0
515#define T3M1    1
516#define T3M2    2
517#define T3TOP   4
518
519#define T3CRB   _SFR_MEM8(0x7E)
520#define T3CTMA  0
521#define T3SAMA  1
522#define T3CRMA  2
523#define T3CTMB  3
524#define T3SAMB  4
525#define T3CRMB  5
526#define T3CPRM  6
527
528#define T3IMR   _SFR_MEM8(0x7F)
529#define T3OIM   0
530#define T3CAIM  1
531#define T3CBIM  2
532#define T3CPIM  3
533
534/* Reserved [0x80] */
535
536#define LFIMR   _SFR_MEM8(0x81)
537#define LFWIM   0
538#define LFBIM   1
539#define LFEIM   2
540
541#define LFRCR   _SFR_MEM8(0x82)
542#define LFEN    0
543#define LFBM    1
544#define LFWM0   2
545#define LFWM1   3
546#define LFRSS   4
547#define LFCS0   5
548#define LFCS1   6
549#define LFCS2   7
550
551#define LFHCR   _SFR_MEM8(0x83)
552
553/* Combine LFIDCL and LFIDCH */
554#define LFIDC   _SFR_MEM16(0x84)
555
556#define LFIDCL  _SFR_MEM8(0x84)
557#define LFIDCH  _SFR_MEM8(0x85)
558
559/* Combine LFCALL and LFCALH */
560#define LFCAL   _SFR_MEM16(0x86)
561
562#define LFCALL  _SFR_MEM8(0x86)
563#define LFCALH  _SFR_MEM8(0x87)
564
565
566
567/* Values and associated defines */
568
569
570#define SLEEP_MODE_IDLE (0x00<<1)
571#define SLEEP_MODE_SENSOR_NOISE_REDUCTION (0x01<<1)
572#define SLEEP_MODE_PWR_DOWN (0x02<<1)
573
574/* Interrupt vectors */
575/* Vector 0 is the reset vector */
576/* External Interrupt Request 0 */
577#define INT0_vect            _VECTOR(1)
578#define INT0_vect_num        1
579
580/* External Interrupt Request 1 */
581#define INT1_vect            _VECTOR(2)
582#define INT1_vect_num        2
583
584/* Pin Change Interrupt Request 0 */
585#define PCINT0_vect            _VECTOR(3)
586#define PCINT0_vect_num        3
587
588/* Pin Change Interrupt Request 1 */
589#define PCINT1_vect            _VECTOR(4)
590#define PCINT1_vect_num        4
591
592/* Pin Change Interrupt Request 2 */
593#define PCINT2_vect            _VECTOR(5)
594#define PCINT2_vect_num        5
595
596/* Voltage Monitor Interrupt */
597#define INTVM_vect            _VECTOR(6)
598#define INTVM_vect_num        6
599
600/* Sensor Interface Interrupt */
601#define SENINT_vect            _VECTOR(7)
602#define SENINT_vect_num        7
603
604/* Timer0 Interval Interrupt */
605#define INTT0_vect            _VECTOR(8)
606#define INTT0_vect_num        8
607
608/* LF-Receiver Wake-up Interrupt */
609#define LFWP_vect            _VECTOR(9)
610#define LFWP_vect_num        9
611
612/* Timer/Counter3 Capture Event */
613#define T3CAP_vect            _VECTOR(10)
614#define T3CAP_vect_num        10
615
616/* Timer/Counter3 Compare Match A */
617#define T3COMA_vect            _VECTOR(11)
618#define T3COMA_vect_num        11
619
620/* Timer/Counter3 Compare Match B */
621#define T3COMB_vect            _VECTOR(12)
622#define T3COMB_vect_num        12
623
624/* Timer/Counter3 Overflow */
625#define T3OVF_vect            _VECTOR(13)
626#define T3OVF_vect_num        13
627
628/* Timer/Counter2 Capture Event */
629#define T2CAP_vect            _VECTOR(14)
630#define T2CAP_vect_num        14
631
632/* Timer/Counter2 Compare Match */
633#define T2COM_vect            _VECTOR(15)
634#define T2COM_vect_num        15
635
636/* Timer/Counter2 Overflow */
637#define T2OVF_vect            _VECTOR(16)
638#define T2OVF_vect_num        16
639
640/* SPI Serial Transfer Complete */
641#define SPISTC_vect            _VECTOR(17)
642#define SPISTC_vect_num        17
643
644/* LF Receive Buffer Interrupt */
645#define LFRXB_vect            _VECTOR(18)
646#define LFRXB_vect_num        18
647
648/* Timer1 Interval Interrupt */
649#define INTT1_vect            _VECTOR(19)
650#define INTT1_vect_num        19
651
652/* Timer2 SSI Receive Buffer Interrupt */
653#define T2RXB_vect            _VECTOR(20)
654#define T2RXB_vect_num        20
655
656/* Timer2 SSI Transmit Buffer Interrupt */
657#define T2TXB_vect            _VECTOR(21)
658#define T2TXB_vect_num        21
659
660/* Timer2 SSI Transmit Complete Interrupt */
661#define T2TXC_vect            _VECTOR(22)
662#define T2TXC_vect_num        22
663
664/* LF-Receiver End of Burst Interrupt */
665#define LFREOB_vect            _VECTOR(23)
666#define LFREOB_vect_num        23
667
668/* External Input Clock break down Interrupt */
669#define EXCM_vect            _VECTOR(24)
670#define EXCM_vect_num        24
671
672/* EEPROM Ready Interrupt */
673#define EEREADY_vect            _VECTOR(25)
674#define EEREADY_vect_num        25
675
676/* Store Program Memory Ready */
677#define SPM_RDY_vect            _VECTOR(26)
678#define SPM_RDY_vect_num        26
679
680#define _VECTORS_SIZE 54
681
682
683/* Constants */
684
685#define SPM_PAGESIZE 64
686#define FLASHSTART   0x0000
687#define FLASHEND     0x1FFF
688#define RAMSTART     0x0100
689#define RAMSIZE      512
690#define RAMEND       0x02FF
691#define E2START     0
692#define E2SIZE      320
693#define E2PAGESIZE  4
694#define E2END       0x013F
695#define XRAMEND      RAMEND
696
697
698/* Fuses */
699
700#define FUSE_MEMORY_SIZE 2
701
702/* Low Fuse Byte */
703#define FUSE_TSRDI       (unsigned char)~_BV(0)
704#define FUSE_BODEN       (unsigned char)~_BV(1)
705#define FUSE_FRCFS       (unsigned char)~_BV(2)
706#define FUSE_WDRCON      (unsigned char)~_BV(3)
707#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(4)
708#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(5)
709#define FUSE_CKOUT       (unsigned char)~_BV(6)
710#define FUSE_CKDIV8      (unsigned char)~_BV(7)
711#define LFUSE_DEFAULT    (FUSE_BODEN & FUSE_FRCFS & FUSE_WDRCON & FUSE_SUT_CKSEL0 & FUSE_CKDIV8)
712
713
714/* High Fuse Byte */
715#define FUSE_BOOTRST     (unsigned char)~_BV(0)
716#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
717#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
718#define FUSE_EESAVE      (unsigned char)~_BV(3)
719#define FUSE_WDTON       (unsigned char)~_BV(4)
720#define FUSE_SPIEN       (unsigned char)~_BV(5)
721#define FUSE_DWEN        (unsigned char)~_BV(6)
722#define FUSE_EELOCK      (unsigned char)~_BV(7)
723#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
724
725
726
727/* Lock Bits */
728#define __LOCK_BITS_EXIST
729#define __BOOT_LOCK_BITS_0_EXIST
730#define __BOOT_LOCK_BITS_1_EXIST
731
732
733/* Signature */
734#define SIGNATURE_0 0x1E
735#define SIGNATURE_1 0x93
736#define SIGNATURE_2 0x82
737
738
739#endif /* #ifdef _AVR_ATA6286_H_INCLUDED */
740
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