source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/ioa6614q.h @ 46

Last change on this file since 46 was 46, checked in by jrpelegrina, 4 years ago

First release to Xenial

File size: 16.7 KB
Line 
1/*****************************************************************************
2 *
3 * Copyright (C) 2014 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATA6614Q_H_INCLUDED
36#define _AVR_ATA6614Q_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "ioa6614q.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINB    _SFR_IO8(0x03)
52#define PINB7   7
53#define PINB6   6
54#define PINB5   5
55#define PINB4   4
56#define PINB3   3
57#define PINB2   2
58#define PINB1   1
59#define PINB0   0
60
61#define DDRB    _SFR_IO8(0x04)
62#define DDB0    0
63#define DDB1    1
64#define DDB2    2
65#define DDB3    3
66#define DDB4    4
67#define DDB5    5
68#define DDB6    6
69#define DDB7    7
70
71#define PORTB   _SFR_IO8(0x05)
72#define PORTB7  7
73#define PORTB6  6
74#define PORTB5  5
75#define PORTB4  4
76#define PORTB3  3
77#define PORTB2  2
78#define PORTB1  1
79#define PORTB0  0
80
81#define PINC    _SFR_IO8(0x06)
82#define PINC6   6
83#define PINC5   5
84#define PINC4   4
85#define PINC3   3
86#define PINC2   2
87#define PINC1   1
88#define PINC0   0
89
90#define DDRC    _SFR_IO8(0x07)
91#define DDC0    0
92#define DDC1    1
93#define DDC2    2
94#define DDC3    3
95#define DDC4    4
96#define DDC5    5
97#define DDC6    6
98
99#define PORTC   _SFR_IO8(0x08)
100#define PORTC6  6
101#define PORTC5  5
102#define PORTC4  4
103#define PORTC3  3
104#define PORTC2  2
105#define PORTC1  1
106#define PORTC0  0
107
108#define PIND    _SFR_IO8(0x09)
109#define PIND7   7
110#define PIND6   6
111#define PIND5   5
112#define PIND4   4
113#define PIND3   3
114#define PIND2   2
115#define PIND1   1
116#define PIND0   0
117
118#define DDRD    _SFR_IO8(0x0A)
119#define DDD0    0
120#define DDD1    1
121#define DDD2    2
122#define DDD3    3
123#define DDD4    4
124#define DDD5    5
125#define DDD6    6
126#define DDD7    7
127
128#define PORTD   _SFR_IO8(0x0B)
129#define PORTD7  7
130#define PORTD6  6
131#define PORTD5  5
132#define PORTD4  4
133#define PORTD3  3
134#define PORTD2  2
135#define PORTD1  1
136#define PORTD0  0
137
138/* Reserved [0x0C..0x14] */
139
140#define TIFR0   _SFR_IO8(0x15)
141#define TOV0    0
142#define OCF0A   1
143#define OCF0B   2
144
145#define TIFR1   _SFR_IO8(0x16)
146#define TOV1    0
147#define OCF1A   1
148#define OCF1B   2
149#define ICF1    5
150
151#define TIFR2   _SFR_IO8(0x17)
152#define TOV2    0
153#define OCF2A   1
154#define OCF2B   2
155
156/* Reserved [0x18..0x1A] */
157
158#define PCIFR   _SFR_IO8(0x1B)
159#define PCIF0   0
160#define PCIF1   1
161#define PCIF2   2
162
163#define EIFR    _SFR_IO8(0x1C)
164#define INTF0   0
165#define INTF1   1
166
167#define EIMSK   _SFR_IO8(0x1D)
168#define INT0    0
169#define INT1    1
170
171#define GPIOR0  _SFR_IO8(0x1E)
172
173#define EECR    _SFR_IO8(0x1F)
174#define EERE    0
175#define EEPE    1
176#define EEMPE   2
177#define EERIE   3
178#define EEPM0   4
179#define EEPM1   5
180
181#define EEDR    _SFR_IO8(0x20)
182
183/* Combine EEARL and EEARH */
184#define EEAR    _SFR_IO16(0x21)
185
186#define EEARL   _SFR_IO8(0x21)
187#define EEARH   _SFR_IO8(0x22)
188
189#define GTCCR   _SFR_IO8(0x23)
190#define PSRSYNC 0
191#define TSM     7
192#define PSRASY  1
193
194#define TCCR0A  _SFR_IO8(0x24)
195#define WGM00   0
196#define WGM01   1
197#define COM0B0  4
198#define COM0B1  5
199#define COM0A0  6
200#define COM0A1  7
201
202#define TCCR0B  _SFR_IO8(0x25)
203#define CS00    0
204#define CS01    1
205#define CS02    2
206#define WGM02   3
207#define FOC0B   6
208#define FOC0A   7
209
210#define TCNT0   _SFR_IO8(0x26)
211
212#define OCR0A   _SFR_IO8(0x27)
213
214#define OCR0B   _SFR_IO8(0x28)
215
216/* Reserved [0x29] */
217
218#define GPIOR1  _SFR_IO8(0x2A)
219
220#define GPIOR2  _SFR_IO8(0x2B)
221
222#define SPCR    _SFR_IO8(0x2C)
223#define SPR0    0
224#define SPR1    1
225#define CPHA    2
226#define CPOL    3
227#define MSTR    4
228#define DORD    5
229#define SPE     6
230#define SPIE    7
231
232#define SPSR    _SFR_IO8(0x2D)
233#define SPI2X   0
234#define WCOL    6
235#define SPIF    7
236
237#define SPDR    _SFR_IO8(0x2E)
238
239/* Reserved [0x2F] */
240
241#define ACSR    _SFR_IO8(0x30)
242#define ACIS0   0
243#define ACIS1   1
244#define ACIC    2
245#define ACIE    3
246#define ACI     4
247#define ACO     5
248#define ACBG    6
249#define ACD     7
250
251/* Reserved [0x31..0x32] */
252
253#define SMCR    _SFR_IO8(0x33)
254#define SE      0
255#define SM0     1
256#define SM1     2
257#define SM2     3
258
259#define MCUSR   _SFR_IO8(0x34)
260#define PORF    0
261#define EXTRF   1
262#define BORF    2
263#define WDRF    3
264
265#define MCUCR   _SFR_IO8(0x35)
266#define IVCE    0
267#define IVSEL   1
268#define PUD     4
269#define BODSE   5
270#define BODS    6
271
272/* Reserved [0x36] */
273
274#define SPMCSR  _SFR_IO8(0x37)
275#define SELFPRGEN 0
276#define PGERS   1
277#define PGWRT   2
278#define BLBSET  3
279#define RWWSRE  4
280#define RWWSB   6
281#define SPMIE   7
282
283/* Reserved [0x38..0x3C] */
284
285/* SP [0x3D..0x3E] */
286
287/* SREG [0x3F] */
288
289#define WDTCSR  _SFR_MEM8(0x60)
290#define WDE     3
291#define WDCE    4
292#define WDP0    0
293#define WDP1    1
294#define WDP2    2
295#define WDP3    5
296#define WDIE    6
297#define WDIF    7
298
299#define CLKPR   _SFR_MEM8(0x61)
300#define CLKPS0  0
301#define CLKPS1  1
302#define CLKPS2  2
303#define CLKPS3  3
304#define CLKPCE  7
305
306/* Reserved [0x62..0x63] */
307
308#define PRR     _SFR_MEM8(0x64)
309#define PRADC   0
310#define PRUSART0 1
311#define PRSPI   2
312#define PRTIM1  3
313#define PRTIM0  5
314#define PRTIM2  6
315#define PRTWI   7
316
317/* Reserved [0x65] */
318
319#define OSCCAL  _SFR_MEM8(0x66)
320#define OSCCAL0 0
321#define OSCCAL1 1
322#define OSCCAL2 2
323#define OSCCAL3 3
324#define OSCCAL4 4
325#define OSCCAL5 5
326#define OSCCAL6 6
327#define OSCCAL7 7
328
329/* Reserved [0x67] */
330
331#define PCICR   _SFR_MEM8(0x68)
332#define PCIE0   0
333#define PCIE1   1
334#define PCIE2   2
335
336#define EICRA   _SFR_MEM8(0x69)
337#define ISC00   0
338#define ISC01   1
339#define ISC10   2
340#define ISC11   3
341
342/* Reserved [0x6A] */
343
344#define PCMSK0  _SFR_MEM8(0x6B)
345#define PCINT0  0
346#define PCINT1  1
347#define PCINT2  2
348#define PCINT3  3
349#define PCINT4  4
350#define PCINT5  5
351#define PCINT6  6
352#define PCINT7  7
353
354#define PCMSK1  _SFR_MEM8(0x6C)
355#define PCINT8  0
356#define PCINT9  1
357#define PCINT10 2
358#define PCINT11 3
359#define PCINT12 4
360#define PCINT13 5
361#define PCINT14 6
362
363#define PCMSK2  _SFR_MEM8(0x6D)
364#define PCINT16 0
365#define PCINT17 1
366#define PCINT18 2
367#define PCINT19 3
368#define PCINT20 4
369#define PCINT21 5
370#define PCINT22 6
371#define PCINT23 7
372
373#define TIMSK0  _SFR_MEM8(0x6E)
374#define TOIE0   0
375#define OCIE0A  1
376#define OCIE0B  2
377
378#define TIMSK1  _SFR_MEM8(0x6F)
379#define TOIE1   0
380#define OCIE1A  1
381#define OCIE1B  2
382#define ICIE1   5
383
384#define TIMSK2  _SFR_MEM8(0x70)
385#define TOIE2   0
386#define OCIE2A  1
387#define OCIE2B  2
388
389/* Reserved [0x71..0x77] */
390
391/* Combine ADCL and ADCH */
392#ifndef __ASSEMBLER__
393#define ADC     _SFR_MEM16(0x78)
394#endif
395#define ADCW    _SFR_MEM16(0x78)
396
397#define ADCL    _SFR_MEM8(0x78)
398#define ADCH    _SFR_MEM8(0x79)
399
400#define ADCSRA  _SFR_MEM8(0x7A)
401#define ADPS0   0
402#define ADPS1   1
403#define ADPS2   2
404#define ADIE    3
405#define ADIF    4
406#define ADATE   5
407#define ADSC    6
408#define ADEN    7
409
410#define ADCSRB  _SFR_MEM8(0x7B)
411#define ADTS0   0
412#define ADTS1   1
413#define ADTS2   2
414#define ACME    6
415
416#define ADMUX   _SFR_MEM8(0x7C)
417#define MUX0    0
418#define MUX1    1
419#define MUX2    2
420#define MUX3    3
421#define ADLAR   5
422#define REFS0   6
423#define REFS1   7
424
425/* Reserved [0x7D] */
426
427#define DIDR0   _SFR_MEM8(0x7E)
428#define ADC0D   0
429#define ADC1D   1
430#define ADC2D   2
431#define ADC3D   3
432#define ADC4D   4
433#define ADC5D   5
434
435#define DIDR1   _SFR_MEM8(0x7F)
436#define AIN0D   0
437#define AIN1D   1
438
439#define TCCR1A  _SFR_MEM8(0x80)
440#define WGM10   0
441#define WGM11   1
442#define COM1B0  4
443#define COM1B1  5
444#define COM1A0  6
445#define COM1A1  7
446
447#define TCCR1B  _SFR_MEM8(0x81)
448#define CS10    0
449#define CS11    1
450#define CS12    2
451#define WGM12   3
452#define WGM13   4
453#define ICES1   6
454#define ICNC1   7
455
456#define TCCR1C  _SFR_MEM8(0x82)
457#define FOC1B   6
458#define FOC1A   7
459
460/* Reserved [0x83] */
461
462/* Combine TCNT1L and TCNT1H */
463#define TCNT1   _SFR_MEM16(0x84)
464
465#define TCNT1L  _SFR_MEM8(0x84)
466#define TCNT1H  _SFR_MEM8(0x85)
467
468/* Combine ICR1L and ICR1H */
469#define ICR1    _SFR_MEM16(0x86)
470
471#define ICR1L   _SFR_MEM8(0x86)
472#define ICR1H   _SFR_MEM8(0x87)
473
474/* Combine OCR1AL and OCR1AH */
475#define OCR1A   _SFR_MEM16(0x88)
476
477#define OCR1AL  _SFR_MEM8(0x88)
478#define OCR1AH  _SFR_MEM8(0x89)
479
480/* Combine OCR1BL and OCR1BH */
481#define OCR1B   _SFR_MEM16(0x8A)
482
483#define OCR1BL  _SFR_MEM8(0x8A)
484#define OCR1BH  _SFR_MEM8(0x8B)
485
486/* Reserved [0x8C..0xAF] */
487
488#define TCCR2A  _SFR_MEM8(0xB0)
489#define WGM20   0
490#define WGM21   1
491#define COM2B0  4
492#define COM2B1  5
493#define COM2A0  6
494#define COM2A1  7
495
496#define TCCR2B  _SFR_MEM8(0xB1)
497#define CS20    0
498#define CS21    1
499#define CS22    2
500#define WGM22   3
501#define FOC2B   6
502#define FOC2A   7
503
504#define TCNT2   _SFR_MEM8(0xB2)
505
506#define OCR2A   _SFR_MEM8(0xB3)
507
508#define OCR2B   _SFR_MEM8(0xB4)
509
510/* Reserved [0xB5] */
511
512#define ASSR    _SFR_MEM8(0xB6)
513#define TCR2BUB 0
514#define TCR2AUB 1
515#define OCR2BUB 2
516#define OCR2AUB 3
517#define TCN2UB  4
518#define AS2     5
519#define EXCLK   6
520
521/* Reserved [0xB7] */
522
523#define TWBR    _SFR_MEM8(0xB8)
524
525#define TWSR    _SFR_MEM8(0xB9)
526#define TWPS0   0
527#define TWPS1   1
528#define TWS3    3
529#define TWS4    4
530#define TWS5    5
531#define TWS6    6
532#define TWS7    7
533
534#define TWAR    _SFR_MEM8(0xBA)
535#define TWGCE   0
536#define TWA0    1
537#define TWA1    2
538#define TWA2    3
539#define TWA3    4
540#define TWA4    5
541#define TWA5    6
542#define TWA6    7
543
544#define TWDR    _SFR_MEM8(0xBB)
545
546#define TWCR    _SFR_MEM8(0xBC)
547#define TWIE    0
548#define TWEN    2
549#define TWWC    3
550#define TWSTO   4
551#define TWSTA   5
552#define TWEA    6
553#define TWINT   7
554
555#define TWAMR   _SFR_MEM8(0xBD)
556#define TWAM0   1
557#define TWAM1   2
558#define TWAM2   3
559#define TWAM3   4
560#define TWAM4   5
561#define TWAM5   6
562#define TWAM6   7
563
564/* Reserved [0xBE..0xBF] */
565
566#define UCSR0A  _SFR_MEM8(0xC0)
567#define MPCM0   0
568#define U2X0    1
569#define UPE0    2
570#define DOR0    3
571#define FE0     4
572#define UDRE0   5
573#define TXC0    6
574#define RXC0    7
575
576#define UCSR0B  _SFR_MEM8(0xC1)
577#define TXB80   0
578#define RXB80   1
579#define UCSZ02  2
580#define TXEN0   3
581#define RXEN0   4
582#define UDRIE0  5
583#define TXCIE0  6
584#define RXCIE0  7
585
586#define UCSR0C  _SFR_MEM8(0xC2)
587#define UCPOL0  0
588#define UCPHA0  1
589#define UDORD0  2
590#define UCSZ00  1
591#define UCSZ01  2
592#define USBS0   3
593#define UPM00   4
594#define UPM01   5
595#define UMSEL00 6
596#define UMSEL01 7
597
598/* Reserved [0xC3] */
599
600/* Combine UBRR0L and UBRR0H */
601#define UBRR0   _SFR_MEM16(0xC4)
602
603#define UBRR0L  _SFR_MEM8(0xC4)
604#define UBRR0H  _SFR_MEM8(0xC5)
605
606#define UDR0    _SFR_MEM8(0xC6)
607
608
609
610/* Interrupt vectors */
611/* Vector 0 is the reset vector */
612/* External Interrupt Request 0 */
613#define INT0_vect            _VECTOR(1)
614#define INT0_vect_num        1
615
616/* External Interrupt Request 1 */
617#define INT1_vect            _VECTOR(2)
618#define INT1_vect_num        2
619
620/* Pin Change Interrupt Request 0 */
621#define PCINT0_vect            _VECTOR(3)
622#define PCINT0_vect_num        3
623
624/* Pin Change Interrupt Request 0 */
625#define PCINT1_vect            _VECTOR(4)
626#define PCINT1_vect_num        4
627
628/* Pin Change Interrupt Request 1 */
629#define PCINT2_vect            _VECTOR(5)
630#define PCINT2_vect_num        5
631
632/* Watchdog Time-out Interrupt */
633#define WDT_vect            _VECTOR(6)
634#define WDT_vect_num        6
635
636/* Timer/Counter2 Compare Match A */
637#define TIMER2_COMPA_vect            _VECTOR(7)
638#define TIMER2_COMPA_vect_num        7
639
640/* Timer/Counter2 Compare Match A */
641#define TIMER2_COMPB_vect            _VECTOR(8)
642#define TIMER2_COMPB_vect_num        8
643
644/* Timer/Counter2 Overflow */
645#define TIMER2_OVF_vect            _VECTOR(9)
646#define TIMER2_OVF_vect_num        9
647
648/* Timer/Counter1 Capture Event */
649#define TIMER1_CAPT_vect            _VECTOR(10)
650#define TIMER1_CAPT_vect_num        10
651
652/* Timer/Counter1 Compare Match A */
653#define TIMER1_COMPA_vect            _VECTOR(11)
654#define TIMER1_COMPA_vect_num        11
655
656/* Timer/Counter1 Compare Match B */
657#define TIMER1_COMPB_vect            _VECTOR(12)
658#define TIMER1_COMPB_vect_num        12
659
660/* Timer/Counter1 Overflow */
661#define TIMER1_OVF_vect            _VECTOR(13)
662#define TIMER1_OVF_vect_num        13
663
664/* TimerCounter0 Compare Match A */
665#define TIMER0_COMPA_vect            _VECTOR(14)
666#define TIMER0_COMPA_vect_num        14
667
668/* TimerCounter0 Compare Match B */
669#define TIMER0_COMPB_vect            _VECTOR(15)
670#define TIMER0_COMPB_vect_num        15
671
672/* Timer/Couner0 Overflow */
673#define TIMER0_OVF_vect            _VECTOR(16)
674#define TIMER0_OVF_vect_num        16
675
676/* SPI Serial Transfer Complete */
677#define SPI_STC_vect            _VECTOR(17)
678#define SPI_STC_vect_num        17
679
680/* USART Rx Complete */
681#define USART_RX_vect            _VECTOR(18)
682#define USART_RX_vect_num        18
683
684/* USART, Data Register Empty */
685#define USART_UDRE_vect            _VECTOR(19)
686#define USART_UDRE_vect_num        19
687
688/* USART Tx Complete */
689#define USART_TX_vect            _VECTOR(20)
690#define USART_TX_vect_num        20
691
692/* ADC Conversion Complete */
693#define ADC_vect            _VECTOR(21)
694#define ADC_vect_num        21
695
696/* EEPROM Ready */
697#define EE_READY_vect            _VECTOR(22)
698#define EE_READY_vect_num        22
699
700/* Analog Comparator */
701#define ANALOG_COMP_vect            _VECTOR(23)
702#define ANALOG_COMP_vect_num        23
703
704/* Two-wire Serial Interface */
705#define TWI_vect            _VECTOR(24)
706#define TWI_vect_num        24
707
708/* Store Program Memory Read */
709#define SPM_Ready_vect            _VECTOR(25)
710#define SPM_Ready_vect_num        25
711
712#define _VECTORS_SIZE 104
713
714
715/* Constants */
716
717#define SPM_PAGESIZE 128
718#define FLASHSTART   0x0000
719#define FLASHEND     0x7FFF
720#define RAMSTART     0x0100
721#define RAMSIZE      2048
722#define RAMEND       0x08FF
723#define E2START     0
724#define E2SIZE      1024
725#define E2PAGESIZE  4
726#define E2END       0x03FF
727#define XRAMEND      RAMEND
728
729
730/* Fuses */
731
732#define FUSE_MEMORY_SIZE 3
733
734/* Low Fuse Byte */
735#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
736#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
737#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
738#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
739#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
740#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
741#define FUSE_CKOUT       (unsigned char)~_BV(6)
742#define FUSE_CKDIV8      (unsigned char)~_BV(7)
743
744/* High Fuse Byte */
745#define FUSE_BOOTRST     (unsigned char)~_BV(0)
746#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
747#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
748#define FUSE_EESAVE      (unsigned char)~_BV(3)
749#define FUSE_WDTON       (unsigned char)~_BV(4)
750#define FUSE_SPIEN       (unsigned char)~_BV(5)
751#define FUSE_DWEN        (unsigned char)~_BV(6)
752#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
753
754/* Extended Fuse Byte */
755#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
756#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
757#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
758
759
760/* Lock Bits */
761#define __LOCK_BITS_EXIST
762#define __BOOT_LOCK_BITS_0_EXIST
763#define __BOOT_LOCK_BITS_1_EXIST
764
765
766/* Signature */
767#define SIGNATURE_0 0x1E
768#define SIGNATURE_1 0x95
769#define SIGNATURE_2 0x0F
770
771
772#endif /* #ifdef _AVR_ATA6614Q_H_INCLUDED */
773
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