source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/ioat94k.h @ 46

Last change on this file since 46 was 46, checked in by jrpelegrina, 4 years ago

First release to Xenial

File size: 14.5 KB
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1/* Copyright (c) 2002, Marek Michalkiewicz
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: ioat94k.h 602 2004-11-01 22:23:56Z arcanum $ */
32
33/* avr/ioat94k.h - definitions for AT94K series FPSLIC(tm) */
34
35#ifndef _AVR_IOAT94K_H_
36#define _AVR_IOAT94K_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "ioat94k.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* I/O registers */
51
52/* UART1 Baud Rate Register */
53#define UBRR1   _SFR_IO8(0x00)
54
55/* UART1 Control and Status Registers */
56#define UCSR1B  _SFR_IO8(0x01)
57#define UCSR1A  _SFR_IO8(0x02)
58
59/* UART1 I/O Data Register */
60#define UDR1    _SFR_IO8(0x03)
61
62/* 0x04 reserved */
63
64/* Input Pins, Port E */
65#define PINE    _SFR_IO8(0x05)
66
67/* Data Direction Register, Port E */
68#define DDRE    _SFR_IO8(0x06)
69
70/* Data Register, Port E */
71#define PORTE   _SFR_IO8(0x07)
72
73/* On Chip Debug Register (reserved) */
74#define OCDR    _SFR_IO8(0x08)
75
76/* UART0 Baud Rate Register */
77#define UBRR0   _SFR_IO8(0x09)
78
79/* UART0 Control and Status Registers */
80#define UCSR0B  _SFR_IO8(0x0A)
81#define UCSR0A  _SFR_IO8(0x0B)
82
83/* UART0 I/O Data Register */
84#define UDR0    _SFR_IO8(0x0C)
85
86/* 0x0D..0x0F reserved */
87
88/* Input Pins, Port D */
89#define PIND    _SFR_IO8(0x10)
90
91/* Data Direction Register, Port D */
92#define DDRD    _SFR_IO8(0x11)
93
94/* Data Register, Port D */
95#define PORTD   _SFR_IO8(0x12)
96
97/* FPGA I/O Select Control Register */
98#define FISCR   _SFR_IO8(0x13)
99
100/* FPGA I/O Select Registers A, B, C, D */
101#define FISUA   _SFR_IO8(0x14)
102#define FISUB   _SFR_IO8(0x15)
103#define FISUC   _SFR_IO8(0x16)
104#define FISUD   _SFR_IO8(0x17)
105
106/* FPGA Cache Logic(R) registers (top secret, under NDA) */
107#define FPGAX   _SFR_IO8(0x18)
108#define FPGAY   _SFR_IO8(0x19)
109#define FPGAZ   _SFR_IO8(0x1A)
110#define FPGAD   _SFR_IO8(0x1B)
111
112/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
113
114/* 2-wire Serial Bit Rate Register */
115#define TWBR    _SFR_IO8(0x1C)
116
117/* 2-wire Serial Status Register */
118#define TWSR    _SFR_IO8(0x1D)
119
120/* 2-wire Serial (Slave) Address Register */
121#define TWAR    _SFR_IO8(0x1E)
122
123/* 2-wire Serial Data Register */
124#define TWDR    _SFR_IO8(0x1F)
125
126/* UART Baud Register High */
127#define UBRRH   _SFR_IO8(0x20)
128#define UBRRHI  UBRRH           /* New name in datasheet (1138F-FPSLI-06/02) */
129
130/* Watchdog Timer Control Register */
131#define WDTCR   _SFR_IO8(0x21)
132
133/* Timer/Counter2 Output Compare Register */
134#define OCR2    _SFR_IO8(0x22)
135
136/* Timer/Counter2 (8-bit) */
137#define TCNT2   _SFR_IO8(0x23)
138
139/* Timer/Counter1 Input Capture Register */
140#define ICR1    _SFR_IO16(0x24)
141#define ICR1L   _SFR_IO8(0x24)
142#define ICR1H   _SFR_IO8(0x25)
143
144/* Asynchronous mode StatuS Register */
145#define ASSR    _SFR_IO8(0x26)
146
147/* Timer/Counter2 Control Register */
148#define TCCR2   _SFR_IO8(0x27)
149
150/* Timer/Counter1 Output Compare RegisterB */
151#define OCR1B   _SFR_IO16(0x28)
152#define OCR1BL  _SFR_IO8(0x28)
153#define OCR1BH  _SFR_IO8(0x29)
154
155/* Timer/Counter1 Output Compare RegisterA */
156#define OCR1A   _SFR_IO16(0x2A)
157#define OCR1AL  _SFR_IO8(0x2A)
158#define OCR1AH  _SFR_IO8(0x2B)
159
160/* Timer/Counter1 */
161#define TCNT1   _SFR_IO16(0x2C)
162#define TCNT1L  _SFR_IO8(0x2C)
163#define TCNT1H  _SFR_IO8(0x2D)
164
165/* Timer/Counter1 Control Register B */
166#define TCCR1B  _SFR_IO8(0x2E)
167
168/* Timer/Counter1 Control Register A */
169#define TCCR1A  _SFR_IO8(0x2F)
170
171/* Special Function IO Register */
172#define SFIOR   _SFR_IO8(0x30)
173
174/* Timer/Counter0 Output Compare Register */
175#define OCR0    _SFR_IO8(0x31)
176
177/* Timer/Counter0 (8-bit) */
178#define TCNT0   _SFR_IO8(0x32)
179
180/* Timer/Counter0 Control Register */
181#define TCCR0   _SFR_IO8(0x33)
182
183/* 0x34 reserved */
184
185/* MCU Control/Status Register */
186#define MCUR    _SFR_IO8(0x35)
187
188/* 2-wire Serial Control Register */
189#define TWCR    _SFR_IO8(0x36)
190
191/* 0x37 reserved */
192
193/* Timer/Counter Interrupt Flag Register */
194#define TIFR    _SFR_IO8(0x38)
195
196/* Timer/Counter Interrupt MaSK Register */
197#define TIMSK   _SFR_IO8(0x39)
198
199/* Software Control Register */
200#define SFTCR   _SFR_IO8(0x3A)
201
202/* External Interrupt Mask/Flag Register */
203#define EIMF    _SFR_IO8(0x3B)
204
205/* 0x3C reserved */
206
207/* 0x3D..0x3E SP */
208
209/* 0x3F SREG */
210
211/* Interrupt vectors */
212
213#define SIG_FPGA_INTERRUPT0     _VECTOR(1)   /* FPGA_INT0  */       
214#define SIG_INTERRUPT0          _VECTOR(2)   /* EXT_INT0   */
215#define SIG_FPGA_INTERRUPT1     _VECTOR(3)   /* FPGA_INT1  */       
216#define SIG_INTERRUPT1          _VECTOR(4)   /* EXT_INT1   */
217#define SIG_FPGA_INTERRUPT2     _VECTOR(5)   /* FPGA_INT2  */       
218#define SIG_INTERRUPT2          _VECTOR(6)   /* EXT_INT2   */
219#define SIG_FPGA_INTERRUPT3     _VECTOR(7)   /* FPGA_INT3  */       
220#define SIG_INTERRUPT3          _VECTOR(8)   /* EXT_INT3   */
221#define SIG_OUTPUT_COMPARE2     _VECTOR(9)   /* TIM2_COMP  */       
222#define SIG_OVERFLOW2           _VECTOR(10)  /* TIM2_OVF   */       
223#define SIG_INPUT_CAPTURE1      _VECTOR(11)  /* TIM1_CAPT  */       
224#define SIG_OUTPUT_COMPARE1A    _VECTOR(12)  /* TIM1_COMPA */       
225#define SIG_OUTPUT_COMPARE1B    _VECTOR(13)  /* TIM1_COMPB */       
226#define SIG_OVERFLOW1           _VECTOR(14)  /* TIM1_OVF   */       
227#define SIG_OUTPUT_COMPARE0     _VECTOR(15)  /* TIM0_COMP  */       
228#define SIG_OVERFLOW0           _VECTOR(16)  /* TIM0_OVF   */       
229#define SIG_FPGA_INTERRUPT4     _VECTOR(17)  /* FPGA_INT4  */       
230#define SIG_FPGA_INTERRUPT5     _VECTOR(18)  /* FPGA_INT5  */       
231#define SIG_FPGA_INTERRUPT6     _VECTOR(19)  /* FPGA_INT6  */       
232#define SIG_FPGA_INTERRUPT7     _VECTOR(20)  /* FPGA_INT7  */       
233#define SIG_UART0_RECV          _VECTOR(21)  /* UART0_RXC  */
234#define SIG_UART0_DATA          _VECTOR(22)  /* UART0_DRE  */
235#define SIG_UART0_TRANS         _VECTOR(23)  /* UART0_TXC  */
236#define SIG_FPGA_INTERRUPT8     _VECTOR(24)  /* FPGA_INT8  */       
237#define SIG_FPGA_INTERRUPT9     _VECTOR(25)  /* FPGA_INT9  */       
238#define SIG_FPGA_INTERRUPT10    _VECTOR(26)  /* FPGA_INT10 */       
239#define SIG_FPGA_INTERRUPT11    _VECTOR(27)  /* FPGA_INT11 */       
240#define SIG_UART1_RECV          _VECTOR(28)  /* UART1_RXC  */
241#define SIG_UART1_DATA          _VECTOR(29)  /* UART1_DRE  */
242#define SIG_UART1_TRANS         _VECTOR(30)  /* UART1_TXC  */
243#define SIG_FPGA_INTERRUPT12    _VECTOR(31)  /* FPGA_INT12 */
244#define SIG_FPGA_INTERRUPT13    _VECTOR(32)  /* FPGA_INT13 */
245#define SIG_FPGA_INTERRUPT14    _VECTOR(33)  /* FPGA_INT14 */
246#define SIG_FPGA_INTERRUPT15    _VECTOR(34)  /* FPGA_INT15 */
247#define SIG_2WIRE_SERIAL        _VECTOR(35)  /* TWS_INT    */
248
249#define _VECTORS_SIZE 144
250
251/* Bit numbers (SFRs alphabetically sorted) */
252
253/* ASSR */
254#define AS2           3
255#define TCN2UB        2
256#define OCR2UB        1
257#define TCR2UB        0
258
259/* DDRD */
260#define DDD7          7
261#define DDD6          6
262#define DDD5          5
263#define DDD4          4
264#define DDD3          3
265#define DDD2          2
266#define DDD1          1
267#define DDD0          0
268
269/* DDRE */
270#define DDE7          7
271#define DDE6          6
272#define DDE5          5
273#define DDE4          4
274#define DDE3          3
275#define DDE2          2
276#define DDE1          1
277#define DDE0          0
278
279/* EIMF */
280#define INTF3         7
281#define INTF2         6
282#define INTF1         5
283#define INTF0         4
284#define INT3          3
285#define INT2          2
286#define INT1          1
287#define INT0          0
288
289/* FISCR */
290#define FIADR         7
291#define XFIS1         1
292#define XFIS0         0
293
294/* FISUA */
295#define FIF3          7
296#define FIF2          6
297#define FIF1          5
298#define FIF0          4
299#define FINT3         3
300#define FINT2         2
301#define FINT1         1
302#define FINT0         0
303
304/* FISUB */
305#define FIF7          7
306#define FIF6          6
307#define FIF5          5
308#define FIF4          4
309#define FINT7         3
310#define FINT6         2
311#define FINT5         1
312#define FINT4         0
313
314/* FISUC */
315#define FIF11         7
316#define FIF10         6
317#define FIF9          5
318#define FIF8          4
319#define FINT11        3
320#define FINT10        2
321#define FINT9         1
322#define FINT8         0
323
324/* FISUD */
325#define FIF15         7
326#define FIF14         6
327#define FIF13         5
328#define FIF12         4
329#define FINT15        3
330#define FINT14        2
331#define FINT13        1
332#define FINT12        0
333
334/* MCUR */
335#define JTRF          7
336#define JTD           6
337#define SE            5
338#define SM1           4
339#define SM0           3
340#define PORF          2
341#define WDRF          1
342#define EXTRF         0
343
344/* OCDR (reserved) */
345#define IDRD          7
346
347/* PIND */
348#define PIND7         7
349#define PIND6         6
350#define PIND5         5
351#define PIND4         4
352#define PIND3         3
353#define PIND2         2
354#define PIND1         1
355#define PIND0         0
356
357/* PINE */
358#define PINE7         7
359#define PINE6         6
360#define PINE5         5
361#define PINE4         4
362#define PINE3         3
363#define PINE2         2
364#define PINE1         1
365#define PINE0         0
366
367/* PORTD */
368#define PD7        7
369#define PD6        6
370#define PD5        5
371#define PD4        4
372#define PD3        3
373#define PD2        2
374#define PD1        1
375#define PD0        0
376
377/* PORTE */
378/*
379   PE7 = IC1  / INT3 (alternate)
380   PE6 = OC1A / INT2 (alternate)
381   PE5 = OC1B / INT1 (alternate)
382   PE4 = ET11 / INT0 (alternate)
383   PE3 = OC2  / RX1  (alternate)
384   PE2 =      / TX1  (alternate)
385   PE1 = OC0  / RX0  (alternate)
386   PE0 = ET0  / TX0  (alternate)
387 */
388#define PE7        7
389#define PE6        6
390#define PE5        5
391#define PE4        4
392#define PE3        3
393#define PE2        2
394#define PE1        1
395#define PE0        0
396
397/* SFIOR */
398#define PSR2          1
399#define PSR10         0
400
401/* SFTCR */
402#define FMXOR         3
403#define WDTS          2
404#define DBG           1
405#define SRST          0
406
407/* TCCR0 */
408#define FOC0          7
409#define PWM0          6
410#define COM01         5
411#define COM00         4
412#define CTC0          3
413#define CS02          2
414#define CS01          1
415#define CS00          0
416
417/* TCCR1A */
418#define COM1A1        7
419#define COM1A0        6
420#define COM1B1        5
421#define COM1B0        4
422#define FOC1A         3
423#define FOC1B         2
424#define PWM11         1
425#define PWM10         0
426
427/* TCCR1B */
428#define ICNC1         7
429#define ICES1         6
430#define ICPE          5
431#define CTC1          3
432#define CS12          2
433#define CS11          1
434#define CS10          0
435
436/* TCCR2 */
437#define FOC2          7
438#define PWM2          6
439#define COM21         5
440#define COM20         4
441#define CTC2          3
442#define CS22          2
443#define CS21          1
444#define CS20          0
445
446/* TIFR */
447#define TOV1          7
448#define OCF1A         6
449#define OCF1B         5
450#define TOV2          4
451#define ICF1          3
452#define OCF2          2
453#define TOV0          1
454#define OCF0          0
455
456/* TIMSK */
457#define TOIE1         7
458#define OCIE1A        6
459#define OCIE1B        5
460#define TOIE2         4
461#define TICIE1        3
462#define OCIE2         2
463#define TOIE0         1
464#define OCIE0         0
465
466/* TWAR */
467/* #define TWA           1 */ /* TWA is bits 7:1 */
468#define TWGCE         0
469
470/* TWCR */
471#define TWINT         7
472#define TWEA          6
473#define TWSTA         5
474#define TWSTO         4
475#define TWWC          3
476#define TWEN          2
477#define TWIE          0
478
479/* TWSR */
480#define TWS7          7
481#define TWS6          6
482#define TWS5          5
483#define TWS4          4
484#define TWS3          3
485
486/* UBRRHI
487   Bits 11..8 of UART1 are bits 7..4 of UBRRHI.
488   Bits 11..8 of UART0 are bits 3..0 of UBRRHI. */
489/* #define UBRRHI1       4 */
490/* #define UBRRHI0       0 */
491
492/* UCSR0A */
493#define RXC0          7
494#define TXC0          6
495#define UDRE0         5
496#define FE0           4
497#define OR0           3
498#define U2X0          1
499#define MPCM0         0
500
501/* UCSR0B */
502#define RXCIE0        7
503#define TXCIE0        6
504#define UDRIE0        5
505#define RXEN0         4
506#define TXEN0         3
507#define CHR90         2
508#define RXB80         1
509#define TXB80         0
510
511/* UCSR1A */
512#define RXC1          7
513#define TXC1          6
514#define UDRE1         5
515#define FE1           4
516#define OR1           3
517#define U2X1          1
518#define MPCM1         0
519
520/* UCSR1B */
521#define RXCIE1        7
522#define TXCIE1        6
523#define UDRIE1        5
524#define RXEN1         4
525#define TXEN1         3
526#define CHR91         2
527#define RXB81         1
528#define TXB81         0
529
530/* WDTCR */
531#define WDTOE         4
532#define WDE           3
533#define WDP2          2
534#define WDP1          1
535#define WDP0          0
536
537/*
538   Last memory addresses - depending on configuration, it is possible
539   to have 20K-32K of program memory and 4K-16K of data memory
540   (all in the same 36K total of SRAM, loaded from external EEPROM).
541 */
542
543#ifndef RAMSTART
544#define RAMSTART 0x60
545#endif
546
547#ifndef RAMEND
548#define RAMEND 0x0FFF
549#endif
550
551#ifndef XRAMEND
552#define XRAMEND RAMEND
553#endif
554
555#define E2END 0
556
557#ifndef FLASHEND
558#define FLASHEND 0x7FFF
559#endif
560
561#endif /* _AVR_IOAT94K_H_ */
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