source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom1284.h @ 46

Last change on this file since 46 was 46, checked in by jrpelegrina, 4 years ago

First release to Xenial

File size: 21.4 KB
Line 
1/*****************************************************************************
2 *
3 * Copyright (C) 2014 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATMEGA1284_H_INCLUDED
36#define _AVR_ATMEGA1284_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "iom1284.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINA    _SFR_IO8(0x00)
52#define PINA7   7
53#define PINA6   6
54#define PINA5   5
55#define PINA4   4
56#define PINA3   3
57#define PINA2   2
58#define PINA1   1
59#define PINA0   0
60
61#define DDRA    _SFR_IO8(0x01)
62#define DDRA7   7
63#define DDRA6   6
64#define DDRA5   5
65#define DDRA4   4
66#define DDRA3   3
67#define DDRA2   2
68#define DDRA1   1
69#define DDRA0   0
70
71#define PORTA   _SFR_IO8(0x02)
72#define PORTA7  7
73#define PORTA6  6
74#define PORTA5  5
75#define PORTA4  4
76#define PORTA3  3
77#define PORTA2  2
78#define PORTA1  1
79#define PORTA0  0
80
81#define PINB    _SFR_IO8(0x03)
82#define PINB7   7
83#define PINB6   6
84#define PINB5   5
85#define PINB4   4
86#define PINB3   3
87#define PINB2   2
88#define PINB1   1
89#define PINB0   0
90
91#define DDRB    _SFR_IO8(0x04)
92#define DDRB7   7
93#define DDRB6   6
94#define DDRB5   5
95#define DDRB4   4
96#define DDRB3   3
97#define DDRB2   2
98#define DDRB1   1
99#define DDRB0   0
100
101#define PORTB   _SFR_IO8(0x05)
102#define PORTB7  7
103#define PORTB6  6
104#define PORTB5  5
105#define PORTB4  4
106#define PORTB3  3
107#define PORTB2  2
108#define PORTB1  1
109#define PORTB0  0
110
111#define PINC    _SFR_IO8(0x06)
112#define PINC7   7
113#define PINC6   6
114#define PINC5   5
115#define PINC4   4
116#define PINC3   3
117#define PINC2   2
118#define PINC1   1
119#define PINC0   0
120
121#define DDRC    _SFR_IO8(0x07)
122#define DDRC7   7
123#define DDRC6   6
124#define DDRC5   5
125#define DDRC4   4
126#define DDRC3   3
127#define DDRC2   2
128#define DDRC1   1
129#define DDRC0   0
130
131#define PORTC   _SFR_IO8(0x08)
132#define PORTC7  7
133#define PORTC6  6
134#define PORTC5  5
135#define PORTC4  4
136#define PORTC3  3
137#define PORTC2  2
138#define PORTC1  1
139#define PORTC0  0
140
141#define PIND    _SFR_IO8(0x09)
142#define PIND7   7
143#define PIND6   6
144#define PIND5   5
145#define PIND4   4
146#define PIND3   3
147#define PIND2   2
148#define PIND1   1
149#define PIND0   0
150
151#define DDRD    _SFR_IO8(0x0A)
152#define DDRD7   7
153#define DDRD6   6
154#define DDRD5   5
155#define DDRD4   4
156#define DDRD3   3
157#define DDRD2   2
158#define DDRD1   1
159#define DDRD0   0
160
161#define PORTD   _SFR_IO8(0x0B)
162#define PORTD7  7
163#define PORTD6  6
164#define PORTD5  5
165#define PORTD4  4
166#define PORTD3  3
167#define PORTD2  2
168#define PORTD1  1
169#define PORTD0  0
170
171/* Reserved [0x0C..0x14] */
172
173#define TIFR0   _SFR_IO8(0x15)
174#define TOV0    0
175#define OCF0A   1
176#define OCF0B   2
177
178#define TIFR1   _SFR_IO8(0x16)
179#define TOV1    0
180#define OCF1A   1
181#define OCF1B   2
182#define ICF1    5
183
184#define TIFR2   _SFR_IO8(0x17)
185#define TOV2    0
186#define OCF2A   1
187#define OCF2B   2
188
189#define TIFR3   _SFR_IO8(0x18)
190#define TOV3    0
191#define OCF3A   1
192#define OCF3B   2
193#define ICF3    5
194
195/* Reserved [0x19..0x1A] */
196
197#define PCIFR   _SFR_IO8(0x1B)
198#define PCIF0   0
199#define PCIF1   1
200#define PCIF2   2
201#define PCIF3   3
202
203#define EIFR    _SFR_IO8(0x1C)
204#define INTF0   0
205#define INTF1   1
206#define INTF2   2
207
208#define EIMSK   _SFR_IO8(0x1D)
209#define INT0    0
210#define INT1    1
211#define INT2    2
212
213#define GPIOR0  _SFR_IO8(0x1E)
214#define GPIOR00 0
215#define GPIOR01 1
216#define GPIOR02 2
217#define GPIOR03 3
218#define GPIOR04 4
219#define GPIOR05 5
220#define GPIOR06 6
221#define GPIOR07 7
222
223#define EECR    _SFR_IO8(0x1F)
224#define EERE    0
225#define EEPE    1
226#define EEMPE   2
227#define EERIE   3
228#define EEPM0   4
229#define EEPM1   5
230
231#define EEDR    _SFR_IO8(0x20)
232
233/* Combine EEARL and EEARH */
234#define EEAR    _SFR_IO16(0x21)
235
236#define EEARL   _SFR_IO8(0x21)
237#define EEARH   _SFR_IO8(0x22)
238
239#define GTCCR   _SFR_IO8(0x23)
240#define PSRSYNC 0
241#define TSM     7
242#define PSRASY  1
243
244#define TCCR0A  _SFR_IO8(0x24)
245#define WGM00   0
246#define WGM01   1
247#define COM0B0  4
248#define COM0B1  5
249#define COM0A0  6
250#define COM0A1  7
251
252#define TCCR0B  _SFR_IO8(0x25)
253#define CS00    0
254#define CS01    1
255#define CS02    2
256#define WGM02   3
257#define FOC0B   6
258#define FOC0A   7
259
260#define TCNT0   _SFR_IO8(0x26)
261
262#define OCR0A   _SFR_IO8(0x27)
263
264#define OCR0B   _SFR_IO8(0x28)
265
266/* Reserved [0x29] */
267
268#define GPIOR1  _SFR_IO8(0x2A)
269#define GPIOR10 0
270#define GPIOR11 1
271#define GPIOR12 2
272#define GPIOR13 3
273#define GPIOR14 4
274#define GPIOR15 5
275#define GPIOR16 6
276#define GPIOR17 7
277
278#define GPIOR2  _SFR_IO8(0x2B)
279#define GPIOR20 0
280#define GPIOR21 1
281#define GPIOR22 2
282#define GPIOR23 3
283#define GPIOR24 4
284#define GPIOR25 5
285#define GPIOR26 6
286#define GPIOR27 7
287
288#define SPCR    _SFR_IO8(0x2C)
289#define SPR0    0
290#define SPR1    1
291#define CPHA    2
292#define CPOL    3
293#define MSTR    4
294#define DORD    5
295#define SPE     6
296#define SPIE    7
297
298#define SPSR    _SFR_IO8(0x2D)
299#define SPI2X   0
300#define WCOL    6
301#define SPIF    7
302
303#define SPDR    _SFR_IO8(0x2E)
304
305/* Reserved [0x2F] */
306
307#define ACSR    _SFR_IO8(0x30)
308#define ACIS0   0
309#define ACIS1   1
310#define ACIC    2
311#define ACIE    3
312#define ACI     4
313#define ACO     5
314#define ACBG    6
315#define ACD     7
316
317#define OCDR    _SFR_IO8(0x31)
318#define OCDR7   7
319#define OCDR6   6
320#define OCDR5   5
321#define OCDR4   4
322#define OCDR3   3
323#define OCDR2   2
324#define OCDR1   1
325#define OCDR0   0
326
327/* Reserved [0x32] */
328
329#define SMCR    _SFR_IO8(0x33)
330#define SE      0
331#define SM0     1
332#define SM1     2
333#define SM2     3
334
335#define MCUSR   _SFR_IO8(0x34)
336#define JTRF    4
337#define PORF    0
338#define EXTRF   1
339#define BORF    2
340#define WDRF    3
341
342#define MCUCR   _SFR_IO8(0x35)
343#define JTD     7
344#define IVCE    0
345#define IVSEL   1
346#define PUD     4
347
348/* Reserved [0x36] */
349
350#define SPMCSR  _SFR_IO8(0x37)
351#define SPMEN   0
352#define PGERS   1
353#define PGWRT   2
354#define BLBSET  3
355#define RWWSRE  4
356#define SIGRD   5
357#define RWWSB   6
358#define SPMIE   7
359
360/* Reserved [0x38..0x3A] */
361
362#define RAMPZ   _SFR_IO8(0x3B)
363
364/* Reserved [0x3C] */
365
366/* SP [0x3D..0x3E] */
367
368/* SREG [0x3F] */
369
370#define WDTCSR  _SFR_MEM8(0x60)
371#define WDE     3
372#define WDCE    4
373#define WDP0    0
374#define WDP1    1
375#define WDP2    2
376#define WDP3    5
377#define WDIE    6
378#define WDIF    7
379
380#define CLKPR   _SFR_MEM8(0x61)
381#define CLKPS0  0
382#define CLKPS1  1
383#define CLKPS2  2
384#define CLKPS3  3
385#define CLKPCE  7
386
387/* Reserved [0x62..0x63] */
388
389#define PRR0    _SFR_MEM8(0x64)
390#define PRADC   0
391#define PRSPI   2
392#define PRTIM1  3
393#define PRUSART0 1
394#define PRUSART1 4
395#define PRTIM0  5
396#define PRTIM2  6
397#define PRTWI   7
398
399#define PRR1    _SFR_MEM8(0x65)
400#define PRTIM3  0
401
402#define OSCCAL  _SFR_MEM8(0x66)
403#define OSCCAL0 0
404#define OSCCAL1 1
405#define OSCCAL2 2
406#define OSCCAL3 3
407#define OSCCAL4 4
408#define OSCCAL5 5
409#define OSCCAL6 6
410#define OSCCAL7 7
411
412/* Reserved [0x67] */
413
414#define PCICR   _SFR_MEM8(0x68)
415#define PCIE0   0
416#define PCIE1   1
417#define PCIE2   2
418#define PCIE3   3
419
420#define EICRA   _SFR_MEM8(0x69)
421#define ISC00   0
422#define ISC01   1
423#define ISC10   2
424#define ISC11   3
425#define ISC20   4
426#define ISC21   5
427
428/* Reserved [0x6A] */
429
430#define PCMSK0  _SFR_MEM8(0x6B)
431#define PCINT0  0
432#define PCINT1  1
433#define PCINT2  2
434#define PCINT3  3
435#define PCINT4  4
436#define PCINT5  5
437#define PCINT6  6
438#define PCINT7  7
439
440#define PCMSK1  _SFR_MEM8(0x6C)
441#define PCINT8  0
442#define PCINT9  1
443#define PCINT10 2
444#define PCINT11 3
445#define PCINT12 4
446#define PCINT13 5
447#define PCINT14 6
448#define PCINT15 7
449
450#define PCMSK2  _SFR_MEM8(0x6D)
451#define PCINT16 0
452#define PCINT17 1
453#define PCINT18 2
454#define PCINT19 3
455#define PCINT20 4
456#define PCINT21 5
457#define PCINT22 6
458#define PCINT23 7
459
460#define TIMSK0  _SFR_MEM8(0x6E)
461#define TOIE0   0
462#define OCIE0A  1
463#define OCIE0B  2
464
465#define TIMSK1  _SFR_MEM8(0x6F)
466#define TOIE1   0
467#define OCIE1A  1
468#define OCIE1B  2
469#define ICIE1   5
470
471#define TIMSK2  _SFR_MEM8(0x70)
472#define TOIE2   0
473#define OCIE2A  1
474#define OCIE2B  2
475
476#define TIMSK3  _SFR_MEM8(0x71)
477#define TOIE3   0
478#define OCIE3A  1
479#define OCIE3B  2
480#define ICIE3   5
481
482/* Reserved [0x72] */
483
484#define PCMSK3  _SFR_MEM8(0x73)
485#define PCINT24 0
486#define PCINT25 1
487#define PCINT26 2
488#define PCINT27 3
489#define PCINT28 4
490#define PCINT29 5
491#define PCINT30 6
492#define PCINT31 7
493
494/* Reserved [0x74..0x77] */
495
496/* Combine ADCL and ADCH */
497#ifndef __ASSEMBLER__
498#define ADC     _SFR_MEM16(0x78)
499#endif
500#define ADCW    _SFR_MEM16(0x78)
501
502#define ADCL    _SFR_MEM8(0x78)
503#define ADCH    _SFR_MEM8(0x79)
504
505#define ADCSRA  _SFR_MEM8(0x7A)
506#define ADPS0   0
507#define ADPS1   1
508#define ADPS2   2
509#define ADIE    3
510#define ADIF    4
511#define ADATE   5
512#define ADSC    6
513#define ADEN    7
514
515#define ADCSRB  _SFR_MEM8(0x7B)
516#define ACME    6
517#define ADTS0   0
518#define ADTS1   1
519#define ADTS2   2
520
521#define ADMUX   _SFR_MEM8(0x7C)
522#define MUX0    0
523#define MUX1    1
524#define MUX2    2
525#define MUX3    3
526#define MUX4    4
527#define ADLAR   5
528#define REFS0   6
529#define REFS1   7
530
531/* Reserved [0x7D] */
532
533#define DIDR0   _SFR_MEM8(0x7E)
534#define ADC0D   0
535#define ADC1D   1
536#define ADC2D   2
537#define ADC3D   3
538#define ADC4D   4
539#define ADC5D   5
540#define ADC6D   6
541#define ADC7D   7
542
543#define DIDR1   _SFR_MEM8(0x7F)
544#define AIN0D   0
545#define AIN1D   1
546
547#define TCCR1A  _SFR_MEM8(0x80)
548#define WGM10   0
549#define WGM11   1
550#define COM1B0  4
551#define COM1B1  5
552#define COM1A0  6
553#define COM1A1  7
554
555#define TCCR1B  _SFR_MEM8(0x81)
556#define CS10    0
557#define CS11    1
558#define CS12    2
559#define WGM12   3
560#define WGM13   4
561#define ICES1   6
562#define ICNC1   7
563
564#define TCCR1C  _SFR_MEM8(0x82)
565#define FOC1B   6
566#define FOC1A   7
567
568/* Reserved [0x83] */
569
570/* Combine TCNT1L and TCNT1H */
571#define TCNT1   _SFR_MEM16(0x84)
572
573#define TCNT1L  _SFR_MEM8(0x84)
574#define TCNT1H  _SFR_MEM8(0x85)
575
576/* Combine ICR1L and ICR1H */
577#define ICR1    _SFR_MEM16(0x86)
578
579#define ICR1L   _SFR_MEM8(0x86)
580#define ICR1H   _SFR_MEM8(0x87)
581
582/* Combine OCR1AL and OCR1AH */
583#define OCR1A   _SFR_MEM16(0x88)
584
585#define OCR1AL  _SFR_MEM8(0x88)
586#define OCR1AH  _SFR_MEM8(0x89)
587
588/* Combine OCR1BL and OCR1BH */
589#define OCR1B   _SFR_MEM16(0x8A)
590
591#define OCR1BL  _SFR_MEM8(0x8A)
592#define OCR1BH  _SFR_MEM8(0x8B)
593
594/* Reserved [0x8C..0x8F] */
595
596#define TCCR3A  _SFR_MEM8(0x90)
597#define WGM30   0
598#define WGM31   1
599#define COM3B0  4
600#define COM3B1  5
601#define COM3A0  6
602#define COM3A1  7
603
604#define TCCR3B  _SFR_MEM8(0x91)
605#define CS30    0
606#define CS31    1
607#define CS32    2
608#define WGM32   3
609#define WGM33   4
610#define ICES3   6
611#define ICNC3   7
612
613#define TCCR3C  _SFR_MEM8(0x92)
614#define FOC3B   6
615#define FOC3A   7
616
617/* Reserved [0x93] */
618
619/* Combine TCNT3L and TCNT3H */
620#define TCNT3   _SFR_MEM16(0x94)
621
622#define TCNT3L  _SFR_MEM8(0x94)
623#define TCNT3H  _SFR_MEM8(0x95)
624
625/* Combine ICR3L and ICR3H */
626#define ICR3    _SFR_MEM16(0x96)
627
628#define ICR3L   _SFR_MEM8(0x96)
629#define ICR3H   _SFR_MEM8(0x97)
630
631/* Combine OCR3AL and OCR3AH */
632#define OCR3A   _SFR_MEM16(0x98)
633
634#define OCR3AL  _SFR_MEM8(0x98)
635#define OCR3AH  _SFR_MEM8(0x99)
636
637/* Combine OCR3BL and OCR3BH */
638#define OCR3B   _SFR_MEM16(0x9A)
639
640#define OCR3BL  _SFR_MEM8(0x9A)
641#define OCR3BH  _SFR_MEM8(0x9B)
642
643/* Reserved [0x9C..0xAF] */
644
645#define TCCR2A  _SFR_MEM8(0xB0)
646#define WGM20   0
647#define WGM21   1
648#define COM2B0  4
649#define COM2B1  5
650#define COM2A0  6
651#define COM2A1  7
652
653#define TCCR2B  _SFR_MEM8(0xB1)
654#define CS20    0
655#define CS21    1
656#define CS22    2
657#define WGM22   3
658#define FOC2B   6
659#define FOC2A   7
660
661#define TCNT2   _SFR_MEM8(0xB2)
662
663#define OCR2A   _SFR_MEM8(0xB3)
664
665#define OCR2B   _SFR_MEM8(0xB4)
666
667/* Reserved [0xB5] */
668
669#define ASSR    _SFR_MEM8(0xB6)
670#define TCR2BUB 0
671#define TCR2AUB 1
672#define OCR2BUB 2
673#define OCR2AUB 3
674#define TCN2UB  4
675#define AS2     5
676#define EXCLK   6
677
678/* Reserved [0xB7] */
679
680#define TWBR    _SFR_MEM8(0xB8)
681
682#define TWSR    _SFR_MEM8(0xB9)
683#define TWPS0   0
684#define TWPS1   1
685#define TWS3    3
686#define TWS4    4
687#define TWS5    5
688#define TWS6    6
689#define TWS7    7
690
691#define TWAR    _SFR_MEM8(0xBA)
692#define TWGCE   0
693#define TWA0    1
694#define TWA1    2
695#define TWA2    3
696#define TWA3    4
697#define TWA4    5
698#define TWA5    6
699#define TWA6    7
700
701#define TWDR    _SFR_MEM8(0xBB)
702
703#define TWCR    _SFR_MEM8(0xBC)
704#define TWIE    0
705#define TWEN    2
706#define TWWC    3
707#define TWSTO   4
708#define TWSTA   5
709#define TWEA    6
710#define TWINT   7
711
712#define TWAMR   _SFR_MEM8(0xBD)
713#define TWAM0   1
714#define TWAM1   2
715#define TWAM2   3
716#define TWAM3   4
717#define TWAM4   5
718#define TWAM5   6
719#define TWAM6   7
720
721/* Reserved [0xBE..0xBF] */
722
723#define UCSR0A  _SFR_MEM8(0xC0)
724#define MPCM0   0
725#define U2X0    1
726#define UPE0    2
727#define DOR0    3
728#define FE0     4
729#define UDRE0   5
730#define TXC0    6
731#define RXC0    7
732
733#define UCSR0B  _SFR_MEM8(0xC1)
734#define TXB80   0
735#define RXB80   1
736#define UCSZ02  2
737#define TXEN0   3
738#define RXEN0   4
739#define UDRIE0  5
740#define TXCIE0  6
741#define RXCIE0  7
742
743#define UCSR0C  _SFR_MEM8(0xC2)
744#define UCPOL0  0
745#define UCSZ00  1
746#define UCSZ01  2
747#define USBS0   3
748#define UPM00   4
749#define UPM01   5
750#define UMSEL00 6
751#define UMSEL01 7
752
753/* Reserved [0xC3] */
754
755/* Combine UBRR0L and UBRR0H */
756#define UBRR0   _SFR_MEM16(0xC4)
757
758#define UBRR0L  _SFR_MEM8(0xC4)
759#define UBRR0H  _SFR_MEM8(0xC5)
760
761#define UDR0    _SFR_MEM8(0xC6)
762
763/* Reserved [0xC7] */
764
765#define UCSR1A  _SFR_MEM8(0xC8)
766#define MPCM1   0
767#define U2X1    1
768#define UPE1    2
769#define DOR1    3
770#define FE1     4
771#define UDRE1   5
772#define TXC1    6
773#define RXC1    7
774
775#define UCSR1B  _SFR_MEM8(0xC9)
776#define TXB81   0
777#define RXB81   1
778#define UCSZ12  2
779#define TXEN1   3
780#define RXEN1   4
781#define UDRIE1  5
782#define TXCIE1  6
783#define RXCIE1  7
784
785#define UCSR1C  _SFR_MEM8(0xCA)
786#define UCPOL1  0
787#define UCSZ10  1
788#define UCSZ11  2
789#define USBS1   3
790#define UPM10   4
791#define UPM11   5
792#define UMSEL10 6
793#define UMSEL11 7
794
795/* Reserved [0xCB] */
796
797/* Combine UBRR1L and UBRR1H */
798#define UBRR1   _SFR_MEM16(0xCC)
799
800#define UBRR1L  _SFR_MEM8(0xCC)
801#define UBRR1H  _SFR_MEM8(0xCD)
802
803#define UDR1    _SFR_MEM8(0xCE)
804
805
806
807/* Interrupt vectors */
808/* Vector 0 is the reset vector */
809/* External Interrupt Request 0 */
810#define INT0_vect            _VECTOR(1)
811#define INT0_vect_num        1
812
813/* External Interrupt Request 1 */
814#define INT1_vect            _VECTOR(2)
815#define INT1_vect_num        2
816
817/* External Interrupt Request 2 */
818#define INT2_vect            _VECTOR(3)
819#define INT2_vect_num        3
820
821/* Pin Change Interrupt Request 0 */
822#define PCINT0_vect            _VECTOR(4)
823#define PCINT0_vect_num        4
824
825/* Pin Change Interrupt Request 1 */
826#define PCINT1_vect            _VECTOR(5)
827#define PCINT1_vect_num        5
828
829/* Pin Change Interrupt Request 2 */
830#define PCINT2_vect            _VECTOR(6)
831#define PCINT2_vect_num        6
832
833/* Pin Change Interrupt Request 3 */
834#define PCINT3_vect            _VECTOR(7)
835#define PCINT3_vect_num        7
836
837/* Watchdog Time-out Interrupt */
838#define WDT_vect            _VECTOR(8)
839#define WDT_vect_num        8
840
841/* Timer/Counter2 Compare Match A */
842#define TIMER2_COMPA_vect            _VECTOR(9)
843#define TIMER2_COMPA_vect_num        9
844
845/* Timer/Counter2 Compare Match B */
846#define TIMER2_COMPB_vect            _VECTOR(10)
847#define TIMER2_COMPB_vect_num        10
848
849/* Timer/Counter2 Overflow */
850#define TIMER2_OVF_vect            _VECTOR(11)
851#define TIMER2_OVF_vect_num        11
852
853/* Timer/Counter1 Capture Event */
854#define TIMER1_CAPT_vect            _VECTOR(12)
855#define TIMER1_CAPT_vect_num        12
856
857/* Timer/Counter1 Compare Match A */
858#define TIMER1_COMPA_vect            _VECTOR(13)
859#define TIMER1_COMPA_vect_num        13
860
861/* Timer/Counter1 Compare Match B */
862#define TIMER1_COMPB_vect            _VECTOR(14)
863#define TIMER1_COMPB_vect_num        14
864
865/* Timer/Counter1 Overflow */
866#define TIMER1_OVF_vect            _VECTOR(15)
867#define TIMER1_OVF_vect_num        15
868
869/* Timer/Counter0 Compare Match A */
870#define TIMER0_COMPA_vect            _VECTOR(16)
871#define TIMER0_COMPA_vect_num        16
872
873/* Timer/Counter0 Compare Match B */
874#define TIMER0_COMPB_vect            _VECTOR(17)
875#define TIMER0_COMPB_vect_num        17
876
877/* Timer/Counter0 Overflow */
878#define TIMER0_OVF_vect            _VECTOR(18)
879#define TIMER0_OVF_vect_num        18
880
881/* SPI Serial Transfer Complete */
882#define SPI_STC_vect            _VECTOR(19)
883#define SPI_STC_vect_num        19
884
885/* USART0, Rx Complete */
886#define USART0_RX_vect            _VECTOR(20)
887#define USART0_RX_vect_num        20
888
889/* USART0 Data register Empty */
890#define USART0_UDRE_vect            _VECTOR(21)
891#define USART0_UDRE_vect_num        21
892
893/* USART0, Tx Complete */
894#define USART0_TX_vect            _VECTOR(22)
895#define USART0_TX_vect_num        22
896
897/* Analog Comparator */
898#define ANALOG_COMP_vect            _VECTOR(23)
899#define ANALOG_COMP_vect_num        23
900
901/* ADC Conversion Complete */
902#define ADC_vect            _VECTOR(24)
903#define ADC_vect_num        24
904
905/* EEPROM Ready */
906#define EE_READY_vect            _VECTOR(25)
907#define EE_READY_vect_num        25
908
909/* 2-wire Serial Interface */
910#define TWI_vect            _VECTOR(26)
911#define TWI_vect_num        26
912
913/* Store Program Memory Read */
914#define SPM_READY_vect            _VECTOR(27)
915#define SPM_READY_vect_num        27
916
917/* USART1 RX complete */
918#define USART1_RX_vect            _VECTOR(28)
919#define USART1_RX_vect_num        28
920
921/* USART1 Data Register Empty */
922#define USART1_UDRE_vect            _VECTOR(29)
923#define USART1_UDRE_vect_num        29
924
925/* USART1 TX complete */
926#define USART1_TX_vect            _VECTOR(30)
927#define USART1_TX_vect_num        30
928
929/* Timer/Counter3 Capture Event */
930#define TIMER3_CAPT_vect            _VECTOR(31)
931#define TIMER3_CAPT_vect_num        31
932
933/* Timer/Counter3 Compare Match A */
934#define TIMER3_COMPA_vect            _VECTOR(32)
935#define TIMER3_COMPA_vect_num        32
936
937/* Timer/Counter3 Compare Match B */
938#define TIMER3_COMPB_vect            _VECTOR(33)
939#define TIMER3_COMPB_vect_num        33
940
941/* Timer/Counter3 Overflow */
942#define TIMER3_OVF_vect            _VECTOR(34)
943#define TIMER3_OVF_vect_num        34
944
945#define _VECTORS_SIZE 140
946
947
948/* Constants */
949
950#define SPM_PAGESIZE 256
951#define FLASHSTART   0x0000
952#define FLASHEND     0x1FFFF
953#define RAMSTART     0x0100
954#define RAMSIZE      16384
955#define RAMEND       0x40FF
956#define E2START     0
957#define E2SIZE      4096
958#define E2PAGESIZE  8
959#define E2END       0x0FFF
960#define XRAMEND      RAMEND
961
962
963/* Fuses */
964
965#define FUSE_MEMORY_SIZE 3
966
967/* Low Fuse Byte */
968#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
969#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
970#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
971#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
972#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
973#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
974#define FUSE_CKOUT       (unsigned char)~_BV(6)
975#define FUSE_CKDIV8      (unsigned char)~_BV(7)
976
977/* High Fuse Byte */
978#define FUSE_BOOTRST     (unsigned char)~_BV(0)
979#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
980#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
981#define FUSE_EESAVE      (unsigned char)~_BV(3)
982#define FUSE_WDTON       (unsigned char)~_BV(4)
983#define FUSE_SPIEN       (unsigned char)~_BV(5)
984#define FUSE_JTAGEN      (unsigned char)~_BV(6)
985#define FUSE_OCDEN       (unsigned char)~_BV(7)
986
987/* Extended Fuse Byte */
988#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
989#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
990#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
991
992
993/* Lock Bits */
994#define __LOCK_BITS_EXIST
995#define __BOOT_LOCK_BITS_0_EXIST
996#define __BOOT_LOCK_BITS_1_EXIST
997
998
999/* Signature */
1000#define SIGNATURE_0 0x1E
1001#define SIGNATURE_1 0x97
1002#define SIGNATURE_2 0x06
1003
1004
1005#endif /* #ifdef _AVR_ATMEGA1284_H_INCLUDED */
1006
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