source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom1284.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

File size: 24.6 KB
Line 
1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATMEGA1284_H_INCLUDED
36#define _AVR_ATMEGA1284_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "iom1284.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINA    _SFR_IO8(0x00)
52#define PINA7   7
53#define PINA6   6
54#define PINA5   5
55#define PINA4   4
56#define PINA3   3
57#define PINA2   2
58#define PINA1   1
59#define PINA0   0
60
61#define DDRA    _SFR_IO8(0x01)
62#define DDRA7   7
63// Inserted "DDA7" from "DDRA7" due to compatibility
64#define DDA7    7
65#define DDRA6   6
66// Inserted "DDA6" from "DDRA6" due to compatibility
67#define DDA6    6
68#define DDRA5   5
69// Inserted "DDA5" from "DDRA5" due to compatibility
70#define DDA5    5
71#define DDRA4   4
72// Inserted "DDA4" from "DDRA4" due to compatibility
73#define DDA4    4
74#define DDRA3   3
75// Inserted "DDA3" from "DDRA3" due to compatibility
76#define DDA3    3
77#define DDRA2   2
78// Inserted "DDA2" from "DDRA2" due to compatibility
79#define DDA2    2
80#define DDRA1   1
81// Inserted "DDA1" from "DDRA1" due to compatibility
82#define DDA1    1
83#define DDRA0   0
84// Inserted "DDA0" from "DDRA0" due to compatibility
85#define DDA0    0
86
87#define PORTA   _SFR_IO8(0x02)
88#define PORTA7  7
89#define PORTA6  6
90#define PORTA5  5
91#define PORTA4  4
92#define PORTA3  3
93#define PORTA2  2
94#define PORTA1  1
95#define PORTA0  0
96
97#define PINB    _SFR_IO8(0x03)
98#define PINB7   7
99#define PINB6   6
100#define PINB5   5
101#define PINB4   4
102#define PINB3   3
103#define PINB2   2
104#define PINB1   1
105#define PINB0   0
106
107#define DDRB    _SFR_IO8(0x04)
108#define DDRB7   7
109// Inserted "DDB7" from "DDRB7" due to compatibility
110#define DDB7    7
111#define DDRB6   6
112// Inserted "DDB6" from "DDRB6" due to compatibility
113#define DDB6    6
114#define DDRB5   5
115// Inserted "DDB5" from "DDRB5" due to compatibility
116#define DDB5    5
117#define DDRB4   4
118// Inserted "DDB4" from "DDRB4" due to compatibility
119#define DDB4    4
120#define DDRB3   3
121// Inserted "DDB3" from "DDRB3" due to compatibility
122#define DDB3    3
123#define DDRB2   2
124// Inserted "DDB2" from "DDRB2" due to compatibility
125#define DDB2    2
126#define DDRB1   1
127// Inserted "DDB1" from "DDRB1" due to compatibility
128#define DDB1    1
129#define DDRB0   0
130// Inserted "DDB0" from "DDRB0" due to compatibility
131#define DDB0    0
132
133#define PORTB   _SFR_IO8(0x05)
134#define PORTB7  7
135#define PORTB6  6
136#define PORTB5  5
137#define PORTB4  4
138#define PORTB3  3
139#define PORTB2  2
140#define PORTB1  1
141#define PORTB0  0
142
143#define PINC    _SFR_IO8(0x06)
144#define PINC7   7
145#define PINC6   6
146#define PINC5   5
147#define PINC4   4
148#define PINC3   3
149#define PINC2   2
150#define PINC1   1
151#define PINC0   0
152
153#define DDRC    _SFR_IO8(0x07)
154#define DDRC7   7
155// Inserted "DDC7" from "DDRC7" due to compatibility
156#define DDC7    7
157#define DDRC6   6
158// Inserted "DDC6" from "DDRC6" due to compatibility
159#define DDC6    6
160#define DDRC5   5
161// Inserted "DDC5" from "DDRC5" due to compatibility
162#define DDC5    5
163#define DDRC4   4
164// Inserted "DDC4" from "DDRC4" due to compatibility
165#define DDC4    4
166#define DDRC3   3
167// Inserted "DDC3" from "DDRC3" due to compatibility
168#define DDC3    3
169#define DDRC2   2
170// Inserted "DDC2" from "DDRC2" due to compatibility
171#define DDC2    2
172#define DDRC1   1
173// Inserted "DDC1" from "DDRC1" due to compatibility
174#define DDC1    1
175#define DDRC0   0
176// Inserted "DDC0" from "DDRC0" due to compatibility
177#define DDC0    0
178
179#define PORTC   _SFR_IO8(0x08)
180#define PORTC7  7
181#define PORTC6  6
182#define PORTC5  5
183#define PORTC4  4
184#define PORTC3  3
185#define PORTC2  2
186#define PORTC1  1
187#define PORTC0  0
188
189#define PIND    _SFR_IO8(0x09)
190#define PIND7   7
191#define PIND6   6
192#define PIND5   5
193#define PIND4   4
194#define PIND3   3
195#define PIND2   2
196#define PIND1   1
197#define PIND0   0
198
199#define DDRD    _SFR_IO8(0x0A)
200#define DDRD7   7
201// Inserted "DDD7" from "DDRD7" due to compatibility
202#define DDD7    7
203#define DDRD6   6
204// Inserted "DDD6" from "DDRD6" due to compatibility
205#define DDD6    6
206#define DDRD5   5
207// Inserted "DDD5" from "DDRD5" due to compatibility
208#define DDD5    5
209#define DDRD4   4
210// Inserted "DDD4" from "DDRD4" due to compatibility
211#define DDD4    4
212#define DDRD3   3
213// Inserted "DDD3" from "DDRD3" due to compatibility
214#define DDD3    3
215#define DDRD2   2
216// Inserted "DDD2" from "DDRD2" due to compatibility
217#define DDD2    2
218#define DDRD1   1
219// Inserted "DDD1" from "DDRD1" due to compatibility
220#define DDD1    1
221#define DDRD0   0
222// Inserted "DDD0" from "DDRD0" due to compatibility
223#define DDD0    0
224
225#define PORTD   _SFR_IO8(0x0B)
226#define PORTD7  7
227#define PORTD6  6
228#define PORTD5  5
229#define PORTD4  4
230#define PORTD3  3
231#define PORTD2  2
232#define PORTD1  1
233#define PORTD0  0
234
235/* Reserved [0x0C..0x14] */
236
237#define TIFR0   _SFR_IO8(0x15)
238#define TOV0    0
239#define OCF0A   1
240#define OCF0B   2
241
242#define TIFR1   _SFR_IO8(0x16)
243#define TOV1    0
244#define OCF1A   1
245#define OCF1B   2
246#define ICF1    5
247
248#define TIFR2   _SFR_IO8(0x17)
249#define TOV2    0
250#define OCF2A   1
251#define OCF2B   2
252
253#define TIFR3   _SFR_IO8(0x18)
254#define TOV3    0
255#define OCF3A   1
256#define OCF3B   2
257#define ICF3    5
258
259/* Reserved [0x19..0x1A] */
260
261#define PCIFR   _SFR_IO8(0x1B)
262#define PCIF0   0
263#define PCIF1   1
264#define PCIF2   2
265#define PCIF3   3
266
267#define EIFR    _SFR_IO8(0x1C)
268#define INTF0   0
269#define INTF1   1
270#define INTF2   2
271
272#define EIMSK   _SFR_IO8(0x1D)
273#define INT0    0
274#define INT1    1
275#define INT2    2
276
277#define GPIOR0  _SFR_IO8(0x1E)
278#define GPIOR00 0
279#define GPIOR01 1
280#define GPIOR02 2
281#define GPIOR03 3
282#define GPIOR04 4
283#define GPIOR05 5
284#define GPIOR06 6
285#define GPIOR07 7
286
287#define EECR    _SFR_IO8(0x1F)
288#define EERE    0
289#define EEPE    1
290#define EEMPE   2
291#define EERIE   3
292#define EEPM0   4
293#define EEPM1   5
294
295#define EEDR    _SFR_IO8(0x20)
296
297/* Combine EEARL and EEARH */
298#define EEAR    _SFR_IO16(0x21)
299
300#define EEARL   _SFR_IO8(0x21)
301#define EEARH   _SFR_IO8(0x22)
302
303#define GTCCR   _SFR_IO8(0x23)
304#define PSRSYNC 0
305#define TSM     7
306#define PSRASY  1
307
308#define TCCR0A  _SFR_IO8(0x24)
309#define WGM00   0
310#define WGM01   1
311#define COM0B0  4
312#define COM0B1  5
313#define COM0A0  6
314#define COM0A1  7
315
316#define TCCR0B  _SFR_IO8(0x25)
317#define CS00    0
318#define CS01    1
319#define CS02    2
320#define WGM02   3
321#define FOC0B   6
322#define FOC0A   7
323
324#define TCNT0   _SFR_IO8(0x26)
325
326#define OCR0A   _SFR_IO8(0x27)
327
328#define OCR0B   _SFR_IO8(0x28)
329
330/* Reserved [0x29] */
331
332#define GPIOR1  _SFR_IO8(0x2A)
333#define GPIOR10 0
334#define GPIOR11 1
335#define GPIOR12 2
336#define GPIOR13 3
337#define GPIOR14 4
338#define GPIOR15 5
339#define GPIOR16 6
340#define GPIOR17 7
341
342#define GPIOR2  _SFR_IO8(0x2B)
343#define GPIOR20 0
344#define GPIOR21 1
345#define GPIOR22 2
346#define GPIOR23 3
347#define GPIOR24 4
348#define GPIOR25 5
349#define GPIOR26 6
350#define GPIOR27 7
351
352#define SPCR    _SFR_IO8(0x2C)
353#define SPR0    0
354#define SPR1    1
355#define CPHA    2
356#define CPOL    3
357#define MSTR    4
358#define DORD    5
359#define SPE     6
360#define SPIE    7
361
362#define SPSR    _SFR_IO8(0x2D)
363#define SPI2X   0
364#define WCOL    6
365#define SPIF    7
366
367#define SPDR    _SFR_IO8(0x2E)
368
369/* Reserved [0x2F] */
370
371#define ACSR    _SFR_IO8(0x30)
372#define ACIS0   0
373#define ACIS1   1
374#define ACIC    2
375#define ACIE    3
376#define ACI     4
377#define ACO     5
378#define ACBG    6
379#define ACD     7
380
381#define OCDR    _SFR_IO8(0x31)
382#define OCDR7   7
383#define OCDR6   6
384#define OCDR5   5
385#define OCDR4   4
386#define OCDR3   3
387#define OCDR2   2
388#define OCDR1   1
389#define OCDR0   0
390
391/* Reserved [0x32] */
392
393#define SMCR    _SFR_IO8(0x33)
394#define SE      0
395#define SM0     1
396#define SM1     2
397#define SM2     3
398
399#define MCUSR   _SFR_IO8(0x34)
400#define JTRF    4
401#define PORF    0
402#define EXTRF   1
403#define BORF    2
404#define WDRF    3
405
406#define MCUCR   _SFR_IO8(0x35)
407#define JTD     7
408#define IVCE    0
409#define IVSEL   1
410#define PUD     4
411
412/* Reserved [0x36] */
413
414#define SPMCSR  _SFR_IO8(0x37)
415#define SPMEN   0
416#define PGERS   1
417#define PGWRT   2
418#define BLBSET  3
419#define RWWSRE  4
420#define SIGRD   5
421#define RWWSB   6
422#define SPMIE   7
423
424/* Reserved [0x38..0x3A] */
425
426#define RAMPZ   _SFR_IO8(0x3B)
427
428/* Reserved [0x3C] */
429
430/* SP [0x3D..0x3E] */
431
432/* SREG [0x3F] */
433
434#define WDTCSR  _SFR_MEM8(0x60)
435#define WDE     3
436#define WDCE    4
437#define WDP0    0
438#define WDP1    1
439#define WDP2    2
440#define WDP3    5
441#define WDIE    6
442#define WDIF    7
443
444#define CLKPR   _SFR_MEM8(0x61)
445#define CLKPS0  0
446#define CLKPS1  1
447#define CLKPS2  2
448#define CLKPS3  3
449#define CLKPCE  7
450
451/* Reserved [0x62..0x63] */
452
453#define PRR0    _SFR_MEM8(0x64)
454#define PRADC   0
455#define PRSPI   2
456#define PRTIM1  3
457#define PRUSART0 1
458#define PRUSART1 4
459#define PRTIM0  5
460#define PRTIM2  6
461#define PRTWI   7
462
463#define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
464#define __AVR_HAVE_PRR0_PRADC
465#define __AVR_HAVE_PRR0_PRSPI
466#define __AVR_HAVE_PRR0_PRTIM1
467#define __AVR_HAVE_PRR0_PRUSART0
468#define __AVR_HAVE_PRR0_PRUSART1
469#define __AVR_HAVE_PRR0_PRTIM0
470#define __AVR_HAVE_PRR0_PRTIM2
471#define __AVR_HAVE_PRR0_PRTWI
472
473#define PRR1    _SFR_MEM8(0x65)
474#define PRTIM3  0
475
476#define __AVR_HAVE_PRR1 (1<<PRTIM3)
477#define __AVR_HAVE_PRR1_PRTIM3
478
479#define OSCCAL  _SFR_MEM8(0x66)
480#define OSCCAL0 0
481#define OSCCAL1 1
482#define OSCCAL2 2
483#define OSCCAL3 3
484#define OSCCAL4 4
485#define OSCCAL5 5
486#define OSCCAL6 6
487#define OSCCAL7 7
488
489/* Reserved [0x67] */
490
491#define PCICR   _SFR_MEM8(0x68)
492#define PCIE0   0
493#define PCIE1   1
494#define PCIE2   2
495#define PCIE3   3
496
497#define EICRA   _SFR_MEM8(0x69)
498#define ISC00   0
499#define ISC01   1
500#define ISC10   2
501#define ISC11   3
502#define ISC20   4
503#define ISC21   5
504
505/* Reserved [0x6A] */
506
507#define PCMSK0  _SFR_MEM8(0x6B)
508#define PCINT0  0
509#define PCINT1  1
510#define PCINT2  2
511#define PCINT3  3
512#define PCINT4  4
513#define PCINT5  5
514#define PCINT6  6
515#define PCINT7  7
516
517#define PCMSK1  _SFR_MEM8(0x6C)
518#define PCINT8  0
519#define PCINT9  1
520#define PCINT10 2
521#define PCINT11 3
522#define PCINT12 4
523#define PCINT13 5
524#define PCINT14 6
525#define PCINT15 7
526
527#define PCMSK2  _SFR_MEM8(0x6D)
528#define PCINT16 0
529#define PCINT17 1
530#define PCINT18 2
531#define PCINT19 3
532#define PCINT20 4
533#define PCINT21 5
534#define PCINT22 6
535#define PCINT23 7
536
537#define TIMSK0  _SFR_MEM8(0x6E)
538#define TOIE0   0
539#define OCIE0A  1
540#define OCIE0B  2
541
542#define TIMSK1  _SFR_MEM8(0x6F)
543#define TOIE1   0
544#define OCIE1A  1
545#define OCIE1B  2
546#define ICIE1   5
547
548#define TIMSK2  _SFR_MEM8(0x70)
549#define TOIE2   0
550#define OCIE2A  1
551#define OCIE2B  2
552
553#define TIMSK3  _SFR_MEM8(0x71)
554#define TOIE3   0
555#define OCIE3A  1
556#define OCIE3B  2
557#define ICIE3   5
558
559/* Reserved [0x72] */
560
561#define PCMSK3  _SFR_MEM8(0x73)
562#define PCINT24 0
563#define PCINT25 1
564#define PCINT26 2
565#define PCINT27 3
566#define PCINT28 4
567#define PCINT29 5
568#define PCINT30 6
569#define PCINT31 7
570
571/* Reserved [0x74..0x77] */
572
573/* Combine ADCL and ADCH */
574#ifndef __ASSEMBLER__
575#define ADC     _SFR_MEM16(0x78)
576#endif
577#define ADCW    _SFR_MEM16(0x78)
578
579#define ADCL    _SFR_MEM8(0x78)
580#define ADCH    _SFR_MEM8(0x79)
581
582#define ADCSRA  _SFR_MEM8(0x7A)
583#define ADPS0   0
584#define ADPS1   1
585#define ADPS2   2
586#define ADIE    3
587#define ADIF    4
588#define ADATE   5
589#define ADSC    6
590#define ADEN    7
591
592#define ADCSRB  _SFR_MEM8(0x7B)
593#define ACME    6
594#define ADTS0   0
595#define ADTS1   1
596#define ADTS2   2
597
598#define ADMUX   _SFR_MEM8(0x7C)
599#define MUX0    0
600#define MUX1    1
601#define MUX2    2
602#define MUX3    3
603#define MUX4    4
604#define ADLAR   5
605#define REFS0   6
606#define REFS1   7
607
608/* Reserved [0x7D] */
609
610#define DIDR0   _SFR_MEM8(0x7E)
611#define ADC0D   0
612#define ADC1D   1
613#define ADC2D   2
614#define ADC3D   3
615#define ADC4D   4
616#define ADC5D   5
617#define ADC6D   6
618#define ADC7D   7
619
620#define DIDR1   _SFR_MEM8(0x7F)
621#define AIN0D   0
622#define AIN1D   1
623
624#define TCCR1A  _SFR_MEM8(0x80)
625#define WGM10   0
626#define WGM11   1
627#define COM1B0  4
628#define COM1B1  5
629#define COM1A0  6
630#define COM1A1  7
631
632#define TCCR1B  _SFR_MEM8(0x81)
633#define CS10    0
634#define CS11    1
635#define CS12    2
636#define WGM12   3
637#define WGM13   4
638#define ICES1   6
639#define ICNC1   7
640
641#define TCCR1C  _SFR_MEM8(0x82)
642#define FOC1B   6
643#define FOC1A   7
644
645/* Reserved [0x83] */
646
647/* Combine TCNT1L and TCNT1H */
648#define TCNT1   _SFR_MEM16(0x84)
649
650#define TCNT1L  _SFR_MEM8(0x84)
651#define TCNT1H  _SFR_MEM8(0x85)
652
653/* Combine ICR1L and ICR1H */
654#define ICR1    _SFR_MEM16(0x86)
655
656#define ICR1L   _SFR_MEM8(0x86)
657#define ICR1H   _SFR_MEM8(0x87)
658
659/* Combine OCR1AL and OCR1AH */
660#define OCR1A   _SFR_MEM16(0x88)
661
662#define OCR1AL  _SFR_MEM8(0x88)
663#define OCR1AH  _SFR_MEM8(0x89)
664
665/* Combine OCR1BL and OCR1BH */
666#define OCR1B   _SFR_MEM16(0x8A)
667
668#define OCR1BL  _SFR_MEM8(0x8A)
669#define OCR1BH  _SFR_MEM8(0x8B)
670
671/* Reserved [0x8C..0x8F] */
672
673#define TCCR3A  _SFR_MEM8(0x90)
674#define WGM30   0
675#define WGM31   1
676#define COM3B0  4
677#define COM3B1  5
678#define COM3A0  6
679#define COM3A1  7
680
681#define TCCR3B  _SFR_MEM8(0x91)
682#define CS30    0
683#define CS31    1
684#define CS32    2
685#define WGM32   3
686#define WGM33   4
687#define ICES3   6
688#define ICNC3   7
689
690#define TCCR3C  _SFR_MEM8(0x92)
691#define FOC3B   6
692#define FOC3A   7
693
694/* Reserved [0x93] */
695
696/* Combine TCNT3L and TCNT3H */
697#define TCNT3   _SFR_MEM16(0x94)
698
699#define TCNT3L  _SFR_MEM8(0x94)
700#define TCNT3H  _SFR_MEM8(0x95)
701
702/* Combine ICR3L and ICR3H */
703#define ICR3    _SFR_MEM16(0x96)
704
705#define ICR3L   _SFR_MEM8(0x96)
706#define ICR3H   _SFR_MEM8(0x97)
707
708/* Combine OCR3AL and OCR3AH */
709#define OCR3A   _SFR_MEM16(0x98)
710
711#define OCR3AL  _SFR_MEM8(0x98)
712#define OCR3AH  _SFR_MEM8(0x99)
713
714/* Combine OCR3BL and OCR3BH */
715#define OCR3B   _SFR_MEM16(0x9A)
716
717#define OCR3BL  _SFR_MEM8(0x9A)
718#define OCR3BH  _SFR_MEM8(0x9B)
719
720/* Reserved [0x9C..0xAF] */
721
722#define TCCR2A  _SFR_MEM8(0xB0)
723#define WGM20   0
724#define WGM21   1
725#define COM2B0  4
726#define COM2B1  5
727#define COM2A0  6
728#define COM2A1  7
729
730#define TCCR2B  _SFR_MEM8(0xB1)
731#define CS20    0
732#define CS21    1
733#define CS22    2
734#define WGM22   3
735#define FOC2B   6
736#define FOC2A   7
737
738#define TCNT2   _SFR_MEM8(0xB2)
739
740#define OCR2A   _SFR_MEM8(0xB3)
741
742#define OCR2B   _SFR_MEM8(0xB4)
743
744/* Reserved [0xB5] */
745
746#define ASSR    _SFR_MEM8(0xB6)
747#define TCR2BUB 0
748#define TCR2AUB 1
749#define OCR2BUB 2
750#define OCR2AUB 3
751#define TCN2UB  4
752#define AS2     5
753#define EXCLK   6
754
755/* Reserved [0xB7] */
756
757#define TWBR    _SFR_MEM8(0xB8)
758
759#define TWSR    _SFR_MEM8(0xB9)
760#define TWPS0   0
761#define TWPS1   1
762#define TWS3    3
763#define TWS4    4
764#define TWS5    5
765#define TWS6    6
766#define TWS7    7
767
768#define TWAR    _SFR_MEM8(0xBA)
769#define TWGCE   0
770#define TWA0    1
771#define TWA1    2
772#define TWA2    3
773#define TWA3    4
774#define TWA4    5
775#define TWA5    6
776#define TWA6    7
777
778#define TWDR    _SFR_MEM8(0xBB)
779
780#define TWCR    _SFR_MEM8(0xBC)
781#define TWIE    0
782#define TWEN    2
783#define TWWC    3
784#define TWSTO   4
785#define TWSTA   5
786#define TWEA    6
787#define TWINT   7
788
789#define TWAMR   _SFR_MEM8(0xBD)
790#define TWAM0   1
791#define TWAM1   2
792#define TWAM2   3
793#define TWAM3   4
794#define TWAM4   5
795#define TWAM5   6
796#define TWAM6   7
797
798/* Reserved [0xBE..0xBF] */
799
800#define UCSR0A  _SFR_MEM8(0xC0)
801#define MPCM0   0
802#define U2X0    1
803#define UPE0    2
804#define DOR0    3
805#define FE0     4
806#define UDRE0   5
807#define TXC0    6
808#define RXC0    7
809
810#define UCSR0B  _SFR_MEM8(0xC1)
811#define TXB80   0
812#define RXB80   1
813#define UCSZ02  2
814#define TXEN0   3
815#define RXEN0   4
816#define UDRIE0  5
817#define TXCIE0  6
818#define RXCIE0  7
819
820#define UCSR0C  _SFR_MEM8(0xC2)
821#define UCPOL0  0
822#define UCSZ00  1
823#define UCSZ01  2
824#define USBS0   3
825#define UPM00   4
826#define UPM01   5
827#define UMSEL00 6
828#define UMSEL01 7
829
830/* Reserved [0xC3] */
831
832/* Combine UBRR0L and UBRR0H */
833#define UBRR0   _SFR_MEM16(0xC4)
834
835#define UBRR0L  _SFR_MEM8(0xC4)
836#define UBRR0H  _SFR_MEM8(0xC5)
837
838#define UDR0    _SFR_MEM8(0xC6)
839
840/* Reserved [0xC7] */
841
842#define UCSR1A  _SFR_MEM8(0xC8)
843#define MPCM1   0
844#define U2X1    1
845#define UPE1    2
846#define DOR1    3
847#define FE1     4
848#define UDRE1   5
849#define TXC1    6
850#define RXC1    7
851
852#define UCSR1B  _SFR_MEM8(0xC9)
853#define TXB81   0
854#define RXB81   1
855#define UCSZ12  2
856#define TXEN1   3
857#define RXEN1   4
858#define UDRIE1  5
859#define TXCIE1  6
860#define RXCIE1  7
861
862#define UCSR1C  _SFR_MEM8(0xCA)
863#define UCPOL1  0
864#define UCSZ10  1
865#define UCSZ11  2
866#define USBS1   3
867#define UPM10   4
868#define UPM11   5
869#define UMSEL10 6
870#define UMSEL11 7
871
872/* Reserved [0xCB] */
873
874/* Combine UBRR1L and UBRR1H */
875#define UBRR1   _SFR_MEM16(0xCC)
876
877#define UBRR1L  _SFR_MEM8(0xCC)
878#define UBRR1H  _SFR_MEM8(0xCD)
879
880#define UDR1    _SFR_MEM8(0xCE)
881
882
883
884/* Values and associated defines */
885
886
887#define SLEEP_MODE_IDLE (0x00<<1)
888#define SLEEP_MODE_ADC (0x01<<1)
889#define SLEEP_MODE_PWR_DOWN (0x02<<1)
890#define SLEEP_MODE_PWR_SAVE (0x03<<1)
891#define SLEEP_MODE_STANDBY (0x06<<1)
892#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
893
894/* Interrupt vectors */
895/* Vector 0 is the reset vector */
896/* External Interrupt Request 0 */
897#define INT0_vect            _VECTOR(1)
898#define INT0_vect_num        1
899
900/* External Interrupt Request 1 */
901#define INT1_vect            _VECTOR(2)
902#define INT1_vect_num        2
903
904/* External Interrupt Request 2 */
905#define INT2_vect            _VECTOR(3)
906#define INT2_vect_num        3
907
908/* Pin Change Interrupt Request 0 */
909#define PCINT0_vect            _VECTOR(4)
910#define PCINT0_vect_num        4
911
912/* Pin Change Interrupt Request 1 */
913#define PCINT1_vect            _VECTOR(5)
914#define PCINT1_vect_num        5
915
916/* Pin Change Interrupt Request 2 */
917#define PCINT2_vect            _VECTOR(6)
918#define PCINT2_vect_num        6
919
920/* Pin Change Interrupt Request 3 */
921#define PCINT3_vect            _VECTOR(7)
922#define PCINT3_vect_num        7
923
924/* Watchdog Time-out Interrupt */
925#define WDT_vect            _VECTOR(8)
926#define WDT_vect_num        8
927
928/* Timer/Counter2 Compare Match A */
929#define TIMER2_COMPA_vect            _VECTOR(9)
930#define TIMER2_COMPA_vect_num        9
931
932/* Timer/Counter2 Compare Match B */
933#define TIMER2_COMPB_vect            _VECTOR(10)
934#define TIMER2_COMPB_vect_num        10
935
936/* Timer/Counter2 Overflow */
937#define TIMER2_OVF_vect            _VECTOR(11)
938#define TIMER2_OVF_vect_num        11
939
940/* Timer/Counter1 Capture Event */
941#define TIMER1_CAPT_vect            _VECTOR(12)
942#define TIMER1_CAPT_vect_num        12
943
944/* Timer/Counter1 Compare Match A */
945#define TIMER1_COMPA_vect            _VECTOR(13)
946#define TIMER1_COMPA_vect_num        13
947
948/* Timer/Counter1 Compare Match B */
949#define TIMER1_COMPB_vect            _VECTOR(14)
950#define TIMER1_COMPB_vect_num        14
951
952/* Timer/Counter1 Overflow */
953#define TIMER1_OVF_vect            _VECTOR(15)
954#define TIMER1_OVF_vect_num        15
955
956/* Timer/Counter0 Compare Match A */
957#define TIMER0_COMPA_vect            _VECTOR(16)
958#define TIMER0_COMPA_vect_num        16
959
960/* Timer/Counter0 Compare Match B */
961#define TIMER0_COMPB_vect            _VECTOR(17)
962#define TIMER0_COMPB_vect_num        17
963
964/* Timer/Counter0 Overflow */
965#define TIMER0_OVF_vect            _VECTOR(18)
966#define TIMER0_OVF_vect_num        18
967
968/* SPI Serial Transfer Complete */
969#define SPI_STC_vect            _VECTOR(19)
970#define SPI_STC_vect_num        19
971
972/* USART0, Rx Complete */
973#define USART0_RX_vect            _VECTOR(20)
974#define USART0_RX_vect_num        20
975
976/* USART0 Data register Empty */
977#define USART0_UDRE_vect            _VECTOR(21)
978#define USART0_UDRE_vect_num        21
979
980/* USART0, Tx Complete */
981#define USART0_TX_vect            _VECTOR(22)
982#define USART0_TX_vect_num        22
983
984/* Analog Comparator */
985#define ANALOG_COMP_vect            _VECTOR(23)
986#define ANALOG_COMP_vect_num        23
987
988/* ADC Conversion Complete */
989#define ADC_vect            _VECTOR(24)
990#define ADC_vect_num        24
991
992/* EEPROM Ready */
993#define EE_READY_vect            _VECTOR(25)
994#define EE_READY_vect_num        25
995
996/* 2-wire Serial Interface */
997#define TWI_vect            _VECTOR(26)
998#define TWI_vect_num        26
999
1000/* Store Program Memory Read */
1001#define SPM_READY_vect            _VECTOR(27)
1002#define SPM_READY_vect_num        27
1003
1004/* USART1 RX complete */
1005#define USART1_RX_vect            _VECTOR(28)
1006#define USART1_RX_vect_num        28
1007
1008/* USART1 Data Register Empty */
1009#define USART1_UDRE_vect            _VECTOR(29)
1010#define USART1_UDRE_vect_num        29
1011
1012/* USART1 TX complete */
1013#define USART1_TX_vect            _VECTOR(30)
1014#define USART1_TX_vect_num        30
1015
1016/* Timer/Counter3 Capture Event */
1017#define TIMER3_CAPT_vect            _VECTOR(31)
1018#define TIMER3_CAPT_vect_num        31
1019
1020/* Timer/Counter3 Compare Match A */
1021#define TIMER3_COMPA_vect            _VECTOR(32)
1022#define TIMER3_COMPA_vect_num        32
1023
1024/* Timer/Counter3 Compare Match B */
1025#define TIMER3_COMPB_vect            _VECTOR(33)
1026#define TIMER3_COMPB_vect_num        33
1027
1028/* Timer/Counter3 Overflow */
1029#define TIMER3_OVF_vect            _VECTOR(34)
1030#define TIMER3_OVF_vect_num        34
1031
1032#define _VECTORS_SIZE 140
1033
1034
1035/* Constants */
1036
1037#define SPM_PAGESIZE 256
1038#define FLASHSTART   0x0000
1039#define FLASHEND     0x1FFFF
1040#define RAMSTART     0x0100
1041#define RAMSIZE      16384
1042#define RAMEND       0x40FF
1043#define E2START     0
1044#define E2SIZE      4096
1045#define E2PAGESIZE  8
1046#define E2END       0x0FFF
1047#define XRAMEND      RAMEND
1048
1049
1050/* Fuses */
1051
1052#define FUSE_MEMORY_SIZE 3
1053
1054/* Low Fuse Byte */
1055#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
1056#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
1057#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
1058#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
1059#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
1060#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
1061#define FUSE_CKOUT       (unsigned char)~_BV(6)
1062#define FUSE_CKDIV8      (unsigned char)~_BV(7)
1063#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
1064
1065
1066/* High Fuse Byte */
1067#define FUSE_BOOTRST     (unsigned char)~_BV(0)
1068#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
1069#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
1070#define FUSE_EESAVE      (unsigned char)~_BV(3)
1071#define FUSE_WDTON       (unsigned char)~_BV(4)
1072#define FUSE_SPIEN       (unsigned char)~_BV(5)
1073#define FUSE_JTAGEN      (unsigned char)~_BV(6)
1074#define FUSE_OCDEN       (unsigned char)~_BV(7)
1075#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
1076
1077
1078/* Extended Fuse Byte */
1079#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
1080#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
1081#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
1082#define EFUSE_DEFAULT    (0xFF)
1083
1084
1085
1086/* Lock Bits */
1087#define __LOCK_BITS_EXIST
1088#define __BOOT_LOCK_BITS_0_EXIST
1089#define __BOOT_LOCK_BITS_1_EXIST
1090
1091
1092/* Signature */
1093#define SIGNATURE_0 0x1E
1094#define SIGNATURE_1 0x97
1095#define SIGNATURE_2 0x06
1096
1097
1098#endif /* #ifdef _AVR_ATMEGA1284_H_INCLUDED */
1099
Note: See TracBrowser for help on using the repository browser.