source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom16.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

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1/* Copyright (c) 2004 Eric B. Weddington
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iom16.h 2228 2011-03-05 15:33:19Z arcanum $ */
32
33/* avr/iom16.h - definitions for ATmega16 */
34
35#ifndef _AVR_IOM16_H_
36#define _AVR_IOM16_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iom16.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* Registers and associated bit numbers */
51
52#define TWBR    _SFR_IO8(0x00)
53
54#define TWSR    _SFR_IO8(0x01)
55#define TWPS0   0
56#define TWPS1   1
57#define TWS3    3
58#define TWS4    4
59#define TWS5    5
60#define TWS6    6
61#define TWS7    7
62
63#define TWAR    _SFR_IO8(0x02)
64#define TWGCE   0
65#define TWA0    1
66#define TWA1    2
67#define TWA2    3
68#define TWA3    4
69#define TWA4    5
70#define TWA5    6
71#define TWA6    7
72
73#define TWDR    _SFR_IO8(0x03)
74
75/* Combine ADCL and ADCH */
76#ifndef __ASSEMBLER__
77#define ADC     _SFR_IO16(0x04)
78#endif
79#define ADCW    _SFR_IO16(0x04)
80#define ADCL    _SFR_IO8(0x04)
81#define ADCH    _SFR_IO8(0x05)
82
83#define ADCSRA  _SFR_IO8(0x06)
84#define ADPS0   0
85#define ADPS1   1
86#define ADPS2   2
87#define ADIE    3
88#define ADIF    4
89#define ADATE   5
90#define ADSC    6
91#define ADEN    7
92
93#define ADMUX   _SFR_IO8(0x07)
94#define MUX0    0
95#define MUX1    1
96#define MUX2    2
97#define MUX3    3
98#define MUX4    4
99#define ADLAR   5
100#define REFS0   6
101#define REFS1   7
102
103#define ACSR    _SFR_IO8(0x08)
104#define ACIS0   0
105#define ACIS1   1
106#define ACIC    2
107#define ACIE    3
108#define ACI     4
109#define ACO     5
110#define ACBG    6
111#define ACD     7
112
113#define UBRRL   _SFR_IO8(0x09)
114
115#define UCSRB   _SFR_IO8(0x0A)
116#define TXB8    0
117#define RXB8    1
118#define UCSZ2   2
119#define TXEN    3
120#define RXEN    4
121#define UDRIE   5
122#define TXCIE   6
123#define RXCIE   7
124
125#define UCSRA   _SFR_IO8(0x0B)
126#define MPCM    0
127#define U2X     1
128#define PE      2
129#define DOR     3
130#define FE      4
131#define UDRE    5
132#define TXC     6
133#define RXC     7
134
135#define UDR     _SFR_IO8(0x0C)
136
137#define SPCR    _SFR_IO8(0x0D)
138#define SPR0    0
139#define SPR1    1
140#define CPHA    2
141#define CPOL    3
142#define MSTR    4
143#define DORD    5
144#define SPE     6
145#define SPIE    7
146
147#define SPSR    _SFR_IO8(0x0E)
148#define SPI2X   0
149#define WCOL    6
150#define SPIF    7
151
152#define SPDR    _SFR_IO8(0x0F)
153
154#define PIND    _SFR_IO8(0x10)
155#define PIND0   0
156#define PIND1   1
157#define PIND2   2
158#define PIND3   3
159#define PIND4   4
160#define PIND5   5
161#define PIND6   6
162#define PIND7   7
163
164#define DDRD    _SFR_IO8(0x11)
165#define DDD0    0
166#define DDD1    1
167#define DDD2    2
168#define DDD3    3
169#define DDD4    4
170#define DDD5    5
171#define DDD6    6
172#define DDD7    7
173
174#define PORTD   _SFR_IO8(0x12)
175#define PD0     0
176#define PD1     1
177#define PD2     2
178#define PD3     3
179#define PD4     4
180#define PD5     5
181#define PD6     6
182#define PD7     7
183
184#define PINC    _SFR_IO8(0x13)
185#define PINC0   0
186#define PINC1   1
187#define PINC2   2
188#define PINC3   3
189#define PINC4   4
190#define PINC5   5
191#define PINC6   6
192#define PINC7   7
193
194#define DDRC    _SFR_IO8(0x14)
195#define DDC0    0
196#define DDC1    1
197#define DDC2    2
198#define DDC3    3
199#define DDC4    4
200#define DDC5    5
201#define DDC6    6
202#define DDC7    7
203
204#define PORTC   _SFR_IO8(0x15)
205#define PC0     0
206#define PC1     1
207#define PC2     2
208#define PC3     3
209#define PC4     4
210#define PC5     5
211#define PC6     6
212#define PC7     7
213
214#define PINB    _SFR_IO8(0x16)
215#define PINB0   0
216#define PINB1   1
217#define PINB2   2
218#define PINB3   3
219#define PINB4   4
220#define PINB5   5
221#define PINB6   6
222#define PINB7   7
223
224#define DDRB    _SFR_IO8(0x17)
225#define DDB0    0
226#define DDB1    1
227#define DDB2    2
228#define DDB3    3
229#define DDB4    4
230#define DDB5    5
231#define DDB6    6
232#define DDB7    7
233
234#define PORTB   _SFR_IO8(0x18)
235#define PB0     0
236#define PB1     1
237#define PB2     2
238#define PB3     3
239#define PB4     4
240#define PB5     5
241#define PB6     6
242#define PB7     7
243
244#define PINA    _SFR_IO8(0x19)
245#define PINA0   0
246#define PINA1   1
247#define PINA2   2
248#define PINA3   3
249#define PINA4   4
250#define PINA5   5
251#define PINA6   6
252#define PINA7   7
253
254#define DDRA    _SFR_IO8(0x1A)
255#define DDA0    0
256#define DDA1    1
257#define DDA2    2
258#define DDA3    3
259#define DDA4    4
260#define DDA5    5
261#define DDA6    6
262#define DDA7    7
263
264#define PORTA   _SFR_IO8(0x1B)
265#define PA0     0
266#define PA1     1
267#define PA2     2
268#define PA3     3
269#define PA4     4
270#define PA5     5
271#define PA6     6
272#define PA7     7
273
274/* EEPROM Control Register */
275#define EECR    _SFR_IO8(0x1C)
276#define EERE    0
277#define EEWE    1
278#define EEMWE   2
279#define EERIE   3
280
281/* EEPROM Data Register */
282#define EEDR    _SFR_IO8(0x1D)
283
284/* EEPROM Address Register */
285#define EEAR    _SFR_IO16(0x1E)
286#define EEARL   _SFR_IO8(0x1E)
287#define EEARH   _SFR_IO8(0x1F)
288
289#define UCSRC   _SFR_IO8(0x20)
290#define UCPOL   0
291#define UCSZ0   1
292#define UCSZ1   2
293#define USBS    3
294#define UPM0    4
295#define UPM1    5
296#define UMSEL   6
297#define URSEL   7
298
299#define UBRRH   _SFR_IO8(0x20)
300#define URSEL   7
301
302#define WDTCR   _SFR_IO8(0x21)
303#define WDP0    0
304#define WDP1    1
305#define WDP2    2
306#define WDE     3
307#define WDTOE   4
308
309#define ASSR    _SFR_IO8(0x22)
310#define TCR2UB  0
311#define OCR2UB  1
312#define TCN2UB  2
313#define AS2     3
314
315#define OCR2    _SFR_IO8(0x23)
316
317#define TCNT2   _SFR_IO8(0x24)
318
319#define TCCR2   _SFR_IO8(0x25)
320#define CS20    0
321#define CS21    1
322#define CS22    2
323#define WGM21   3
324#define COM20   4
325#define COM21   5
326#define WGM20   6
327#define FOC2    7
328
329/* Combine ICR1L and ICR1H */
330#define ICR1    _SFR_IO16(0x26)
331
332#define ICR1L   _SFR_IO8(0x26)
333#define ICR1H   _SFR_IO8(0x27)
334
335/* Combine OCR1BL and OCR1BH */
336#define OCR1B   _SFR_IO16(0x28)
337
338#define OCR1BL  _SFR_IO8(0x28)
339#define OCR1BH  _SFR_IO8(0x29)
340
341/* Combine OCR1AL and OCR1AH */
342#define OCR1A   _SFR_IO16(0x2A)
343
344#define OCR1AL  _SFR_IO8(0x2A)
345#define OCR1AH  _SFR_IO8(0x2B)
346
347/* Combine TCNT1L and TCNT1H */
348#define TCNT1   _SFR_IO16(0x2C)
349
350#define TCNT1L  _SFR_IO8(0x2C)
351#define TCNT1H  _SFR_IO8(0x2D)
352
353#define TCCR1B  _SFR_IO8(0x2E)
354#define CS10    0
355#define CS11    1
356#define CS12    2
357#define WGM12   3
358#define WGM13   4
359#define ICES1   6
360#define ICNC1   7
361
362#define TCCR1A  _SFR_IO8(0x2F)
363#define WGM10   0
364#define WGM11   1
365#define FOC1B   2
366#define FOC1A   3
367#define COM1B0  4
368#define COM1B1  5
369#define COM1A0  6
370#define COM1A1  7
371
372/*
373   The ADHSM bit has been removed from all documentation,
374   as being not needed at all since the comparator has proven
375   to be fast enough even without feeding it more power.
376*/
377
378#define SFIOR   _SFR_IO8(0x30)
379#define PSR10   0
380#define PSR2    1
381#define PUD     2
382#define ACME    3
383#define ADTS0   5
384#define ADTS1   6
385#define ADTS2   7
386
387#define OSCCAL  _SFR_IO8(0x31)
388
389#define OCDR    _SFR_IO8(0x31)
390
391#define TCNT0   _SFR_IO8(0x32)
392
393#define TCCR0   _SFR_IO8(0x33)
394#define CS00    0
395#define CS01    1
396#define CS02    2
397#define WGM01   3
398#define COM00   4
399#define COM01   5
400#define WGM00   6
401#define FOC0    7
402
403#define MCUCSR  _SFR_IO8(0x34)
404#define PORF    0
405#define EXTRF   1
406#define BORF    2
407#define WDRF    3
408#define JTRF    4
409#define ISC2    6
410#define JTD     7
411
412#define MCUCR   _SFR_IO8(0x35)
413#define ISC00   0
414#define ISC01   1
415#define ISC10   2
416#define ISC11   3
417#define SM0     4
418#define SM1     5
419#define SE      6
420#define SM2     7
421
422#define TWCR    _SFR_IO8(0x36)
423#define TWIE    0
424#define TWEN    2
425#define TWWC    3
426#define TWSTO   4
427#define TWSTA   5
428#define TWEA    6
429#define TWINT   7
430
431#define SPMCR   _SFR_IO8(0x37)
432#define SPMEN   0
433#define PGERS   1
434#define PGWRT   2
435#define BLBSET  3
436#define RWWSRE  4
437#define RWWSB   6
438#define SPMIE   7
439
440#define TIFR    _SFR_IO8(0x38)
441#define TOV0    0
442#define OCF0    1
443#define TOV1    2
444#define OCF1B   3
445#define OCF1A   4
446#define ICF1    5
447#define TOV2    6
448#define OCF2    7
449
450#define TIMSK   _SFR_IO8(0x39)
451#define TOIE0   0
452#define OCIE0   1
453#define TOIE1   2
454#define OCIE1B  3
455#define OCIE1A  4
456#define TICIE1  5
457#define TOIE2   6
458#define OCIE2   7
459
460#define GIFR    _SFR_IO8(0x3A)
461#define INTF2   5
462#define INTF0   6
463#define INTF1   7
464
465#define GICR    _SFR_IO8(0x3B)
466#define IVCE    0
467#define IVSEL   1
468#define INT2    5
469#define INT0    6
470#define INT1    7
471
472#define OCR0    _SFR_IO8(0x3C)
473
474/* SP [0x3D..0x3E] */
475/* SREG [0x3F] */
476
477
478/* Interrupt vectors */
479/* Vector 0 is the reset vector. */
480/* External Interrupt Request 0 */
481#define INT0_vect_num                   1
482#define INT0_vect                               _VECTOR(1)
483#define SIG_INTERRUPT0                  _VECTOR(1)
484
485/* External Interrupt Request 1 */
486#define INT1_vect_num                   2
487#define INT1_vect                               _VECTOR(2)
488#define SIG_INTERRUPT1                  _VECTOR(2)
489
490/* Timer/Counter2 Compare Match */
491#define TIMER2_COMP_vect_num    3
492#define TIMER2_COMP_vect                _VECTOR(3)
493#define SIG_OUTPUT_COMPARE2             _VECTOR(3)
494
495/* Timer/Counter2 Overflow */
496#define TIMER2_OVF_vect_num             4
497#define TIMER2_OVF_vect                 _VECTOR(4)
498#define SIG_OVERFLOW2                   _VECTOR(4)
499
500/* Timer/Counter1 Capture Event */
501#define TIMER1_CAPT_vect_num    5
502#define TIMER1_CAPT_vect                _VECTOR(5)
503#define SIG_INPUT_CAPTURE1              _VECTOR(5)
504
505/* Timer/Counter1 Compare Match A */
506#define TIMER1_COMPA_vect_num   6
507#define TIMER1_COMPA_vect               _VECTOR(6)
508#define SIG_OUTPUT_COMPARE1A    _VECTOR(6)
509
510/* Timer/Counter1 Compare Match B */
511#define TIMER1_COMPB_vect_num   7
512#define TIMER1_COMPB_vect               _VECTOR(7)
513#define SIG_OUTPUT_COMPARE1B    _VECTOR(7)
514
515/* Timer/Counter1 Overflow */
516#define TIMER1_OVF_vect_num             8
517#define TIMER1_OVF_vect                 _VECTOR(8)
518#define SIG_OVERFLOW1                   _VECTOR(8)
519
520/* Timer/Counter0 Overflow */
521#define TIMER0_OVF_vect_num             9
522#define TIMER0_OVF_vect                 _VECTOR(9)
523#define SIG_OVERFLOW0                   _VECTOR(9)
524
525/* Serial Transfer Complete */
526#define SPI_STC_vect_num                10
527#define SPI_STC_vect                    _VECTOR(10)
528#define SIG_SPI                                 _VECTOR(10)
529
530/* USART, Rx Complete */
531#define USART_RXC_vect_num              11
532#define USART_RXC_vect                  _VECTOR(11)
533#define SIG_USART_RECV                  _VECTOR(11)
534#define SIG_UART_RECV                   _VECTOR(11)
535
536/* USART Data Register Empty */
537#define USART_UDRE_vect_num             12
538#define USART_UDRE_vect                 _VECTOR(12)
539#define SIG_USART_DATA                  _VECTOR(12)
540#define SIG_UART_DATA                   _VECTOR(12)
541
542/* USART, Tx Complete */
543#define USART_TXC_vect_num              13
544#define USART_TXC_vect                  _VECTOR(13)
545#define SIG_USART_TRANS                 _VECTOR(13)
546#define SIG_UART_TRANS                  _VECTOR(13)
547
548/* ADC Conversion Complete */
549#define ADC_vect_num                    14
550#define ADC_vect                                _VECTOR(14)
551#define SIG_ADC                                 _VECTOR(14)
552
553/* EEPROM Ready */
554#define EE_RDY_vect_num                 15
555#define EE_RDY_vect                             _VECTOR(15)
556#define SIG_EEPROM_READY                _VECTOR(15)
557
558/* Analog Comparator */
559#define ANA_COMP_vect_num               16
560#define ANA_COMP_vect                   _VECTOR(16)
561#define SIG_COMPARATOR                  _VECTOR(16)
562
563/* 2-wire Serial Interface */
564#define TWI_vect_num                    17
565#define TWI_vect                                _VECTOR(17)
566#define SIG_2WIRE_SERIAL                _VECTOR(17)
567
568/* External Interrupt Request 2 */
569#define INT2_vect_num                   18
570#define INT2_vect                               _VECTOR(18)
571#define SIG_INTERRUPT2                  _VECTOR(18)
572
573/* Timer/Counter0 Compare Match */
574#define TIMER0_COMP_vect_num    19
575#define TIMER0_COMP_vect                _VECTOR(19)
576#define SIG_OUTPUT_COMPARE0             _VECTOR(19)
577
578/* Store Program Memory Ready */
579#define SPM_RDY_vect_num                20
580#define SPM_RDY_vect                    _VECTOR(20)
581#define SIG_SPM_READY                   _VECTOR(20)
582
583#define _VECTORS_SIZE 84
584
585
586/* Constants */
587#define SPM_PAGESIZE    128
588#define RAMSTART        (0x60)
589#define RAMEND          0x45F
590#define XRAMEND         RAMEND
591#define E2END           0x1FF
592#define E2PAGESIZE      4
593#define FLASHEND        0x3FFF
594
595
596/* Fuses */
597
598#define FUSE_MEMORY_SIZE 2
599
600/* Low Fuse Byte */
601#define FUSE_CKSEL0      (unsigned char)~_BV(0)
602#define FUSE_CKSEL1      (unsigned char)~_BV(1)
603#define FUSE_CKSEL2      (unsigned char)~_BV(2)
604#define FUSE_CKSEL3      (unsigned char)~_BV(3)
605#define FUSE_SUT0        (unsigned char)~_BV(4)
606#define FUSE_SUT1        (unsigned char)~_BV(5)
607#define FUSE_BODEN       (unsigned char)~_BV(6)
608#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
609#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0)
610
611/* High Fuse Byte */
612#define FUSE_BOOTRST     (unsigned char)~_BV(0)
613#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
614#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
615#define FUSE_EESAVE      (unsigned char)~_BV(3)
616#define FUSE_CKOPT       (unsigned char)~_BV(4)
617#define FUSE_SPIEN       (unsigned char)~_BV(5)
618#define FUSE_JTAGEN      (unsigned char)~_BV(6)
619#define FUSE_OCDEN       (unsigned char)~_BV(7)
620#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
621
622
623/* Lock Bits */
624#define __LOCK_BITS_EXIST
625#define __BOOT_LOCK_BITS_0_EXIST
626#define __BOOT_LOCK_BITS_1_EXIST
627
628
629/* Signature */
630#define SIGNATURE_0 0x1E
631#define SIGNATURE_1 0x94
632#define SIGNATURE_2 0x03
633
634
635
636/* Deprecated items */
637#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
638
639#pragma GCC system_header
640
641#pragma GCC poison
642
643#pragma GCC poison SIG_INTERRUPT0
644#pragma GCC poison SIG_INTERRUPT1
645#pragma GCC poison SIG_OUTPUT_COMPARE2
646#pragma GCC poison SIG_OVERFLOW2
647#pragma GCC poison SIG_INPUT_CAPTURE1
648#pragma GCC poison SIG_OUTPUT_COMPARE1A
649#pragma GCC poison SIG_OUTPUT_COMPARE1B
650#pragma GCC poison SIG_OVERFLOW1
651#pragma GCC poison SIG_OVERFLOW0
652#pragma GCC poison SIG_SPI
653#pragma GCC poison SIG_USART_RECV
654#pragma GCC poison SIG_UART_RECV
655#pragma GCC poison SIG_USART_DATA
656#pragma GCC poison SIG_UART_DATA
657#pragma GCC poison SIG_USART_TRANS
658#pragma GCC poison SIG_UART_TRANS
659#pragma GCC poison SIG_ADC
660#pragma GCC poison SIG_EEPROM_READY
661#pragma GCC poison SIG_COMPARATOR
662#pragma GCC poison SIG_2WIRE_SERIAL
663#pragma GCC poison SIG_INTERRUPT2
664#pragma GCC poison SIG_OUTPUT_COMPARE0
665#pragma GCC poison SIG_SPM_READY
666
667#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
668
669#define SLEEP_MODE_IDLE (0x00<<4)
670#define SLEEP_MODE_ADC (0x01<<4)
671#define SLEEP_MODE_PWR_DOWN (0x02<<4)
672#define SLEEP_MODE_PWR_SAVE (0x03<<4)
673#define SLEEP_MODE_STANDBY (0x0A<<4)
674#define SLEEP_MODE_EXT_STANDBY (0x0B<<4)
675
676#endif /* _AVR_IOM16_H_ */
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