source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom161.h @ 4837

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1/* Copyright (c) 2002, Marek Michalkiewicz
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iom161.h 2229 2011-03-05 17:00:18Z arcanum $ */
32
33/* avr/iom161.h - definitions for ATmega161 */
34
35#ifndef _AVR_IOM161_H_
36#define _AVR_IOM161_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iom161.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* I/O registers */
51
52/* UART1 Baud Rate Register */
53#define UBRR1   _SFR_IO8(0x00)
54
55/* UART1 Control and Status Registers */
56#define UCSR1B  _SFR_IO8(0x01)
57#define UCSR1A  _SFR_IO8(0x02)
58
59/* UART1 I/O Data Register */
60#define UDR1    _SFR_IO8(0x03)
61
62/* 0x04 reserved */
63
64/* Input Pins, Port E */
65#define PINE    _SFR_IO8(0x05)
66
67/* Data Direction Register, Port E */
68#define DDRE    _SFR_IO8(0x06)
69
70/* Data Register, Port E */
71#define PORTE   _SFR_IO8(0x07)
72
73/* Analog Comparator Control and Status Register */
74#define ACSR    _SFR_IO8(0x08)
75
76/* UART0 Baud Rate Register */
77#define UBRR0   _SFR_IO8(0x09)
78
79/* UART0 Control and Status Registers */
80#define UCSR0B  _SFR_IO8(0x0A)
81#define UCSR0A  _SFR_IO8(0x0B)
82
83/* UART0 I/O Data Register */
84#define UDR0    _SFR_IO8(0x0C)
85
86/* SPI Control Register */
87#define SPCR    _SFR_IO8(0x0D)
88
89/* SPI Status Register */
90#define SPSR    _SFR_IO8(0x0E)
91
92/* SPI I/O Data Register */
93#define SPDR    _SFR_IO8(0x0F)
94
95/* Input Pins, Port D */
96#define PIND    _SFR_IO8(0x10)
97
98/* Data Direction Register, Port D */
99#define DDRD    _SFR_IO8(0x11)
100
101/* Data Register, Port D */
102#define PORTD   _SFR_IO8(0x12)
103
104/* Input Pins, Port C */
105#define PINC    _SFR_IO8(0x13)
106
107/* Data Direction Register, Port C */
108#define DDRC    _SFR_IO8(0x14)
109
110/* Data Register, Port C */
111#define PORTC   _SFR_IO8(0x15)
112
113/* Input Pins, Port B */
114#define PINB    _SFR_IO8(0x16)
115
116/* Data Direction Register, Port B */
117#define DDRB    _SFR_IO8(0x17)
118
119/* Data Register, Port B */
120#define PORTB   _SFR_IO8(0x18)
121
122/* Input Pins, Port A */
123#define PINA    _SFR_IO8(0x19)
124
125/* Data Direction Register, Port A */
126#define DDRA    _SFR_IO8(0x1A)
127
128/* Data Register, Port A */
129#define PORTA   _SFR_IO8(0x1B)
130
131/* EEPROM Control Register */
132#define EECR    _SFR_IO8(0x1C)
133
134/* EEPROM Data Register */
135#define EEDR    _SFR_IO8(0x1D)
136
137/* EEPROM Address Register */
138#define EEAR    _SFR_IO16(0x1E)
139#define EEARL   _SFR_IO8(0x1E)
140#define EEARH   _SFR_IO8(0x1F)
141
142/* UART Baud Register HIgh */
143#define UBRRH   _SFR_IO8(0x20)
144
145/* Watchdog Timer Control Register */
146#define WDTCR   _SFR_IO8(0x21)
147
148/* Timer/Counter2 Output Compare Register */
149#define OCR2    _SFR_IO8(0x22)
150
151/* Timer/Counter2 (8-bit) */
152#define TCNT2   _SFR_IO8(0x23)
153
154/* Timer/Counter1 Input Capture Register */
155#define ICR1    _SFR_IO16(0x24)
156#define ICR1L   _SFR_IO8(0x24)
157#define ICR1H   _SFR_IO8(0x25)
158
159/* ASynchronous mode Status Register */
160#define ASSR    _SFR_IO8(0x26)
161
162/* Timer/Counter2 Control Register */
163#define TCCR2   _SFR_IO8(0x27)
164
165/* Timer/Counter1 Output Compare RegisterB */
166#define OCR1B   _SFR_IO16(0x28)
167#define OCR1BL  _SFR_IO8(0x28)
168#define OCR1BH  _SFR_IO8(0x29)
169
170/* Timer/Counter1 Output Compare RegisterA */
171#define OCR1A   _SFR_IO16(0x2A)
172#define OCR1AL  _SFR_IO8(0x2A)
173#define OCR1AH  _SFR_IO8(0x2B)
174
175/* Timer/Counter1 */
176#define TCNT1   _SFR_IO16(0x2C)
177#define TCNT1L  _SFR_IO8(0x2C)
178#define TCNT1H  _SFR_IO8(0x2D)
179
180/* Timer/Counter1 Control Register B */
181#define TCCR1B  _SFR_IO8(0x2E)
182
183/* Timer/Counter1 Control Register A */
184#define TCCR1A  _SFR_IO8(0x2F)
185
186/* Special Function IO Register */
187#define SFIOR   _SFR_IO8(0x30)
188
189/* Timer/Counter0 Output Compare Register */
190#define OCR0    _SFR_IO8(0x31)
191
192/* Timer/Counter0 (8-bit) */
193#define TCNT0   _SFR_IO8(0x32)
194
195/* Timer/Counter0 Control Register */
196#define TCCR0   _SFR_IO8(0x33)
197
198/* MCU general Status Register */
199#define MCUSR   _SFR_IO8(0x34)
200
201/* MCU general Control Register */
202#define MCUCR   _SFR_IO8(0x35)
203
204/* Extended MCU general Control Register */
205#define EMCUCR  _SFR_IO8(0x36)
206
207/* Store Program Memory Control Register */
208#define SPMCR   _SFR_IO8(0x37)
209
210/* Timer/Counter Interrupt Flag Register */
211#define TIFR    _SFR_IO8(0x38)
212
213/* Timer/Counter Interrupt MaSK Register */
214#define TIMSK   _SFR_IO8(0x39)
215
216/* General Interrupt Flag Register */
217#define GIFR    _SFR_IO8(0x3A)
218
219/* General Interrupt MaSK register */
220#define GIMSK   _SFR_IO8(0x3B)
221
222/* 0x3C reserved */
223
224/* 0x3D..0x3E SP */
225
226/* 0x3F SREG */
227
228/* Interrupt vectors */
229
230/* External Interrupt 0 */
231#define INT0_vect_num                   1
232#define INT0_vect                               _VECTOR(1)
233#define SIG_INTERRUPT0                  _VECTOR(1)
234
235/* External Interrupt 1 */
236#define INT1_vect_num                   2
237#define INT1_vect                               _VECTOR(2)
238#define SIG_INTERRUPT1                  _VECTOR(2)
239
240/* External Interrupt 2 */
241#define INT2_vect_num                   3
242#define INT2_vect                               _VECTOR(3)
243#define SIG_INTERRUPT2                  _VECTOR(3)
244
245/* Timer/Counter2 Compare Match */
246#define TIMER2_COMP_vect_num    4
247#define TIMER2_COMP_vect                _VECTOR(4)
248#define SIG_OUTPUT_COMPARE2             _VECTOR(4)
249
250/* Timer/Counter2 Overflow */
251#define TIMER2_OVF_vect_num             5
252#define TIMER2_OVF_vect                 _VECTOR(5)
253#define SIG_OVERFLOW2                   _VECTOR(5)
254
255/* Timer/Counter1 Capture Event */
256#define TIMER1_CAPT_vect_num    6
257#define TIMER1_CAPT_vect                _VECTOR(6)
258#define SIG_INPUT_CAPTURE1              _VECTOR(6)
259
260/* Timer/Counter1 Compare Match A */
261#define TIMER1_COMPA_vect_num   7
262#define TIMER1_COMPA_vect               _VECTOR(7)
263#define SIG_OUTPUT_COMPARE1A    _VECTOR(7)
264
265/* Timer/Counter1 Compare Match B */
266#define TIMER1_COMPB_vect_num   8
267#define TIMER1_COMPB_vect               _VECTOR(8)
268#define SIG_OUTPUT_COMPARE1B    _VECTOR(8)
269
270/* Timer/Counter1 Overflow */
271#define TIMER1_OVF_vect_num             9
272#define TIMER1_OVF_vect                 _VECTOR(9)
273#define SIG_OVERFLOW1                   _VECTOR(9)
274
275/* Timer/Counter0 Compare Match */
276#define TIMER0_COMP_vect_num    10
277#define TIMER0_COMP_vect                _VECTOR(10)
278#define SIG_OUTPUT_COMPARE0             _VECTOR(10)
279
280/* Timer/Counter0 Overflow */
281#define TIMER0_OVF_vect_num             11
282#define TIMER0_OVF_vect                 _VECTOR(11)
283#define SIG_OVERFLOW0                   _VECTOR(11)
284
285/* Serial Transfer Complete */
286#define SPI_STC_vect_num                12
287#define SPI_STC_vect                    _VECTOR(12)
288#define SIG_SPI                             _VECTOR(12)
289
290/* UART0, Rx Complete */
291#define UART0_RX_vect_num               13
292#define UART0_RX_vect                   _VECTOR(13)
293#define SIG_UART0_RECV                  _VECTOR(13)
294
295/* UART1, Rx Complete */
296#define UART1_RX_vect_num               14
297#define UART1_RX_vect                   _VECTOR(14)
298#define SIG_UART1_RECV                  _VECTOR(14)
299
300/* UART0 Data Register Empty */
301#define UART0_UDRE_vect_num             15
302#define UART0_UDRE_vect                 _VECTOR(15)
303#define SIG_UART0_DATA                  _VECTOR(15)
304
305/* UART1 Data Register Empty */
306#define UART1_UDRE_vect_num             16
307#define UART1_UDRE_vect                 _VECTOR(16)
308#define SIG_UART1_DATA                  _VECTOR(16)
309
310/* UART0, Tx Complete */
311#define UART0_TX_vect_num               17
312#define UART0_TX_vect                   _VECTOR(17)
313#define SIG_UART0_TRANS                 _VECTOR(17)
314
315/* UART1, Tx Complete */
316#define UART1_TX_vect_num               18
317#define UART1_TX_vect                   _VECTOR(18)
318#define SIG_UART1_TRANS                 _VECTOR(18)
319
320/* EEPROM Ready */
321#define EE_RDY_vect_num                 19
322#define EE_RDY_vect                         _VECTOR(19)
323#define SIG_EEPROM_READY                _VECTOR(19)
324
325/* Analog Comparator */
326#define ANA_COMP_vect_num               20
327#define ANA_COMP_vect                   _VECTOR(20)
328#define SIG_COMPARATOR                  _VECTOR(20)
329
330#define _VECTORS_SIZE 84
331
332/* Bit numbers */
333
334/* GIMSK */
335#define INT1    7
336#define INT0    6
337#define INT2    5
338
339/* GIFR */
340#define INTF1   7
341#define INTF0   6
342#define INTF2   5
343
344/* TIMSK */
345#define TOIE1   7
346#define OCIE1A  6
347#define OCIE1B  5
348#define TOIE2   4
349#define TICIE1  3
350#define OCIE2   2
351#define TOIE0   1
352#define OCIE0   0
353
354/* TIFR */
355#define TOV1    7
356#define OCF1A   6
357#define OCF1B   5
358#define TOV2    4
359#define ICF1    3
360#define OCF2    2
361#define TOV0    1
362#define OCF0    0
363
364/* MCUCR */
365#define SRE     7
366#define SRW10   6
367#define SE      5
368#define SM1     4
369#define ISC11   3
370#define ISC10   2
371#define ISC01   1
372#define ISC00   0
373
374/* EMCUCR */
375#define SM0     7
376#define SRL2    6
377#define SRL1    5
378#define SRL0    4
379#define SRW01   3
380#define SRW00   2
381#define SRW11   1
382#define ISC2    0
383
384/* SPMCR */
385#define BLBSET  3
386#define PGWRT   2
387#define PGERS   1
388#define SPMEN   0
389
390/* SFIOR */
391#define PSR2    1
392#define PSR10   0
393
394/* TCCR0 */
395#define FOC0    7
396#define PWM0    6
397#define COM01   5
398#define COM00   4
399#define CTC0    3
400#define CS02    2
401#define CS01    1
402#define CS00    0
403
404/* TCCR2 */
405#define FOC2    7
406#define PWM2    6
407#define COM21   5
408#define COM20   4
409#define CTC2    3
410#define CS22    2
411#define CS21    1
412#define CS20    0
413
414/* ASSR */
415#define AS2     3
416#define TCN2UB  2
417#define OCR2UB  1
418#define TCR2UB  0
419
420/* TCCR1A */
421#define COM1A1  7
422#define COM1A0  6
423#define COM1B1  5
424#define COM1B0  4
425#define FOC1A   3
426#define FOC1B   2
427#define PWM11   1
428#define PWM10   0
429
430/* TCCR1B */
431#define ICNC1   7
432#define ICES1   6
433#define CTC1    3
434#define CS12    2
435#define CS11    1
436#define CS10    0
437
438/* WDTCR */
439#define WDTOE   4
440#define WDE     3
441#define WDP2    2
442#define WDP1    1
443#define WDP0    0
444
445/* PORTA */
446#define PA7     7
447#define PA6     6
448#define PA5     5
449#define PA4     4
450#define PA3     3
451#define PA2     2
452#define PA1     1
453#define PA0     0
454
455/* DDRA */
456#define DDA7    7
457#define DDA6    6
458#define DDA5    5
459#define DDA4    4
460#define DDA3    3
461#define DDA2    2
462#define DDA1    1
463#define DDA0    0
464
465/* PINA */
466#define PINA7   7
467#define PINA6   6
468#define PINA5   5
469#define PINA4   4
470#define PINA3   3
471#define PINA2   2
472#define PINA1   1
473#define PINA0   0
474
475/*
476   PB7 = SCK
477   PB6 = MISO
478   PB5 = MOSI
479   PB4 = SS#
480   PB3 = TXD1 / AIN1
481   PB2 = RXD1 / AIN0
482   PB1 = OC2 / T1
483   PB0 = OC0 / T0
484 */
485
486/* PORTB */
487#define PB7     7
488#define PB6     6
489#define PB5     5
490#define PB4     4
491#define PB3     3
492#define PB2     2
493#define PB1     1
494#define PB0     0
495
496/* DDRB */
497#define DDB7    7
498#define DDB6    6
499#define DDB5    5
500#define DDB4    4
501#define DDB3    3
502#define DDB2    2
503#define DDB1    1
504#define DDB0    0
505
506/* PINB */
507#define PINB7   7
508#define PINB6   6
509#define PINB5   5
510#define PINB4   4
511#define PINB3   3
512#define PINB2   2
513#define PINB1   1
514#define PINB0   0
515
516/* PORTC */
517#define PC7      7
518#define PC6      6
519#define PC5      5
520#define PC4      4
521#define PC3      3
522#define PC2      2
523#define PC1      1
524#define PC0      0
525
526/* DDRC */
527#define DDC7    7
528#define DDC6    6
529#define DDC5    5
530#define DDC4    4
531#define DDC3    3
532#define DDC2    2
533#define DDC1    1
534#define DDC0    0
535
536/* PINC */
537#define PINC7   7
538#define PINC6   6
539#define PINC5   5
540#define PINC4   4
541#define PINC3   3
542#define PINC2   2
543#define PINC1   1
544#define PINC0   0
545
546/*
547   PD7 = RD#
548   PD6 = WR#
549   PD5 = TOSC2 / OC1A
550   PD4 = TOSC1
551   PD3 = INT1
552   PD2 = INT0
553   PD1 = TXD0
554   PD0 = RXD0
555 */
556
557/* PORTD */
558#define PD7      7
559#define PD6      6
560#define PD5      5
561#define PD4      4
562#define PD3      3
563#define PD2      2
564#define PD1      1
565#define PD0      0
566
567/* DDRD */
568#define DDD7    7
569#define DDD6    6
570#define DDD5    5
571#define DDD4    4
572#define DDD3    3
573#define DDD2    2
574#define DDD1    1
575#define DDD0    0
576
577/* PIND */
578#define PIND7   7
579#define PIND6   6
580#define PIND5   5
581#define PIND4   4
582#define PIND3   3
583#define PIND2   2
584#define PIND1   1
585#define PIND0   0
586
587/*
588   PE2 = ALE
589   PE1 = OC1B
590   PE0 = ICP / INT2
591 */
592
593/* PORTE */
594#define PE2     2
595#define PE1     1
596#define PE0     0
597
598/* DDRE */
599#define DDE2    2
600#define DDE1    1
601#define DDE0    0
602
603/* PINE */
604#define PINE2   2
605#define PINE1   1
606#define PINE0   0
607
608/* SPSR */
609#define SPIF    7
610#define WCOL    6
611#define SPI2X   0
612
613/* SPCR */
614#define SPIE    7
615#define SPE     6
616#define DORD    5
617#define MSTR    4
618#define CPOL    3
619#define CPHA    2
620#define SPR1    1
621#define SPR0    0
622
623/* UCSR0A, UCSR1A */
624#define RXC     7
625#define TXC     6
626#define UDRE    5
627#define FE      4
628#define DOR     3
629#define U2X     1
630#define MPCM    0
631
632/* UCSR0B, UCSR1B */
633#define RXCIE   7
634#define TXCIE   6
635#define UDRIE   5
636#define RXEN    4
637#define TXEN    3
638#define CHR9    2
639#define RXB8    1
640#define TXB8    0
641
642/* ACSR */
643#define ACD     7
644#define AINBG   6
645#define ACO     5
646#define ACI     4
647#define ACIE    3
648#define ACIC    2
649#define ACIS1   1
650#define ACIS0   0
651
652/* EEPROM Control Register */
653#define    EERIE        3
654#define    EEMWE        2
655#define    EEWE         1
656#define    EERE         0
657
658/* Constants */
659#define SPM_PAGESIZE 128
660#define RAMSTART    0x60
661#define RAMEND          0x45F
662#define XRAMEND         0xFFFF
663#define E2END           0x1FF
664#define E2PAGESIZE  0
665#define FLASHEND        0x3FFF
666
667
668/* Fuses */
669
670#define FUSE_MEMORY_SIZE 1
671
672/* Fuse Byte */
673#define FUSE_CKSEL0      (unsigned char)~_BV(0)
674#define FUSE_CKSEL1      (unsigned char)~_BV(1)
675#define FUSE_CKSEL2      (unsigned char)~_BV(2)
676#define FUSE_SUT         (unsigned char)~_BV(4)
677#define FUSE_SPIEN       (unsigned char)~_BV(5)
678#define FUSE_BOOTRST     (unsigned char)~_BV(6)
679#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SPIEN)
680
681
682/* Lock Bits */
683#define __LOCK_BITS_EXIST
684#define __BOOT_LOCK_BITS_0_EXIST
685#define __BOOT_LOCK_BITS_1_EXIST
686
687
688/* Signature */
689#define SIGNATURE_0 0x1E
690#define SIGNATURE_1 0x94
691#define SIGNATURE_2 0x01
692
693#define SLEEP_MODE_IDLE         0
694#define SLEEP_MODE_PWR_DOWN     1
695#define SLEEP_MODE_PWR_SAVE     2
696
697/* Deprecated items */
698#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
699
700#pragma GCC system_header
701
702#pragma GCC poison SIG_INTERRUPT0
703#pragma GCC poison SIG_INTERRUPT1
704#pragma GCC poison SIG_INTERRUPT2
705#pragma GCC poison SIG_OUTPUT_COMPARE2
706#pragma GCC poison SIG_OVERFLOW2
707#pragma GCC poison SIG_INPUT_CAPTURE1
708#pragma GCC poison SIG_OUTPUT_COMPARE1A
709#pragma GCC poison SIG_OUTPUT_COMPARE1B
710#pragma GCC poison SIG_OVERFLOW1
711#pragma GCC poison SIG_OUTPUT_COMPARE0
712#pragma GCC poison SIG_OVERFLOW0
713#pragma GCC poison SIG_SPI
714#pragma GCC poison SIG_UART0_RECV
715#pragma GCC poison SIG_UART1_RECV
716#pragma GCC poison SIG_UART0_DATA
717#pragma GCC poison SIG_UART1_DATA
718#pragma GCC poison SIG_UART0_TRANS
719#pragma GCC poison SIG_UART1_TRANS
720#pragma GCC poison SIG_EEPROM_READY
721#pragma GCC poison SIG_COMPARATOR
722
723#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
724
725
726#endif /* _AVR_IOM161_H_ */
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