source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom162.h @ 4837

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1/* Copyright (c) 2002, Nils Kristian Strom <nilsst@omegav.ntnu.no>
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iom162.h 2230 2011-03-06 02:42:04Z arcanum $ */
32
33/* iom162.h - definitions for ATmega162 */
34
35#ifndef _AVR_IOM162_H_
36#define _AVR_IOM162_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iom162.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* Memory mapped I/O registers */
51
52/* Timer/Counter3 Control Register A */
53#define TCCR3A  _SFR_MEM8(0x8B)
54
55/* Timer/Counter3 Control Register B */
56#define TCCR3B  _SFR_MEM8(0x8A)
57
58/* Timer/Counter3 - Counter Register */
59#define TCNT3H  _SFR_MEM8(0x89)
60#define TCNT3L  _SFR_MEM8(0x88)
61#define TCNT3   _SFR_MEM16(0x88)
62
63/* Timer/Counter3 - Output Compare Register A */
64#define OCR3AH  _SFR_MEM8(0x87)
65#define OCR3AL  _SFR_MEM8(0x86)
66#define OCR3A   _SFR_MEM16(0x86)
67
68/* Timer/Counter3 - Output Compare Register B */
69#define OCR3BH  _SFR_MEM8(0x85)
70#define OCR3BL  _SFR_MEM8(0x84)
71#define OCR3B   _SFR_MEM16(0x84)
72
73/* Timer/Counter3 - Input Capture Register */
74#define ICR3H   _SFR_MEM8(0x81)
75#define ICR3L   _SFR_MEM8(0x80)
76#define ICR3    _SFR_MEM16(0x80)
77
78/* Extended Timer/Counter Interrupt Mask */
79#define ETIMSK  _SFR_MEM8(0x7D)
80
81/* Extended Timer/Counter Interrupt Flag Register */
82#define ETIFR   _SFR_MEM8(0x7C)
83
84/* Pin Change Mask Register 1 */
85#define PCMSK1  _SFR_MEM8(0x6C)
86
87/* Pin Change Mask Register 0 */
88#define PCMSK0  _SFR_MEM8(0x6B)
89
90/* Clock PRescale */
91#define CLKPR   _SFR_MEM8(0x61)
92
93
94/* Standard I/O registers */
95
96/* 0x3F SREG */
97/* 0x3D..0x3E SP */
98#define UBRR1H  _SFR_IO8(0x3C)  /* USART 1 Baud Rate Register High Byte, Shared with UCSR1C */
99#define UCSR1C  _SFR_IO8(0x3C)  /* USART 1 Control and Status Register, Shared with UBRR1H */
100#define GICR    _SFR_IO8(0x3B)  /* General Interrupt Control Register */
101#define GIFR    _SFR_IO8(0x3A)  /* General Interrupt Flag Register */
102#define TIMSK   _SFR_IO8(0x39)  /* Timer Interrupt Mask */
103#define TIFR    _SFR_IO8(0x38)  /* Timer Interrupt Flag Register */
104#define SPMCR   _SFR_IO8(0x37)  /* Store Program Memory Control Register */
105#define EMCUCR  _SFR_IO8(0x36)  /* Extended MCU Control Register */
106#define MCUCR   _SFR_IO8(0x35)  /* MCU Control Register */
107#define MCUCSR  _SFR_IO8(0x34)  /* MCU Control and Status Register */
108#define TCCR0   _SFR_IO8(0x33)  /* Timer/Counter 0 Control Register */
109#define TCNT0   _SFR_IO8(0x32)  /* TImer/Counter 0 */
110#define OCR0    _SFR_IO8(0x31)  /* Output Compare Register 0 */
111#define SFIOR   _SFR_IO8(0x30)  /* Special Function I/O Register */
112#define TCCR1A  _SFR_IO8(0x2F)  /* Timer/Counter 1 Control Register A */
113#define TCCR1B  _SFR_IO8(0x2E)  /* Timer/Counter 1 Control Register A */
114#define TCNT1H  _SFR_IO8(0x2D)  /* Timer/Counter 1 High Byte */
115#define TCNT1L  _SFR_IO8(0x2C)  /* Timer/Counter 1 Low Byte */
116#define TCNT1   _SFR_IO16(0x2C) /* Timer/Counter 1 */
117#define OCR1AH  _SFR_IO8(0x2B)  /* Timer/Counter 1 Output Compare Register A High Byte */
118#define OCR1AL  _SFR_IO8(0x2A)  /* Timer/Counter 1 Output Compare Register A Low Byte */
119#define OCR1A   _SFR_IO16(0x2A) /* Timer/Counter 1 Output Compare Register A */
120#define OCR1BH  _SFR_IO8(0x29)  /* Timer/Counter 1 Output Compare Register B High Byte */
121#define OCR1BL  _SFR_IO8(0x28)  /* Timer/Counter 1 Output Compare Register B Low Byte */
122#define OCR1B   _SFR_IO16(0x28) /* Timer/Counter 1 Output Compare Register B */
123#define TCCR2   _SFR_IO8(0x27)  /* Timer/Counter 2 Control Register */
124#define ASSR    _SFR_IO8(0x26)  /* Asynchronous Status Register */
125#define ICR1H   _SFR_IO8(0x25)  /* Input Capture Register 1 High Byte */
126#define ICR1L   _SFR_IO8(0x24)  /* Input Capture Register 1 Low Byte */
127#define ICR1    _SFR_IO16(0x24) /* Input Capture Register 1 */
128#define TCNT2   _SFR_IO8(0x23)  /* Timer/Counter 2 */
129#define OCR2    _SFR_IO8(0x22)  /* Timer/Counter 2 Output Compare Register */
130#define WDTCR   _SFR_IO8(0x21)  /* Watchdow Timer Control Register */
131#define UBRR0H  _SFR_IO8(0x20)  /* USART 0 Baud-Rate Register High Byte, Shared with UCSR0C */
132#define UCSR0C  _SFR_IO8(0x20)  /* USART 0 Control and Status Register C, Shared with UBRR0H */
133#define EEARH   _SFR_IO8(0x1F)  /* EEPROM Address Register High Byte */
134#define EEARL   _SFR_IO8(0x1E)  /* EEPROM Address Register Low Byte */
135#define EEAR    _SFR_IO16(0x1E) /* EEPROM Address Register */
136#define EEDR    _SFR_IO8(0x1D)  /* EEPROM Data Register */
137#define EECR    _SFR_IO8(0x1C)  /* EEPROM Control Register */
138#define PORTA   _SFR_IO8(0x1B)  /* Port A */
139#define DDRA    _SFR_IO8(0x1A)  /* Port A Data Direction Register */
140#define PINA    _SFR_IO8(0x19)  /* Port A Pin Register */
141#define PORTB   _SFR_IO8(0x18)  /* Port B */
142#define DDRB    _SFR_IO8(0x17)  /* Port B Data Direction Register */
143#define PINB    _SFR_IO8(0x16)  /* Port B Pin Register */
144#define PORTC   _SFR_IO8(0x15)  /* Port C */
145#define DDRC    _SFR_IO8(0x14)  /* Port C Data Direction Register */
146#define PINC    _SFR_IO8(0x13)  /* Port C Pin Register */
147#define PORTD   _SFR_IO8(0x12)  /* Port D */
148#define DDRD    _SFR_IO8(0x11)  /* Port D Data Direction Register */
149#define PIND    _SFR_IO8(0x10)  /* Port D Pin Register */
150#define SPDR    _SFR_IO8(0x0F)  /* SPI Data Register */
151#define SPSR    _SFR_IO8(0x0E)  /* SPI Status Register */
152#define SPCR    _SFR_IO8(0x0D)  /* SPI Control Register */
153#define UDR0    _SFR_IO8(0x0C)  /* USART 0 Data Register */
154#define UCSR0A  _SFR_IO8(0x0B)  /* USART 0 Control and Status Register A */
155#define UCSR0B  _SFR_IO8(0x0A)  /* USART 0 Control and Status Register B */
156#define UBRR0L  _SFR_IO8(0x09)  /* USART 0 Baud-Rate Register Low Byte */
157#define ACSR    _SFR_IO8(0x08)  /* Analog Comparator Status Register */
158#define PORTE   _SFR_IO8(0x07)  /* Port E */
159#define DDRE    _SFR_IO8(0x06)  /* Port E Data Direction Register */
160#define PINE    _SFR_IO8(0x05)  /* Port E Pin Register */
161#define OSCCAL  _SFR_IO8(0x04)  /* Oscillator Calibration, Shared with OCDR */
162#define OCDR    _SFR_IO8(0x04)  /* On-Chip Debug Register, Shared with OSCCAL */
163#define UDR1    _SFR_IO8(0x03)  /* USART 1 Data Register */
164#define UCSR1A  _SFR_IO8(0x02)  /* USART 1 Control and Status Register A */
165#define UCSR1B  _SFR_IO8(0x01)  /* USART 1 Control and Status Register B */
166#define UBRR1L  _SFR_IO8(0x00)  /* USART 0 Baud Rate Register High Byte */
167 
168
169/* Interrupt vectors (byte addresses) */
170
171/* External Interrupt Request 0 */
172#define INT0_vect_num                   1
173#define INT0_vect                       _VECTOR(1)
174#define SIG_INTERRUPT0                  _VECTOR(1)
175
176/* External Interrupt Request 1 */
177#define INT1_vect_num                   2
178#define INT1_vect                           _VECTOR(2)
179#define SIG_INTERRUPT1                  _VECTOR(2)
180
181/* External Interrupt Request 2 */
182#define INT2_vect_num                   3
183#define INT2_vect                       _VECTOR(3)
184#define SIG_INTERRUPT2                  _VECTOR(3)
185
186/* Pin Change Interrupt Request 0 */
187#define PCINT0_vect_num                 4
188#define PCINT0_vect                         _VECTOR(4)
189#define SIG_PIN_CHANGE0                 _VECTOR(4)
190
191/* Pin Change Interrupt Request 1 */
192#define PCINT1_vect_num                 5
193#define PCINT1_vect                         _VECTOR(5)
194#define SIG_PIN_CHANGE1                 _VECTOR(5)
195
196/* Timer/Counter3 Capture Event */
197#define TIMER3_CAPT_vect_num    6
198#define TIMER3_CAPT_vect                _VECTOR(6)
199#define SIG_INPUT_CAPTURE3              _VECTOR(6)
200
201/* Timer/Counter3 Compare Match A */
202#define TIMER3_COMPA_vect_num   7
203#define TIMER3_COMPA_vect           _VECTOR(7)
204#define SIG_OUTPUT_COMPARE3A    _VECTOR(7)
205
206/* Timer/Counter3 Compare Match B */
207#define TIMER3_COMPB_vect_num   8
208#define TIMER3_COMPB_vect               _VECTOR(8)
209#define SIG_OUTPUT_COMPARE3B    _VECTOR(8)
210
211/* Timer/Counter3 Overflow */
212#define TIMER3_OVF_vect_num             9
213#define TIMER3_OVF_vect                 _VECTOR(9)
214#define SIG_OVERFLOW3                   _VECTOR(9)
215
216/* Timer/Counter2 Compare Match */
217#define TIMER2_COMP_vect_num    10
218#define TIMER2_COMP_vect                _VECTOR(10)
219#define SIG_OUTPUT_COMPARE2             _VECTOR(10)
220
221/* Timer/Counter2 Overflow */
222#define TIMER2_OVF_vect_num             11
223#define TIMER2_OVF_vect                 _VECTOR(11)
224#define SIG_OVERFLOW2                   _VECTOR(11)
225
226/* Timer/Counter1 Capture Event */
227#define TIMER1_CAPT_vect_num    12
228#define TIMER1_CAPT_vect                _VECTOR(12)
229#define SIG_INPUT_CAPTURE1              _VECTOR(12)
230
231/* Timer/Counter1 Compare Match A */
232#define TIMER1_COMPA_vect_num   13
233#define TIMER1_COMPA_vect               _VECTOR(13)
234#define SIG_OUTPUT_COMPARE1A    _VECTOR(13)
235
236/* Timer/Counter Compare Match B */
237#define TIMER1_COMPB_vect_num   14
238#define TIMER1_COMPB_vect               _VECTOR(14)
239#define SIG_OUTPUT_COMPARE1B    _VECTOR(14)
240
241/* Timer/Counter1 Overflow */
242#define TIMER1_OVF_vect_num             15
243#define TIMER1_OVF_vect                 _VECTOR(15)
244#define SIG_OVERFLOW1                   _VECTOR(15)
245
246/* Timer/Counter0 Compare Match */
247#define TIMER0_COMP_vect_num    16
248#define TIMER0_COMP_vect                _VECTOR(16)
249#define SIG_OUTPUT_COMPARE0             _VECTOR(16)
250
251/* Timer/Counter0 Overflow */
252#define TIMER0_OVF_vect_num             17
253#define TIMER0_OVF_vect                 _VECTOR(17)
254#define SIG_OVERFLOW0                   _VECTOR(17)
255
256/* SPI Serial Transfer Complete */
257#define SPI_STC_vect_num                18
258#define SPI_STC_vect                    _VECTOR(18)
259#define SIG_SPI                                 _VECTOR(18)
260
261/* USART0, Rx Complete */
262#define USART0_RXC_vect_num             19
263#define USART0_RXC_vect                 _VECTOR(19)
264#define SIG_USART0_RECV                 _VECTOR(19)
265
266/* USART1, Rx Complete */
267#define USART1_RXC_vect_num             20
268#define USART1_RXC_vect                 _VECTOR(20)
269#define SIG_USART1_RECV                 _VECTOR(20)
270
271/* USART0 Data register Empty */
272#define USART0_UDRE_vect_num    21
273#define USART0_UDRE_vect                _VECTOR(21)
274#define SIG_USART0_DATA                 _VECTOR(21)
275
276/* USART1, Data register Empty */
277#define USART1_UDRE_vect_num    22
278#define USART1_UDRE_vect                _VECTOR(22)
279#define SIG_USART1_DATA                 _VECTOR(22)
280
281/* USART0, Tx Complete */
282#define USART0_TXC_vect_num             23
283#define USART0_TXC_vect                 _VECTOR(23)
284#define SIG_USART0_TRANS                _VECTOR(23)
285
286/* USART1, Tx Complete */
287#define USART1_TXC_vect_num             24
288#define USART1_TXC_vect                 _VECTOR(24)
289#define SIG_USART1_TRANS                _VECTOR(24)
290
291/* EEPROM Ready */
292#define EE_RDY_vect_num                 25
293#define EE_RDY_vect                         _VECTOR(25)
294#define SIG_EEPROM_READY                _VECTOR(25)
295
296/* Analog Comparator */
297#define ANA_COMP_vect_num               26
298#define ANA_COMP_vect                   _VECTOR(26)
299#define SIG_COMPARATOR                  _VECTOR(26)
300
301/* Store Program Memory Read */
302#define SPM_RDY_vect_num                27
303#define SPM_RDY_vect                    _VECTOR(27)
304#define SIG_SPM_READY                   _VECTOR(27)
305
306#define _VECTORS_SIZE 112 /* = (num vec+1) * 4 */
307
308
309
310
311
312/* TCCR3B bit definitions, memory mapped I/O */
313
314#define ICNC3   7
315#define ICES3   6
316#define WGM33   4
317#define WGM32   3
318#define CS32    2
319#define CS31    1
320#define CS30    0
321
322
323
324/* TCCR3A bit definitions, memory mapped I/O */
325
326#define COM3A1  7
327#define COM3A0  6
328#define COM3B1  5
329#define COM3B0  4
330#define FOC3A   3
331#define FOC3B   2
332#define WGM31   1
333#define WGM30   0
334
335
336
337/* ETIMSK bit definitions, memory mapped I/O */
338
339#define TICIE3          5
340#define OCIE3A          4
341#define OCIE3B          3
342#define TOIE3           2
343
344
345
346/* ETIFR bit definitions, memory mapped I/O */
347
348#define ICF3            5
349#define OCF3A           4
350#define OCF3B           3
351#define TOV3            2
352
353
354
355/* PCMSK1 bit definitions, memory mapped I/O */
356#define PCINT15 7
357#define PCINT14 6
358#define PCINT13 5
359#define PCINT12 4
360#define PCINT11 3
361#define PCINT10 2
362#define PCINT9  1
363#define PCINT8  0
364
365
366
367/* PCMSK0 bit definitions, memory mapped I/O */
368
369#define PCINT7  7
370#define PCINT6  6
371#define PCINT5  5
372#define PCINT4  4
373#define PCINT3  3
374#define PCINT2  2
375#define PCINT1  1
376#define PCINT0  0
377
378
379
380/* CLKPR bit definitions, memory mapped I/O */
381
382#define CLKPCE  7
383#define CLKPS3  3
384#define CLKPS2  2
385#define CLKPS1  1
386#define CLKPS0  0
387
388
389
390/* SPH bit definitions */
391
392#define SP15    15
393#define SP14    14
394#define SP13    13
395#define SP12    12
396#define SP11    11
397#define SP10    10
398#define SP9     9
399#define SP8     8
400
401
402
403/* SPL bit definitions */
404
405#define SP7     7
406#define SP6     6
407#define SP5     5
408#define SP4     4
409#define SP3     3
410#define SP2     2
411#define SP1     1
412#define SP0     0
413
414
415
416/* UBRR1H bit definitions */
417
418#define URSEL1  7
419#define UBRR111 3
420#define UBRR110 2
421#define UBRR19  1
422#define UBRR18  0
423
424
425
426/* UCSR1C bit definitions */
427
428#define URSEL1  7
429#define UMSEL1  6
430#define UPM11   5
431#define UPM10   4
432#define USBS1   3
433#define UCSZ11  2
434#define UCSZ10  1
435#define UCPOL1  0
436
437
438
439/* GICR bit definitions */
440
441#define INT1    7
442#define INT0    6
443#define INT2    5
444#define PCIE1   4
445#define PCIE0   3
446#define IVSEL   1
447#define IVCE    0
448
449
450
451/* GIFR bit definitions */
452
453#define INTF1   7
454#define INTF0   6
455#define INTF2   5
456#define PCIF1   4
457#define PCIF0   3
458
459
460
461/* TIMSK bit definitions */
462
463#define TOIE1   7
464#define OCIE1A  6
465#define OCIE1B  5
466#define OCIE2   4
467#define TICIE1  3
468#define TOIE2   2
469#define TOIE0   1
470#define OCIE0   0
471
472
473
474/* TIFR bit definitions */
475
476#define TOV1    7
477#define OCF1A   6
478#define OCF1B   5
479#define OCF2    4
480#define ICF1    3
481#define TOV2    2
482#define TOV0    1
483#define OCF0    0
484
485
486
487/* SPMCR bit definitions */ 
488
489#define SPMIE   7
490#define RWWSB   6
491#define RWWSRE  4
492#define BLBSET  3
493#define PGWRT   2
494#define PGERS   1
495#define SPMEN   0
496
497
498
499/* EMCUCR bit definitions */
500
501#define SM0     7
502#define SRL2    6
503#define SRL1    5
504#define SRL0    4
505#define SRW01   3
506#define SRW00   2
507#define SRW11   1
508#define ISC2    0
509
510
511
512/* MCUCR bit definitions */
513
514#define SRE     7
515#define SRW10   6
516#define SE      5
517#define SM1     4
518#define ISC11   3
519#define ISC10   2
520#define ISC01   1
521#define ISC00   0
522
523
524
525/* MCUCSR bit definitions */
526
527#define JTD     7
528#define SM2     5
529#define JTRF    4
530#define WDRF    3
531#define BORF    2
532#define EXTRF   1
533#define PORF    0
534
535
536
537/* TCCR0 bit definitions */
538
539#define FOC0    7
540#define WGM00   6
541#define COM01   5
542#define COM00   4
543#define WGM01   3
544#define CS02    2
545#define CS01    1
546#define CS00    0
547
548
549
550/* SFIOR bit definitions */
551
552#define TSM     7
553#define XMBK    6
554#define XMM2    5
555#define XMM1    4
556#define XMM0    3
557#define PUD     2
558#define PSR2    1
559#define PSR310  0
560
561
562
563/* TCCR1A bit definitions */
564
565#define COM1A1  7
566#define COM1A0  6
567#define COM1B1  5
568#define COM1B0  4
569#define FOC1A   3
570#define FOC1B   2
571#define WGM11   1
572#define WGM10   0
573
574
575
576
577/* TCCR1B bit definitions */
578
579#define ICNC1   7               /* Input Capture Noise Canceler */
580#define ICES1   6               /* Input Capture Edge Select */
581#define WGM13   4               /* Waveform Generation Mode 3 */
582#define WGM12   3               /* Waveform Generation Mode 2 */
583#define CS12    2               /* Clock Select 2 */
584#define CS11    1               /* Clock Select 1 */
585#define CS10    0               /* Clock Select 0 */
586
587
588
589/* TCCR2 bit definitions */
590
591#define FOC2    7
592#define WGM20   6
593#define COM21   5
594#define COM20   4
595#define WGM21   3
596#define CS22    2
597#define CS21    1
598#define CS20    0
599
600
601
602/* ASSR bit definitions */
603
604#define AS2     3
605#define TCN2UB  2
606#define TCON2UB 2   /* Kept for backwards compatibility. */
607#define OCR2UB  1
608#define TCR2UB  0
609
610
611
612/* WDTCR bit definitions */
613
614#define WDCE    4
615#define WDE     3
616#define WDP2    2
617#define WDP1    1
618#define WDP0    0
619
620
621
622/* UBRR0H bif definitions */
623
624#define URSEL0  7
625#define UBRR011 3
626#define UBRR010 2
627#define UBRR09  1
628#define UBRR08  0
629
630
631
632/* UCSR0C bit definitions */
633
634#define URSEL0  7
635#define UMSEL0  6
636#define UPM01   5
637#define UPM00   4
638#define USBS0   3
639#define UCSZ01  2
640#define UCSZ00  1
641#define UCPOL0  0
642
643
644
645/* EEARH bit definitions */
646
647#define EEAR8   0
648
649
650
651/* EECR bit definitions */
652
653#define EERIE   3
654#define EEMWE   2
655#define EEWE    1
656#define EERE    0
657
658
659
660/* PORTA bit definitions */
661
662#define PA7     7
663#define PA6     6
664#define PA5     5
665#define PA4     4
666#define PA3     3
667#define PA2     2
668#define PA1     1
669#define PA0     0
670
671
672
673/* DDRA bit definitions */
674
675#define DDA7    7
676#define DDA6    6
677#define DDA5    5
678#define DDA4    4
679#define DDA3    3
680#define DDA2    2
681#define DDA1    1
682#define DDA0    0
683
684
685
686/* PINA bit definitions */
687
688#define PINA7   7
689#define PINA6   6
690#define PINA5   5
691#define PINA4   4
692#define PINA3   3
693#define PINA2   2
694#define PINA1   1
695#define PINA0   0
696
697
698/* PORTB bit definitions */
699
700#define PB7     7
701#define PB6     6
702#define PB5     5
703#define PB4     4
704#define PB3     3
705#define PB2     2
706#define PB1     1
707#define PB0     0
708
709
710
711/* DDRB bit definitions */
712
713#define DDB7    7
714#define DDB6    6
715#define DDB5    5
716#define DDB4    4
717#define DDB3    3
718#define DDB2    2
719#define DDB1    1
720#define DDB0    0
721
722
723
724/* PINB bit definitions */
725
726#define PINB7   7
727#define PINB6   6
728#define PINB5   5
729#define PINB4   4
730#define PINB3   3
731#define PINB2   2
732#define PINB1   1
733#define PINB0   0
734
735
736
737/* PORTC bit definitions */
738
739#define PC7      7
740#define PC6      6
741#define PC5      5
742#define PC4      4
743#define PC3      3
744#define PC2      2
745#define PC1      1
746#define PC0      0
747
748
749
750/* DDRC bit definitions */
751
752#define DDC7    7
753#define DDC6    6
754#define DDC5    5
755#define DDC4    4
756#define DDC3    3
757#define DDC2    2
758#define DDC1    1
759#define DDC0    0
760
761
762
763/* PINC bit definitions */
764
765#define PINC7   7
766#define PINC6   6
767#define PINC5   5
768#define PINC4   4
769#define PINC3   3
770#define PINC2   2
771#define PINC1   1
772#define PINC0   0
773
774
775
776/* PORTD bit definitions */
777
778#define PD7      7
779#define PD6      6
780#define PD5      5
781#define PD4      4
782#define PD3      3
783#define PD2      2
784#define PD1      1
785#define PD0      0
786
787
788
789/* DDRD bit definitions */
790
791#define DDD7    7
792#define DDD6    6
793#define DDD5    5
794#define DDD4    4
795#define DDD3    3
796#define DDD2    2
797#define DDD1    1
798#define DDD0    0
799
800
801
802/* PIND bit definitions */
803
804#define PIND7   7
805#define PIND6   6
806#define PIND5   5
807#define PIND4   4
808#define PIND3   3
809#define PIND2   2
810#define PIND1   1
811#define PIND0   0
812
813
814
815/* SPSR bit definitions */
816
817#define SPIF    7
818#define WCOL    6
819#define SPI2X   0
820
821
822
823/* SPCR bit definitions */
824
825#define SPIE    7
826#define SPE     6
827#define DORD    5
828#define MSTR    4
829#define CPOL    3
830#define CPHA    2
831#define SPR1    1
832#define SPR0    0
833
834
835
836/* UCSR0A bit definitions */
837
838#define RXC0    7
839#define TXC0    6
840#define UDRE0   5
841#define FE0     4
842#define DOR0    3
843#define UPE0    2
844#define U2X0    1
845#define MPCM0   0
846
847
848
849/* UCSR0B bit definitions */
850
851#define RXCIE0  7
852#define TXCIE0  6
853#define UDRIE0  5
854#define RXEN0   4
855#define TXEN0   3
856#define UCSZ02  2
857#define RXB80   1
858#define TXB80   0
859
860
861
862/* ACSR bit definitions */
863
864#define ACD     7
865#define ACBG    6
866#define ACO     5
867#define ACI     4
868#define ACIE    3
869#define ACIC    2
870#define ACIS1   1
871#define ACIS0   0
872
873
874
875/* PORTE bit definitions */
876
877#define PE2     2
878#define PE1     1
879#define PE0     0
880
881
882
883/* DDRE bit definitions */
884
885#define DDE2    2
886#define DDE1    1
887#define DDE0    0
888
889
890
891/* PINE bit definitions */
892
893#define PINE2   2
894#define PINE1   1
895#define PINE0   0
896
897
898
899/* UCSR1A bit definitions */
900
901#define RXC1    7
902#define TXC1    6
903#define UDRE1   5
904#define FE1     4
905#define DOR1    3
906#define UPE1    2
907#define U2X1    1
908#define MPCM1   0
909
910
911
912/* UCSR1B bit definitions */
913
914#define RXCIE1  7
915#define TXCIE1  6
916#define UDRIE1  5
917#define RXEN1   4
918#define TXEN1   3
919#define UCSZ12  2
920#define RXB81   1
921#define TXB81   0
922
923
924/* Constants */
925#define SPM_PAGESIZE 128
926#define RAMSTART    0x100
927#define RAMEND          0x4FF
928#define XRAMEND         0xFFFF
929#define E2END           0x1FF
930#define E2PAGESIZE  4
931#define FLASHEND        0x3FFF
932
933
934/* Fuses */
935
936#define FUSE_MEMORY_SIZE 3
937
938/* Low Fuse Byte */
939#define FUSE_CKSEL0      (unsigned char)~_BV(0)
940#define FUSE_CKSEL1      (unsigned char)~_BV(1)
941#define FUSE_CKSEL2      (unsigned char)~_BV(2)
942#define FUSE_CKSEL3      (unsigned char)~_BV(3)
943#define FUSE_SUT0        (unsigned char)~_BV(4)
944#define FUSE_SUT1        (unsigned char)~_BV(5)
945#define FUSE_CKOUT       (unsigned char)~_BV(6)
946#define FUSE_CKDIV8      (unsigned char)~_BV(7)
947#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
948
949/* High Fuse Byte */
950#define FUSE_BOOTRST     (unsigned char)~_BV(0)
951#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
952#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
953#define FUSE_EESAVE      (unsigned char)~_BV(3)
954#define FUSE_WDTON       (unsigned char)~_BV(4)
955#define FUSE_SPIEN       (unsigned char)~_BV(5)
956#define FUSE_JTAGEN      (unsigned char)~_BV(6)
957#define FUSE_OCDEN       (unsigned char)~_BV(7)
958#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
959
960/* Extended Fuse Byte */
961#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
962#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
963#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
964#define FUSE_M161C       (unsigned char)~_BV(4)
965#define EFUSE_DEFAULT (0xFF)
966
967
968/* Lock Bits */
969#define __LOCK_BITS_EXIST
970#define __BOOT_LOCK_BITS_0_EXIST
971#define __BOOT_LOCK_BITS_1_EXIST
972
973
974/* Signature */
975#define SIGNATURE_0 0x1E
976#define SIGNATURE_1 0x94
977#define SIGNATURE_2 0x04
978
979#define SLEEP_MODE_IDLE         0
980#define SLEEP_MODE_PWR_DOWN     1
981#define SLEEP_MODE_PWR_SAVE     2
982#define SLEEP_MODE_ADC          3
983#define SLEEP_MODE_STANDBY      4
984#define SLEEP_MODE_EXT_STANDBY  5
985
986/* Deprecated items */
987#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
988
989#pragma GCC system_header
990
991#pragma GCC poison SIG_INTERRUPT0
992#pragma GCC poison SIG_INTERRUPT1
993#pragma GCC poison SIG_INTERRUPT2
994#pragma GCC poison SIG_PIN_CHANGE0
995#pragma GCC poison SIG_PIN_CHANGE1
996#pragma GCC poison SIG_INPUT_CAPTURE3
997#pragma GCC poison SIG_OUTPUT_COMPARE3A
998#pragma GCC poison SIG_OUTPUT_COMPARE3B
999#pragma GCC poison SIG_OVERFLOW3
1000#pragma GCC poison SIG_OUTPUT_COMPARE2
1001#pragma GCC poison SIG_OVERFLOW2
1002#pragma GCC poison SIG_INPUT_CAPTURE1
1003#pragma GCC poison SIG_OUTPUT_COMPARE1A
1004#pragma GCC poison SIG_OUTPUT_COMPARE1B
1005#pragma GCC poison SIG_OVERFLOW1
1006#pragma GCC poison SIG_OUTPUT_COMPARE0
1007#pragma GCC poison SIG_OVERFLOW0
1008#pragma GCC poison SIG_SPI
1009#pragma GCC poison SIG_USART0_RECV
1010#pragma GCC poison SIG_USART1_RECV
1011#pragma GCC poison SIG_USART0_DATA
1012#pragma GCC poison SIG_USART1_DATA
1013#pragma GCC poison SIG_USART0_TRANS
1014#pragma GCC poison SIG_USART1_TRANS
1015#pragma GCC poison SIG_EEPROM_READY
1016#pragma GCC poison SIG_COMPARATOR
1017#pragma GCC poison SIG_SPM_READY
1018
1019#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
1020
1021
1022#endif  /* _AVR_IOM162_H_ */
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