source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom165pa.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

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1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATMEGA165PA_H_INCLUDED
36#define _AVR_ATMEGA165PA_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "iom165pa.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINA    _SFR_IO8(0x00)
52#define PINA7   7
53#define PINA6   6
54#define PINA5   5
55#define PINA4   4
56#define PINA3   3
57#define PINA2   2
58#define PINA1   1
59#define PINA0   0
60
61#define DDRA    _SFR_IO8(0x01)
62#define DDRA7   7
63// Inserted "DDA7" from "DDRA7" due to compatibility
64#define DDA7    7
65#define DDRA6   6
66// Inserted "DDA6" from "DDRA6" due to compatibility
67#define DDA6    6
68#define DDRA5   5
69// Inserted "DDA5" from "DDRA5" due to compatibility
70#define DDA5    5
71#define DDRA4   4
72// Inserted "DDA4" from "DDRA4" due to compatibility
73#define DDA4    4
74#define DDRA3   3
75// Inserted "DDA3" from "DDRA3" due to compatibility
76#define DDA3    3
77#define DDRA2   2
78// Inserted "DDA2" from "DDRA2" due to compatibility
79#define DDA2    2
80#define DDRA1   1
81// Inserted "DDA1" from "DDRA1" due to compatibility
82#define DDA1    1
83#define DDRA0   0
84// Inserted "DDA0" from "DDRA0" due to compatibility
85#define DDA0    0
86
87#define PORTA   _SFR_IO8(0x02)
88#define PORTA7  7
89#define PORTA6  6
90#define PORTA5  5
91#define PORTA4  4
92#define PORTA3  3
93#define PORTA2  2
94#define PORTA1  1
95#define PORTA0  0
96
97#define PINB    _SFR_IO8(0x03)
98#define PINB7   7
99#define PINB6   6
100#define PINB5   5
101#define PINB4   4
102#define PINB3   3
103#define PINB2   2
104#define PINB1   1
105#define PINB0   0
106
107#define DDRB    _SFR_IO8(0x04)
108#define DDRB7   7
109// Inserted "DDB7" from "DDRB7" due to compatibility
110#define DDB7    7
111#define DDRB6   6
112// Inserted "DDB6" from "DDRB6" due to compatibility
113#define DDB6    6
114#define DDRB5   5
115// Inserted "DDB5" from "DDRB5" due to compatibility
116#define DDB5    5
117#define DDRB4   4
118// Inserted "DDB4" from "DDRB4" due to compatibility
119#define DDB4    4
120#define DDRB3   3
121// Inserted "DDB3" from "DDRB3" due to compatibility
122#define DDB3    3
123#define DDRB2   2
124// Inserted "DDB2" from "DDRB2" due to compatibility
125#define DDB2    2
126#define DDRB1   1
127// Inserted "DDB1" from "DDRB1" due to compatibility
128#define DDB1    1
129#define DDRB0   0
130// Inserted "DDB0" from "DDRB0" due to compatibility
131#define DDB0    0
132
133#define PORTB   _SFR_IO8(0x05)
134#define PORTB7  7
135#define PORTB6  6
136#define PORTB5  5
137#define PORTB4  4
138#define PORTB3  3
139#define PORTB2  2
140#define PORTB1  1
141#define PORTB0  0
142
143#define PINC    _SFR_IO8(0x06)
144#define PINC7   7
145#define PINC6   6
146#define PINC5   5
147#define PINC4   4
148#define PINC3   3
149#define PINC2   2
150#define PINC1   1
151#define PINC0   0
152
153#define DDRC    _SFR_IO8(0x07)
154#define DDRC7   7
155// Inserted "DDC7" from "DDRC7" due to compatibility
156#define DDC7    7
157#define DDRC6   6
158// Inserted "DDC6" from "DDRC6" due to compatibility
159#define DDC6    6
160#define DDRC5   5
161// Inserted "DDC5" from "DDRC5" due to compatibility
162#define DDC5    5
163#define DDRC4   4
164// Inserted "DDC4" from "DDRC4" due to compatibility
165#define DDC4    4
166#define DDRC3   3
167// Inserted "DDC3" from "DDRC3" due to compatibility
168#define DDC3    3
169#define DDRC2   2
170// Inserted "DDC2" from "DDRC2" due to compatibility
171#define DDC2    2
172#define DDRC1   1
173// Inserted "DDC1" from "DDRC1" due to compatibility
174#define DDC1    1
175#define DDRC0   0
176// Inserted "DDC0" from "DDRC0" due to compatibility
177#define DDC0    0
178
179#define PORTC   _SFR_IO8(0x08)
180#define PORTC7  7
181#define PORTC6  6
182#define PORTC5  5
183#define PORTC4  4
184#define PORTC3  3
185#define PORTC2  2
186#define PORTC1  1
187#define PORTC0  0
188
189#define PIND    _SFR_IO8(0x09)
190#define PIND7   7
191#define PIND6   6
192#define PIND5   5
193#define PIND4   4
194#define PIND3   3
195#define PIND2   2
196#define PIND1   1
197#define PIND0   0
198
199#define DDRD    _SFR_IO8(0x0A)
200#define DDRD7   7
201// Inserted "DDD7" from "DDRD7" due to compatibility
202#define DDD7    7
203#define DDRD6   6
204// Inserted "DDD6" from "DDRD6" due to compatibility
205#define DDD6    6
206#define DDRD5   5
207// Inserted "DDD5" from "DDRD5" due to compatibility
208#define DDD5    5
209#define DDRD4   4
210// Inserted "DDD4" from "DDRD4" due to compatibility
211#define DDD4    4
212#define DDRD3   3
213// Inserted "DDD3" from "DDRD3" due to compatibility
214#define DDD3    3
215#define DDRD2   2
216// Inserted "DDD2" from "DDRD2" due to compatibility
217#define DDD2    2
218#define DDRD1   1
219// Inserted "DDD1" from "DDRD1" due to compatibility
220#define DDD1    1
221#define DDRD0   0
222// Inserted "DDD0" from "DDRD0" due to compatibility
223#define DDD0    0
224
225#define PORTD   _SFR_IO8(0x0B)
226#define PORTD7  7
227#define PORTD6  6
228#define PORTD5  5
229#define PORTD4  4
230#define PORTD3  3
231#define PORTD2  2
232#define PORTD1  1
233#define PORTD0  0
234
235#define PINE    _SFR_IO8(0x0C)
236#define PINE7   7
237#define PINE6   6
238#define PINE5   5
239#define PINE4   4
240#define PINE3   3
241#define PINE2   2
242#define PINE1   1
243#define PINE0   0
244
245#define DDRE    _SFR_IO8(0x0D)
246#define DDRE7   7
247// Inserted "DDE7" from "DDRE7" due to compatibility
248#define DDE7    7
249#define DDRE6   6
250// Inserted "DDE6" from "DDRE6" due to compatibility
251#define DDE6    6
252#define DDRE5   5
253// Inserted "DDE5" from "DDRE5" due to compatibility
254#define DDE5    5
255#define DDRE4   4
256// Inserted "DDE4" from "DDRE4" due to compatibility
257#define DDE4    4
258#define DDRE3   3
259// Inserted "DDE3" from "DDRE3" due to compatibility
260#define DDE3    3
261#define DDRE2   2
262// Inserted "DDE2" from "DDRE2" due to compatibility
263#define DDE2    2
264#define DDRE1   1
265// Inserted "DDE1" from "DDRE1" due to compatibility
266#define DDE1    1
267#define DDRE0   0
268// Inserted "DDE0" from "DDRE0" due to compatibility
269#define DDE0    0
270
271#define PORTE   _SFR_IO8(0x0E)
272#define PORTE7  7
273#define PORTE6  6
274#define PORTE5  5
275#define PORTE4  4
276#define PORTE3  3
277#define PORTE2  2
278#define PORTE1  1
279#define PORTE0  0
280
281#define PINF    _SFR_IO8(0x0F)
282#define PINF7   7
283#define PINF6   6
284#define PINF5   5
285#define PINF4   4
286#define PINF3   3
287#define PINF2   2
288#define PINF1   1
289#define PINF0   0
290
291#define DDRF    _SFR_IO8(0x10)
292#define DDRF7   7
293// Inserted "DDF7" from "DDRF7" due to compatibility
294#define DDF7    7
295#define DDRF6   6
296// Inserted "DDF6" from "DDRF6" due to compatibility
297#define DDF6    6
298#define DDRF5   5
299// Inserted "DDF5" from "DDRF5" due to compatibility
300#define DDF5    5
301#define DDRF4   4
302// Inserted "DDF4" from "DDRF4" due to compatibility
303#define DDF4    4
304#define DDRF3   3
305// Inserted "DDF3" from "DDRF3" due to compatibility
306#define DDF3    3
307#define DDRF2   2
308// Inserted "DDF2" from "DDRF2" due to compatibility
309#define DDF2    2
310#define DDRF1   1
311// Inserted "DDF1" from "DDRF1" due to compatibility
312#define DDF1    1
313#define DDRF0   0
314// Inserted "DDF0" from "DDRF0" due to compatibility
315#define DDF0    0
316
317#define PORTF   _SFR_IO8(0x11)
318#define PORTF7  7
319#define PORTF6  6
320#define PORTF5  5
321#define PORTF4  4
322#define PORTF3  3
323#define PORTF2  2
324#define PORTF1  1
325#define PORTF0  0
326
327#define PING    _SFR_IO8(0x12)
328#define PING5   5
329#define PING4   4
330#define PING3   3
331#define PING2   2
332#define PING1   1
333#define PING0   0
334
335#define DDRG    _SFR_IO8(0x13)
336#define DDRG4   4
337// Inserted "DDG4" from "DDRG4" due to compatibility
338#define DDG4    4
339#define DDRG3   3
340// Inserted "DDG3" from "DDRG3" due to compatibility
341#define DDG3    3
342#define DDRG2   2
343// Inserted "DDG2" from "DDRG2" due to compatibility
344#define DDG2    2
345#define DDRG1   1
346// Inserted "DDG1" from "DDRG1" due to compatibility
347#define DDG1    1
348#define DDRG0   0
349// Inserted "DDG0" from "DDRG0" due to compatibility
350#define DDG0    0
351
352#define PORTG   _SFR_IO8(0x14)
353#define PORTG4  4
354#define PORTG3  3
355#define PORTG2  2
356#define PORTG1  1
357#define PORTG0  0
358
359#define TIFR0   _SFR_IO8(0x15)
360#define TOV0    0
361#define OCF0A   1
362
363#define TIFR1   _SFR_IO8(0x16)
364#define TOV1    0
365#define OCF1A   1
366#define OCF1B   2
367#define ICF1    5
368
369#define TIFR2   _SFR_IO8(0x17)
370#define TOV2    0
371#define OCF2A   1
372
373/* Reserved [0x18..0x1B] */
374
375#define EIFR    _SFR_IO8(0x1C)
376#define INTF0   0
377#define PCIF0   4
378#define PCIF1   5
379
380#define EIMSK   _SFR_IO8(0x1D)
381#define INT0    0
382#define PCIE0   4
383#define PCIE1   5
384
385#define GPIOR0  _SFR_IO8(0x1E)
386
387#define EECR    _SFR_IO8(0x1F)
388#define EERE    0
389#define EEWE    1
390#define EEMWE   2
391#define EERIE   3
392
393#define EEDR    _SFR_IO8(0x20)
394
395/* Combine EEARL and EEARH */
396#define EEAR    _SFR_IO16(0x21)
397
398#define EEARL   _SFR_IO8(0x21)
399#define EEARH   _SFR_IO8(0x22)
400
401#define GTCCR   _SFR_IO8(0x23)
402#define PSR310  0
403#define TSM     7
404#define PSR2    1
405
406#define TCCR0A  _SFR_IO8(0x24)
407#define CS00    0
408#define CS01    1
409#define CS02    2
410#define WGM01   3
411#define COM0A0  4
412#define COM0A1  5
413#define WGM00   6
414#define FOC0A   7
415
416/* Reserved [0x25] */
417
418#define TCNT0   _SFR_IO8(0x26)
419
420#define OCR0A   _SFR_IO8(0x27)
421
422/* Reserved [0x28..0x29] */
423
424#define GPIOR1  _SFR_IO8(0x2A)
425
426#define GPIOR2  _SFR_IO8(0x2B)
427
428#define SPCR    _SFR_IO8(0x2C)
429#define SPR0    0
430#define SPR1    1
431#define CPHA    2
432#define CPOL    3
433#define MSTR    4
434#define DORD    5
435#define SPE     6
436#define SPIE    7
437
438#define SPSR    _SFR_IO8(0x2D)
439#define SPI2X   0
440#define WCOL    6
441#define SPIF    7
442
443#define SPDR    _SFR_IO8(0x2E)
444
445/* Reserved [0x2F] */
446
447#define ACSR    _SFR_IO8(0x30)
448#define ACIS0   0
449#define ACIS1   1
450#define ACIC    2
451#define ACIE    3
452#define ACI     4
453#define ACO     5
454#define ACBG    6
455#define ACD     7
456
457#define OCDR    _SFR_IO8(0x31)
458#define OCDR7   7
459#define OCDR6   6
460#define OCDR5   5
461#define OCDR4   4
462#define OCDR3   3
463#define OCDR2   2
464#define OCDR1   1
465#define OCDR0   0
466
467/* Reserved [0x32] */
468
469#define SMCR    _SFR_IO8(0x33)
470#define SE      0
471#define SM0     1
472#define SM1     2
473#define SM2     3
474
475#define MCUSR   _SFR_IO8(0x34)
476#define JTRF    4
477#define PORF    0
478#define EXTRF   1
479#define BORF    2
480#define WDRF    3
481
482#define MCUCR   _SFR_IO8(0x35)
483#define JTD     7
484#define IVCE    0
485#define IVSEL   1
486#define PUD     4
487#define BODSE   5
488#define BODS    6
489
490/* Reserved [0x36] */
491
492#define SPMCSR  _SFR_IO8(0x37)
493#define SPMEN   0
494#define PGERS   1
495#define PGWRT   2
496#define BLBSET  3
497#define RWWSRE  4
498#define RWWSB   6
499#define SPMIE   7
500
501/* Reserved [0x38..0x3C] */
502
503/* SP [0x3D..0x3E] */
504
505/* SREG [0x3F] */
506
507#define WDTCR   _SFR_MEM8(0x60)
508#define WDP0    0
509#define WDP1    1
510#define WDP2    2
511#define WDE     3
512#define WDCE    4
513
514#define CLKPR   _SFR_MEM8(0x61)
515#define CLKPS0  0
516#define CLKPS1  1
517#define CLKPS2  2
518#define CLKPS3  3
519#define CLKPCE  7
520
521/* Reserved [0x62..0x63] */
522
523#define PRR     _SFR_MEM8(0x64)
524#define PRADC   0
525#define PRUSART0 1
526#define PRSPI   2
527#define PRTIM1  3
528
529#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1))
530#define __AVR_HAVE_PRR_PRADC
531#define __AVR_HAVE_PRR_PRUSART0
532#define __AVR_HAVE_PRR_PRSPI
533#define __AVR_HAVE_PRR_PRTIM1
534
535/* Reserved [0x65] */
536
537#define OSCCAL  _SFR_MEM8(0x66)
538#define OSCCAL0 0
539#define OSCCAL1 1
540#define OSCCAL2 2
541#define OSCCAL3 3
542#define OSCCAL4 4
543#define OSCCAL5 5
544#define OSCCAL6 6
545#define OSCCAL7 7
546
547/* Reserved [0x67..0x68] */
548
549#define EICRA   _SFR_MEM8(0x69)
550#define ISC00   0
551#define ISC01   1
552
553/* Reserved [0x6A] */
554
555#define PCMSK0  _SFR_MEM8(0x6B)
556#define PCINT0  0
557#define PCINT1  1
558#define PCINT2  2
559#define PCINT3  3
560#define PCINT4  4
561#define PCINT5  5
562#define PCINT6  6
563#define PCINT7  7
564
565#define PCMSK1  _SFR_MEM8(0x6C)
566#define PCINT8  0
567#define PCINT9  1
568#define PCINT10 2
569#define PCINT11 3
570#define PCINT12 4
571#define PCINT13 5
572#define PCINT14 6
573#define PCINT15 7
574
575/* Reserved [0x6D] */
576
577#define TIMSK0  _SFR_MEM8(0x6E)
578#define TOIE0   0
579#define OCIE0A  1
580
581#define TIMSK1  _SFR_MEM8(0x6F)
582#define TOIE1   0
583#define OCIE1A  1
584#define OCIE1B  2
585#define ICIE1   5
586
587#define TIMSK2  _SFR_MEM8(0x70)
588#define TOIE2   0
589#define OCIE2A  1
590
591/* Reserved [0x71..0x77] */
592
593/* Combine ADCL and ADCH */
594#ifndef __ASSEMBLER__
595#define ADC     _SFR_MEM16(0x78)
596#endif
597#define ADCW    _SFR_MEM16(0x78)
598
599#define ADCL    _SFR_MEM8(0x78)
600#define ADCH    _SFR_MEM8(0x79)
601
602#define ADCSRA  _SFR_MEM8(0x7A)
603#define ADPS0   0
604#define ADPS1   1
605#define ADPS2   2
606#define ADIE    3
607#define ADIF    4
608#define ADATE   5
609#define ADSC    6
610#define ADEN    7
611
612#define ADCSRB  _SFR_MEM8(0x7B)
613#define ACME    6
614#define ADTS0   0
615#define ADTS1   1
616#define ADTS2   2
617
618#define ADMUX   _SFR_MEM8(0x7C)
619#define MUX0    0
620#define MUX1    1
621#define MUX2    2
622#define MUX3    3
623#define MUX4    4
624#define ADLAR   5
625#define REFS0   6
626#define REFS1   7
627
628/* Reserved [0x7D] */
629
630#define DIDR0   _SFR_MEM8(0x7E)
631#define ADC0D   0
632#define ADC1D   1
633#define ADC2D   2
634#define ADC3D   3
635#define ADC4D   4
636#define ADC5D   5
637#define ADC6D   6
638#define ADC7D   7
639
640#define DIDR1   _SFR_MEM8(0x7F)
641#define AIN0D   0
642#define AIN1D   1
643
644#define TCCR1A  _SFR_MEM8(0x80)
645#define WGM10   0
646#define WGM11   1
647#define COM1B0  4
648#define COM1B1  5
649#define COM1A0  6
650#define COM1A1  7
651
652#define TCCR1B  _SFR_MEM8(0x81)
653#define CS10    0
654#define CS11    1
655#define CS12    2
656#define WGM12   3
657#define WGM13   4
658#define ICES1   6
659#define ICNC1   7
660
661#define TCCR1C  _SFR_MEM8(0x82)
662#define FOC1B   6
663#define FOC1A   7
664
665/* Reserved [0x83] */
666
667/* Combine TCNT1L and TCNT1H */
668#define TCNT1   _SFR_MEM16(0x84)
669
670#define TCNT1L  _SFR_MEM8(0x84)
671#define TCNT1H  _SFR_MEM8(0x85)
672
673/* Combine ICR1L and ICR1H */
674#define ICR1    _SFR_MEM16(0x86)
675
676#define ICR1L   _SFR_MEM8(0x86)
677#define ICR1H   _SFR_MEM8(0x87)
678
679/* Combine OCR1AL and OCR1AH */
680#define OCR1A   _SFR_MEM16(0x88)
681
682#define OCR1AL  _SFR_MEM8(0x88)
683#define OCR1AH  _SFR_MEM8(0x89)
684
685/* Combine OCR1BL and OCR1BH */
686#define OCR1B   _SFR_MEM16(0x8A)
687
688#define OCR1BL  _SFR_MEM8(0x8A)
689#define OCR1BH  _SFR_MEM8(0x8B)
690
691/* Reserved [0x8C..0xAF] */
692
693#define TCCR2A  _SFR_MEM8(0xB0)
694#define CS20    0
695#define CS21    1
696#define CS22    2
697#define WGM21   3
698#define COM2A0  4
699#define COM2A1  5
700#define WGM20   6
701#define FOC2A   7
702
703/* Reserved [0xB1] */
704
705#define TCNT2   _SFR_MEM8(0xB2)
706
707#define OCR2A   _SFR_MEM8(0xB3)
708
709/* Reserved [0xB4..0xB5] */
710
711#define ASSR    _SFR_MEM8(0xB6)
712#define TCR2UB  0
713#define OCR2UB  1
714#define TCN2UB  2
715#define AS2     3
716#define EXCLK   4
717
718/* Reserved [0xB7] */
719
720#define USICR   _SFR_MEM8(0xB8)
721#define USITC   0
722#define USICLK  1
723#define USICS0  2
724#define USICS1  3
725#define USIWM0  4
726#define USIWM1  5
727#define USIOIE  6
728#define USISIE  7
729
730#define USISR   _SFR_MEM8(0xB9)
731#define USICNT0 0
732#define USICNT1 1
733#define USICNT2 2
734#define USICNT3 3
735#define USIDC   4
736#define USIPF   5
737#define USIOIF  6
738#define USISIF  7
739
740#define USIDR   _SFR_MEM8(0xBA)
741
742/* Reserved [0xBB..0xBF] */
743
744#define UCSR0A  _SFR_MEM8(0xC0)
745#define MPCM0   0
746#define U2X0    1
747#define UPE0    2
748#define DOR0    3
749#define FE0     4
750#define UDRE0   5
751#define TXC0    6
752#define RXC0    7
753
754#define UCSR0B  _SFR_MEM8(0xC1)
755#define TXB80   0
756#define RXB80   1
757#define UCSZ02  2
758#define TXEN0   3
759#define RXEN0   4
760#define UDRIE0  5
761#define TXCIE0  6
762#define RXCIE0  7
763
764#define UCSR0C  _SFR_MEM8(0xC2)
765#define UCPOL0  0
766#define UCSZ00  1
767#define UCSZ01  2
768#define USBS0   3
769#define UPM00   4
770#define UPM01   5
771#define UMSEL0  6
772
773/* Reserved [0xC3] */
774
775/* Combine UBRR0L and UBRR0H */
776#define UBRR0   _SFR_MEM16(0xC4)
777
778#define UBRR0L  _SFR_MEM8(0xC4)
779#define UBRR0H  _SFR_MEM8(0xC5)
780
781#define UDR0    _SFR_MEM8(0xC6)
782
783
784
785/* Values and associated defines */
786
787
788#define SLEEP_MODE_IDLE (0x00<<1)
789#define SLEEP_MODE_ADC (0x01<<1)
790#define SLEEP_MODE_PWR_DOWN (0x02<<1)
791#define SLEEP_MODE_PWR_SAVE (0x03<<1)
792#define SLEEP_MODE_STANDBY (0x06<<1)
793
794/* Interrupt vectors */
795/* Vector 0 is the reset vector */
796/* External Interrupt Request 0 */
797#define INT0_vect            _VECTOR(1)
798#define INT0_vect_num        1
799
800/* Pin Change Interrupt Request 0 */
801#define PCINT0_vect            _VECTOR(2)
802#define PCINT0_vect_num        2
803
804/* Pin Change Interrupt Request 1 */
805#define PCINT1_vect            _VECTOR(3)
806#define PCINT1_vect_num        3
807
808/* Timer/Counter2 Compare Match */
809#define TIMER2_COMP_vect            _VECTOR(4)
810#define TIMER2_COMP_vect_num        4
811
812/* Timer/Counter2 Overflow */
813#define TIMER2_OVF_vect            _VECTOR(5)
814#define TIMER2_OVF_vect_num        5
815
816/* Timer/Counter1 Capture Event */
817#define TIMER1_CAPT_vect            _VECTOR(6)
818#define TIMER1_CAPT_vect_num        6
819
820/* Timer/Counter1 Compare Match A */
821#define TIMER1_COMPA_vect            _VECTOR(7)
822#define TIMER1_COMPA_vect_num        7
823
824/* Timer/Counter Compare Match B */
825#define TIMER1_COMPB_vect            _VECTOR(8)
826#define TIMER1_COMPB_vect_num        8
827
828/* Timer/Counter1 Overflow */
829#define TIMER1_OVF_vect            _VECTOR(9)
830#define TIMER1_OVF_vect_num        9
831
832/* Timer/Counter0 Compare Match */
833#define TIMER0_COMP_vect            _VECTOR(10)
834#define TIMER0_COMP_vect_num        10
835
836/* Timer/Counter0 Overflow */
837#define TIMER0_OVF_vect            _VECTOR(11)
838#define TIMER0_OVF_vect_num        11
839
840/* SPI Serial Transfer Complete */
841#define SPI_STC_vect            _VECTOR(12)
842#define SPI_STC_vect_num        12
843
844/* USART0, Rx Complete */
845#define USART0_RX_vect            _VECTOR(13)
846#define USART0_RX_vect_num        13
847
848/* USART0 Data register Empty */
849#define USART0_UDRE_vect            _VECTOR(14)
850#define USART0_UDRE_vect_num        14
851
852/* USART0, Tx Complete */
853#define USART0_TX_vect            _VECTOR(15)
854#define USART0_TX_vect_num        15
855
856/* USI Start Condition */
857#define USI_START_vect            _VECTOR(16)
858#define USI_START_vect_num        16
859
860/* USI Overflow */
861#define USI_OVERFLOW_vect            _VECTOR(17)
862#define USI_OVERFLOW_vect_num        17
863
864/* Analog Comparator */
865#define ANALOG_COMP_vect            _VECTOR(18)
866#define ANALOG_COMP_vect_num        18
867
868/* ADC Conversion Complete */
869#define ADC_vect            _VECTOR(19)
870#define ADC_vect_num        19
871
872/* EEPROM Ready */
873#define EE_READY_vect            _VECTOR(20)
874#define EE_READY_vect_num        20
875
876/* Store Program Memory Read */
877#define SPM_READY_vect            _VECTOR(21)
878#define SPM_READY_vect_num        21
879
880#define _VECTORS_SIZE 88
881
882
883/* Constants */
884
885#define SPM_PAGESIZE 128
886#define FLASHSTART   0x0000
887#define FLASHEND     0x3FFF
888#define RAMSTART     0x0100
889#define RAMSIZE      1024
890#define RAMEND       0x04FF
891#define E2START     0
892#define E2SIZE      512
893#define E2PAGESIZE  4
894#define E2END       0x01FF
895#define XRAMEND      RAMEND
896
897
898/* Fuses */
899
900#define FUSE_MEMORY_SIZE 3
901
902/* Low Fuse Byte */
903#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
904#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
905#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
906#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
907#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
908#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
909#define FUSE_CKOUT       (unsigned char)~_BV(6)
910#define FUSE_CKDIV8      (unsigned char)~_BV(7)
911#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
912
913
914/* High Fuse Byte */
915#define FUSE_BOOTRST     (unsigned char)~_BV(0)
916#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
917#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
918#define FUSE_EESAVE      (unsigned char)~_BV(3)
919#define FUSE_WDTON       (unsigned char)~_BV(4)
920#define FUSE_SPIEN       (unsigned char)~_BV(5)
921#define FUSE_JTAGEN      (unsigned char)~_BV(6)
922#define FUSE_OCDEN       (unsigned char)~_BV(7)
923#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
924
925
926/* Extended Fuse Byte */
927#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
928#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
929#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
930#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
931#define EFUSE_DEFAULT    (0xFF)
932
933
934
935/* Lock Bits */
936#define __LOCK_BITS_EXIST
937#define __BOOT_LOCK_BITS_0_EXIST
938#define __BOOT_LOCK_BITS_1_EXIST
939
940
941/* Signature */
942#define SIGNATURE_0 0x1E
943#define SIGNATURE_1 0x94
944#define SIGNATURE_2 0x07
945
946
947#endif /* #ifdef _AVR_ATMEGA165PA_H_INCLUDED */
948
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