source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom168p.h @ 4837

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1/* Copyright (c) 2007 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE.
30*/
31
32/* $Id: iom168p.h 2225 2011-03-02 16:27:26Z arcanum $ */
33
34/* avr/iom168p.h - definitions for ATmega168P. */
35
36/* This file should only be included from <avr/io.h>, never directly. */
37
38#ifndef _AVR_IO_H_
39#  error "Include <avr/io.h> instead of this file."
40#endif
41
42#ifndef _AVR_IOXXX_H_
43#  define _AVR_IOXXX_H_ "iom168p.h"
44#else
45#  error "Attempt to include more than one <avr/ioXXX.h> file."
46#endif
47
48
49#ifndef _AVR_IOM168P_H_
50#define _AVR_IOM168P_H_ 1
51
52/* Registers and associated bit numbers */
53
54#define PINB _SFR_IO8(0x03)
55#define PINB0 0
56#define PINB1 1
57#define PINB2 2
58#define PINB3 3
59#define PINB4 4
60#define PINB5 5
61#define PINB6 6
62#define PINB7 7
63
64#define DDRB _SFR_IO8(0x04)
65#define DDB0 0
66#define DDB1 1
67#define DDB2 2
68#define DDB3 3
69#define DDB4 4
70#define DDB5 5
71#define DDB6 6
72#define DDB7 7
73
74#define PORTB _SFR_IO8(0x05)
75#define PORTB0 0
76#define PORTB1 1
77#define PORTB2 2
78#define PORTB3 3
79#define PORTB4 4
80#define PORTB5 5
81#define PORTB6 6
82#define PORTB7 7
83
84#define PINC _SFR_IO8(0x06)
85#define PINC0 0
86#define PINC1 1
87#define PINC2 2
88#define PINC3 3
89#define PINC4 4
90#define PINC5 5
91#define PINC6 6
92
93#define DDRC _SFR_IO8(0x07)
94#define DDC0 0
95#define DDC1 1
96#define DDC2 2
97#define DDC3 3
98#define DDC4 4
99#define DDC5 5
100#define DDC6 6
101
102#define PORTC _SFR_IO8(0x08)
103#define PORTC0 0
104#define PORTC1 1
105#define PORTC2 2
106#define PORTC3 3
107#define PORTC4 4
108#define PORTC5 5
109#define PORTC6 6
110
111#define PIND _SFR_IO8(0x09)
112#define PIND0 0
113#define PIND1 1
114#define PIND2 2
115#define PIND3 3
116#define PIND4 4
117#define PIND5 5
118#define PIND6 6
119#define PIND7 7
120
121#define DDRD _SFR_IO8(0x0A)
122#define DDD0 0
123#define DDD1 1
124#define DDD2 2
125#define DDD3 3
126#define DDD4 4
127#define DDD5 5
128#define DDD6 6
129#define DDD7 7
130
131#define PORTD _SFR_IO8(0x0B)
132#define PORTD0 0
133#define PORTD1 1
134#define PORTD2 2
135#define PORTD3 3
136#define PORTD4 4
137#define PORTD5 5
138#define PORTD6 6
139#define PORTD7 7
140
141#define TIFR0 _SFR_IO8(0x15)
142#define TOV0 0
143#define OCF0A 1
144#define OCF0B 2
145
146#define TIFR1 _SFR_IO8(0x16)
147#define TOV1 0
148#define OCF1A 1
149#define OCF1B 2
150#define ICF1 5
151
152#define TIFR2 _SFR_IO8(0x17)
153#define TOV2 0
154#define OCF2A 1
155#define OCF2B 2
156
157#define PCIFR _SFR_IO8(0x1B)
158#define PCIF0 0
159#define PCIF1 1
160#define PCIF2 2
161
162#define EIFR _SFR_IO8(0x1C)
163#define INTF0 0
164#define INTF1 1
165
166#define EIMSK _SFR_IO8(0x1D)
167#define INT0 0
168#define INT1 1
169
170#define GPIOR0 _SFR_IO8(0x1E)
171#define GPIOR00 0
172#define GPIOR01 1
173#define GPIOR02 2
174#define GPIOR03 3
175#define GPIOR04 4
176#define GPIOR05 5
177#define GPIOR06 6
178#define GPIOR07 7
179
180#define EECR _SFR_IO8(0x1F)
181#define EERE 0
182#define EEPE 1
183#define EEMPE 2
184#define EERIE 3
185#define EEPM0 4
186#define EEPM1 5
187
188#define EEDR _SFR_IO8(0x20)
189#define EEDR0 0
190#define EEDR1 1
191#define EEDR2 2
192#define EEDR3 3
193#define EEDR4 4
194#define EEDR5 5
195#define EEDR6 6
196#define EEDR7 7
197
198#define EEAR _SFR_IO16(0x21)
199
200#define EEARL _SFR_IO8(0x21)
201#define EEAR0 0
202#define EEAR1 1
203#define EEAR2 2
204#define EEAR3 3
205#define EEAR4 4
206#define EEAR5 5
207#define EEAR6 6
208#define EEAR7 7
209
210#define EEARH _SFR_IO8(0x22)
211#define EEAR8 0
212
213#define EEPROM_REG_LOCATIONS 1F2021
214
215#define GTCCR _SFR_IO8(0x23)
216#define PSRSYNC 0
217#define PSRASY 1
218#define TSM 7
219
220#define TCCR0A _SFR_IO8(0x24)
221#define WGM00 0
222#define WGM01 1
223#define COM0B0 4
224#define COM0B1 5
225#define COM0A0 6
226#define COM0A1 7
227
228#define TCCR0B _SFR_IO8(0x25)
229#define CS00 0
230#define CS01 1
231#define CS02 2
232#define WGM02 3
233#define FOC0B 6
234#define FOC0A 7
235
236#define TCNT0 _SFR_IO8(0x26)
237#define TCNT0_0 0
238#define TCNT0_1 1
239#define TCNT0_2 2
240#define TCNT0_3 3
241#define TCNT0_4 4
242#define TCNT0_5 5
243#define TCNT0_6 6
244#define TCNT0_7 7
245
246#define OCR0A _SFR_IO8(0x27)
247#define OCR0A_0 0
248#define OCR0A_1 1
249#define OCR0A_2 2
250#define OCR0A_3 3
251#define OCR0A_4 4
252#define OCR0A_5 5
253#define OCR0A_6 6
254#define OCR0A_7 7
255
256#define OCR0B _SFR_IO8(0x28)
257#define OCR0B_0 0
258#define OCR0B_1 1
259#define OCR0B_2 2
260#define OCR0B_3 3
261#define OCR0B_4 4
262#define OCR0B_5 5
263#define OCR0B_6 6
264#define OCR0B_7 7
265
266#define GPIOR1 _SFR_IO8(0x2A)
267#define GPIOR10 0
268#define GPIOR11 1
269#define GPIOR12 2
270#define GPIOR13 3
271#define GPIOR14 4
272#define GPIOR15 5
273#define GPIOR16 6
274#define GPIOR17 7
275
276#define GPIOR2 _SFR_IO8(0x2B)
277#define GPIOR20 0
278#define GPIOR21 1
279#define GPIOR22 2
280#define GPIOR23 3
281#define GPIOR24 4
282#define GPIOR25 5
283#define GPIOR26 6
284#define GPIOR27 7
285
286#define SPCR _SFR_IO8(0x2C)
287#define SPR0 0
288#define SPR1 1
289#define CPHA 2
290#define CPOL 3
291#define MSTR 4
292#define DORD 5
293#define SPE 6
294#define SPIE 7
295
296#define SPSR _SFR_IO8(0x2D)
297#define SPI2X 0
298#define WCOL 6
299#define SPIF 7
300
301#define SPDR _SFR_IO8(0x2E)
302#define SPDR0 0
303#define SPDR1 1
304#define SPDR2 2
305#define SPDR3 3
306#define SPDR4 4
307#define SPDR5 5
308#define SPDR6 6
309#define SPDR7 7
310
311#define ACSR _SFR_IO8(0x30)
312#define ACIS0 0
313#define ACIS1 1
314#define ACIC 2
315#define ACIE 3
316#define ACI 4
317#define ACO 5
318#define ACBG 6
319#define ACD 7
320
321#define SMCR _SFR_IO8(0x33)
322#define SE 0
323#define SM0 1
324#define SM1 2
325#define SM2 3
326
327#define MCUSR _SFR_IO8(0x34)
328#define PORF 0
329#define EXTRF 1
330#define BORF 2
331#define WDRF 3
332
333#define MCUCR _SFR_IO8(0x35)
334#define IVCE 0
335#define IVSEL 1
336#define PUD 4
337#define BODSE 5
338#define BODS 6
339
340#define SPMCSR _SFR_IO8(0x37)
341#define SELFPRGEN 0
342#define SPMEN 0
343#define PGERS 1
344#define PGWRT 2
345#define BLBSET 3
346#define RWWSRE 4
347#define SIGRD 5
348#define RWWSB 6
349#define SPMIE 7
350
351#define WDTCSR _SFR_MEM8(0x60)
352#define WDP0 0
353#define WDP1 1
354#define WDP2 2
355#define WDE 3
356#define WDCE 4
357#define WDP3 5
358#define WDIE 6
359#define WDIF 7
360
361#define CLKPR _SFR_MEM8(0x61)
362#define CLKPS0 0
363#define CLKPS1 1
364#define CLKPS2 2
365#define CLKPS3 3
366#define CLKPCE 7
367
368#define PRR _SFR_MEM8(0x64)
369#define PRADC 0
370#define PRUSART0 1
371#define PRSPI 2
372#define PRTIM1 3
373#define PRTIM0 5
374#define PRTIM2 6
375#define PRTWI 7
376
377#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
378#define __AVR_HAVE_PRR_PRADC
379#define __AVR_HAVE_PRR_PRUSART0
380#define __AVR_HAVE_PRR_PRSPI
381#define __AVR_HAVE_PRR_PRTIM1
382#define __AVR_HAVE_PRR_PRTIM0
383#define __AVR_HAVE_PRR_PRTIM2
384#define __AVR_HAVE_PRR_PRTWI
385
386#define OSCCAL _SFR_MEM8(0x66)
387#define CAL0 0
388#define CAL1 1
389#define CAL2 2
390#define CAL3 3
391#define CAL4 4
392#define CAL5 5
393#define CAL6 6
394#define CAL7 7
395
396#define PCICR _SFR_MEM8(0x68)
397#define PCIE0 0
398#define PCIE1 1
399#define PCIE2 2
400
401#define EICRA _SFR_MEM8(0x69)
402#define ISC00 0
403#define ISC01 1
404#define ISC10 2
405#define ISC11 3
406
407#define PCMSK0 _SFR_MEM8(0x6B)
408#define PCINT0 0
409#define PCINT1 1
410#define PCINT2 2
411#define PCINT3 3
412#define PCINT4 4
413#define PCINT5 5
414#define PCINT6 6
415#define PCINT7 7
416
417#define PCMSK1 _SFR_MEM8(0x6C)
418#define PCINT8 0
419#define PCINT9 1
420#define PCINT10 2
421#define PCINT11 3
422#define PCINT12 4
423#define PCINT13 5
424#define PCINT14 6
425
426#define PCMSK2 _SFR_MEM8(0x6D)
427#define PCINT16 0
428#define PCINT17 1
429#define PCINT18 2
430#define PCINT19 3
431#define PCINT20 4
432#define PCINT21 5
433#define PCINT22 6
434#define PCINT23 7
435
436#define TIMSK0 _SFR_MEM8(0x6E)
437#define TOIE0 0
438#define OCIE0A 1
439#define OCIE0B 2
440
441#define TIMSK1 _SFR_MEM8(0x6F)
442#define TOIE1 0
443#define OCIE1A 1
444#define OCIE1B 2
445#define ICIE1 5
446
447#define TIMSK2 _SFR_MEM8(0x70)
448#define TOIE2 0
449#define OCIE2A 1
450#define OCIE2B 2
451
452#ifndef __ASSEMBLER__
453#define ADC     _SFR_MEM16(0x78)
454#endif
455#define ADCW    _SFR_MEM16(0x78)
456
457#define ADCL _SFR_MEM8(0x78)
458#define ADCL0 0
459#define ADCL1 1
460#define ADCL2 2
461#define ADCL3 3
462#define ADCL4 4
463#define ADCL5 5
464#define ADCL6 6
465#define ADCL7 7
466
467#define ADCH _SFR_MEM8(0x79)
468#define ADCH0 0
469#define ADCH1 1
470#define ADCH2 2
471#define ADCH3 3
472#define ADCH4 4
473#define ADCH5 5
474#define ADCH6 6
475#define ADCH7 7
476
477#define ADCSRA _SFR_MEM8(0x7A)
478#define ADPS0 0
479#define ADPS1 1
480#define ADPS2 2
481#define ADIE 3
482#define ADIF 4
483#define ADATE 5
484#define ADSC 6
485#define ADEN 7
486
487#define ADCSRB _SFR_MEM8(0x7B)
488#define ADTS0 0
489#define ADTS1 1
490#define ADTS2 2
491#define ACME 6
492
493#define ADMUX _SFR_MEM8(0x7C)
494#define MUX0 0
495#define MUX1 1
496#define MUX2 2
497#define MUX3 3
498#define ADLAR 5
499#define REFS0 6
500#define REFS1 7
501
502#define DIDR0 _SFR_MEM8(0x7E)
503#define ADC0D 0
504#define ADC1D 1
505#define ADC2D 2
506#define ADC3D 3
507#define ADC4D 4
508#define ADC5D 5
509
510#define DIDR1 _SFR_MEM8(0x7F)
511#define AIN0D 0
512#define AIN1D 1
513
514#define TCCR1A _SFR_MEM8(0x80)
515#define WGM10 0
516#define WGM11 1
517#define COM1B0 4
518#define COM1B1 5
519#define COM1A0 6
520#define COM1A1 7
521
522#define TCCR1B _SFR_MEM8(0x81)
523#define CS10 0
524#define CS11 1
525#define CS12 2
526#define WGM12 3
527#define WGM13 4
528#define ICES1 6
529#define ICNC1 7
530
531#define TCCR1C _SFR_MEM8(0x82)
532#define FOC1B 6
533#define FOC1A 7
534
535#define TCNT1 _SFR_MEM16(0x84)
536
537#define TCNT1L _SFR_MEM8(0x84)
538#define TCNT1L0 0
539#define TCNT1L1 1
540#define TCNT1L2 2
541#define TCNT1L3 3
542#define TCNT1L4 4
543#define TCNT1L5 5
544#define TCNT1L6 6
545#define TCNT1L7 7
546
547#define TCNT1H _SFR_MEM8(0x85)
548#define TCNT1H0 0
549#define TCNT1H1 1
550#define TCNT1H2 2
551#define TCNT1H3 3
552#define TCNT1H4 4
553#define TCNT1H5 5
554#define TCNT1H6 6
555#define TCNT1H7 7
556
557#define ICR1 _SFR_MEM16(0x86)
558
559#define ICR1L _SFR_MEM8(0x86)
560#define ICR1L0 0
561#define ICR1L1 1
562#define ICR1L2 2
563#define ICR1L3 3
564#define ICR1L4 4
565#define ICR1L5 5
566#define ICR1L6 6
567#define ICR1L7 7
568
569#define ICR1H _SFR_MEM8(0x87)
570#define ICR1H0 0
571#define ICR1H1 1
572#define ICR1H2 2
573#define ICR1H3 3
574#define ICR1H4 4
575#define ICR1H5 5
576#define ICR1H6 6
577#define ICR1H7 7
578
579#define OCR1A _SFR_MEM16(0x88)
580
581#define OCR1AL _SFR_MEM8(0x88)
582#define OCR1AL0 0
583#define OCR1AL1 1
584#define OCR1AL2 2
585#define OCR1AL3 3
586#define OCR1AL4 4
587#define OCR1AL5 5
588#define OCR1AL6 6
589#define OCR1AL7 7
590
591#define OCR1AH _SFR_MEM8(0x89)
592#define OCR1AH0 0
593#define OCR1AH1 1
594#define OCR1AH2 2
595#define OCR1AH3 3
596#define OCR1AH4 4
597#define OCR1AH5 5
598#define OCR1AH6 6
599#define OCR1AH7 7
600
601#define OCR1B _SFR_MEM16(0x8A)
602
603#define OCR1BL _SFR_MEM8(0x8A)
604#define OCR1BL0 0
605#define OCR1BL1 1
606#define OCR1BL2 2
607#define OCR1BL3 3
608#define OCR1BL4 4
609#define OCR1BL5 5
610#define OCR1BL6 6
611#define OCR1BL7 7
612
613#define OCR1BH _SFR_MEM8(0x8B)
614#define OCR1BH0 0
615#define OCR1BH1 1
616#define OCR1BH2 2
617#define OCR1BH3 3
618#define OCR1BH4 4
619#define OCR1BH5 5
620#define OCR1BH6 6
621#define OCR1BH7 7
622
623#define TCCR2A _SFR_MEM8(0xB0)
624#define WGM20 0
625#define WGM21 1
626#define COM2B0 4
627#define COM2B1 5
628#define COM2A0 6
629#define COM2A1 7
630
631#define TCCR2B _SFR_MEM8(0xB1)
632#define CS20 0
633#define CS21 1
634#define CS22 2
635#define WGM22 3
636#define FOC2B 6
637#define FOC2A 7
638
639#define TCNT2 _SFR_MEM8(0xB2)
640#define TCNT2_0 0
641#define TCNT2_1 1
642#define TCNT2_2 2
643#define TCNT2_3 3
644#define TCNT2_4 4
645#define TCNT2_5 5
646#define TCNT2_6 6
647#define TCNT2_7 7
648
649#define OCR2A _SFR_MEM8(0xB3)
650#define OCR2_0 0
651#define OCR2_1 1
652#define OCR2_2 2
653#define OCR2_3 3
654#define OCR2_4 4
655#define OCR2_5 5
656#define OCR2_6 6
657#define OCR2_7 7
658
659#define OCR2B _SFR_MEM8(0xB4)
660#define OCR2_0 0
661#define OCR2_1 1
662#define OCR2_2 2
663#define OCR2_3 3
664#define OCR2_4 4
665#define OCR2_5 5
666#define OCR2_6 6
667#define OCR2_7 7
668
669#define ASSR _SFR_MEM8(0xB6)
670#define TCR2BUB 0
671#define TCR2AUB 1
672#define OCR2BUB 2
673#define OCR2AUB 3
674#define TCN2UB 4
675#define AS2 5
676#define EXCLK 6
677
678#define TWBR _SFR_MEM8(0xB8)
679#define TWBR0 0
680#define TWBR1 1
681#define TWBR2 2
682#define TWBR3 3
683#define TWBR4 4
684#define TWBR5 5
685#define TWBR6 6
686#define TWBR7 7
687
688#define TWSR _SFR_MEM8(0xB9)
689#define TWPS0 0
690#define TWPS1 1
691#define TWS3 3
692#define TWS4 4
693#define TWS5 5
694#define TWS6 6
695#define TWS7 7
696
697#define TWAR _SFR_MEM8(0xBA)
698#define TWGCE 0
699#define TWA0 1
700#define TWA1 2
701#define TWA2 3
702#define TWA3 4
703#define TWA4 5
704#define TWA5 6
705#define TWA6 7
706
707#define TWDR _SFR_MEM8(0xBB)
708#define TWD0 0
709#define TWD1 1
710#define TWD2 2
711#define TWD3 3
712#define TWD4 4
713#define TWD5 5
714#define TWD6 6
715#define TWD7 7
716
717#define TWCR _SFR_MEM8(0xBC)
718#define TWIE 0
719#define TWEN 2
720#define TWWC 3
721#define TWSTO 4
722#define TWSTA 5
723#define TWEA 6
724#define TWINT 7
725
726#define TWAMR _SFR_MEM8(0xBD)
727#define TWAM0 0
728#define TWAM1 1
729#define TWAM2 2
730#define TWAM3 3
731#define TWAM4 4
732#define TWAM5 5
733#define TWAM6 6
734
735#define UCSR0A _SFR_MEM8(0xC0)
736#define MPCM0 0
737#define U2X0 1
738#define UPE0 2
739#define DOR0 3
740#define FE0 4
741#define UDRE0 5
742#define TXC0 6
743#define RXC0 7
744
745#define UCSR0B _SFR_MEM8(0xC1)
746#define TXB80 0
747#define RXB80 1
748#define UCSZ02 2
749#define TXEN0 3
750#define RXEN0 4
751#define UDRIE0 5
752#define TXCIE0 6
753#define RXCIE0 7
754
755#define UCSR0C _SFR_MEM8(0xC2)
756#define UCPOL0 0
757#define UCSZ00 1
758#define UCPHA0 1
759#define UCSZ01 2
760#define UDORD0 2
761#define USBS0 3
762#define UPM00 4
763#define UPM01 5
764#define UMSEL00 6
765#define UMSEL01 7
766
767#define UBRR0 _SFR_MEM16(0xC4)
768
769#define UBRR0L _SFR_MEM8(0xC4)
770#define UBRR0_0 0
771#define UBRR0_1 1
772#define UBRR0_2 2
773#define UBRR0_3 3
774#define UBRR0_4 4
775#define UBRR0_5 5
776#define UBRR0_6 6
777#define UBRR0_7 7
778
779#define UBRR0H _SFR_MEM8(0xC5)
780#define UBRR0_8 0
781#define UBRR0_9 1
782#define UBRR0_10 2
783#define UBRR0_11 3
784
785#define UDR0 _SFR_MEM8(0xC6)
786#define UDR0_0 0
787#define UDR0_1 1
788#define UDR0_2 2
789#define UDR0_3 3
790#define UDR0_4 4
791#define UDR0_5 5
792#define UDR0_6 6
793#define UDR0_7 7
794
795
796
797/* Interrupt Vectors */
798/* Interrupt Vector 0 is the reset vector. */
799
800#define INT0_vect_num     1
801#define INT0_vect         _VECTOR(1)   /* External Interrupt Request 0 */
802
803#define INT1_vect_num     2
804#define INT1_vect         _VECTOR(2)   /* External Interrupt Request 1 */
805
806#define PCINT0_vect_num   3
807#define PCINT0_vect       _VECTOR(3)   /* Pin Change Interrupt Request 0 */
808
809#define PCINT1_vect_num   4
810#define PCINT1_vect       _VECTOR(4)   /* Pin Change Interrupt Request 0 */
811
812#define PCINT2_vect_num   5
813#define PCINT2_vect       _VECTOR(5)   /* Pin Change Interrupt Request 1 */
814
815#define WDT_vect_num      6
816#define WDT_vect          _VECTOR(6)   /* Watchdog Time-out Interrupt */
817
818#define TIMER2_COMPA_vect_num 7
819#define TIMER2_COMPA_vect _VECTOR(7)   /* Timer/Counter2 Compare Match A */
820
821#define TIMER2_COMPB_vect_num 8
822#define TIMER2_COMPB_vect _VECTOR(8)   /* Timer/Counter2 Compare Match A */
823
824#define TIMER2_OVF_vect_num   9
825#define TIMER2_OVF_vect   _VECTOR(9)   /* Timer/Counter2 Overflow */
826
827#define TIMER1_CAPT_vect_num  10
828#define TIMER1_CAPT_vect  _VECTOR(10)  /* Timer/Counter1 Capture Event */
829
830#define TIMER1_COMPA_vect_num 11
831#define TIMER1_COMPA_vect _VECTOR(11)  /* Timer/Counter1 Compare Match A */
832
833#define TIMER1_COMPB_vect_num 12
834#define TIMER1_COMPB_vect _VECTOR(12)  /* Timer/Counter1 Compare Match B */ 
835
836#define TIMER1_OVF_vect_num   13
837#define TIMER1_OVF_vect   _VECTOR(13)  /* Timer/Counter1 Overflow */
838
839#define TIMER0_COMPA_vect_num 14
840#define TIMER0_COMPA_vect _VECTOR(14)  /* TimerCounter0 Compare Match A */
841
842#define TIMER0_COMPB_vect_num 15
843#define TIMER0_COMPB_vect _VECTOR(15)  /* TimerCounter0 Compare Match B */
844
845#define TIMER0_OVF_vect_num   16
846#define TIMER0_OVF_vect   _VECTOR(16)  /* Timer/Couner0 Overflow */
847
848#define SPI_STC_vect_num  17
849#define SPI_STC_vect      _VECTOR(17)  /* SPI Serial Transfer Complete */
850
851#define USART_RX_vect_num 18
852#define USART_RX_vect     _VECTOR(18)  /* USART Rx Complete */
853
854#define USART_UDRE_vect_num   19
855#define USART_UDRE_vect   _VECTOR(19)  /* USART, Data Register Empty */
856
857#define USART_TX_vect_num 20
858#define USART_TX_vect     _VECTOR(20)  /* USART Tx Complete */
859
860#define ADC_vect_num      21
861#define ADC_vect          _VECTOR(21)  /* ADC Conversion Complete */
862
863#define EE_READY_vect_num 22
864#define EE_READY_vect     _VECTOR(22)  /* EEPROM Ready */
865
866#define ANALOG_COMP_vect_num  23
867#define ANALOG_COMP_vect  _VECTOR(23)  /* Analog Comparator */
868
869#define TWI_vect_num      24
870#define TWI_vect          _VECTOR(24)  /* Two-wire Serial Interface */
871
872#define SPM_READY_vect_num  25
873#define SPM_READY_vect    _VECTOR(25)  /* Store Program Memory Read */
874
875#define _VECTORS_SIZE (26 * 4)
876
877
878
879/* Constants */
880#define SPM_PAGESIZE 128
881#define RAMSTART     (0x100)
882#define RAMEND       0x4FF     /* Last On-Chip SRAM Location */
883#define XRAMSIZE     0
884#define XRAMEND      RAMEND
885#define E2END        0x1FF
886#define E2PAGESIZE   4
887#define FLASHEND     0x3FFF
888
889
890
891/* Fuses */
892#define FUSE_MEMORY_SIZE 3
893
894/* Low Fuse Byte */
895#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
896#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
897#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
898#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
899#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
900#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
901#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
902#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
903#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
904
905/* High Fuse Byte */
906#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
907#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
908#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
909#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
910#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog Timer Always On */
911#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
912#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
913#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External reset disable */
914#define HFUSE_DEFAULT (FUSE_SPIEN)
915
916/* Extended Fuse Byte */
917#define FUSE_BOOTRST (unsigned char)~_BV(0)
918#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
919#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
920#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
921
922
923
924/* Lock Bits */
925#define __LOCK_BITS_EXIST
926#define __BOOT_LOCK_BITS_0_EXIST
927#define __BOOT_LOCK_BITS_1_EXIST
928
929
930/* Signature */
931#define SIGNATURE_0 0x1E
932#define SIGNATURE_1 0x94
933#define SIGNATURE_2 0x0B
934
935#define SLEEP_MODE_IDLE (0x00<<1)
936#define SLEEP_MODE_ADC (0x01<<1)
937#define SLEEP_MODE_PWR_DOWN (0x02<<1)
938#define SLEEP_MODE_PWR_SAVE (0x03<<1)
939#define SLEEP_MODE_STANDBY (0x06<<1)
940#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
941
942#endif  /* _AVR_IOM168P_H_ */
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