source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom169pa.h @ 4837

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1/* Copyright (c) 2009 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iom169pa.h 2192 2010-11-08 13:53:24Z arcanum $ */
32
33/* avr/iom169pa.h - definitions for ATmega169PA */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iom169pa.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_ATmega169PA_H_
49#define _AVR_ATmega169PA_H_ 1
50
51
52/* Registers and associated bit numbers. */
53
54#define PINA _SFR_IO8(0x00)
55#define PINA0 0
56#define PINA1 1
57#define PINA2 2
58#define PINA3 3
59#define PINA4 4
60#define PINA5 5
61#define PINA6 6
62#define PINA7 7
63
64#define DDRA _SFR_IO8(0x01)
65#define DDA0 0
66#define DDA1 1
67#define DDA2 2
68#define DDA3 3
69#define DDA4 4
70#define DDA5 5
71#define DDA6 6
72#define DDA7 7
73
74#define PORTA _SFR_IO8(0x02)
75#define PORTA0 0
76#define PORTA1 1
77#define PORTA2 2
78#define PORTA3 3
79#define PORTA4 4
80#define PORTA5 5
81#define PORTA6 6
82#define PORTA7 7
83
84#define PINB _SFR_IO8(0x03)
85#define PINB0 0
86#define PINB1 1
87#define PINB2 2
88#define PINB3 3
89#define PINB4 4
90#define PINB5 5
91#define PINB6 6
92#define PINB7 7
93
94#define DDRB _SFR_IO8(0x04)
95#define DDB0 0
96#define DDB1 1
97#define DDB2 2
98#define DDB3 3
99#define DDB4 4
100#define DDB5 5
101#define DDB6 6
102#define DDB7 7
103
104#define PORTB _SFR_IO8(0x05)
105#define PORTB0 0
106#define PORTB1 1
107#define PORTB2 2
108#define PORTB3 3
109#define PORTB4 4
110#define PORTB5 5
111#define PORTB6 6
112#define PORTB7 7
113
114#define PINC _SFR_IO8(0x06)
115#define PINC0 0
116#define PINC1 1
117#define PINC2 2
118#define PINC3 3
119#define PINC4 4
120#define PINC5 5
121#define PINC6 6
122#define PINC7 7
123
124#define DDRC _SFR_IO8(0x07)
125#define DDC0 0
126#define DDC1 1
127#define DDC2 2
128#define DDC3 3
129#define DDC4 4
130#define DDC5 5
131#define DDC6 6
132#define DDC7 7
133
134#define PORTC _SFR_IO8(0x08)
135#define PORTC0 0
136#define PORTC1 1
137#define PORTC2 2
138#define PORTC3 3
139#define PORTC4 4
140#define PORTC5 5
141#define PORTC6 6
142#define PORTC7 7
143
144#define PIND _SFR_IO8(0x09)
145#define PIND0 0
146#define PIND1 1
147#define PIND2 2
148#define PIND3 3
149#define PIND4 4
150#define PIND5 5
151#define PIND6 6
152#define PIND7 7
153
154#define DDRD _SFR_IO8(0x0A)
155#define DDD0 0
156#define DDD1 1
157#define DDD2 2
158#define DDD3 3
159#define DDD4 4
160#define DDD5 5
161#define DDD6 6
162#define DDD7 7
163
164#define PORTD _SFR_IO8(0x0B)
165#define PORTD0 0
166#define PORTD1 1
167#define PORTD2 2
168#define PORTD3 3
169#define PORTD4 4
170#define PORTD5 5
171#define PORTD6 6
172#define PORTD7 7
173
174#define PINE _SFR_IO8(0x0C)
175#define PINE0 0
176#define PINE1 1
177#define PINE2 2
178#define PINE3 3
179#define PINE4 4
180#define PINE5 5
181#define PINE6 6
182#define PINE7 7
183
184#define DDRE _SFR_IO8(0x0D)
185#define DDE0 0
186#define DDE1 1
187#define DDE2 2
188#define DDE3 3
189#define DDE4 4
190#define DDE5 5
191#define DDE6 6
192#define DDE7 7
193
194#define PORTE _SFR_IO8(0x0E)
195#define PORTE0 0
196#define PORTE1 1
197#define PORTE2 2
198#define PORTE3 3
199#define PORTE4 4
200#define PORTE5 5
201#define PORTE6 6
202#define PORTE7 7
203
204#define PINF _SFR_IO8(0x0F)
205#define PINF0 0
206#define PINF1 1
207#define PINF2 2
208#define PINF3 3
209#define PINF4 4
210#define PINF5 5
211#define PINF6 6
212#define PINF7 7
213
214#define DDRF _SFR_IO8(0x10)
215#define DDF0 0
216#define DDF1 1
217#define DDF2 2
218#define DDF3 3
219#define DDF4 4
220#define DDF5 5
221#define DDF6 6
222#define DDF7 7
223
224#define PORTF _SFR_IO8(0x11)
225#define PORTF0 0
226#define PORTF1 1
227#define PORTF2 2
228#define PORTF3 3
229#define PORTF4 4
230#define PORTF5 5
231#define PORTF6 6
232#define PORTF7 7
233
234#define PING _SFR_IO8(0x12)
235#define PING0 0
236#define PING1 1
237#define PING2 2
238#define PING3 3
239#define PING4 4
240#define PING5 5
241
242#define DDRG _SFR_IO8(0x13)
243#define DDG0 0
244#define DDG1 1
245#define DDG2 2
246#define DDG3 3
247#define DDG4 4
248#define DDG5 5
249
250#define PORTG _SFR_IO8(0x14)
251#define PORTG0 0
252#define PORTG1 1
253#define PORTG2 2
254#define PORTG3 3
255#define PORTG4 4
256#define PORTG5 5
257
258#define TIFR0 _SFR_IO8(0x15)
259#define TOV0 0
260#define OCF0A 1
261
262#define TIFR1 _SFR_IO8(0x16)
263#define TOV1 0
264#define OCF1A 1
265#define OCF1B 2
266#define ICF1 5
267
268#define TIFR2 _SFR_IO8(0x17)
269#define TOV2 0
270#define OCF2A 1
271
272#define EIFR _SFR_IO8(0x1C)
273#define INTF0 0
274#define PCIF0 4
275#define PCIF1 5
276
277#define EIMSK _SFR_IO8(0x1D)
278#define INT0 0
279#define PCIE0 4
280#define PCIE1 5
281
282#define GPIOR0 _SFR_IO8(0x1E)
283#define GPIOR00 0
284#define GPIOR01 1
285#define GPIOR02 2
286#define GPIOR03 3
287#define GPIOR04 4
288#define GPIOR05 5
289#define GPIOR06 6
290#define GPIOR07 7
291
292#define EECR _SFR_IO8(0x1F)
293#define EERE 0
294#define EEWE 1
295#define EEMWE 2
296#define EERIE 3
297
298#define EEDR _SFR_IO8(0x20)
299#define EEDR0 0
300#define EEDR1 1
301#define EEDR2 2
302#define EEDR3 3
303#define EEDR4 4
304#define EEDR5 5
305#define EEDR6 6
306#define EEDR7 7
307
308#define EEAR _SFR_IO16(0x21)
309
310#define EEARL _SFR_IO8(0x21)
311#define EEAR0 0
312#define EEAR1 1
313#define EEAR2 2
314#define EEAR3 3
315#define EEAR4 4
316#define EEAR5 5
317#define EEAR6 6
318#define EEAR7 7
319
320#define EEARH _SFR_IO8(0x22)
321#define EEAR8 0
322
323#define GTCCR _SFR_IO8(0x23)
324#define PSR310 0
325#define PSR2 1
326#define TSM 7
327
328#define TCCR0A _SFR_IO8(0x24)
329#define CS00 0
330#define CS01 1
331#define CS02 2
332#define WGM01 3
333#define COM0A0 4
334#define COM0A1 5
335#define WGM00 6
336#define FOC0A 7
337
338#define TCNT0 _SFR_IO8(0x26)
339#define TCNT0_0 0
340#define TCNT0_1 1
341#define TCNT0_2 2
342#define TCNT0_3 3
343#define TCNT0_4 4
344#define TCNT0_5 5
345#define TCNT0_6 6
346#define TCNT0_7 7
347
348#define OCR0A _SFR_IO8(0x27)
349#define OCR0A0 0
350#define OCR0A1 1
351#define OCR0A2 2
352#define OCR0A3 3
353#define OCR0A4 4
354#define OCR0A5 5
355#define OCR0A6 6
356#define OCR0A7 7
357
358#define GPIOR1 _SFR_IO8(0x2A)
359#define GPIOR10 0
360#define GPIOR11 1
361#define GPIOR12 2
362#define GPIOR13 3
363#define GPIOR14 4
364#define GPIOR15 5
365#define GPIOR16 6
366#define GPIOR17 7
367
368#define GPIOR2 _SFR_IO8(0x2B)
369#define GPIOR20 0
370#define GPIOR21 1
371#define GPIOR22 2
372#define GPIOR23 3
373#define GPIOR24 4
374#define GPIOR25 5
375#define GPIOR26 6
376#define GPIOR27 7
377
378#define SPCR _SFR_IO8(0x2C)
379#define SPR0 0
380#define SPR1 1
381#define CPHA 2
382#define CPOL 3
383#define MSTR 4
384#define DORD 5
385#define SPE 6
386#define SPIE 7
387
388#define SPSR _SFR_IO8(0x2D)
389#define SPI2X 0
390#define WCOL 6
391#define SPIF 7
392
393#define SPDR _SFR_IO8(0x2E)
394#define SPDR0 0
395#define SPDR1 1
396#define SPDR2 2
397#define SPDR3 3
398#define SPDR4 4
399#define SPDR5 5
400#define SPDR6 6
401#define SPDR7 7
402
403#define ACSR _SFR_IO8(0x30)
404#define ACIS0 0
405#define ACIS1 1
406#define ACIC 2
407#define ACIE 3
408#define ACI 4
409#define ACO 5
410#define ACBG 6
411#define ACD 7
412
413#define OCDR _SFR_IO8(0x31)
414#define OCDR0 0
415#define OCDR1 1
416#define OCDR2 2
417#define OCDR3 3
418#define OCDR4 4
419#define OCDR5 5
420#define OCDR6 6
421#define OCDR7 7
422
423#define SMCR _SFR_IO8(0x33)
424#define SE 0
425#define SM0 1
426#define SM1 2
427#define SM2 3
428
429#define MCUSR _SFR_IO8(0x34)
430#define PORF 0
431#define EXTRF 1
432#define BORF 2
433#define WDRF 3
434#define JTRF 4
435
436#define MCUCR _SFR_IO8(0x35)
437#define IVCE 0
438#define IVSEL 1
439#define PUD 4
440#define BODSE 5
441#define BODS 6
442#define JTD 7
443
444#define SPMCSR _SFR_IO8(0x37)
445#define SPMEN 0
446#define PGERS 1
447#define PGWRT 2
448#define BLBSET 3
449#define RWWSRE 4
450#define RWWSB 6
451#define SPMIE 7
452
453#define WDTCR _SFR_MEM8(0x60)
454#define WDP0 0
455#define WDP1 1
456#define WDP2 2
457#define WDE 3
458#define WDCE 4
459
460#define CLKPR _SFR_MEM8(0x61)
461#define CLKPS0 0
462#define CLKPS1 1
463#define CLKPS2 2
464#define CLKPS3 3
465#define CLKPCE 7
466
467#define PRR _SFR_MEM8(0x64)
468#define PRADC 0
469#define PRUSART0 1
470#define PRSPI 2
471#define PRTIM1 3
472#define PRLCD 4
473
474#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRLCD))
475#define __AVR_HAVE_PRR_PRADC
476#define __AVR_HAVE_PRR_PRUSART0
477#define __AVR_HAVE_PRR_PRSPI
478#define __AVR_HAVE_PRR_PRTIM1
479#define __AVR_HAVE_PRR_PRLCD
480
481#define OSCCAL _SFR_MEM8(0x66)
482#define CAL0 0
483#define CAL1 1
484#define CAL2 2
485#define CAL3 3
486#define CAL4 4
487#define CAL5 5
488#define CAL6 6
489#define CAL7 7
490
491#define EICRA _SFR_MEM8(0x69)
492#define ISC00 0
493#define ISC01 1
494
495#define PCMSK0 _SFR_MEM8(0x6B)
496#define PCINT0 0
497#define PCINT1 1
498#define PCINT2 2
499#define PCINT3 3
500#define PCINT4 4
501#define PCINT5 5
502#define PCINT6 6
503#define PCINT7 7
504
505#define PCMSK1 _SFR_MEM8(0x6C)
506#define PCINT8 0
507#define PCINT9 1
508#define PCINT10 2
509#define PCINT11 3
510#define PCINT12 4
511#define PCINT13 5
512#define PCINT14 6
513#define PCINT15 7
514
515#define TIMSK0 _SFR_MEM8(0x6E)
516#define TOIE0 0
517#define OCIE0A 1
518
519#define TIMSK1 _SFR_MEM8(0x6F)
520#define TOIE1 0
521#define OCIE1A 1
522#define OCIE1B 2
523#define ICIE1 5
524
525#define TIMSK2 _SFR_MEM8(0x70)
526#define TOIE2 0
527#define OCIE2A 1
528
529#ifndef __ASSEMBLER__
530#define ADC _SFR_MEM16(0x78)
531#endif
532#define ADCW _SFR_MEM16(0x78)
533
534#define ADCL _SFR_MEM8(0x78)
535#define ADCL0 0
536#define ADCL1 1
537#define ADCL2 2
538#define ADCL3 3
539#define ADCL4 4
540#define ADCL5 5
541#define ADCL6 6
542#define ADCL7 7
543
544#define ADCH _SFR_MEM8(0x79)
545#define ADCH0 0
546#define ADCH1 1
547#define ADCH2 2
548#define ADCH3 3
549#define ADCH4 4
550#define ADCH5 5
551#define ADCH6 6
552#define ADCH7 7
553
554#define ADCSRA _SFR_MEM8(0x7A)
555#define ADPS0 0
556#define ADPS1 1
557#define ADPS2 2
558#define ADIE 3
559#define ADIF 4
560#define ADATE 5
561#define ADSC 6
562#define ADEN 7
563
564#define ADCSRB _SFR_MEM8(0x7B)
565#define ADTS0 0
566#define ADTS1 1
567#define ADTS2 2
568#define ACME 6
569
570#define ADMUX _SFR_MEM8(0x7C)
571#define MUX0 0
572#define MUX1 1
573#define MUX2 2
574#define MUX3 3
575#define MUX4 4
576#define ADLAR 5
577#define REFS0 6
578#define REFS1 7
579
580#define DIDR0 _SFR_MEM8(0x7E)
581#define ADC0D 0
582#define ADC1D 1
583#define ADC2D 2
584#define ADC3D 3
585#define ADC4D 4
586#define ADC5D 5
587#define ADC6D 6
588#define ADC7D 7
589
590#define DIDR1 _SFR_MEM8(0x7F)
591#define AIN0D 0
592#define AIN1D 1
593
594#define TCCR1A _SFR_MEM8(0x80)
595#define WGM10 0
596#define WGM11 1
597#define COM1B0 4
598#define COM1B1 5
599#define COM1A0 6
600#define COM1A1 7
601
602#define TCCR1B _SFR_MEM8(0x81)
603#define CS10 0
604#define CS11 1
605#define CS12 2
606#define WGM12 3
607#define WGM13 4
608#define ICES1 6
609#define ICNC1 7
610
611#define TCCR1C _SFR_MEM8(0x82)
612#define FOC1B 6
613#define FOC1A 7
614
615#define TCNT1 _SFR_MEM16(0x84)
616
617#define TCNT1L _SFR_MEM8(0x84)
618#define TCNT1L0 0
619#define TCNT1L1 1
620#define TCNT1L2 2
621#define TCNT1L3 3
622#define TCNT1L4 4
623#define TCNT1L5 5
624#define TCNT1L6 6
625#define TCNT1L7 7
626
627#define TCNT1H _SFR_MEM8(0x85)
628#define TCNT1H0 0
629#define TCNT1H1 1
630#define TCNT1H2 2
631#define TCNT1H3 3
632#define TCNT1H4 4
633#define TCNT1H5 5
634#define TCNT1H6 6
635#define TCNT1H7 7
636
637#define ICR1 _SFR_MEM16(0x86)
638
639#define ICR1L _SFR_MEM8(0x86)
640#define ICR1L0 0
641#define ICR1L1 1
642#define ICR1L2 2
643#define ICR1L3 3
644#define ICR1L4 4
645#define ICR1L5 5
646#define ICR1L6 6
647#define ICR1L7 7
648
649#define ICR1H _SFR_MEM8(0x87)
650#define ICR1H0 0
651#define ICR1H1 1
652#define ICR1H2 2
653#define ICR1H3 3
654#define ICR1H4 4
655#define ICR1H5 5
656#define ICR1H6 6
657#define ICR1H7 7
658
659#define OCR1A _SFR_MEM16(0x88)
660
661#define OCR1AL _SFR_MEM8(0x88)
662#define OCR1AL0 0
663#define OCR1AL1 1
664#define OCR1AL2 2
665#define OCR1AL3 3
666#define OCR1AL4 4
667#define OCR1AL5 5
668#define OCR1AL6 6
669#define OCR1AL7 7
670
671#define OCR1AH _SFR_MEM8(0x89)
672#define OCR1AH0 0
673#define OCR1AH1 1
674#define OCR1AH2 2
675#define OCR1AH3 3
676#define OCR1AH4 4
677#define OCR1AH5 5
678#define OCR1AH6 6
679#define OCR1AH7 7
680
681#define OCR1B _SFR_MEM16(0x8A)
682
683#define OCR1BL _SFR_MEM8(0x8A)
684#define OCR1BL0 0
685#define OCR1BL1 1
686#define OCR1BL2 2
687#define OCR1BL3 3
688#define OCR1BL4 4
689#define OCR1BL5 5
690#define OCR1BL6 6
691#define OCR1BL7 7
692
693#define OCR1BH _SFR_MEM8(0x8B)
694#define OCR1BH0 0
695#define OCR1BH1 1
696#define OCR1BH2 2
697#define OCR1BH3 3
698#define OCR1BH4 4
699#define OCR1BH5 5
700#define OCR1BH6 6
701#define OCR1BH7 7
702
703#define TCCR2A _SFR_MEM8(0xB0)
704#define CS20 0
705#define CS21 1
706#define CS22 2
707#define WGM21 3
708#define COM2A0 4
709#define COM2A1 5
710#define WGM20 6
711#define FOC2A 7
712
713#define TCCR2B _SFR_MEM8(0xB1)
714
715#define TCNT2 _SFR_MEM8(0xB2)
716#define TCNT2_0 0
717#define TCNT2_1 1
718#define TCNT2_2 2
719#define TCNT2_3 3
720#define TCNT2_4 4
721#define TCNT2_5 5
722#define TCNT2_6 6
723#define TCNT2_7 7
724
725#define OCR2A _SFR_MEM8(0xB3)
726#define OCR2A0 0
727#define OCR2A1 1
728#define OCR2A2 2
729#define OCR2A3 3
730#define OCR2A4 4
731#define OCR2A5 5
732#define OCR2A6 6
733#define OCR2A7 7
734
735#define ASSR _SFR_MEM8(0xB6)
736#define TCR2UB 0
737#define OCR2UB 1
738#define TCN2UB 2
739#define AS2 3
740#define EXCLK 4
741
742#define USICR _SFR_MEM8(0xB8)
743#define USITC 0
744#define USICLK 1
745#define USICS0 2
746#define USICS1 3
747#define USIWM0 4
748#define USIWM1 5
749#define USIOIE 6
750#define USISIE 7
751
752#define USISR _SFR_MEM8(0xB9)
753#define USICNT0 0
754#define USICNT1 1
755#define USICNT2 2
756#define USICNT3 3
757#define USIDC 4
758#define USIPF 5
759#define USIOIF 6
760#define USISIF 7
761
762#define USIDR _SFR_MEM8(0xBA)
763#define USIDR0 0
764#define USIDR1 1
765#define USIDR2 2
766#define USIDR3 3
767#define USIDR4 4
768#define USIDR5 5
769#define USIDR6 6
770#define USIDR7 7
771
772#define UCSR0A _SFR_MEM8(0xC0)
773#define MPCM0 0
774#define U2X0 1
775#define UPE0 2
776#define DOR0 3
777#define FE0 4
778#define UDRE0 5
779#define TXC0 6
780#define RXC0 7
781
782#define UCSR0B _SFR_MEM8(0xC1)
783#define TXB80 0
784#define RXB80 1
785#define UCSZ02 2
786#define TXEN0 3
787#define RXEN0 4
788#define UDRIE0 5
789#define TXCIE0 6
790#define RXCIE0 7
791
792#define UCSR0C _SFR_MEM8(0xC2)
793#define UCPOL0 0
794#define UCSZ00 1
795#define UCSZ01 2
796#define USBS0 3
797#define UPM00 4
798#define UPM01 5
799#define UMSEL0 6
800
801#define UBRR0 _SFR_MEM16(0xC4)
802
803#define UBRR0L _SFR_MEM8(0xC4)
804#define UBRR0_0 0
805#define UBRR0_1 1
806#define UBRR0_2 2
807#define UBRR0_3 3
808#define UBRR0_4 4
809#define UBRR0_5 5
810#define UBRR0_6 6
811#define UBRR0_7 7
812
813#define UBRR0H _SFR_MEM8(0xC5)
814#define UBRR0_8 0
815#define UBRR0_9 1
816#define UBRR0_10 2
817#define UBRR0_11 3
818
819#define UDR0 _SFR_MEM8(0xC6)
820#define UDR00 0
821#define UDR01 1
822#define UDR02 2
823#define UDR03 3
824#define UDR04 4
825#define UDR05 5
826#define UDR06 6
827#define UDR07 7
828
829#define LCDCRA _SFR_MEM8(0xE4)
830#define LCDBL 0
831#define LCDCCD 1
832#define LCDBD 2
833#define LCDIE 3
834#define LCDIF 4
835#define LCDAB 6
836#define LCDEN 7
837
838#define LCDCRB _SFR_MEM8(0xE5)
839#define LCDPM0 0
840#define LCDPM1 1
841#define LCDPM2 2
842#define LCDMUX0 4
843#define LCDMUX1 5
844#define LCD2B 6
845#define LCDCS 7
846
847#define LCDFRR _SFR_MEM8(0xE6)
848#define LCDCD0 0
849#define LCDCD1 1
850#define LCDCD2 2
851#define LCDPS0 4
852#define LCDPS1 5
853#define LCDPS2 6
854
855#define LCDCCR _SFR_MEM8(0xE7)
856#define LCDCC0 0
857#define LCDCC1 1
858#define LCDCC2 2
859#define LCDCC3 3
860#define LCDMDT 4
861#define LCDDC0 5
862#define LCDDC1 6
863#define LCDDC2 7
864
865#define LCDDR0 _SFR_MEM8(0xEC)
866#define SEG000 0
867#define SEG001 1
868#define SEG002 2
869#define SEG003 3
870#define SEG004 4
871#define SEG005 5
872#define SEG006 6
873#define SEG007 7
874
875#define LCDDR1 _SFR_MEM8(0xED)
876#define SEG008 0
877#define SEG009 1
878#define SEG010 2
879#define SEG011 3
880#define SEG012 4
881#define SEG013 5
882#define SEG014 6
883#define SEG015 7
884
885#define LCDDR2 _SFR_MEM8(0xEE)
886#define SEG016 0
887#define SEG017 1
888#define SEG018 2
889#define SEG019 3
890#define SEG020 4
891#define SEG021 5
892#define SEG022 6
893#define SEG023 7
894
895#define LCDDR3 _SFR_MEM8(0xEF)
896#define SEG024 0
897
898#define LCDDR5 _SFR_MEM8(0xF1)
899#define SEG100 0
900#define SEG101 1
901#define SEG102 2
902#define SEG103 3
903#define SEG104 4
904#define SEG105 5
905#define SEG106 6
906#define SEG107 7
907
908#define LCDDR6 _SFR_MEM8(0xF2)
909#define SEG108 0
910#define SEG109 1
911#define SEG110 2
912#define SEG111 3
913#define SEG112 4
914#define SEG113 5
915#define SEG114 6
916#define SEG115 7
917
918#define LCDDR7 _SFR_MEM8(0xF3)
919#define SEG116 0
920#define SEG117 1
921#define SEG118 2
922#define SEG119 3
923#define SEG120 4
924#define SEG121 5
925#define SEG122 6
926#define SEG123 7
927
928#define LCDDR8 _SFR_MEM8(0xF4)
929#define SEG124 0
930
931#define LCDDR10 _SFR_MEM8(0xF6)
932#define SEG200 0
933#define SEG201 1
934#define SEG202 2
935#define SEG203 3
936#define SEG204 4
937#define SEG205 5
938#define SEG206 6
939#define SEG207 7
940
941#define LCDDR11 _SFR_MEM8(0xF7)
942#define SEG208 0
943#define SEG209 1
944#define SEG210 2
945#define SEG211 3
946#define SEG212 4
947#define SEG213 5
948#define SEG214 6
949#define SEG215 7
950
951#define LCDDR12 _SFR_MEM8(0xF8)
952#define SEG216 0
953#define SEG217 1
954#define SEG218 2
955#define SEG219 3
956#define SEG220 4
957#define SEG221 5
958#define SEG222 6
959#define SEG223 7
960
961#define LCDDR13 _SFR_MEM8(0xF9)
962#define SEG224 0
963
964#define LCDDR15 _SFR_MEM8(0xFB)
965#define SEG300 0
966#define SEG301 1
967#define SEG302 2
968#define SEG303 3
969#define SEG304 4
970#define SEG305 5
971#define SEG306 6
972#define SEG307 7
973
974#define LCDDR16 _SFR_MEM8(0xFC)
975#define SEG308 0
976#define SEG309 1
977#define SEG310 2
978#define SEG311 3
979#define SEG312 4
980#define SEG313 5
981#define SEG314 6
982#define SEG315 7
983
984#define LCDDR17 _SFR_MEM8(0xFD)
985#define SEG316 0
986#define SEG317 1
987#define SEG318 2
988#define SEG319 3
989#define SEG320 4
990#define SEG321 5
991#define SEG322 6
992#define SEG323 7
993
994#define LCDDR18 _SFR_MEM8(0xFE)
995#define SEG324 0
996
997
998/* Interrupt vectors */
999/* Vector 0 is the reset vector */
1000#define INT0_vect_num  1
1001#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
1002#define PCINT0_vect_num  2
1003#define PCINT0_vect      _VECTOR(2)  /* Pin Change Interrupt Request 0 */
1004#define PCINT1_vect_num  3
1005#define PCINT1_vect      _VECTOR(3)  /* Pin Change Interrupt Request 1 */
1006#define TIMER2_COMP_vect_num  4
1007#define TIMER2_COMP_vect      _VECTOR(4)  /* Timer/Counter2 Compare Match */
1008#define TIMER2_OVF_vect_num  5
1009#define TIMER2_OVF_vect      _VECTOR(5)  /* Timer/Counter2 Overflow */
1010#define TIMER1_CAPT_vect_num  6
1011#define TIMER1_CAPT_vect      _VECTOR(6)  /* Timer/Counter1 Capture Event */
1012#define TIMER1_COMPA_vect_num  7
1013#define TIMER1_COMPA_vect      _VECTOR(7)  /* Timer/Counter1 Compare Match A */
1014#define TIMER1_COMPB_vect_num  8
1015#define TIMER1_COMPB_vect      _VECTOR(8)  /* Timer/Counter Compare Match B */
1016#define TIMER1_OVF_vect_num  9
1017#define TIMER1_OVF_vect      _VECTOR(9)  /* Timer/Counter1 Overflow */
1018#define TIMER0_COMP_vect_num  10
1019#define TIMER0_COMP_vect      _VECTOR(10)  /* Timer/Counter0 Compare Match */
1020#define TIMER0_OVF_vect_num  11
1021#define TIMER0_OVF_vect      _VECTOR(11)  /* Timer/Counter0 Overflow */
1022#define SPI_STC_vect_num  12
1023#define SPI_STC_vect      _VECTOR(12)  /* SPI Serial Transfer Complete */
1024#define USART0_RX_vect_num  13
1025#define USART0_RX_vect      _VECTOR(13)  /* USART0, Rx Complete */
1026#define USART0_UDRE_vect_num  14
1027#define USART0_UDRE_vect      _VECTOR(14)  /* USART0 Data register Empty */
1028#define USART0_TX_vect_num  15
1029#define USART0_TX_vect      _VECTOR(15)  /* USART0, Tx Complete */
1030#define USI_START_vect_num  16
1031#define USI_START_vect      _VECTOR(16)  /* USI Start Condition */
1032#define USI_OVERFLOW_vect_num  17
1033#define USI_OVERFLOW_vect      _VECTOR(17)  /* USI Overflow */
1034#define ANALOG_COMP_vect_num  18
1035#define ANALOG_COMP_vect      _VECTOR(18)  /* Analog Comparator */
1036#define ADC_vect_num  19
1037#define ADC_vect      _VECTOR(19)  /* ADC Conversion Complete */
1038#define EE_READY_vect_num  20
1039#define EE_READY_vect      _VECTOR(20)  /* EEPROM Ready */
1040#define SPM_READY_vect_num  21
1041#define SPM_READY_vect      _VECTOR(21)  /* Store Program Memory Read */
1042#define LCD_vect_num  22
1043#define LCD_vect      _VECTOR(22)  /* LCD Start of Frame */
1044
1045#define _VECTOR_SIZE 4 /* Size of individual vector. */
1046#define _VECTORS_SIZE (23 * _VECTOR_SIZE)
1047
1048
1049/* Constants */
1050#define SPM_PAGESIZE (128)
1051#define RAMSTART     (0x100)
1052#define RAMSIZE      (1024)
1053#define RAMEND       (RAMSTART + RAMSIZE - 1)
1054#define XRAMSTART    (NA)
1055#define XRAMSIZE     (0)
1056#define XRAMEND      (RAMEND)
1057#define E2END        (0x1FF)
1058#define E2PAGESIZE   (4)
1059#define FLASHEND     (0x3FFF)
1060
1061
1062/* Fuses */
1063#define FUSE_MEMORY_SIZE 3
1064
1065/* Low Fuse Byte */
1066#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
1067#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
1068#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
1069#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
1070#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
1071#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
1072#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator options */
1073#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
1074#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
1075
1076/* High Fuse Byte */
1077#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
1078#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
1079#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
1080#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
1081#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
1082#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
1083#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
1084#define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
1085#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
1086
1087/* Extended Fuse Byte */
1088#define FUSE_RSTDISBL  (unsigned char)~_BV(0)  /* Disable external reset */
1089#define FUSE_BODLEVEL0  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
1090#define FUSE_BODLEVEL1  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
1091#define FUSE_BODLEVEL2  (unsigned char)~_BV(3)  /* Brown out detector trigger level */
1092#define EFUSE_DEFAULT (0xFF)
1093
1094
1095/* Lock Bits */
1096#define __LOCK_BITS_EXIST
1097#define __BOOT_LOCK_BITS_0_EXIST
1098#define __BOOT_LOCK_BITS_1_EXIST
1099
1100
1101/* Signature */
1102#define SIGNATURE_0 0x1E
1103#define SIGNATURE_1 0x94
1104#define SIGNATURE_2 0x05
1105
1106
1107/* Device Pin Definitions */
1108#define RXD_DDR   DDRE
1109#define RXD_PORT  PORTE
1110#define RXD_PIN   PINE
1111#define RXD_BIT   0
1112
1113#define PCINT0_DDR   DDRE
1114#define PCINT0_PORT  PORTE
1115#define PCINT0_PIN   PINE
1116#define PCINT0_BIT   0
1117
1118#define TXD_DDR   DDRE
1119#define TXD_PORT  PORTE
1120#define TXD_PIN   PINE
1121#define TXD_BIT   1
1122
1123#define PCINT1_DDR   DDRE
1124#define PCINT1_PORT  PORTE
1125#define PCINT1_PIN   PINE
1126#define PCINT1_BIT   1
1127
1128#define XCK_DDR   DDRE
1129#define XCK_PORT  PORTE
1130#define XCK_PIN   PINE
1131#define XCK_BIT   2
1132
1133#define AIN0_DDR   DDRE
1134#define AIN0_PORT  PORTE
1135#define AIN0_PIN   PINE
1136#define AIN0_BIT   2
1137
1138#define PCINT2_DDR   DDRE
1139#define PCINT2_PORT  PORTE
1140#define PCINT2_PIN   PINE
1141#define PCINT2_BIT   2
1142
1143#define AIN1_DDR   DDRE
1144#define AIN1_PORT  PORTE
1145#define AIN1_PIN   PINE
1146#define AIN1_BIT   3
1147
1148#define PCINT3_DDR   DDRE
1149#define PCINT3_PORT  PORTE
1150#define PCINT3_PIN   PINE
1151#define PCINT3_BIT   3
1152
1153#define USCK_DDR   DDRE
1154#define USCK_PORT  PORTE
1155#define USCK_PIN   PINE
1156#define USCK_BIT   4
1157
1158#define SCL_DDR   DDRE
1159#define SCL_PORT  PORTE
1160#define SCL_PIN   PINE
1161#define SCL_BIT   4
1162
1163#define PCINT4_DDR   DDRE
1164#define PCINT4_PORT  PORTE
1165#define PCINT4_PIN   PINE
1166#define PCINT4_BIT   4
1167
1168#define DI_DDR   DDRE
1169#define DI_PORT  PORTE
1170#define DI_PIN   PINE
1171#define DI_BIT   5
1172
1173#define SDA_DDR   DDRE
1174#define SDA_PORT  PORTE
1175#define SDA_PIN   PINE
1176#define SDA_BIT   5
1177
1178#define PCINT5_DDR   DDRE
1179#define PCINT5_PORT  PORTE
1180#define PCINT5_PIN   PINE
1181#define PCINT5_BIT   5
1182
1183#define DO_DDR   DDRE
1184#define DO_PORT  PORTE
1185#define DO_PIN   PINE
1186#define DO_BIT   6
1187
1188#define PCINT6_DDR   DDRE
1189#define PCINT6_PORT  PORTE
1190#define PCINT6_PIN   PINE
1191#define PCINT6_BIT   6
1192
1193#define PCINT7_DDR   DDRE
1194#define PCINT7_PORT  PORTE
1195#define PCINT7_PIN   PINE
1196#define PCINT7_BIT   7
1197
1198#define SS_DDR   DDRB
1199#define SS_PORT  PORTB
1200#define SS_PIN   PINB
1201#define SS_BIT   0
1202
1203#define PCINT8_DDR   DDRB
1204#define PCINT8_PORT  PORTB
1205#define PCINT8_PIN   PINB
1206#define PCINT8_BIT   0
1207
1208#define SCK_DDR   DDRB
1209#define SCK_PORT  PORTB
1210#define SCK_PIN   PINB
1211#define SCK_BIT   1
1212
1213#define PCINT9_DDR   DDRB
1214#define PCINT9_PORT  PORTB
1215#define PCINT9_PIN   PINB
1216#define PCINT9_BIT   1
1217
1218#define MOSI_DDR   DDRB
1219#define MOSI_PORT  PORTB
1220#define MOSI_PIN   PINB
1221#define MOSI_BIT   2
1222
1223#define PCINT10_DDR   DDRB
1224#define PCINT10_PORT  PORTB
1225#define PCINT10_PIN   PINB
1226#define PCINT10_BIT   2
1227
1228#define MISO_DDR   DDRB
1229#define MISO_PORT  PORTB
1230#define MISO_PIN   PINB
1231#define MISO_BIT   3
1232
1233#define PCINT11_DDR   DDRB
1234#define PCINT11_PORT  PORTB
1235#define PCINT11_PIN   PINB
1236#define PCINT11_BIT   3
1237
1238#define OC0_DDR   DDRB
1239#define OC0_PORT  PORTB
1240#define OC0_PIN   PINB
1241#define OC0_BIT   4
1242
1243#define PCINT12_DDR   DDRB
1244#define PCINT12_PORT  PORTB
1245#define PCINT12_PIN   PINB
1246#define PCINT12_BIT   4
1247
1248#define OC1A_DDR   DDRB
1249#define OC1A_PORT  PORTB
1250#define OC1A_PIN   PINB
1251#define OC1A_BIT   5
1252
1253#define PCINT13_DDR   DDRB
1254#define PCINT13_PORT  PORTB
1255#define PCINT13_PIN   PINB
1256#define PCINT13_BIT   5
1257
1258#define OC1B_DDR   DDRB
1259#define OC1B_PORT  PORTB
1260#define OC1B_PIN   PINB
1261#define OC1B_BIT   6
1262
1263#define PCINT14_DDR   DDRB
1264#define PCINT14_PORT  PORTB
1265#define PCINT14_PIN   PINB
1266#define PCINT14_BIT   6
1267
1268#define OC2_DDR   DDRB
1269#define OC2_PORT  PORTB
1270#define OC2_PIN   PINB
1271#define OC2_BIT   7
1272
1273#define PCINT15_DDR   DDRB
1274#define PCINT15_PORT  PORTB
1275#define PCINT15_PIN   PINB
1276#define PCINT15_BIT   7
1277
1278#define T1_DDR   DDRG
1279#define T1_PORT  PORTG
1280#define T1_PIN   PING
1281#define T1_BIT   3
1282
1283#define SEG24_DDR   DDRG
1284#define SEG24_PORT  PORTG
1285#define SEG24_PIN   PING
1286#define SEG24_BIT   3
1287
1288#define T0_DDR   DDRG
1289#define T0_PORT  PORTG
1290#define T0_PIN   PING
1291#define T0_BIT   4
1292
1293#define SEG23_DDR   DDRG
1294#define SEG23_PORT  PORTG
1295#define SEG23_PIN   PING
1296#define SEG23_BIT   4
1297
1298#define SEG22_DDR   DDRD
1299#define SEG22_PORT  PORTD
1300#define SEG22_PIN   PIND
1301#define SEG22_BIT   0
1302
1303#define SEG21_DDR   DDRD
1304#define SEG21_PORT  PORTD
1305#define SEG21_PIN   PIND
1306#define SEG21_BIT   1
1307
1308#define SEG20_DDR   DDRD
1309#define SEG20_PORT  PORTD
1310#define SEG20_PIN   PIND
1311#define SEG20_BIT   2
1312
1313#define SEG19_DDR   DDRD
1314#define SEG19_PORT  PORTD
1315#define SEG19_PIN   PIND
1316#define SEG19_BIT   3
1317
1318#define SEG18_DDR   DDRD
1319#define SEG18_PORT  PORTD
1320#define SEG18_PIN   PIND
1321#define SEG18_BIT   4
1322
1323#define SEG17_DDR   DDRD
1324#define SEG17_PORT  PORTD
1325#define SEG17_PIN   PIND
1326#define SEG17_BIT   5
1327
1328#define SEG16_DDR   DDRD
1329#define SEG16_PORT  PORTD
1330#define SEG16_PIN   PIND
1331#define SEG16_BIT   6
1332
1333#define SEG15_DDR   DDRD
1334#define SEG15_PORT  PORTD
1335#define SEG15_PIN   PIND
1336#define SEG15_BIT   7
1337
1338#define SEG14_DDR   DDRG
1339#define SEG14_PORT  PORTG
1340#define SEG14_PIN   PING
1341#define SEG14_BIT   0
1342
1343#define SEG13_DDR   DDRG
1344#define SEG13_PORT  PORTG
1345#define SEG13_PIN   PING
1346#define SEG13_BIT   1
1347
1348#define SEG12_DDR   DDRC
1349#define SEG12_PORT  PORTC
1350#define SEG12_PIN   PINC
1351#define SEG12_BIT   0
1352
1353#define SEG11_DDR   DDRC
1354#define SEG11_PORT  PORTC
1355#define SEG11_PIN   PINC
1356#define SEG11_BIT   1
1357
1358#define SEG10_DDR   DDRC
1359#define SEG10_PORT  PORTC
1360#define SEG10_PIN   PINC
1361#define SEG10_BIT   2
1362
1363#define SEG9_DDR   DDRC
1364#define SEG9_PORT  PORTC
1365#define SEG9_PIN   PINC
1366#define SEG9_BIT   3
1367
1368#define SEG8_DDR   DDRC
1369#define SEG8_PORT  PORTC
1370#define SEG8_PIN   PINC
1371#define SEG8_BIT   4
1372
1373#define SEG7_DDR   DDRC
1374#define SEG7_PORT  PORTC
1375#define SEG7_PIN   PINC
1376#define SEG7_BIT   5
1377
1378#define SEG6_DDR   DDRC
1379#define SEG6_PORT  PORTC
1380#define SEG6_PIN   PINC
1381#define SEG6_BIT   6
1382
1383#define SEG5_DDR   DDRC
1384#define SEG5_PORT  PORTC
1385#define SEG5_PIN   PINC
1386#define SEG5_BIT   7
1387
1388#define SEG4_DDR   DDRG
1389#define SEG4_PORT  PORTG
1390#define SEG4_PIN   PING
1391#define SEG4_BIT   2
1392
1393#define SEG3_DDR   DDRA
1394#define SEG3_PORT  PORTA
1395#define SEG3_PIN   PINA
1396#define SEG3_BIT   7
1397
1398#define SEG2_DDR   DDRA
1399#define SEG2_PORT  PORTA
1400#define SEG2_PIN   PINA
1401#define SEG2_BIT   6
1402
1403#define SEG1_DDR   DDRA
1404#define SEG1_PORT  PORTA
1405#define SEG1_PIN   PINA
1406#define SEG1_BIT   5
1407
1408#define SEG0_DDR   DDRA
1409#define SEG0_PORT  PORTA
1410#define SEG0_PIN   PINA
1411#define SEG0_BIT   4
1412
1413#define COM3_DDR   DDRA
1414#define COM3_PORT  PORTA
1415#define COM3_PIN   PINA
1416#define COM3_BIT   3
1417
1418#define COM2_DDR   DDRA
1419#define COM2_PORT  PORTA
1420#define COM2_PIN   PINA
1421#define COM2_BIT   2
1422
1423#define COM1_DDR   DDRA
1424#define COM1_PORT  PORTA
1425#define COM1_PIN   PINA
1426#define COM1_BIT   1
1427
1428#define COM0_DDR   DDRA
1429#define COM0_PORT  PORTA
1430#define COM0_PIN   PINA
1431#define COM0_BIT   0
1432
1433#define ADC7_DDR   DDRF
1434#define ADC7_PORT  PORTF
1435#define ADC7_PIN   PINF
1436#define ADC7_BIT   7
1437
1438#define ADC6_DDR   DDRF
1439#define ADC6_PORT  PORTF
1440#define ADC6_PIN   PINF
1441#define ADC6_BIT   6
1442
1443#define TD0_DDR   DDRF
1444#define TD0_PORT  PORTF
1445#define TD0_PIN   PINF
1446#define TD0_BIT   6
1447
1448#define ADC5_DDR   DDRF
1449#define ADC5_PORT  PORTF
1450#define ADC5_PIN   PINF
1451#define ADC5_BIT   5
1452
1453#define ADC4_DDR   DDRF
1454#define ADC4_PORT  PORTF
1455#define ADC4_PIN   PINF
1456#define ADC4_BIT   4
1457
1458#define ADC3_DDR   DDRF
1459#define ADC3_PORT  PORTF
1460#define ADC3_PIN   PINF
1461#define ADC3_BIT   3
1462
1463#define ADC2_DDR   DDRF
1464#define ADC2_PORT  PORTF
1465#define ADC2_PIN   PINF
1466#define ADC2_BIT   2
1467
1468#define ADC1_DDR   DDRF
1469#define ADC1_PORT  PORTF
1470#define ADC1_PIN   PINF
1471#define ADC1_BIT   1
1472
1473#define ADC0_DDR   DDRF
1474#define ADC0_PORT  PORTF
1475#define ADC0_PIN   PINF
1476#define ADC0_BIT   0
1477
1478#define SLEEP_MODE_IDLE (0x00<<1)
1479#define SLEEP_MODE_ADC (0x01<<1)
1480#define SLEEP_MODE_PWR_DOWN (0x02<<1)
1481#define SLEEP_MODE_PWR_SAVE (0x03<<1)
1482#define SLEEP_MODE_STANDBY (0x06<<1)
1483
1484#endif /* _AVR_ATmega169PA_H_ */
1485
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