source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom256rfr2.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

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1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATMEGA256RFR2_H_INCLUDED
36#define _AVR_ATMEGA256RFR2_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "iom256rfr2.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINA    _SFR_IO8(0x00)
52#define PINA7   7
53#define PINA6   6
54#define PINA5   5
55#define PINA4   4
56#define PINA3   3
57#define PINA2   2
58#define PINA1   1
59#define PINA0   0
60
61#define DDRA    _SFR_IO8(0x01)
62#define DDRA7   7
63// Inserted "DDA7" from "DDRA7" due to compatibility
64#define DDA7    7
65#define DDRA6   6
66// Inserted "DDA6" from "DDRA6" due to compatibility
67#define DDA6    6
68#define DDRA5   5
69// Inserted "DDA5" from "DDRA5" due to compatibility
70#define DDA5    5
71#define DDRA4   4
72// Inserted "DDA4" from "DDRA4" due to compatibility
73#define DDA4    4
74#define DDRA3   3
75// Inserted "DDA3" from "DDRA3" due to compatibility
76#define DDA3    3
77#define DDRA2   2
78// Inserted "DDA2" from "DDRA2" due to compatibility
79#define DDA2    2
80#define DDRA1   1
81// Inserted "DDA1" from "DDRA1" due to compatibility
82#define DDA1    1
83#define DDRA0   0
84// Inserted "DDA0" from "DDRA0" due to compatibility
85#define DDA0    0
86
87#define PORTA   _SFR_IO8(0x02)
88#define PORTA7  7
89#define PORTA6  6
90#define PORTA5  5
91#define PORTA4  4
92#define PORTA3  3
93#define PORTA2  2
94#define PORTA1  1
95#define PORTA0  0
96
97#define PINB    _SFR_IO8(0x03)
98#define PINB7   7
99#define PINB6   6
100#define PINB5   5
101#define PINB4   4
102#define PINB3   3
103#define PINB2   2
104#define PINB1   1
105#define PINB0   0
106
107#define DDRB    _SFR_IO8(0x04)
108#define DDRB7   7
109// Inserted "DDB7" from "DDRB7" due to compatibility
110#define DDB7    7
111#define DDRB6   6
112// Inserted "DDB6" from "DDRB6" due to compatibility
113#define DDB6    6
114#define DDRB5   5
115// Inserted "DDB5" from "DDRB5" due to compatibility
116#define DDB5    5
117#define DDRB4   4
118// Inserted "DDB4" from "DDRB4" due to compatibility
119#define DDB4    4
120#define DDRB3   3
121// Inserted "DDB3" from "DDRB3" due to compatibility
122#define DDB3    3
123#define DDRB2   2
124// Inserted "DDB2" from "DDRB2" due to compatibility
125#define DDB2    2
126#define DDRB1   1
127// Inserted "DDB1" from "DDRB1" due to compatibility
128#define DDB1    1
129#define DDRB0   0
130// Inserted "DDB0" from "DDRB0" due to compatibility
131#define DDB0    0
132
133#define PORTB   _SFR_IO8(0x05)
134#define PORTB7  7
135#define PORTB6  6
136#define PORTB5  5
137#define PORTB4  4
138#define PORTB3  3
139#define PORTB2  2
140#define PORTB1  1
141#define PORTB0  0
142
143#define PINC    _SFR_IO8(0x06)
144#define PINC7   7
145#define PINC6   6
146#define PINC5   5
147#define PINC4   4
148#define PINC3   3
149#define PINC2   2
150#define PINC1   1
151#define PINC0   0
152
153#define DDRC    _SFR_IO8(0x07)
154#define DDRC7   7
155// Inserted "DDC7" from "DDRC7" due to compatibility
156#define DDC7    7
157#define DDRC6   6
158// Inserted "DDC6" from "DDRC6" due to compatibility
159#define DDC6    6
160#define DDRC5   5
161// Inserted "DDC5" from "DDRC5" due to compatibility
162#define DDC5    5
163#define DDRC4   4
164// Inserted "DDC4" from "DDRC4" due to compatibility
165#define DDC4    4
166#define DDRC3   3
167// Inserted "DDC3" from "DDRC3" due to compatibility
168#define DDC3    3
169#define DDRC2   2
170// Inserted "DDC2" from "DDRC2" due to compatibility
171#define DDC2    2
172#define DDRC1   1
173// Inserted "DDC1" from "DDRC1" due to compatibility
174#define DDC1    1
175#define DDRC0   0
176// Inserted "DDC0" from "DDRC0" due to compatibility
177#define DDC0    0
178
179#define PORTC   _SFR_IO8(0x08)
180#define PORTC7  7
181#define PORTC6  6
182#define PORTC5  5
183#define PORTC4  4
184#define PORTC3  3
185#define PORTC2  2
186#define PORTC1  1
187#define PORTC0  0
188
189#define PIND    _SFR_IO8(0x09)
190#define PIND7   7
191#define PIND6   6
192#define PIND5   5
193#define PIND4   4
194#define PIND3   3
195#define PIND2   2
196#define PIND1   1
197#define PIND0   0
198
199#define DDRD    _SFR_IO8(0x0A)
200#define DDRD7   7
201// Inserted "DDD7" from "DDRD7" due to compatibility
202#define DDD7    7
203#define DDRD6   6
204// Inserted "DDD6" from "DDRD6" due to compatibility
205#define DDD6    6
206#define DDRD5   5
207// Inserted "DDD5" from "DDRD5" due to compatibility
208#define DDD5    5
209#define DDRD4   4
210// Inserted "DDD4" from "DDRD4" due to compatibility
211#define DDD4    4
212#define DDRD3   3
213// Inserted "DDD3" from "DDRD3" due to compatibility
214#define DDD3    3
215#define DDRD2   2
216// Inserted "DDD2" from "DDRD2" due to compatibility
217#define DDD2    2
218#define DDRD1   1
219// Inserted "DDD1" from "DDRD1" due to compatibility
220#define DDD1    1
221#define DDRD0   0
222// Inserted "DDD0" from "DDRD0" due to compatibility
223#define DDD0    0
224
225#define PORTD   _SFR_IO8(0x0B)
226#define PORTD7  7
227#define PORTD6  6
228#define PORTD5  5
229#define PORTD4  4
230#define PORTD3  3
231#define PORTD2  2
232#define PORTD1  1
233#define PORTD0  0
234
235#define PINE    _SFR_IO8(0x0C)
236#define PINE7   7
237#define PINE6   6
238#define PINE5   5
239#define PINE4   4
240#define PINE3   3
241#define PINE2   2
242#define PINE1   1
243#define PINE0   0
244
245#define DDRE    _SFR_IO8(0x0D)
246#define DDRE7   7
247// Inserted "DDE7" from "DDRE7" due to compatibility
248#define DDE7    7
249#define DDRE6   6
250// Inserted "DDE6" from "DDRE6" due to compatibility
251#define DDE6    6
252#define DDRE5   5
253// Inserted "DDE5" from "DDRE5" due to compatibility
254#define DDE5    5
255#define DDRE4   4
256// Inserted "DDE4" from "DDRE4" due to compatibility
257#define DDE4    4
258#define DDRE3   3
259// Inserted "DDE3" from "DDRE3" due to compatibility
260#define DDE3    3
261#define DDRE2   2
262// Inserted "DDE2" from "DDRE2" due to compatibility
263#define DDE2    2
264#define DDRE1   1
265// Inserted "DDE1" from "DDRE1" due to compatibility
266#define DDE1    1
267#define DDRE0   0
268// Inserted "DDE0" from "DDRE0" due to compatibility
269#define DDE0    0
270
271#define PORTE   _SFR_IO8(0x0E)
272#define PORTE7  7
273#define PORTE6  6
274#define PORTE5  5
275#define PORTE4  4
276#define PORTE3  3
277#define PORTE2  2
278#define PORTE1  1
279#define PORTE0  0
280
281#define PINF    _SFR_IO8(0x0F)
282#define PINF7   7
283#define PINF6   6
284#define PINF5   5
285#define PINF4   4
286#define PINF3   3
287#define PINF2   2
288#define PINF1   1
289#define PINF0   0
290
291#define DDRF    _SFR_IO8(0x10)
292#define DDRF7   7
293// Inserted "DDF7" from "DDRF7" due to compatibility
294#define DDF7    7
295#define DDRF6   6
296// Inserted "DDF6" from "DDRF6" due to compatibility
297#define DDF6    6
298#define DDRF5   5
299// Inserted "DDF5" from "DDRF5" due to compatibility
300#define DDF5    5
301#define DDRF4   4
302// Inserted "DDF4" from "DDRF4" due to compatibility
303#define DDF4    4
304#define DDRF3   3
305// Inserted "DDF3" from "DDRF3" due to compatibility
306#define DDF3    3
307#define DDRF2   2
308// Inserted "DDF2" from "DDRF2" due to compatibility
309#define DDF2    2
310#define DDRF1   1
311// Inserted "DDF1" from "DDRF1" due to compatibility
312#define DDF1    1
313#define DDRF0   0
314// Inserted "DDF0" from "DDRF0" due to compatibility
315#define DDF0    0
316
317#define PORTF   _SFR_IO8(0x11)
318#define PORTF7  7
319#define PORTF6  6
320#define PORTF5  5
321#define PORTF4  4
322#define PORTF3  3
323#define PORTF2  2
324#define PORTF1  1
325#define PORTF0  0
326
327#define PING    _SFR_IO8(0x12)
328#define PING7   7
329#define PING6   6
330#define PING5   5
331#define PING4   4
332#define PING3   3
333#define PING2   2
334#define PING1   1
335#define PING0   0
336
337#define DDRG    _SFR_IO8(0x13)
338#define DDRG7   7
339// Inserted "DDG7" from "DDRG7" due to compatibility
340#define DDG7    7
341#define DDRG6   6
342// Inserted "DDG6" from "DDRG6" due to compatibility
343#define DDG6    6
344#define DDRG5   5
345// Inserted "DDG5" from "DDRG5" due to compatibility
346#define DDG5    5
347#define DDRG4   4
348// Inserted "DDG4" from "DDRG4" due to compatibility
349#define DDG4    4
350#define DDRG3   3
351// Inserted "DDG3" from "DDRG3" due to compatibility
352#define DDG3    3
353#define DDRG2   2
354// Inserted "DDG2" from "DDRG2" due to compatibility
355#define DDG2    2
356#define DDRG1   1
357// Inserted "DDG1" from "DDRG1" due to compatibility
358#define DDG1    1
359#define DDRG0   0
360// Inserted "DDG0" from "DDRG0" due to compatibility
361#define DDG0    0
362
363#define PORTG   _SFR_IO8(0x14)
364#define PORTG7  7
365#define PORTG6  6
366#define PORTG5  5
367#define PORTG4  4
368#define PORTG3  3
369#define PORTG2  2
370#define PORTG1  1
371#define PORTG0  0
372
373#define TIFR0   _SFR_IO8(0x15)
374#define TOV0    0
375#define OCF0A   1
376#define OCF0B   2
377#define Res0    3
378#define Res1    4
379#define Res2    5
380#define Res3    6
381#define Res4    7
382
383#define TIFR1   _SFR_IO8(0x16)
384#define TOV1    0
385#define OCF1A   1
386#define OCF1B   2
387#define OCF1C   3
388#define ICF1    5
389
390#define TIFR2   _SFR_IO8(0x17)
391#define TOV2    0
392#define OCF2A   1
393#define OCF2B   2
394
395#define TIFR3   _SFR_IO8(0x18)
396#define TOV3    0
397#define OCF3A   1
398#define OCF3B   2
399#define OCF3C   3
400#define ICF3    5
401
402#define TIFR4   _SFR_IO8(0x19)
403#define TOV4    0
404#define OCF4A   1
405#define OCF4B   2
406#define OCF4C   3
407#define ICF4    5
408
409#define TIFR5   _SFR_IO8(0x1A)
410#define TOV5    0
411#define OCF5A   1
412#define OCF5B   2
413#define OCF5C   3
414#define ICF5    5
415
416#define PCIFR   _SFR_IO8(0x1B)
417#define PCIF0   0
418#define PCIF1   1
419#define PCIF2   2
420
421#define EIFR    _SFR_IO8(0x1C)
422#define INTF0   0
423#define INTF1   1
424#define INTF2   2
425#define INTF3   3
426#define INTF4   4
427#define INTF5   5
428#define INTF6   6
429#define INTF7   7
430
431#define EIMSK   _SFR_IO8(0x1D)
432#define INT0    0
433#define INT1    1
434#define INT2    2
435#define INT3    3
436#define INT4    4
437#define INT5    5
438#define INT6    6
439#define INT7    7
440
441#define GPIOR0  _SFR_IO8(0x1E)
442#define GPIOR00 0
443#define GPIOR01 1
444#define GPIOR02 2
445#define GPIOR03 3
446#define GPIOR04 4
447#define GPIOR05 5
448#define GPIOR06 6
449#define GPIOR07 7
450
451#define EECR    _SFR_IO8(0x1F)
452#define EERE    0
453#define EEPE    1
454#define EEMPE   2
455#define EERIE   3
456#define EEPM0   4
457#define EEPM1   5
458
459#define EEDR    _SFR_IO8(0x20)
460
461/* Combine EEARL and EEARH */
462#define EEAR    _SFR_IO16(0x21)
463
464#define EEARL   _SFR_IO8(0x21)
465#define EEARH   _SFR_IO8(0x22)
466
467#define GTCCR   _SFR_IO8(0x23)
468#define PSRSYNC 0
469#define PSRASY  1
470#define TSM     7
471
472#define TCCR0A  _SFR_IO8(0x24)
473#define WGM00   0
474#define WGM01   1
475#define COM0B0  4
476#define COM0B1  5
477#define COM0A0  6
478#define COM0A1  7
479
480#define TCCR0B  _SFR_IO8(0x25)
481#define CS00    0
482#define CS01    1
483#define CS02    2
484#define WGM02   3
485#define FOC0B   6
486#define FOC0A   7
487
488#define TCNT0   _SFR_IO8(0x26)
489
490#define OCR0A   _SFR_IO8(0x27)
491
492#define OCR0B   _SFR_IO8(0x28)
493
494/* Reserved [0x29] */
495
496#define GPIOR1  _SFR_IO8(0x2A)
497#define GPIOR10 0
498#define GPIOR11 1
499#define GPIOR12 2
500#define GPIOR13 3
501#define GPIOR14 4
502#define GPIOR15 5
503#define GPIOR16 6
504#define GPIOR17 7
505
506#define GPIOR2  _SFR_IO8(0x2B)
507#define GPIOR20 0
508#define GPIOR21 1
509#define GPIOR22 2
510#define GPIOR23 3
511#define GPIOR24 4
512#define GPIOR25 5
513#define GPIOR26 6
514#define GPIOR27 7
515
516#define SPCR    _SFR_IO8(0x2C)
517#define SPR0    0
518#define SPR1    1
519#define CPHA    2
520#define CPOL    3
521#define MSTR    4
522#define DORD    5
523#define SPE     6
524#define SPIE    7
525
526#define SPSR    _SFR_IO8(0x2D)
527#define SPI2X   0
528#define WCOL    6
529#define SPIF    7
530
531#define SPDR    _SFR_IO8(0x2E)
532
533/* Reserved [0x2F] */
534
535#define ACSR    _SFR_IO8(0x30)
536#define ACIS0   0
537#define ACIS1   1
538#define ACIC    2
539#define ACIE    3
540#define ACI     4
541#define ACO     5
542#define ACBG    6
543#define ACD     7
544
545#define OCDR    _SFR_IO8(0x31)
546#define OCDR0   0
547#define OCDR1   1
548#define OCDR2   2
549#define OCDR3   3
550#define OCDR4   4
551#define OCDR5   5
552#define OCDR6   6
553#define OCDR7   7
554
555/* Reserved [0x32] */
556
557#define SMCR    _SFR_IO8(0x33)
558#define SE      0
559#define SM0     1
560#define SM1     2
561#define SM2     3
562
563#define MCUSR   _SFR_IO8(0x34)
564#define JTRF    4
565#define PORF    0
566#define EXTRF   1
567#define BORF    2
568#define WDRF    3
569
570#define MCUCR   _SFR_IO8(0x35)
571#define JTD     7
572#define IVCE    0
573#define IVSEL   1
574#define PUD     4
575
576/* Reserved [0x36] */
577
578#define SPMCSR  _SFR_IO8(0x37)
579#define SPMEN   0
580#define PGERS   1
581#define PGWRT   2
582#define BLBSET  3
583#define RWWSRE  4
584#define SIGRD   5
585#define RWWSB   6
586#define SPMIE   7
587
588/* Reserved [0x38..0x3A] */
589
590#define RAMPZ   _SFR_IO8(0x3B)
591#define RAMPZ0  0
592#define RAMPZ1  1
593#define Res5    7
594
595#define EIND    _SFR_IO8(0x3C)
596
597/* SP [0x3D..0x3E] */
598
599/* SREG [0x3F] */
600
601#define WDTCSR  _SFR_MEM8(0x60)
602#define WDE     3
603#define WDCE    4
604#define WDP0    0
605#define WDP1    1
606#define WDP2    2
607#define WDP3    5
608#define WDIE    6
609#define WDIF    7
610
611#define CLKPR   _SFR_MEM8(0x61)
612#define CLKPS0  0
613#define CLKPS1  1
614#define CLKPS2  2
615#define CLKPS3  3
616#define CLKPCE  7
617
618/* Reserved [0x62] */
619
620#define PRR2    _SFR_MEM8(0x63)
621#define PRRAM0  0
622#define PRRAM1  1
623#define PRRAM2  2
624#define PRRAM3  3
625
626#define __AVR_HAVE_PRR2 ((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3))
627#define __AVR_HAVE_PRR2_PRRAM0
628#define __AVR_HAVE_PRR2_PRRAM1
629#define __AVR_HAVE_PRR2_PRRAM2
630#define __AVR_HAVE_PRR2_PRRAM3
631
632#define PRR0    _SFR_MEM8(0x64)
633#define PRADC   0
634#define PRUSART0 1
635#define PRSPI   2
636#define PRTIM1  3
637#define PRPGA   4
638#define PRTIM0  5
639#define PRTIM2  6
640#define PRTWI   7
641
642#define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPGA)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
643#define __AVR_HAVE_PRR0_PRADC
644#define __AVR_HAVE_PRR0_PRUSART0
645#define __AVR_HAVE_PRR0_PRSPI
646#define __AVR_HAVE_PRR0_PRTIM1
647#define __AVR_HAVE_PRR0_PRPGA
648#define __AVR_HAVE_PRR0_PRTIM0
649#define __AVR_HAVE_PRR0_PRTIM2
650#define __AVR_HAVE_PRR0_PRTWI
651
652#define PRR1    _SFR_MEM8(0x65)
653#define PRUSART1 0
654#define PRTIM3  3
655#define PRTIM4  4
656#define PRTIM5  5
657#define PRTRX24 6
658#define Res     7
659
660#define __AVR_HAVE_PRR1 ((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24))
661#define __AVR_HAVE_PRR1_PRUSART1
662#define __AVR_HAVE_PRR1_PRTIM3
663#define __AVR_HAVE_PRR1_PRTIM4
664#define __AVR_HAVE_PRR1_PRTIM5
665#define __AVR_HAVE_PRR1_PRTRX24
666
667#define OSCCAL  _SFR_MEM8(0x66)
668#define CAL0    0
669#define CAL1    1
670#define CAL2    2
671#define CAL3    3
672#define CAL4    4
673#define CAL5    5
674#define CAL6    6
675#define CAL7    7
676#define OSCCAL0 0
677#define OSCCAL1 1
678#define OSCCAL2 2
679#define OSCCAL3 3
680#define OSCCAL4 4
681#define OSCCAL5 5
682#define OSCCAL6 6
683#define OSCCAL7 7
684
685#define BGCR    _SFR_MEM8(0x67)
686#define BGCAL0  0
687#define BGCAL1  1
688#define BGCAL2  2
689#define BGCAL_FINE0 3
690#define BGCAL_FINE1 4
691#define BGCAL_FINE2 5
692#define BGCAL_FINE3 6
693
694#define PCICR   _SFR_MEM8(0x68)
695#define PCIE0   0
696#define PCIE1   1
697#define PCIE2   2
698
699#define EICRA   _SFR_MEM8(0x69)
700#define ISC00   0
701#define ISC01   1
702#define ISC10   2
703#define ISC11   3
704#define ISC20   4
705#define ISC21   5
706#define ISC30   6
707#define ISC31   7
708
709#define EICRB   _SFR_MEM8(0x6A)
710#define ISC40   0
711#define ISC41   1
712#define ISC50   2
713#define ISC51   3
714#define ISC60   4
715#define ISC61   5
716#define ISC70   6
717#define ISC71   7
718
719#define PCMSK0  _SFR_MEM8(0x6B)
720#define PCINT0  0
721#define PCINT1  1
722#define PCINT2  2
723#define PCINT3  3
724#define PCINT4  4
725#define PCINT5  5
726#define PCINT6  6
727#define PCINT7  7
728
729#define PCMSK1  _SFR_MEM8(0x6C)
730#define PCINT8  0
731#define PCINT9  1
732#define PCINT10 2
733#define PCINT11 3
734#define PCINT12 4
735#define PCINT13 5
736#define PCINT14 6
737#define PCINT15 7
738
739#define PCMSK2  _SFR_MEM8(0x6D)
740#define PCINT16 0
741#define PCINT17 1
742#define PCINT18 2
743#define PCINT19 3
744#define PCINT20 4
745#define PCINT21 5
746#define PCINT22 6
747#define PCINT23 7
748
749#define TIMSK0  _SFR_MEM8(0x6E)
750#define TOIE0   0
751#define OCIE0A  1
752#define OCIE0B  2
753
754#define TIMSK1  _SFR_MEM8(0x6F)
755#define TOIE1   0
756#define OCIE1A  1
757#define OCIE1B  2
758#define OCIE1C  3
759#define ICIE1   5
760
761#define TIMSK2  _SFR_MEM8(0x70)
762#define TOIE2   0
763#define OCIE2A  1
764#define OCIE2B  2
765
766#define TIMSK3  _SFR_MEM8(0x71)
767#define TOIE3   0
768#define OCIE3A  1
769#define OCIE3B  2
770#define OCIE3C  3
771#define ICIE3   5
772
773#define TIMSK4  _SFR_MEM8(0x72)
774#define TOIE4   0
775#define OCIE4A  1
776#define OCIE4B  2
777#define OCIE4C  3
778#define ICIE4   5
779
780#define TIMSK5  _SFR_MEM8(0x73)
781#define TOIE5   0
782#define OCIE5A  1
783#define OCIE5B  2
784#define OCIE5C  3
785#define ICIE5   5
786
787/* Reserved [0x74] */
788
789#define NEMCR   _SFR_MEM8(0x75)
790#define AEAM0   4
791#define AEAM1   5
792#define ENEAM   6
793
794/* Reserved [0x76] */
795
796#define ADCSRC  _SFR_MEM8(0x77)
797#define ADSUT0  0
798#define ADSUT1  1
799#define ADSUT2  2
800#define ADSUT3  3
801#define ADSUT4  4
802#define ADTHT0  6
803#define ADTHT1  7
804
805/* Combine ADCL and ADCH */
806#ifndef __ASSEMBLER__
807#define ADC     _SFR_MEM16(0x78)
808#endif
809#define ADCW    _SFR_MEM16(0x78)
810
811#define ADCL    _SFR_MEM8(0x78)
812#define ADCH    _SFR_MEM8(0x79)
813
814#define ADCSRA  _SFR_MEM8(0x7A)
815#define ADPS0   0
816#define ADPS1   1
817#define ADPS2   2
818#define ADIE    3
819#define ADIF    4
820#define ADATE   5
821#define ADSC    6
822#define ADEN    7
823
824#define ADCSRB  _SFR_MEM8(0x7B)
825#define ACME    6
826#define ADTS0   0
827#define ADTS1   1
828#define ADTS2   2
829#define MUX5    3
830#define ACCH    4
831#define REFOK   5
832#define AVDDOK  7
833
834#define ADMUX   _SFR_MEM8(0x7C)
835#define MUX0    0
836#define MUX1    1
837#define MUX2    2
838#define MUX3    3
839#define MUX4    4
840#define ADLAR   5
841#define REFS0   6
842#define REFS1   7
843
844#define DIDR2   _SFR_MEM8(0x7D)
845#define ADC8D   0
846#define ADC9D   1
847#define ADC10D  2
848#define ADC11D  3
849#define ADC12D  4
850#define ADC13D  5
851#define ADC14D  6
852#define ADC15D  7
853
854#define DIDR0   _SFR_MEM8(0x7E)
855#define ADC0D   0
856#define ADC1D   1
857#define ADC2D   2
858#define ADC3D   3
859#define ADC4D   4
860#define ADC5D   5
861#define ADC6D   6
862#define ADC7D   7
863
864#define DIDR1   _SFR_MEM8(0x7F)
865#define AIN0D   0
866#define AIN1D   1
867
868#define TCCR1A  _SFR_MEM8(0x80)
869#define WGM10   0
870#define WGM11   1
871#define COM1C0  2
872#define COM1C1  3
873#define COM1B0  4
874#define COM1B1  5
875#define COM1A0  6
876#define COM1A1  7
877
878#define TCCR1B  _SFR_MEM8(0x81)
879#define CS10    0
880#define CS11    1
881#define CS12    2
882#define WGM12   3
883#define WGM13   4
884#define ICES1   6
885#define ICNC1   7
886
887#define TCCR1C  _SFR_MEM8(0x82)
888#define FOC1C   5
889#define FOC1B   6
890#define FOC1A   7
891
892/* Reserved [0x83] */
893
894/* Combine TCNT1L and TCNT1H */
895#define TCNT1   _SFR_MEM16(0x84)
896
897#define TCNT1L  _SFR_MEM8(0x84)
898#define TCNT1H  _SFR_MEM8(0x85)
899
900/* Combine ICR1L and ICR1H */
901#define ICR1    _SFR_MEM16(0x86)
902
903#define ICR1L   _SFR_MEM8(0x86)
904#define ICR1H   _SFR_MEM8(0x87)
905
906/* Combine OCR1AL and OCR1AH */
907#define OCR1A   _SFR_MEM16(0x88)
908
909#define OCR1AL  _SFR_MEM8(0x88)
910#define OCR1AH  _SFR_MEM8(0x89)
911
912/* Combine OCR1BL and OCR1BH */
913#define OCR1B   _SFR_MEM16(0x8A)
914
915#define OCR1BL  _SFR_MEM8(0x8A)
916#define OCR1BH  _SFR_MEM8(0x8B)
917
918/* Combine OCR1CL and OCR1CH */
919#define OCR1C   _SFR_MEM16(0x8C)
920
921#define OCR1CL  _SFR_MEM8(0x8C)
922#define OCR1CH  _SFR_MEM8(0x8D)
923
924/* Reserved [0x8E..0x8F] */
925
926#define TCCR3A  _SFR_MEM8(0x90)
927#define WGM30   0
928#define WGM31   1
929#define COM3C0  2
930#define COM3C1  3
931#define COM3B0  4
932#define COM3B1  5
933#define COM3A0  6
934#define COM3A1  7
935
936#define TCCR3B  _SFR_MEM8(0x91)
937#define CS30    0
938#define CS31    1
939#define CS32    2
940#define WGM32   3
941#define WGM33   4
942#define ICES3   6
943#define ICNC3   7
944
945#define TCCR3C  _SFR_MEM8(0x92)
946#define FOC3C   5
947#define FOC3B   6
948#define FOC3A   7
949
950/* Reserved [0x93] */
951
952/* Combine TCNT3L and TCNT3H */
953#define TCNT3   _SFR_MEM16(0x94)
954
955#define TCNT3L  _SFR_MEM8(0x94)
956#define TCNT3H  _SFR_MEM8(0x95)
957
958/* Combine ICR3L and ICR3H */
959#define ICR3    _SFR_MEM16(0x96)
960
961#define ICR3L   _SFR_MEM8(0x96)
962#define ICR3H   _SFR_MEM8(0x97)
963
964/* Combine OCR3AL and OCR3AH */
965#define OCR3A   _SFR_MEM16(0x98)
966
967#define OCR3AL  _SFR_MEM8(0x98)
968#define OCR3AH  _SFR_MEM8(0x99)
969
970/* Combine OCR3BL and OCR3BH */
971#define OCR3B   _SFR_MEM16(0x9A)
972
973#define OCR3BL  _SFR_MEM8(0x9A)
974#define OCR3BH  _SFR_MEM8(0x9B)
975
976/* Combine OCR3CL and OCR3CH */
977#define OCR3C   _SFR_MEM16(0x9C)
978
979#define OCR3CL  _SFR_MEM8(0x9C)
980#define OCR3CH  _SFR_MEM8(0x9D)
981
982/* Reserved [0x9E..0x9F] */
983
984#define TCCR4A  _SFR_MEM8(0xA0)
985#define WGM40   0
986#define WGM41   1
987#define COM4C0  2
988#define COM4C1  3
989#define COM4B0  4
990#define COM4B1  5
991#define COM4A0  6
992#define COM4A1  7
993
994#define TCCR4B  _SFR_MEM8(0xA1)
995#define CS40    0
996#define CS41    1
997#define CS42    2
998#define WGM42   3
999#define WGM43   4
1000#define ICES4   6
1001#define ICNC4   7
1002
1003#define TCCR4C  _SFR_MEM8(0xA2)
1004#define FOC4C   5
1005#define FOC4B   6
1006#define FOC4A   7
1007
1008/* Reserved [0xA3] */
1009
1010/* Combine TCNT4L and TCNT4H */
1011#define TCNT4   _SFR_MEM16(0xA4)
1012
1013#define TCNT4L  _SFR_MEM8(0xA4)
1014#define TCNT4H  _SFR_MEM8(0xA5)
1015
1016/* Combine ICR4L and ICR4H */
1017#define ICR4    _SFR_MEM16(0xA6)
1018
1019#define ICR4L   _SFR_MEM8(0xA6)
1020#define ICR4H   _SFR_MEM8(0xA7)
1021
1022/* Combine OCR4AL and OCR4AH */
1023#define OCR4A   _SFR_MEM16(0xA8)
1024
1025#define OCR4AL  _SFR_MEM8(0xA8)
1026#define OCR4AH  _SFR_MEM8(0xA9)
1027
1028/* Combine OCR4BL and OCR4BH */
1029#define OCR4B   _SFR_MEM16(0xAA)
1030
1031#define OCR4BL  _SFR_MEM8(0xAA)
1032#define OCR4BH  _SFR_MEM8(0xAB)
1033
1034/* Combine OCR4CL and OCR4CH */
1035#define OCR4C   _SFR_MEM16(0xAC)
1036
1037#define OCR4CL  _SFR_MEM8(0xAC)
1038#define OCR4CH  _SFR_MEM8(0xAD)
1039
1040/* Reserved [0xAE..0xAF] */
1041
1042#define TCCR2A  _SFR_MEM8(0xB0)
1043#define WGM20   0
1044#define WGM21   1
1045#define COM2B0  4
1046#define COM2B1  5
1047#define COM2A0  6
1048#define COM2A1  7
1049
1050#define TCCR2B  _SFR_MEM8(0xB1)
1051#define CS20    0
1052#define CS21    1
1053#define CS22    2
1054#define WGM22   3
1055#define FOC2B   6
1056#define FOC2A   7
1057
1058#define TCNT2   _SFR_MEM8(0xB2)
1059
1060#define OCR2A   _SFR_MEM8(0xB3)
1061
1062#define OCR2B   _SFR_MEM8(0xB4)
1063
1064/* Reserved [0xB5] */
1065
1066#define ASSR    _SFR_MEM8(0xB6)
1067#define TCR2BUB 0
1068#define TCR2AUB 1
1069#define OCR2BUB 2
1070#define OCR2AUB 3
1071#define TCN2UB  4
1072#define AS2     5
1073#define EXCLK   6
1074#define EXCLKAMR 7
1075
1076/* Reserved [0xB7] */
1077
1078#define TWBR    _SFR_MEM8(0xB8)
1079
1080#define TWSR    _SFR_MEM8(0xB9)
1081#define TWPS0   0
1082#define TWPS1   1
1083#define TWS3    3
1084#define TWS4    4
1085#define TWS5    5
1086#define TWS6    6
1087#define TWS7    7
1088
1089#define TWAR    _SFR_MEM8(0xBA)
1090#define TWGCE   0
1091#define TWA0    1
1092#define TWA1    2
1093#define TWA2    3
1094#define TWA3    4
1095#define TWA4    5
1096#define TWA5    6
1097#define TWA6    7
1098
1099#define TWDR    _SFR_MEM8(0xBB)
1100
1101#define TWCR    _SFR_MEM8(0xBC)
1102#define TWIE    0
1103#define TWEN    2
1104#define TWWC    3
1105#define TWSTO   4
1106#define TWSTA   5
1107#define TWEA    6
1108#define TWINT   7
1109
1110#define TWAMR   _SFR_MEM8(0xBD)
1111#define TWAM0   1
1112#define TWAM1   2
1113#define TWAM2   3
1114#define TWAM3   4
1115#define TWAM4   5
1116#define TWAM5   6
1117#define TWAM6   7
1118
1119#define IRQ_MASK1 _SFR_MEM8(0xBE)
1120#define TX_START_EN 0
1121#define MAF_0_AMI_EN 1
1122#define MAF_1_AMI_EN 2
1123#define MAF_2_AMI_EN 3
1124#define MAF_3_AMI_EN 4
1125
1126#define IRQ_STATUS1 _SFR_MEM8(0xBF)
1127#define TX_START 0
1128#define MAF_0_AMI 1
1129#define MAF_1_AMI 2
1130#define MAF_2_AMI 3
1131#define MAF_3_AMI 4
1132
1133#define UCSR0A  _SFR_MEM8(0xC0)
1134#define MPCM0   0
1135#define U2X0    1
1136#define UPE0    2
1137#define DOR0    3
1138#define FE0     4
1139#define UDRE0   5
1140#define TXC0    6
1141#define RXC0    7
1142
1143#define UCSR0B  _SFR_MEM8(0xC1)
1144#define TXB80   0
1145#define RXB80   1
1146#define UCSZ02  2
1147#define TXEN0   3
1148#define RXEN0   4
1149#define UDRIE0  5
1150#define TXCIE0  6
1151#define RXCIE0  7
1152
1153#define UCSR0C  _SFR_MEM8(0xC2)
1154#define UCPOL0  0
1155#define UCSZ00  1
1156#define UCSZ01  2
1157#define USBS0   3
1158#define UPM00   4
1159#define UPM01   5
1160#define UMSEL00 6
1161#define UMSEL01 7
1162#define UCPHA0  1
1163#define UDORD0  2
1164
1165/* Reserved [0xC3] */
1166
1167/* Combine UBRR0L and UBRR0H */
1168#define UBRR0   _SFR_MEM16(0xC4)
1169
1170#define UBRR0L  _SFR_MEM8(0xC4)
1171#define UBRR0H  _SFR_MEM8(0xC5)
1172
1173#define UDR0    _SFR_MEM8(0xC6)
1174
1175/* Reserved [0xC7] */
1176
1177#define UCSR1A  _SFR_MEM8(0xC8)
1178#define MPCM1   0
1179#define U2X1    1
1180#define UPE1    2
1181#define DOR1    3
1182#define FE1     4
1183#define UDRE1   5
1184#define TXC1    6
1185#define RXC1    7
1186
1187#define UCSR1B  _SFR_MEM8(0xC9)
1188#define TXB81   0
1189#define RXB81   1
1190#define UCSZ12  2
1191#define TXEN1   3
1192#define RXEN1   4
1193#define UDRIE1  5
1194#define TXCIE1  6
1195#define RXCIE1  7
1196
1197#define UCSR1C  _SFR_MEM8(0xCA)
1198#define UCPOL1  0
1199#define UCSZ10  1
1200#define UCSZ11  2
1201#define USBS1   3
1202#define UPM10   4
1203#define UPM11   5
1204#define UMSEL10 6
1205#define UMSEL11 7
1206#define UCPHA1  1
1207#define UDORD1  2
1208
1209/* Reserved [0xCB] */
1210
1211/* Combine UBRR1L and UBRR1H */
1212#define UBRR1   _SFR_MEM16(0xCC)
1213
1214#define UBRR1L  _SFR_MEM8(0xCC)
1215#define UBRR1H  _SFR_MEM8(0xCD)
1216
1217#define UDR1    _SFR_MEM8(0xCE)
1218
1219/* Reserved [0xCF..0xD6] */
1220
1221#define SCRSTRLL _SFR_MEM8(0xD7)
1222#define SCRSTRLL0 0
1223#define SCRSTRLL1 1
1224#define SCRSTRLL2 2
1225#define SCRSTRLL3 3
1226#define SCRSTRLL4 4
1227#define SCRSTRLL5 5
1228#define SCRSTRLL6 6
1229#define SCRSTRLL7 7
1230
1231#define SCRSTRLH _SFR_MEM8(0xD8)
1232#define SCRSTRLH0 0
1233#define SCRSTRLH1 1
1234#define SCRSTRLH2 2
1235#define SCRSTRLH3 3
1236#define SCRSTRLH4 4
1237#define SCRSTRLH5 5
1238#define SCRSTRLH6 6
1239#define SCRSTRLH7 7
1240
1241#define SCRSTRHL _SFR_MEM8(0xD9)
1242#define SCRSTRHL0 0
1243#define SCRSTRHL1 1
1244#define SCRSTRHL2 2
1245#define SCRSTRHL3 3
1246#define SCRSTRHL4 4
1247#define SCRSTRHL5 5
1248#define SCRSTRHL6 6
1249#define SCRSTRHL7 7
1250
1251#define SCRSTRHH _SFR_MEM8(0xDA)
1252#define SCRSTRHH0 0
1253#define SCRSTRHH1 1
1254#define SCRSTRHH2 2
1255#define SCRSTRHH3 3
1256#define SCRSTRHH4 4
1257#define SCRSTRHH5 5
1258#define SCRSTRHH6 6
1259#define SCRSTRHH7 7
1260
1261#define SCCSR   _SFR_MEM8(0xDB)
1262#define SCCS10  0
1263#define SCCS11  1
1264#define SCCS20  2
1265#define SCCS21  3
1266#define SCCS30  4
1267#define SCCS31  5
1268
1269#define SCCR0   _SFR_MEM8(0xDC)
1270#define SCCMP1  0
1271#define SCCMP2  1
1272#define SCCMP3  2
1273#define SCTSE   3
1274#define SCCKSEL 4
1275#define SCEN    5
1276#define SCMBTS  6
1277#define SCRES   7
1278
1279#define SCCR1   _SFR_MEM8(0xDD)
1280#define SCENBO  0
1281#define SCEECLK 1
1282#define SCCKDIV0 2
1283#define SCCKDIV1 3
1284#define SCCKDIV2 4
1285#define SCBTSM  5
1286#define Res6    7
1287
1288#define SCSR    _SFR_MEM8(0xDE)
1289#define SCBSY   0
1290
1291#define SCIRQM  _SFR_MEM8(0xDF)
1292#define IRQMCP1 0
1293#define IRQMCP2 1
1294#define IRQMCP3 2
1295#define IRQMOF  3
1296#define IRQMBO  4
1297
1298#define SCIRQS  _SFR_MEM8(0xE0)
1299#define IRQSCP1 0
1300#define IRQSCP2 1
1301#define IRQSCP3 2
1302#define IRQSOF  3
1303#define IRQSBO  4
1304
1305#define SCCNTLL _SFR_MEM8(0xE1)
1306#define SCCNTLL0 0
1307#define SCCNTLL1 1
1308#define SCCNTLL2 2
1309#define SCCNTLL3 3
1310#define SCCNTLL4 4
1311#define SCCNTLL5 5
1312#define SCCNTLL6 6
1313#define SCCNTLL7 7
1314
1315#define SCCNTLH _SFR_MEM8(0xE2)
1316#define SCCNTLH0 0
1317#define SCCNTLH1 1
1318#define SCCNTLH2 2
1319#define SCCNTLH3 3
1320#define SCCNTLH4 4
1321#define SCCNTLH5 5
1322#define SCCNTLH6 6
1323#define SCCNTLH7 7
1324
1325#define SCCNTHL _SFR_MEM8(0xE3)
1326#define SCCNTHL0 0
1327#define SCCNTHL1 1
1328#define SCCNTHL2 2
1329#define SCCNTHL3 3
1330#define SCCNTHL4 4
1331#define SCCNTHL5 5
1332#define SCCNTHL6 6
1333#define SCCNTHL7 7
1334
1335#define SCCNTHH _SFR_MEM8(0xE4)
1336#define SCCNTHH0 0
1337#define SCCNTHH1 1
1338#define SCCNTHH2 2
1339#define SCCNTHH3 3
1340#define SCCNTHH4 4
1341#define SCCNTHH5 5
1342#define SCCNTHH6 6
1343#define SCCNTHH7 7
1344
1345#define SCBTSRLL _SFR_MEM8(0xE5)
1346#define SCBTSRLL0 0
1347#define SCBTSRLL1 1
1348#define SCBTSRLL2 2
1349#define SCBTSRLL3 3
1350#define SCBTSRLL4 4
1351#define SCBTSRLL5 5
1352#define SCBTSRLL6 6
1353#define SCBTSRLL7 7
1354
1355#define SCBTSRLH _SFR_MEM8(0xE6)
1356#define SCBTSRLH0 0
1357#define SCBTSRLH1 1
1358#define SCBTSRLH2 2
1359#define SCBTSRLH3 3
1360#define SCBTSRLH4 4
1361#define SCBTSRLH5 5
1362#define SCBTSRLH6 6
1363#define SCBTSRLH7 7
1364
1365#define SCBTSRHL _SFR_MEM8(0xE7)
1366#define SCBTSRHL0 0
1367#define SCBTSRHL1 1
1368#define SCBTSRHL2 2
1369#define SCBTSRHL3 3
1370#define SCBTSRHL4 4
1371#define SCBTSRHL5 5
1372#define SCBTSRHL6 6
1373#define SCBTSRHL7 7
1374
1375#define SCBTSRHH _SFR_MEM8(0xE8)
1376#define SCBTSRHH0 0
1377#define SCBTSRHH1 1
1378#define SCBTSRHH2 2
1379#define SCBTSRHH3 3
1380#define SCBTSRHH4 4
1381#define SCBTSRHH5 5
1382#define SCBTSRHH6 6
1383#define SCBTSRHH7 7
1384
1385#define SCTSRLL _SFR_MEM8(0xE9)
1386#define SCTSRLL0 0
1387#define SCTSRLL1 1
1388#define SCTSRLL2 2
1389#define SCTSRLL3 3
1390#define SCTSRLL4 4
1391#define SCTSRLL5 5
1392#define SCTSRLL6 6
1393#define SCTSRLL7 7
1394
1395#define SCTSRLH _SFR_MEM8(0xEA)
1396#define SCTSRLH0 0
1397#define SCTSRLH1 1
1398#define SCTSRLH2 2
1399#define SCTSRLH3 3
1400#define SCTSRLH4 4
1401#define SCTSRLH5 5
1402#define SCTSRLH6 6
1403#define SCTSRLH7 7
1404
1405#define SCTSRHL _SFR_MEM8(0xEB)
1406#define SCTSRHL0 0
1407#define SCTSRHL1 1
1408#define SCTSRHL2 2
1409#define SCTSRHL3 3
1410#define SCTSRHL4 4
1411#define SCTSRHL5 5
1412#define SCTSRHL6 6
1413#define SCTSRHL7 7
1414
1415#define SCTSRHH _SFR_MEM8(0xEC)
1416#define SCTSRHH0 0
1417#define SCTSRHH1 1
1418#define SCTSRHH2 2
1419#define SCTSRHH3 3
1420#define SCTSRHH4 4
1421#define SCTSRHH5 5
1422#define SCTSRHH6 6
1423#define SCTSRHH7 7
1424
1425#define SCOCR3LL _SFR_MEM8(0xED)
1426#define SCOCR3LL0 0
1427#define SCOCR3LL1 1
1428#define SCOCR3LL2 2
1429#define SCOCR3LL3 3
1430#define SCOCR3LL4 4
1431#define SCOCR3LL5 5
1432#define SCOCR3LL6 6
1433#define SCOCR3LL7 7
1434
1435#define SCOCR3LH _SFR_MEM8(0xEE)
1436#define SCOCR3LH0 0
1437#define SCOCR3LH1 1
1438#define SCOCR3LH2 2
1439#define SCOCR3LH3 3
1440#define SCOCR3LH4 4
1441#define SCOCR3LH5 5
1442#define SCOCR3LH6 6
1443#define SCOCR3LH7 7
1444
1445#define SCOCR3HL _SFR_MEM8(0xEF)
1446#define SCOCR3HL0 0
1447#define SCOCR3HL1 1
1448#define SCOCR3HL2 2
1449#define SCOCR3HL3 3
1450#define SCOCR3HL4 4
1451#define SCOCR3HL5 5
1452#define SCOCR3HL6 6
1453#define SCOCR3HL7 7
1454
1455#define SCOCR3HH _SFR_MEM8(0xF0)
1456#define SCOCR3HH0 0
1457#define SCOCR3HH1 1
1458#define SCOCR3HH2 2
1459#define SCOCR3HH3 3
1460#define SCOCR3HH4 4
1461#define SCOCR3HH5 5
1462#define SCOCR3HH6 6
1463#define SCOCR3HH7 7
1464
1465#define SCOCR2LL _SFR_MEM8(0xF1)
1466#define SCOCR2LL0 0
1467#define SCOCR2LL1 1
1468#define SCOCR2LL2 2
1469#define SCOCR2LL3 3
1470#define SCOCR2LL4 4
1471#define SCOCR2LL5 5
1472#define SCOCR2LL6 6
1473#define SCOCR2LL7 7
1474
1475#define SCOCR2LH _SFR_MEM8(0xF2)
1476#define SCOCR2LH0 0
1477#define SCOCR2LH1 1
1478#define SCOCR2LH2 2
1479#define SCOCR2LH3 3
1480#define SCOCR2LH4 4
1481#define SCOCR2LH5 5
1482#define SCOCR2LH6 6
1483#define SCOCR2LH7 7
1484
1485#define SCOCR2HL _SFR_MEM8(0xF3)
1486#define SCOCR2HL0 0
1487#define SCOCR2HL1 1
1488#define SCOCR2HL2 2
1489#define SCOCR2HL3 3
1490#define SCOCR2HL4 4
1491#define SCOCR2HL5 5
1492#define SCOCR2HL6 6
1493#define SCOCR2HL7 7
1494
1495#define SCOCR2HH _SFR_MEM8(0xF4)
1496#define SCOCR2HH0 0
1497#define SCOCR2HH1 1
1498#define SCOCR2HH2 2
1499#define SCOCR2HH3 3
1500#define SCOCR2HH4 4
1501#define SCOCR2HH5 5
1502#define SCOCR2HH6 6
1503#define SCOCR2HH7 7
1504
1505#define SCOCR1LL _SFR_MEM8(0xF5)
1506#define SCOCR1LL0 0
1507#define SCOCR1LL1 1
1508#define SCOCR1LL2 2
1509#define SCOCR1LL3 3
1510#define SCOCR1LL4 4
1511#define SCOCR1LL5 5
1512#define SCOCR1LL6 6
1513#define SCOCR1LL7 7
1514
1515#define SCOCR1LH _SFR_MEM8(0xF6)
1516#define SCOCR1LH0 0
1517#define SCOCR1LH1 1
1518#define SCOCR1LH2 2
1519#define SCOCR1LH3 3
1520#define SCOCR1LH4 4
1521#define SCOCR1LH5 5
1522#define SCOCR1LH6 6
1523#define SCOCR1LH7 7
1524
1525#define SCOCR1HL _SFR_MEM8(0xF7)
1526#define SCOCR1HL0 0
1527#define SCOCR1HL1 1
1528#define SCOCR1HL2 2
1529#define SCOCR1HL3 3
1530#define SCOCR1HL4 4
1531#define SCOCR1HL5 5
1532#define SCOCR1HL6 6
1533#define SCOCR1HL7 7
1534
1535#define SCOCR1HH _SFR_MEM8(0xF8)
1536#define SCOCR1HH0 0
1537#define SCOCR1HH1 1
1538#define SCOCR1HH2 2
1539#define SCOCR1HH3 3
1540#define SCOCR1HH4 4
1541#define SCOCR1HH5 5
1542#define SCOCR1HH6 6
1543#define SCOCR1HH7 7
1544
1545#define SCTSTRLL _SFR_MEM8(0xF9)
1546#define SCTSTRLL0 0
1547#define SCTSTRLL1 1
1548#define SCTSTRLL2 2
1549#define SCTSTRLL3 3
1550#define SCTSTRLL4 4
1551#define SCTSTRLL5 5
1552#define SCTSTRLL6 6
1553#define SCTSTRLL7 7
1554
1555#define SCTSTRLH _SFR_MEM8(0xFA)
1556#define SCTSTRLH0 0
1557#define SCTSTRLH1 1
1558#define SCTSTRLH2 2
1559#define SCTSTRLH3 3
1560#define SCTSTRLH4 4
1561#define SCTSTRLH5 5
1562#define SCTSTRLH6 6
1563#define SCTSTRLH7 7
1564
1565#define SCTSTRHL _SFR_MEM8(0xFB)
1566#define SCTSTRHL0 0
1567#define SCTSTRHL1 1
1568#define SCTSTRHL2 2
1569#define SCTSTRHL3 3
1570#define SCTSTRHL4 4
1571#define SCTSTRHL5 5
1572#define SCTSTRHL6 6
1573#define SCTSTRHL7 7
1574
1575#define SCTSTRHH _SFR_MEM8(0xFC)
1576#define SCTSTRHH0 0
1577#define SCTSTRHH1 1
1578#define SCTSTRHH2 2
1579#define SCTSTRHH3 3
1580#define SCTSTRHH4 4
1581#define SCTSTRHH5 5
1582#define SCTSTRHH6 6
1583#define SCTSTRHH7 7
1584
1585/* Reserved [0xFD..0x10B] */
1586
1587#define MAFCR0  _SFR_MEM8(0x10C)
1588#define MAF0EN  0
1589#define MAF1EN  1
1590#define MAF2EN  2
1591#define MAF3EN  3
1592
1593#define MAFCR1  _SFR_MEM8(0x10D)
1594#define AACK_0_I_AM_COORD 0
1595#define AACK_0_SET_PD 1
1596#define AACK_1_I_AM_COORD 2
1597#define AACK_1_SET_PD 3
1598#define AACK_2_I_AM_COORD 4
1599#define AACK_2_SET_PD 5
1600#define AACK_3_I_AM_COORD 6
1601#define AACK_3_SET_PD 7
1602
1603#define MAFSA0L _SFR_MEM8(0x10E)
1604#define MAFSA0L0 0
1605#define MAFSA0L1 1
1606#define MAFSA0L2 2
1607#define MAFSA0L3 3
1608#define MAFSA0L4 4
1609#define MAFSA0L5 5
1610#define MAFSA0L6 6
1611#define MAFSA0L7 7
1612
1613#define MAFSA0H _SFR_MEM8(0x10F)
1614#define MAFSA0H0 0
1615#define MAFSA0H1 1
1616#define MAFSA0H2 2
1617#define MAFSA0H3 3
1618#define MAFSA0H4 4
1619#define MAFSA0H5 5
1620#define MAFSA0H6 6
1621#define MAFSA0H7 7
1622
1623#define MAFPA0L _SFR_MEM8(0x110)
1624#define MAFPA0L0 0
1625#define MAFPA0L1 1
1626#define MAFPA0L2 2
1627#define MAFPA0L3 3
1628#define MAFPA0L4 4
1629#define MAFPA0L5 5
1630#define MAFPA0L6 6
1631#define MAFPA0L7 7
1632
1633#define MAFPA0H _SFR_MEM8(0x111)
1634#define MAFPA0H0 0
1635#define MAFPA0H1 1
1636#define MAFPA0H2 2
1637#define MAFPA0H3 3
1638#define MAFPA0H4 4
1639#define MAFPA0H5 5
1640#define MAFPA0H6 6
1641#define MAFPA0H7 7
1642
1643#define MAFSA1L _SFR_MEM8(0x112)
1644#define MAFSA1L0 0
1645#define MAFSA1L1 1
1646#define MAFSA1L2 2
1647#define MAFSA1L3 3
1648#define MAFSA1L4 4
1649#define MAFSA1L5 5
1650#define MAFSA1L6 6
1651#define MAFSA1L7 7
1652
1653#define MAFSA1H _SFR_MEM8(0x113)
1654#define MAFSA1H0 0
1655#define MAFSA1H1 1
1656#define MAFSA1H2 2
1657#define MAFSA1H3 3
1658#define MAFSA1H4 4
1659#define MAFSA1H5 5
1660#define MAFSA1H6 6
1661#define MAFSA1H7 7
1662
1663#define MAFPA1L _SFR_MEM8(0x114)
1664#define MAFPA1L0 0
1665#define MAFPA1L1 1
1666#define MAFPA1L2 2
1667#define MAFPA1L3 3
1668#define MAFPA1L4 4
1669#define MAFPA1L5 5
1670#define MAFPA1L6 6
1671#define MAFPA1L7 7
1672
1673#define MAFPA1H _SFR_MEM8(0x115)
1674#define MAFPA1H0 0
1675#define MAFPA1H1 1
1676#define MAFPA1H2 2
1677#define MAFPA1H3 3
1678#define MAFPA1H4 4
1679#define MAFPA1H5 5
1680#define MAFPA1H6 6
1681#define MAFPA1H7 7
1682
1683#define MAFSA2L _SFR_MEM8(0x116)
1684#define MAFSA2L0 0
1685#define MAFSA2L1 1
1686#define MAFSA2L2 2
1687#define MAFSA2L3 3
1688#define MAFSA2L4 4
1689#define MAFSA2L5 5
1690#define MAFSA2L6 6
1691#define MAFSA2L7 7
1692
1693#define MAFSA2H _SFR_MEM8(0x117)
1694#define MAFSA2H0 0
1695#define MAFSA2H1 1
1696#define MAFSA2H2 2
1697#define MAFSA2H3 3
1698#define MAFSA2H4 4
1699#define MAFSA2H5 5
1700#define MAFSA2H6 6
1701#define MAFSA2H7 7
1702
1703#define MAFPA2L _SFR_MEM8(0x118)
1704#define MAFPA2L0 0
1705#define MAFPA2L1 1
1706#define MAFPA2L2 2
1707#define MAFPA2L3 3
1708#define MAFPA2L4 4
1709#define MAFPA2L5 5
1710#define MAFPA2L6 6
1711#define MAFPA2L7 7
1712
1713#define MAFPA2H _SFR_MEM8(0x119)
1714#define MAFPA2H0 0
1715#define MAFPA2H1 1
1716#define MAFPA2H2 2
1717#define MAFPA2H3 3
1718#define MAFPA2H4 4
1719#define MAFPA2H5 5
1720#define MAFPA2H6 6
1721#define MAFPA2H7 7
1722
1723#define MAFSA3L _SFR_MEM8(0x11A)
1724#define MAFSA3L0 0
1725#define MAFSA3L1 1
1726#define MAFSA3L2 2
1727#define MAFSA3L3 3
1728#define MAFSA3L4 4
1729#define MAFSA3L5 5
1730#define MAFSA3L6 6
1731#define MAFSA3L7 7
1732
1733#define MAFSA3H _SFR_MEM8(0x11B)
1734#define MAFSA3H0 0
1735#define MAFSA3H1 1
1736#define MAFSA3H2 2
1737#define MAFSA3H3 3
1738#define MAFSA3H4 4
1739#define MAFSA3H5 5
1740#define MAFSA3H6 6
1741#define MAFSA3H7 7
1742
1743#define MAFPA3L _SFR_MEM8(0x11C)
1744#define MAFPA3L0 0
1745#define MAFPA3L1 1
1746#define MAFPA3L2 2
1747#define MAFPA3L3 3
1748#define MAFPA3L4 4
1749#define MAFPA3L5 5
1750#define MAFPA3L6 6
1751#define MAFPA3L7 7
1752
1753#define MAFPA3H _SFR_MEM8(0x11D)
1754#define MAFPA3H0 0
1755#define MAFPA3H1 1
1756#define MAFPA3H2 2
1757#define MAFPA3H3 3
1758#define MAFPA3H4 4
1759#define MAFPA3H5 5
1760#define MAFPA3H6 6
1761#define MAFPA3H7 7
1762
1763/* Reserved [0x11E..0x11F] */
1764
1765#define TCCR5A  _SFR_MEM8(0x120)
1766#define WGM50   0
1767#define WGM51   1
1768#define COM5C0  2
1769#define COM5C1  3
1770#define COM5B0  4
1771#define COM5B1  5
1772#define COM5A0  6
1773#define COM5A1  7
1774
1775#define TCCR5B  _SFR_MEM8(0x121)
1776#define CS50    0
1777#define CS51    1
1778#define CS52    2
1779#define WGM52   3
1780#define WGM53   4
1781#define ICES5   6
1782#define ICNC5   7
1783
1784#define TCCR5C  _SFR_MEM8(0x122)
1785#define FOC5C   5
1786#define FOC5B   6
1787#define FOC5A   7
1788
1789/* Reserved [0x123] */
1790
1791/* Combine TCNT5L and TCNT5H */
1792#define TCNT5   _SFR_MEM16(0x124)
1793
1794#define TCNT5L  _SFR_MEM8(0x124)
1795#define TCNT5H  _SFR_MEM8(0x125)
1796
1797/* Combine ICR5L and ICR5H */
1798#define ICR5    _SFR_MEM16(0x126)
1799
1800#define ICR5L   _SFR_MEM8(0x126)
1801#define ICR5H   _SFR_MEM8(0x127)
1802
1803/* Combine OCR5AL and OCR5AH */
1804#define OCR5A   _SFR_MEM16(0x128)
1805
1806#define OCR5AL  _SFR_MEM8(0x128)
1807#define OCR5AH  _SFR_MEM8(0x129)
1808
1809/* Combine OCR5BL and OCR5BH */
1810#define OCR5B   _SFR_MEM16(0x12A)
1811
1812#define OCR5BL  _SFR_MEM8(0x12A)
1813#define OCR5BH  _SFR_MEM8(0x12B)
1814
1815/* Combine OCR5CL and OCR5CH */
1816#define OCR5C   _SFR_MEM16(0x12C)
1817
1818#define OCR5CL  _SFR_MEM8(0x12C)
1819#define OCR5CH  _SFR_MEM8(0x12D)
1820
1821/* Reserved [0x12E] */
1822
1823#define LLCR    _SFR_MEM8(0x12F)
1824#define LLENCAL 0
1825#define LLSHORT 1
1826#define LLTCO   2
1827#define LLCAL   3
1828#define LLCOMP  4
1829#define LLDONE  5
1830
1831#define LLDRL   _SFR_MEM8(0x130)
1832#define LLDRL0  0
1833#define LLDRL1  1
1834#define LLDRL2  2
1835#define LLDRL3  3
1836
1837#define LLDRH   _SFR_MEM8(0x131)
1838#define LLDRH0  0
1839#define LLDRH1  1
1840#define LLDRH2  2
1841#define LLDRH3  3
1842#define LLDRH4  4
1843
1844#define DRTRAM3 _SFR_MEM8(0x132)
1845#define ENDRT   4
1846#define DRTSWOK 5
1847
1848#define DRTRAM2 _SFR_MEM8(0x133)
1849
1850#define DRTRAM1 _SFR_MEM8(0x134)
1851
1852#define DRTRAM0 _SFR_MEM8(0x135)
1853
1854#define DPDS0   _SFR_MEM8(0x136)
1855#define PBDRV0  0
1856#define PBDRV1  1
1857#define PDDRV0  2
1858#define PDDRV1  3
1859#define PEDRV0  4
1860#define PEDRV1  5
1861#define PFDRV0  6
1862#define PFDRV1  7
1863
1864#define DPDS1   _SFR_MEM8(0x137)
1865#define PGDRV0  0
1866#define PGDRV1  1
1867
1868#define PARCR   _SFR_MEM8(0x138)
1869#define PARUFI  0
1870#define PARDFI  1
1871#define PALTU0  2
1872#define PALTU1  3
1873#define PALTU2  4
1874#define PALTD0  5
1875#define PALTD1  6
1876#define PALTD2  7
1877
1878#define TRXPR   _SFR_MEM8(0x139)
1879#define TRXRST  0
1880#define SLPTR   1
1881
1882/* Reserved [0x13A..0x13B] */
1883
1884#define AES_CTRL _SFR_MEM8(0x13C)
1885#define AES_IM  2
1886#define AES_DIR 3
1887#define AES_MODE 5
1888#define AES_REQUEST 7
1889
1890#define AES_STATUS _SFR_MEM8(0x13D)
1891#define AES_DONE 0
1892#define AES_ER  7
1893
1894#define AES_STATE _SFR_MEM8(0x13E)
1895#define AES_STATE0 0
1896#define AES_STATE1 1
1897#define AES_STATE2 2
1898#define AES_STATE3 3
1899#define AES_STATE4 4
1900#define AES_STATE5 5
1901#define AES_STATE6 6
1902#define AES_STATE7 7
1903
1904#define AES_KEY _SFR_MEM8(0x13F)
1905#define AES_KEY0 0
1906#define AES_KEY1 1
1907#define AES_KEY2 2
1908#define AES_KEY3 3
1909#define AES_KEY4 4
1910#define AES_KEY5 5
1911#define AES_KEY6 6
1912#define AES_KEY7 7
1913
1914/* Reserved [0x140] */
1915
1916#define TRX_STATUS _SFR_MEM8(0x141)
1917#define TRX_STATUS0 0
1918#define TRX_STATUS1 1
1919#define TRX_STATUS2 2
1920#define TRX_STATUS3 3
1921#define TRX_STATUS4 4
1922#define TST_STATUS 5
1923#define CCA_STATUS 6
1924#define CCA_DONE 7
1925
1926#define TRX_STATE _SFR_MEM8(0x142)
1927#define TRX_CMD0 0
1928#define TRX_CMD1 1
1929#define TRX_CMD2 2
1930#define TRX_CMD3 3
1931#define TRX_CMD4 4
1932#define TRAC_STATUS0 5
1933#define TRAC_STATUS1 6
1934#define TRAC_STATUS2 7
1935
1936#define TRX_CTRL_0 _SFR_MEM8(0x143)
1937#define PMU_IF_INV 4
1938#define PMU_START 5
1939#define PMU_EN  6
1940#define Res7    7
1941
1942#define TRX_CTRL_1 _SFR_MEM8(0x144)
1943#define PLL_TX_FLT 4
1944#define TX_AUTO_CRC_ON 5
1945#define IRQ_2_EXT_EN 6
1946#define PA_EXT_EN 7
1947
1948#define PHY_TX_PWR _SFR_MEM8(0x145)
1949#define TX_PWR0 0
1950#define TX_PWR1 1
1951#define TX_PWR2 2
1952#define TX_PWR3 3
1953
1954#define PHY_RSSI _SFR_MEM8(0x146)
1955#define RSSI0   0
1956#define RSSI1   1
1957#define RSSI2   2
1958#define RSSI3   3
1959#define RSSI4   4
1960#define RND_VALUE0 5
1961#define RND_VALUE1 6
1962#define RX_CRC_VALID 7
1963
1964#define PHY_ED_LEVEL _SFR_MEM8(0x147)
1965#define ED_LEVEL0 0
1966#define ED_LEVEL1 1
1967#define ED_LEVEL2 2
1968#define ED_LEVEL3 3
1969#define ED_LEVEL4 4
1970#define ED_LEVEL5 5
1971#define ED_LEVEL6 6
1972#define ED_LEVEL7 7
1973
1974#define PHY_CC_CCA _SFR_MEM8(0x148)
1975#define CHANNEL0 0
1976#define CHANNEL1 1
1977#define CHANNEL2 2
1978#define CHANNEL3 3
1979#define CHANNEL4 4
1980#define CCA_MODE0 5
1981#define CCA_MODE1 6
1982#define CCA_REQUEST 7
1983
1984#define CCA_THRES _SFR_MEM8(0x149)
1985#define CCA_ED_THRES0 0
1986#define CCA_ED_THRES1 1
1987#define CCA_ED_THRES2 2
1988#define CCA_ED_THRES3 3
1989#define CCA_CS_THRES0 4
1990#define CCA_CS_THRES1 5
1991#define CCA_CS_THRES2 6
1992#define CCA_CS_THRES3 7
1993
1994#define RX_CTRL _SFR_MEM8(0x14A)
1995#define PDT_THRES0 0
1996#define PDT_THRES1 1
1997#define PDT_THRES2 2
1998#define PDT_THRES3 3
1999
2000#define SFD_VALUE _SFR_MEM8(0x14B)
2001#define SFD_VALUE0 0
2002#define SFD_VALUE1 1
2003#define SFD_VALUE2 2
2004#define SFD_VALUE3 3
2005#define SFD_VALUE4 4
2006#define SFD_VALUE5 5
2007#define SFD_VALUE6 6
2008#define SFD_VALUE7 7
2009
2010#define TRX_CTRL_2 _SFR_MEM8(0x14C)
2011#define OQPSK_DATA_RATE0 0
2012#define OQPSK_DATA_RATE1 1
2013#define RX_SAFE_MODE 7
2014
2015#define ANT_DIV _SFR_MEM8(0x14D)
2016#define ANT_CTRL0 0
2017#define ANT_CTRL1 1
2018#define ANT_EXT_SW_EN 2
2019#define ANT_DIV_EN 3
2020#define ANT_SEL 7
2021
2022#define IRQ_MASK _SFR_MEM8(0x14E)
2023#define PLL_LOCK_EN 0
2024#define PLL_UNLOCK_EN 1
2025#define RX_START_EN 2
2026#define RX_END_EN 3
2027#define CCA_ED_DONE_EN 4
2028#define AMI_EN  5
2029#define TX_END_EN 6
2030#define AWAKE_EN 7
2031
2032#define IRQ_STATUS _SFR_MEM8(0x14F)
2033#define PLL_LOCK 0
2034#define PLL_UNLOCK 1
2035#define RX_START 2
2036#define RX_END  3
2037#define CCA_ED_DONE 4
2038#define AMI     5
2039#define TX_END  6
2040#define AWAKE   7
2041
2042#define VREG_CTRL _SFR_MEM8(0x150)
2043#define DVDD_OK 2
2044#define DVREG_EXT 3
2045#define AVDD_OK 6
2046#define AVREG_EXT 7
2047
2048#define BATMON  _SFR_MEM8(0x151)
2049#define BATMON_VTH0 0
2050#define BATMON_VTH1 1
2051#define BATMON_VTH2 2
2052#define BATMON_VTH3 3
2053#define BATMON_HR 4
2054#define BATMON_OK 5
2055#define BAT_LOW_EN 6
2056#define BAT_LOW 7
2057
2058#define XOSC_CTRL _SFR_MEM8(0x152)
2059#define XTAL_TRIM0 0
2060#define XTAL_TRIM1 1
2061#define XTAL_TRIM2 2
2062#define XTAL_TRIM3 3
2063#define XTAL_MODE0 4
2064#define XTAL_MODE1 5
2065#define XTAL_MODE2 6
2066#define XTAL_MODE3 7
2067
2068#define CC_CTRL_0 _SFR_MEM8(0x153)
2069#define CC_NUMBER0 0
2070#define CC_NUMBER1 1
2071#define CC_NUMBER2 2
2072#define CC_NUMBER3 3
2073#define CC_NUMBER4 4
2074#define CC_NUMBER5 5
2075#define CC_NUMBER6 6
2076#define CC_NUMBER7 7
2077
2078#define CC_CTRL_1 _SFR_MEM8(0x154)
2079#define CC_BAND0 0
2080#define CC_BAND1 1
2081#define CC_BAND2 2
2082#define CC_BAND3 3
2083
2084#define RX_SYN  _SFR_MEM8(0x155)
2085#define RX_PDT_LEVEL0 0
2086#define RX_PDT_LEVEL1 1
2087#define RX_PDT_LEVEL2 2
2088#define RX_PDT_LEVEL3 3
2089#define RX_OVERRIDE 6
2090#define RX_PDT_DIS 7
2091
2092#define TRX_RPC _SFR_MEM8(0x156)
2093#define XAH_RPC_EN 0
2094#define IPAN_RPC_EN 1
2095#define PLL_RPC_EN 3
2096#define PDT_RPC_EN 4
2097#define RX_RPC_EN 5
2098#define RX_RPC_CTRL0 6
2099#define RX_RPC_CTRL1 7
2100
2101#define XAH_CTRL_1 _SFR_MEM8(0x157)
2102#define AACK_PROM_MODE 1
2103#define AACK_ACK_TIME 2
2104#define AACK_UPLD_RES_FT 4
2105#define AACK_FLTR_RES_FT 5
2106
2107#define FTN_CTRL _SFR_MEM8(0x158)
2108#define FTN_START 7
2109
2110/* Reserved [0x159] */
2111
2112#define PLL_CF  _SFR_MEM8(0x15A)
2113#define PLL_CF_START 7
2114
2115#define PLL_DCU _SFR_MEM8(0x15B)
2116#define PLL_DCU_START 7
2117
2118#define PART_NUM _SFR_MEM8(0x15C)
2119#define PART_NUM0 0
2120#define PART_NUM1 1
2121#define PART_NUM2 2
2122#define PART_NUM3 3
2123#define PART_NUM4 4
2124#define PART_NUM5 5
2125#define PART_NUM6 6
2126#define PART_NUM7 7
2127
2128#define VERSION_NUM _SFR_MEM8(0x15D)
2129#define VERSION_NUM0 0
2130#define VERSION_NUM1 1
2131#define VERSION_NUM2 2
2132#define VERSION_NUM3 3
2133#define VERSION_NUM4 4
2134#define VERSION_NUM5 5
2135#define VERSION_NUM6 6
2136#define VERSION_NUM7 7
2137
2138#define MAN_ID_0 _SFR_MEM8(0x15E)
2139#define MAN_ID_00 0
2140#define MAN_ID_01 1
2141#define MAN_ID_02 2
2142#define MAN_ID_03 3
2143#define MAN_ID_04 4
2144#define MAN_ID_05 5
2145#define MAN_ID_06 6
2146#define MAN_ID_07 7
2147
2148#define MAN_ID_1 _SFR_MEM8(0x15F)
2149#define MAN_ID_10 0
2150#define MAN_ID_11 1
2151#define MAN_ID_12 2
2152#define MAN_ID_13 3
2153#define MAN_ID_14 4
2154#define MAN_ID_15 5
2155#define MAN_ID_16 6
2156#define MAN_ID_17 7
2157
2158#define SHORT_ADDR_0 _SFR_MEM8(0x160)
2159#define SHORT_ADDR_00 0
2160#define SHORT_ADDR_01 1
2161#define SHORT_ADDR_02 2
2162#define SHORT_ADDR_03 3
2163#define SHORT_ADDR_04 4
2164#define SHORT_ADDR_05 5
2165#define SHORT_ADDR_06 6
2166#define SHORT_ADDR_07 7
2167
2168#define SHORT_ADDR_1 _SFR_MEM8(0x161)
2169#define SHORT_ADDR_10 0
2170#define SHORT_ADDR_11 1
2171#define SHORT_ADDR_12 2
2172#define SHORT_ADDR_13 3
2173#define SHORT_ADDR_14 4
2174#define SHORT_ADDR_15 5
2175#define SHORT_ADDR_16 6
2176#define SHORT_ADDR_17 7
2177
2178#define PAN_ID_0 _SFR_MEM8(0x162)
2179#define PAN_ID_00 0
2180#define PAN_ID_01 1
2181#define PAN_ID_02 2
2182#define PAN_ID_03 3
2183#define PAN_ID_04 4
2184#define PAN_ID_05 5
2185#define PAN_ID_06 6
2186#define PAN_ID_07 7
2187
2188#define PAN_ID_1 _SFR_MEM8(0x163)
2189#define PAN_ID_10 0
2190#define PAN_ID_11 1
2191#define PAN_ID_12 2
2192#define PAN_ID_13 3
2193#define PAN_ID_14 4
2194#define PAN_ID_15 5
2195#define PAN_ID_16 6
2196#define PAN_ID_17 7
2197
2198#define IEEE_ADDR_0 _SFR_MEM8(0x164)
2199#define IEEE_ADDR_00 0
2200#define IEEE_ADDR_01 1
2201#define IEEE_ADDR_02 2
2202#define IEEE_ADDR_03 3
2203#define IEEE_ADDR_04 4
2204#define IEEE_ADDR_05 5
2205#define IEEE_ADDR_06 6
2206#define IEEE_ADDR_07 7
2207
2208#define IEEE_ADDR_1 _SFR_MEM8(0x165)
2209#define IEEE_ADDR_10 0
2210#define IEEE_ADDR_11 1
2211#define IEEE_ADDR_12 2
2212#define IEEE_ADDR_13 3
2213#define IEEE_ADDR_14 4
2214#define IEEE_ADDR_15 5
2215#define IEEE_ADDR_16 6
2216#define IEEE_ADDR_17 7
2217
2218#define IEEE_ADDR_2 _SFR_MEM8(0x166)
2219#define IEEE_ADDR_20 0
2220#define IEEE_ADDR_21 1
2221#define IEEE_ADDR_22 2
2222#define IEEE_ADDR_23 3
2223#define IEEE_ADDR_24 4
2224#define IEEE_ADDR_25 5
2225#define IEEE_ADDR_26 6
2226#define IEEE_ADDR_27 7
2227
2228#define IEEE_ADDR_3 _SFR_MEM8(0x167)
2229#define IEEE_ADDR_30 0
2230#define IEEE_ADDR_31 1
2231#define IEEE_ADDR_32 2
2232#define IEEE_ADDR_33 3
2233#define IEEE_ADDR_34 4
2234#define IEEE_ADDR_35 5
2235#define IEEE_ADDR_36 6
2236#define IEEE_ADDR_37 7
2237
2238#define IEEE_ADDR_4 _SFR_MEM8(0x168)
2239#define IEEE_ADDR_40 0
2240#define IEEE_ADDR_41 1
2241#define IEEE_ADDR_42 2
2242#define IEEE_ADDR_43 3
2243#define IEEE_ADDR_44 4
2244#define IEEE_ADDR_45 5
2245#define IEEE_ADDR_46 6
2246#define IEEE_ADDR_47 7
2247
2248#define IEEE_ADDR_5 _SFR_MEM8(0x169)
2249#define IEEE_ADDR_50 0
2250#define IEEE_ADDR_51 1
2251#define IEEE_ADDR_52 2
2252#define IEEE_ADDR_53 3
2253#define IEEE_ADDR_54 4
2254#define IEEE_ADDR_55 5
2255#define IEEE_ADDR_56 6
2256#define IEEE_ADDR_57 7
2257
2258#define IEEE_ADDR_6 _SFR_MEM8(0x16A)
2259#define IEEE_ADDR_60 0
2260#define IEEE_ADDR_61 1
2261#define IEEE_ADDR_62 2
2262#define IEEE_ADDR_63 3
2263#define IEEE_ADDR_64 4
2264#define IEEE_ADDR_65 5
2265#define IEEE_ADDR_66 6
2266#define IEEE_ADDR_67 7
2267
2268#define IEEE_ADDR_7 _SFR_MEM8(0x16B)
2269#define IEEE_ADDR_70 0
2270#define IEEE_ADDR_71 1
2271#define IEEE_ADDR_72 2
2272#define IEEE_ADDR_73 3
2273#define IEEE_ADDR_74 4
2274#define IEEE_ADDR_75 5
2275#define IEEE_ADDR_76 6
2276#define IEEE_ADDR_77 7
2277
2278#define XAH_CTRL_0 _SFR_MEM8(0x16C)
2279#define SLOTTED_OPERATION 0
2280#define MAX_CSMA_RETRIES0 1
2281#define MAX_CSMA_RETRIES1 2
2282#define MAX_CSMA_RETRIES2 3
2283#define MAX_FRAME_RETRIES0 4
2284#define MAX_FRAME_RETRIES1 5
2285#define MAX_FRAME_RETRIES2 6
2286#define MAX_FRAME_RETRIES3 7
2287
2288#define CSMA_SEED_0 _SFR_MEM8(0x16D)
2289#define CSMA_SEED_00 0
2290#define CSMA_SEED_01 1
2291#define CSMA_SEED_02 2
2292#define CSMA_SEED_03 3
2293#define CSMA_SEED_04 4
2294#define CSMA_SEED_05 5
2295#define CSMA_SEED_06 6
2296#define CSMA_SEED_07 7
2297
2298#define CSMA_SEED_1 _SFR_MEM8(0x16E)
2299#define CSMA_SEED_10 0
2300#define CSMA_SEED_11 1
2301#define CSMA_SEED_12 2
2302#define AACK_I_AM_COORD 3
2303#define AACK_DIS_ACK 4
2304#define AACK_SET_PD 5
2305#define AACK_FVN_MODE0 6
2306#define AACK_FVN_MODE1 7
2307
2308#define CSMA_BE _SFR_MEM8(0x16F)
2309#define MIN_BE0 0
2310#define MIN_BE1 1
2311#define MIN_BE2 2
2312#define MIN_BE3 3
2313#define MAX_BE0 4
2314#define MAX_BE1 5
2315#define MAX_BE2 6
2316#define MAX_BE3 7
2317
2318/* Reserved [0x170..0x175] */
2319
2320#define TST_CTRL_DIGI _SFR_MEM8(0x176)
2321#define TST_CTRL_DIG0 0
2322#define TST_CTRL_DIG1 1
2323#define TST_CTRL_DIG2 2
2324#define TST_CTRL_DIG3 3
2325
2326/* Reserved [0x177..0x17A] */
2327
2328#define TST_RX_LENGTH _SFR_MEM8(0x17B)
2329#define RX_LENGTH0 0
2330#define RX_LENGTH1 1
2331#define RX_LENGTH2 2
2332#define RX_LENGTH3 3
2333#define RX_LENGTH4 4
2334#define RX_LENGTH5 5
2335#define RX_LENGTH6 6
2336#define RX_LENGTH7 7
2337
2338/* Reserved [0x17C..0x17F] */
2339
2340#define TRXFBST _SFR_MEM8(0x180)
2341
2342/* Reserved [0x181..0x1FE] */
2343
2344#define TRXFBEND _SFR_MEM8(0x1FF)
2345
2346
2347
2348/* Values and associated defines */
2349
2350
2351#define SLEEP_MODE_IDLE (0x00<<1)
2352#define SLEEP_MODE_ADC (0x01<<1)
2353#define SLEEP_MODE_PWR_DOWN (0x02<<1)
2354#define SLEEP_MODE_PWR_SAVE (0x03<<1)
2355#define SLEEP_MODE_STANDBY (0x06<<1)
2356#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
2357
2358/* Interrupt vectors */
2359/* Vector 0 is the reset vector */
2360/* External Interrupt Request 0 */
2361#define INT0_vect            _VECTOR(1)
2362#define INT0_vect_num        1
2363
2364/* External Interrupt Request 1 */
2365#define INT1_vect            _VECTOR(2)
2366#define INT1_vect_num        2
2367
2368/* External Interrupt Request 2 */
2369#define INT2_vect            _VECTOR(3)
2370#define INT2_vect_num        3
2371
2372/* External Interrupt Request 3 */
2373#define INT3_vect            _VECTOR(4)
2374#define INT3_vect_num        4
2375
2376/* External Interrupt Request 4 */
2377#define INT4_vect            _VECTOR(5)
2378#define INT4_vect_num        5
2379
2380/* External Interrupt Request 5 */
2381#define INT5_vect            _VECTOR(6)
2382#define INT5_vect_num        6
2383
2384/* External Interrupt Request 6 */
2385#define INT6_vect            _VECTOR(7)
2386#define INT6_vect_num        7
2387
2388/* External Interrupt Request 7 */
2389#define INT7_vect            _VECTOR(8)
2390#define INT7_vect_num        8
2391
2392/* Pin Change Interrupt Request 0 */
2393#define PCINT0_vect            _VECTOR(9)
2394#define PCINT0_vect_num        9
2395
2396/* Pin Change Interrupt Request 1 */
2397#define PCINT1_vect            _VECTOR(10)
2398#define PCINT1_vect_num        10
2399
2400/* Pin Change Interrupt Request 2 */
2401#define PCINT2_vect            _VECTOR(11)
2402#define PCINT2_vect_num        11
2403
2404/* Watchdog Time-out Interrupt */
2405#define WDT_vect            _VECTOR(12)
2406#define WDT_vect_num        12
2407
2408/* Timer/Counter2 Compare Match A */
2409#define TIMER2_COMPA_vect            _VECTOR(13)
2410#define TIMER2_COMPA_vect_num        13
2411
2412/* Timer/Counter2 Compare Match B */
2413#define TIMER2_COMPB_vect            _VECTOR(14)
2414#define TIMER2_COMPB_vect_num        14
2415
2416/* Timer/Counter2 Overflow */
2417#define TIMER2_OVF_vect            _VECTOR(15)
2418#define TIMER2_OVF_vect_num        15
2419
2420/* Timer/Counter1 Capture Event */
2421#define TIMER1_CAPT_vect            _VECTOR(16)
2422#define TIMER1_CAPT_vect_num        16
2423
2424/* Timer/Counter1 Compare Match A */
2425#define TIMER1_COMPA_vect            _VECTOR(17)
2426#define TIMER1_COMPA_vect_num        17
2427
2428/* Timer/Counter1 Compare Match B */
2429#define TIMER1_COMPB_vect            _VECTOR(18)
2430#define TIMER1_COMPB_vect_num        18
2431
2432/* Timer/Counter1 Compare Match C */
2433#define TIMER1_COMPC_vect            _VECTOR(19)
2434#define TIMER1_COMPC_vect_num        19
2435
2436/* Timer/Counter1 Overflow */
2437#define TIMER1_OVF_vect            _VECTOR(20)
2438#define TIMER1_OVF_vect_num        20
2439
2440/* Timer/Counter0 Compare Match A */
2441#define TIMER0_COMPA_vect            _VECTOR(21)
2442#define TIMER0_COMPA_vect_num        21
2443
2444/* Timer/Counter0 Compare Match B */
2445#define TIMER0_COMPB_vect            _VECTOR(22)
2446#define TIMER0_COMPB_vect_num        22
2447
2448/* Timer/Counter0 Overflow */
2449#define TIMER0_OVF_vect            _VECTOR(23)
2450#define TIMER0_OVF_vect_num        23
2451
2452/* SPI Serial Transfer Complete */
2453#define SPI_STC_vect            _VECTOR(24)
2454#define SPI_STC_vect_num        24
2455
2456/* USART0, Rx Complete */
2457#define USART0_RX_vect            _VECTOR(25)
2458#define USART0_RX_vect_num        25
2459
2460/* USART0 Data register Empty */
2461#define USART0_UDRE_vect            _VECTOR(26)
2462#define USART0_UDRE_vect_num        26
2463
2464/* USART0, Tx Complete */
2465#define USART0_TX_vect            _VECTOR(27)
2466#define USART0_TX_vect_num        27
2467
2468/* Analog Comparator */
2469#define ANALOG_COMP_vect            _VECTOR(28)
2470#define ANALOG_COMP_vect_num        28
2471
2472/* ADC Conversion Complete */
2473#define ADC_vect            _VECTOR(29)
2474#define ADC_vect_num        29
2475
2476/* EEPROM Ready */
2477#define EE_READY_vect            _VECTOR(30)
2478#define EE_READY_vect_num        30
2479
2480/* Timer/Counter3 Capture Event */
2481#define TIMER3_CAPT_vect            _VECTOR(31)
2482#define TIMER3_CAPT_vect_num        31
2483
2484/* Timer/Counter3 Compare Match A */
2485#define TIMER3_COMPA_vect            _VECTOR(32)
2486#define TIMER3_COMPA_vect_num        32
2487
2488/* Timer/Counter3 Compare Match B */
2489#define TIMER3_COMPB_vect            _VECTOR(33)
2490#define TIMER3_COMPB_vect_num        33
2491
2492/* Timer/Counter3 Compare Match C */
2493#define TIMER3_COMPC_vect            _VECTOR(34)
2494#define TIMER3_COMPC_vect_num        34
2495
2496/* Timer/Counter3 Overflow */
2497#define TIMER3_OVF_vect            _VECTOR(35)
2498#define TIMER3_OVF_vect_num        35
2499
2500/* USART1, Rx Complete */
2501#define USART1_RX_vect            _VECTOR(36)
2502#define USART1_RX_vect_num        36
2503
2504/* USART1 Data register Empty */
2505#define USART1_UDRE_vect            _VECTOR(37)
2506#define USART1_UDRE_vect_num        37
2507
2508/* USART1, Tx Complete */
2509#define USART1_TX_vect            _VECTOR(38)
2510#define USART1_TX_vect_num        38
2511
2512/* 2-wire Serial Interface */
2513#define TWI_vect            _VECTOR(39)
2514#define TWI_vect_num        39
2515
2516/* Store Program Memory Read */
2517#define SPM_READY_vect            _VECTOR(40)
2518#define SPM_READY_vect_num        40
2519
2520/* Timer/Counter4 Capture Event */
2521#define TIMER4_CAPT_vect            _VECTOR(41)
2522#define TIMER4_CAPT_vect_num        41
2523
2524/* Timer/Counter4 Compare Match A */
2525#define TIMER4_COMPA_vect            _VECTOR(42)
2526#define TIMER4_COMPA_vect_num        42
2527
2528/* Timer/Counter4 Compare Match B */
2529#define TIMER4_COMPB_vect            _VECTOR(43)
2530#define TIMER4_COMPB_vect_num        43
2531
2532/* Timer/Counter4 Compare Match C */
2533#define TIMER4_COMPC_vect            _VECTOR(44)
2534#define TIMER4_COMPC_vect_num        44
2535
2536/* Timer/Counter4 Overflow */
2537#define TIMER4_OVF_vect            _VECTOR(45)
2538#define TIMER4_OVF_vect_num        45
2539
2540/* Timer/Counter5 Capture Event */
2541#define TIMER5_CAPT_vect            _VECTOR(46)
2542#define TIMER5_CAPT_vect_num        46
2543
2544/* Timer/Counter5 Compare Match A */
2545#define TIMER5_COMPA_vect            _VECTOR(47)
2546#define TIMER5_COMPA_vect_num        47
2547
2548/* Timer/Counter5 Compare Match B */
2549#define TIMER5_COMPB_vect            _VECTOR(48)
2550#define TIMER5_COMPB_vect_num        48
2551
2552/* Timer/Counter5 Compare Match C */
2553#define TIMER5_COMPC_vect            _VECTOR(49)
2554#define TIMER5_COMPC_vect_num        49
2555
2556/* Timer/Counter5 Overflow */
2557#define TIMER5_OVF_vect            _VECTOR(50)
2558#define TIMER5_OVF_vect_num        50
2559
2560/* TRX24 - PLL lock interrupt */
2561#define TRX24_PLL_LOCK_vect            _VECTOR(57)
2562#define TRX24_PLL_LOCK_vect_num        57
2563
2564/* TRX24 - PLL unlock interrupt */
2565#define TRX24_PLL_UNLOCK_vect            _VECTOR(58)
2566#define TRX24_PLL_UNLOCK_vect_num        58
2567
2568/* TRX24 - Receive start interrupt */
2569#define TRX24_RX_START_vect            _VECTOR(59)
2570#define TRX24_RX_START_vect_num        59
2571
2572/* TRX24 - RX_END interrupt */
2573#define TRX24_RX_END_vect            _VECTOR(60)
2574#define TRX24_RX_END_vect_num        60
2575
2576/* TRX24 - CCA/ED done interrupt */
2577#define TRX24_CCA_ED_DONE_vect            _VECTOR(61)
2578#define TRX24_CCA_ED_DONE_vect_num        61
2579
2580/* TRX24 - XAH - AMI */
2581#define TRX24_XAH_AMI_vect            _VECTOR(62)
2582#define TRX24_XAH_AMI_vect_num        62
2583
2584/* TRX24 - TX_END interrupt */
2585#define TRX24_TX_END_vect            _VECTOR(63)
2586#define TRX24_TX_END_vect_num        63
2587
2588/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
2589#define TRX24_AWAKE_vect            _VECTOR(64)
2590#define TRX24_AWAKE_vect_num        64
2591
2592/* Symbol counter - compare match 1 interrupt */
2593#define SCNT_CMP1_vect            _VECTOR(65)
2594#define SCNT_CMP1_vect_num        65
2595
2596/* Symbol counter - compare match 2 interrupt */
2597#define SCNT_CMP2_vect            _VECTOR(66)
2598#define SCNT_CMP2_vect_num        66
2599
2600/* Symbol counter - compare match 3 interrupt */
2601#define SCNT_CMP3_vect            _VECTOR(67)
2602#define SCNT_CMP3_vect_num        67
2603
2604/* Symbol counter - overflow interrupt */
2605#define SCNT_OVFL_vect            _VECTOR(68)
2606#define SCNT_OVFL_vect_num        68
2607
2608/* Symbol counter - backoff interrupt */
2609#define SCNT_BACKOFF_vect            _VECTOR(69)
2610#define SCNT_BACKOFF_vect_num        69
2611
2612/* AES engine ready interrupt */
2613#define AES_READY_vect            _VECTOR(70)
2614#define AES_READY_vect_num        70
2615
2616/* Battery monitor indicates supply voltage below threshold */
2617#define BAT_LOW_vect            _VECTOR(71)
2618#define BAT_LOW_vect_num        71
2619
2620/* TRX24 TX start interrupt */
2621#define TRX24_TX_START_vect            _VECTOR(72)
2622#define TRX24_TX_START_vect_num        72
2623
2624/* Address match interrupt of address filter 0 */
2625#define TRX24_AMI0_vect            _VECTOR(73)
2626#define TRX24_AMI0_vect_num        73
2627
2628/* Address match interrupt of address filter 1 */
2629#define TRX24_AMI1_vect            _VECTOR(74)
2630#define TRX24_AMI1_vect_num        74
2631
2632/* Address match interrupt of address filter 2 */
2633#define TRX24_AMI2_vect            _VECTOR(75)
2634#define TRX24_AMI2_vect_num        75
2635
2636/* Address match interrupt of address filter 3 */
2637#define TRX24_AMI3_vect            _VECTOR(76)
2638#define TRX24_AMI3_vect_num        76
2639
2640#define _VECTORS_SIZE 308
2641
2642
2643/* Constants */
2644
2645#define SPM_PAGESIZE 256
2646#define FLASHSTART   0x0000
2647#define FLASHEND     0x3FFFF
2648#define RAMSTART     0x0200
2649#define RAMSIZE      32768
2650#define RAMEND       0x81FF
2651#define E2START     0
2652#define E2SIZE      8192
2653#define E2PAGESIZE  8
2654#define E2END       0x1FFF
2655#define XRAMEND      RAMEND
2656
2657
2658/* Fuses */
2659
2660#define FUSE_MEMORY_SIZE 3
2661
2662/* Low Fuse Byte */
2663#define FUSE_CKSEL_SUT0  (unsigned char)~_BV(0)
2664#define FUSE_CKSEL_SUT1  (unsigned char)~_BV(1)
2665#define FUSE_CKSEL_SUT2  (unsigned char)~_BV(2)
2666#define FUSE_CKSEL_SUT3  (unsigned char)~_BV(3)
2667#define FUSE_CKSEL_SUT4  (unsigned char)~_BV(4)
2668#define FUSE_CKSEL_SUT5  (unsigned char)~_BV(5)
2669#define FUSE_CKOUT       (unsigned char)~_BV(6)
2670#define FUSE_CKDIV8      (unsigned char)~_BV(7)
2671#define LFUSE_DEFAULT    (FUSE_CKSEL_SUT0 & FUSE_CKSEL_SUT2 & FUSE_CKSEL_SUT3 & FUSE_CKSEL_SUT4 & FUSE_CKDIV8)
2672
2673
2674/* High Fuse Byte */
2675#define FUSE_BOOTRST     (unsigned char)~_BV(0)
2676#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
2677#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
2678#define FUSE_EESAVE      (unsigned char)~_BV(3)
2679#define FUSE_WDTON       (unsigned char)~_BV(4)
2680#define FUSE_SPIEN       (unsigned char)~_BV(5)
2681#define FUSE_JTAGEN      (unsigned char)~_BV(6)
2682#define FUSE_OCDEN       (unsigned char)~_BV(7)
2683#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
2684
2685
2686/* Extended Fuse Byte */
2687#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
2688#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
2689#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
2690#define EFUSE_DEFAULT    (FUSE_BODLEVEL0)
2691
2692
2693
2694/* Lock Bits */
2695#define __LOCK_BITS_EXIST
2696#define __BOOT_LOCK_BITS_0_EXIST
2697#define __BOOT_LOCK_BITS_1_EXIST
2698
2699
2700/* Signature */
2701#define SIGNATURE_0 0x1E
2702#define SIGNATURE_1 0xA8
2703#define SIGNATURE_2 0x02
2704
2705
2706#endif /* #ifdef _AVR_ATMEGA256RFR2_H_INCLUDED */
2707
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