source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom324p.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

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1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATMEGA324P_H_INCLUDED
36#define _AVR_ATMEGA324P_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "iom324p.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINA    _SFR_IO8(0x00)
52#define PINA7   7
53#define PINA6   6
54#define PINA5   5
55#define PINA4   4
56#define PINA3   3
57#define PINA2   2
58#define PINA1   1
59#define PINA0   0
60
61#define DDRA    _SFR_IO8(0x01)
62#define DDRA7   7
63// Inserted "DDA7" from "DDRA7" due to compatibility
64#define DDA7    7
65#define DDRA6   6
66// Inserted "DDA6" from "DDRA6" due to compatibility
67#define DDA6    6
68#define DDRA5   5
69// Inserted "DDA5" from "DDRA5" due to compatibility
70#define DDA5    5
71#define DDRA4   4
72// Inserted "DDA4" from "DDRA4" due to compatibility
73#define DDA4    4
74#define DDRA3   3
75// Inserted "DDA3" from "DDRA3" due to compatibility
76#define DDA3    3
77#define DDRA2   2
78// Inserted "DDA2" from "DDRA2" due to compatibility
79#define DDA2    2
80#define DDRA1   1
81// Inserted "DDA1" from "DDRA1" due to compatibility
82#define DDA1    1
83#define DDRA0   0
84// Inserted "DDA0" from "DDRA0" due to compatibility
85#define DDA0    0
86
87#define PORTA   _SFR_IO8(0x02)
88#define PORTA7  7
89#define PORTA6  6
90#define PORTA5  5
91#define PORTA4  4
92#define PORTA3  3
93#define PORTA2  2
94#define PORTA1  1
95#define PORTA0  0
96
97#define PINB    _SFR_IO8(0x03)
98#define PINB7   7
99#define PINB6   6
100#define PINB5   5
101#define PINB4   4
102#define PINB3   3
103#define PINB2   2
104#define PINB1   1
105#define PINB0   0
106
107#define DDRB    _SFR_IO8(0x04)
108#define DDRB7   7
109// Inserted "DDB7" from "DDRB7" due to compatibility
110#define DDB7    7
111#define DDRB6   6
112// Inserted "DDB6" from "DDRB6" due to compatibility
113#define DDB6    6
114#define DDRB5   5
115// Inserted "DDB5" from "DDRB5" due to compatibility
116#define DDB5    5
117#define DDRB4   4
118// Inserted "DDB4" from "DDRB4" due to compatibility
119#define DDB4    4
120#define DDRB3   3
121// Inserted "DDB3" from "DDRB3" due to compatibility
122#define DDB3    3
123#define DDRB2   2
124// Inserted "DDB2" from "DDRB2" due to compatibility
125#define DDB2    2
126#define DDRB1   1
127// Inserted "DDB1" from "DDRB1" due to compatibility
128#define DDB1    1
129#define DDRB0   0
130// Inserted "DDB0" from "DDRB0" due to compatibility
131#define DDB0    0
132
133#define PORTB   _SFR_IO8(0x05)
134#define PORTB7  7
135#define PORTB6  6
136#define PORTB5  5
137#define PORTB4  4
138#define PORTB3  3
139#define PORTB2  2
140#define PORTB1  1
141#define PORTB0  0
142
143#define PINC    _SFR_IO8(0x06)
144#define PINC7   7
145#define PINC6   6
146#define PINC5   5
147#define PINC4   4
148#define PINC3   3
149#define PINC2   2
150#define PINC1   1
151#define PINC0   0
152
153#define DDRC    _SFR_IO8(0x07)
154#define DDRC7   7
155// Inserted "DDC7" from "DDRC7" due to compatibility
156#define DDC7    7
157#define DDRC6   6
158// Inserted "DDC6" from "DDRC6" due to compatibility
159#define DDC6    6
160#define DDRC5   5
161// Inserted "DDC5" from "DDRC5" due to compatibility
162#define DDC5    5
163#define DDRC4   4
164// Inserted "DDC4" from "DDRC4" due to compatibility
165#define DDC4    4
166#define DDRC3   3
167// Inserted "DDC3" from "DDRC3" due to compatibility
168#define DDC3    3
169#define DDRC2   2
170// Inserted "DDC2" from "DDRC2" due to compatibility
171#define DDC2    2
172#define DDRC1   1
173// Inserted "DDC1" from "DDRC1" due to compatibility
174#define DDC1    1
175#define DDRC0   0
176// Inserted "DDC0" from "DDRC0" due to compatibility
177#define DDC0    0
178
179#define PORTC   _SFR_IO8(0x08)
180#define PORTC7  7
181#define PORTC6  6
182#define PORTC5  5
183#define PORTC4  4
184#define PORTC3  3
185#define PORTC2  2
186#define PORTC1  1
187#define PORTC0  0
188
189#define PIND    _SFR_IO8(0x09)
190#define PIND7   7
191#define PIND6   6
192#define PIND5   5
193#define PIND4   4
194#define PIND3   3
195#define PIND2   2
196#define PIND1   1
197#define PIND0   0
198
199#define DDRD    _SFR_IO8(0x0A)
200#define DDRD7   7
201// Inserted "DDD7" from "DDRD7" due to compatibility
202#define DDD7    7
203#define DDRD6   6
204// Inserted "DDD6" from "DDRD6" due to compatibility
205#define DDD6    6
206#define DDRD5   5
207// Inserted "DDD5" from "DDRD5" due to compatibility
208#define DDD5    5
209#define DDRD4   4
210// Inserted "DDD4" from "DDRD4" due to compatibility
211#define DDD4    4
212#define DDRD3   3
213// Inserted "DDD3" from "DDRD3" due to compatibility
214#define DDD3    3
215#define DDRD2   2
216// Inserted "DDD2" from "DDRD2" due to compatibility
217#define DDD2    2
218#define DDRD1   1
219// Inserted "DDD1" from "DDRD1" due to compatibility
220#define DDD1    1
221#define DDRD0   0
222// Inserted "DDD0" from "DDRD0" due to compatibility
223#define DDD0    0
224
225#define PORTD   _SFR_IO8(0x0B)
226#define PORTD7  7
227#define PORTD6  6
228#define PORTD5  5
229#define PORTD4  4
230#define PORTD3  3
231#define PORTD2  2
232#define PORTD1  1
233#define PORTD0  0
234
235/* Reserved [0x0C..0x14] */
236
237#define TIFR0   _SFR_IO8(0x15)
238#define TOV0    0
239#define OCF0A   1
240#define OCF0B   2
241
242#define TIFR1   _SFR_IO8(0x16)
243#define TOV1    0
244#define OCF1A   1
245#define OCF1B   2
246#define ICF1    5
247
248#define TIFR2   _SFR_IO8(0x17)
249#define TOV2    0
250#define OCF2A   1
251#define OCF2B   2
252
253/* Reserved [0x18..0x1A] */
254
255#define PCIFR   _SFR_IO8(0x1B)
256#define PCIF0   0
257#define PCIF1   1
258#define PCIF2   2
259#define PCIF3   3
260
261#define EIFR    _SFR_IO8(0x1C)
262#define INTF0   0
263#define INTF1   1
264#define INTF2   2
265
266#define EIMSK   _SFR_IO8(0x1D)
267#define INT0    0
268#define INT1    1
269#define INT2    2
270
271#define GPIOR0  _SFR_IO8(0x1E)
272#define GPIOR00 0
273#define GPIOR01 1
274#define GPIOR02 2
275#define GPIOR03 3
276#define GPIOR04 4
277#define GPIOR05 5
278#define GPIOR06 6
279#define GPIOR07 7
280
281#define EECR    _SFR_IO8(0x1F)
282#define EERE    0
283#define EEPE    1
284#define EEMPE   2
285#define EERIE   3
286#define EEPM0   4
287#define EEPM1   5
288
289#define EEDR    _SFR_IO8(0x20)
290
291/* Combine EEARL and EEARH */
292#define EEAR    _SFR_IO16(0x21)
293
294#define EEARL   _SFR_IO8(0x21)
295#define EEARH   _SFR_IO8(0x22)
296
297#define GTCCR   _SFR_IO8(0x23)
298#define PSRSYNC 0
299#define TSM     7
300#define PSRASY  1
301
302#define TCCR0A  _SFR_IO8(0x24)
303#define WGM00   0
304#define WGM01   1
305#define COM0B0  4
306#define COM0B1  5
307#define COM0A0  6
308#define COM0A1  7
309
310#define TCCR0B  _SFR_IO8(0x25)
311#define CS00    0
312#define CS01    1
313#define CS02    2
314#define WGM02   3
315#define FOC0B   6
316#define FOC0A   7
317
318#define TCNT0   _SFR_IO8(0x26)
319
320#define OCR0A   _SFR_IO8(0x27)
321
322#define OCR0B   _SFR_IO8(0x28)
323
324/* Reserved [0x29] */
325
326#define GPIOR1  _SFR_IO8(0x2A)
327#define GPIOR10 0
328#define GPIOR11 1
329#define GPIOR12 2
330#define GPIOR13 3
331#define GPIOR14 4
332#define GPIOR15 5
333#define GPIOR16 6
334#define GPIOR17 7
335
336#define GPIOR2  _SFR_IO8(0x2B)
337#define GPIOR20 0
338#define GPIOR21 1
339#define GPIOR22 2
340#define GPIOR23 3
341#define GPIOR24 4
342#define GPIOR25 5
343#define GPIOR26 6
344#define GPIOR27 7
345
346#define SPCR0   _SFR_IO8(0x2C)
347#define SPR00   0
348#define SPR10   1
349#define CPHA0   2
350#define CPOL0   3
351#define MSTR0   4
352#define DORD0   5
353#define SPE0    6
354#define SPIE0   7
355
356#define SPSR0   _SFR_IO8(0x2D)
357#define SPI2X0  0
358#define WCOL0   6
359#define SPIF0   7
360
361#define SPDR0   _SFR_IO8(0x2E)
362
363/* Reserved [0x2F] */
364
365#define ACSR    _SFR_IO8(0x30)
366#define ACIS0   0
367#define ACIS1   1
368#define ACIC    2
369#define ACIE    3
370#define ACI     4
371#define ACO     5
372#define ACBG    6
373#define ACD     7
374
375#define OCDR    _SFR_IO8(0x31)
376#define OCDR7   7
377#define OCDR6   6
378#define OCDR5   5
379#define OCDR4   4
380#define OCDR3   3
381#define OCDR2   2
382#define OCDR1   1
383#define OCDR0   0
384
385/* Reserved [0x32] */
386
387#define SMCR    _SFR_IO8(0x33)
388#define SE      0
389#define SM0     1
390#define SM1     2
391#define SM2     3
392
393#define MCUSR   _SFR_IO8(0x34)
394#define JTRF    4
395#define PORF    0
396#define EXTRF   1
397#define BORF    2
398#define WDRF    3
399
400#define MCUCR   _SFR_IO8(0x35)
401#define JTD     7
402#define IVCE    0
403#define IVSEL   1
404#define PUD     4
405#define BODSE   5
406#define BODS    6
407
408/* Reserved [0x36] */
409
410#define SPMCSR  _SFR_IO8(0x37)
411#define SPMEN   0
412#define PGERS   1
413#define PGWRT   2
414#define BLBSET  3
415#define RWWSRE  4
416#define SIGRD   5
417#define RWWSB   6
418#define SPMIE   7
419
420/* Reserved [0x38..0x3C] */
421
422/* SP [0x3D..0x3E] */
423
424/* SREG [0x3F] */
425
426#define WDTCSR  _SFR_MEM8(0x60)
427#define WDE     3
428#define WDCE    4
429#define WDP0    0
430#define WDP1    1
431#define WDP2    2
432#define WDP3    5
433#define WDIE    6
434#define WDIF    7
435
436#define CLKPR   _SFR_MEM8(0x61)
437#define CLKPS0  0
438#define CLKPS1  1
439#define CLKPS2  2
440#define CLKPS3  3
441#define CLKPCE  7
442
443/* Reserved [0x62..0x63] */
444
445#define PRR0    _SFR_MEM8(0x64)
446#define PRADC   0
447#define PRUSART0 1
448#define PRSPI   2
449#define PRTIM1  3
450#define PRUSART1 4
451#define PRTIM0  5
452#define PRTIM2  6
453#define PRTWI   7
454
455#define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
456#define __AVR_HAVE_PRR0_PRADC
457#define __AVR_HAVE_PRR0_PRUSART0
458#define __AVR_HAVE_PRR0_PRSPI
459#define __AVR_HAVE_PRR0_PRTIM1
460#define __AVR_HAVE_PRR0_PRUSART1
461#define __AVR_HAVE_PRR0_PRTIM0
462#define __AVR_HAVE_PRR0_PRTIM2
463#define __AVR_HAVE_PRR0_PRTWI
464
465/* Reserved [0x65] */
466
467#define OSCCAL  _SFR_MEM8(0x66)
468#define OSCCAL0 0
469#define OSCCAL1 1
470#define OSCCAL2 2
471#define OSCCAL3 3
472#define OSCCAL4 4
473#define OSCCAL5 5
474#define OSCCAL6 6
475#define OSCCAL7 7
476
477/* Reserved [0x67] */
478
479#define PCICR   _SFR_MEM8(0x68)
480#define PCIE0   0
481#define PCIE1   1
482#define PCIE2   2
483#define PCIE3   3
484
485#define EICRA   _SFR_MEM8(0x69)
486#define ISC00   0
487#define ISC01   1
488#define ISC10   2
489#define ISC11   3
490#define ISC20   4
491#define ISC21   5
492
493/* Reserved [0x6A] */
494
495#define PCMSK0  _SFR_MEM8(0x6B)
496#define PCINT0  0
497#define PCINT1  1
498#define PCINT2  2
499#define PCINT3  3
500#define PCINT4  4
501#define PCINT5  5
502#define PCINT6  6
503#define PCINT7  7
504
505#define PCMSK1  _SFR_MEM8(0x6C)
506#define PCINT8  0
507#define PCINT9  1
508#define PCINT10 2
509#define PCINT11 3
510#define PCINT12 4
511#define PCINT13 5
512#define PCINT14 6
513#define PCINT15 7
514
515#define PCMSK2  _SFR_MEM8(0x6D)
516#define PCINT16 0
517#define PCINT17 1
518#define PCINT18 2
519#define PCINT19 3
520#define PCINT20 4
521#define PCINT21 5
522#define PCINT22 6
523#define PCINT23 7
524
525#define TIMSK0  _SFR_MEM8(0x6E)
526#define TOIE0   0
527#define OCIE0A  1
528#define OCIE0B  2
529
530#define TIMSK1  _SFR_MEM8(0x6F)
531#define TOIE1   0
532#define OCIE1A  1
533#define OCIE1B  2
534#define ICIE1   5
535
536#define TIMSK2  _SFR_MEM8(0x70)
537#define TOIE2   0
538#define OCIE2A  1
539#define OCIE2B  2
540
541/* Reserved [0x71..0x72] */
542
543#define PCMSK3  _SFR_MEM8(0x73)
544#define PCINT24 0
545#define PCINT25 1
546#define PCINT26 2
547#define PCINT27 3
548#define PCINT28 4
549#define PCINT29 5
550#define PCINT30 6
551#define PCINT31 7
552
553/* Reserved [0x74..0x77] */
554
555/* Combine ADCL and ADCH */
556#ifndef __ASSEMBLER__
557#define ADC     _SFR_MEM16(0x78)
558#endif
559#define ADCW    _SFR_MEM16(0x78)
560
561#define ADCL    _SFR_MEM8(0x78)
562#define ADCH    _SFR_MEM8(0x79)
563
564#define ADCSRA  _SFR_MEM8(0x7A)
565#define ADPS0   0
566#define ADPS1   1
567#define ADPS2   2
568#define ADIE    3
569#define ADIF    4
570#define ADATE   5
571#define ADSC    6
572#define ADEN    7
573
574#define ADCSRB  _SFR_MEM8(0x7B)
575#define ACME    6
576#define ADTS0   0
577#define ADTS1   1
578#define ADTS2   2
579
580#define ADMUX   _SFR_MEM8(0x7C)
581#define MUX0    0
582#define MUX1    1
583#define MUX2    2
584#define MUX3    3
585#define MUX4    4
586#define ADLAR   5
587#define REFS0   6
588#define REFS1   7
589
590/* Reserved [0x7D] */
591
592#define DIDR0   _SFR_MEM8(0x7E)
593#define ADC0D   0
594#define ADC1D   1
595#define ADC2D   2
596#define ADC3D   3
597#define ADC4D   4
598#define ADC5D   5
599#define ADC6D   6
600#define ADC7D   7
601
602#define DIDR1   _SFR_MEM8(0x7F)
603#define AIN0D   0
604#define AIN1D   1
605
606#define TCCR1A  _SFR_MEM8(0x80)
607#define WGM10   0
608#define WGM11   1
609#define COM1B0  4
610#define COM1B1  5
611#define COM1A0  6
612#define COM1A1  7
613
614#define TCCR1B  _SFR_MEM8(0x81)
615#define CS10    0
616#define CS11    1
617#define CS12    2
618#define WGM12   3
619#define WGM13   4
620#define ICES1   6
621#define ICNC1   7
622
623#define TCCR1C  _SFR_MEM8(0x82)
624#define FOC1B   6
625#define FOC1A   7
626
627/* Reserved [0x83] */
628
629/* Combine TCNT1L and TCNT1H */
630#define TCNT1   _SFR_MEM16(0x84)
631
632#define TCNT1L  _SFR_MEM8(0x84)
633#define TCNT1H  _SFR_MEM8(0x85)
634
635/* Combine ICR1L and ICR1H */
636#define ICR1    _SFR_MEM16(0x86)
637
638#define ICR1L   _SFR_MEM8(0x86)
639#define ICR1H   _SFR_MEM8(0x87)
640
641/* Combine OCR1AL and OCR1AH */
642#define OCR1A   _SFR_MEM16(0x88)
643
644#define OCR1AL  _SFR_MEM8(0x88)
645#define OCR1AH  _SFR_MEM8(0x89)
646
647/* Combine OCR1BL and OCR1BH */
648#define OCR1B   _SFR_MEM16(0x8A)
649
650#define OCR1BL  _SFR_MEM8(0x8A)
651#define OCR1BH  _SFR_MEM8(0x8B)
652
653/* Reserved [0x8C..0xAF] */
654
655#define TCCR2A  _SFR_MEM8(0xB0)
656#define WGM20   0
657#define WGM21   1
658#define COM2B0  4
659#define COM2B1  5
660#define COM2A0  6
661#define COM2A1  7
662
663#define TCCR2B  _SFR_MEM8(0xB1)
664#define CS20    0
665#define CS21    1
666#define CS22    2
667#define WGM22   3
668#define FOC2B   6
669#define FOC2A   7
670
671#define TCNT2   _SFR_MEM8(0xB2)
672
673#define OCR2A   _SFR_MEM8(0xB3)
674
675#define OCR2B   _SFR_MEM8(0xB4)
676
677/* Reserved [0xB5] */
678
679#define ASSR    _SFR_MEM8(0xB6)
680#define TCR2BUB 0
681#define TCR2AUB 1
682#define OCR2BUB 2
683#define OCR2AUB 3
684#define TCN2UB  4
685#define AS2     5
686#define EXCLK   6
687
688/* Reserved [0xB7] */
689
690#define TWBR    _SFR_MEM8(0xB8)
691
692#define TWSR    _SFR_MEM8(0xB9)
693#define TWPS0   0
694#define TWPS1   1
695#define TWS3    3
696#define TWS4    4
697#define TWS5    5
698#define TWS6    6
699#define TWS7    7
700
701#define TWAR    _SFR_MEM8(0xBA)
702#define TWGCE   0
703#define TWA0    1
704#define TWA1    2
705#define TWA2    3
706#define TWA3    4
707#define TWA4    5
708#define TWA5    6
709#define TWA6    7
710
711#define TWDR    _SFR_MEM8(0xBB)
712
713#define TWCR    _SFR_MEM8(0xBC)
714#define TWIE    0
715#define TWEN    2
716#define TWWC    3
717#define TWSTO   4
718#define TWSTA   5
719#define TWEA    6
720#define TWINT   7
721
722#define TWAMR   _SFR_MEM8(0xBD)
723#define TWAM0   1
724#define TWAM1   2
725#define TWAM2   3
726#define TWAM3   4
727#define TWAM4   5
728#define TWAM5   6
729#define TWAM6   7
730
731/* Reserved [0xBE..0xBF] */
732
733#define UCSR0A  _SFR_MEM8(0xC0)
734#define MPCM0   0
735#define U2X0    1
736#define UPE0    2
737#define DOR0    3
738#define FE0     4
739#define UDRE0   5
740#define TXC0    6
741#define RXC0    7
742
743#define UCSR0B  _SFR_MEM8(0xC1)
744#define TXB80   0
745#define RXB80   1
746#define UCSZ02  2
747#define TXEN0   3
748#define RXEN0   4
749#define UDRIE0  5
750#define TXCIE0  6
751#define RXCIE0  7
752
753#define UCSR0C  _SFR_MEM8(0xC2)
754#define UCPOL0  0
755#define UCSZ00  1
756#define UCSZ01  2
757#define USBS0   3
758#define UPM00   4
759#define UPM01   5
760#define UMSEL00 6
761#define UMSEL01 7
762
763/* Reserved [0xC3] */
764
765/* Combine UBRR0L and UBRR0H */
766#define UBRR0   _SFR_MEM16(0xC4)
767
768#define UBRR0L  _SFR_MEM8(0xC4)
769#define UBRR0H  _SFR_MEM8(0xC5)
770
771#define UDR0    _SFR_MEM8(0xC6)
772
773/* Reserved [0xC7] */
774
775#define UCSR1A  _SFR_MEM8(0xC8)
776#define MPCM1   0
777#define U2X1    1
778#define UPE1    2
779#define DOR1    3
780#define FE1     4
781#define UDRE1   5
782#define TXC1    6
783#define RXC1    7
784
785#define UCSR1B  _SFR_MEM8(0xC9)
786#define TXB81   0
787#define RXB81   1
788#define UCSZ12  2
789#define TXEN1   3
790#define RXEN1   4
791#define UDRIE1  5
792#define TXCIE1  6
793#define RXCIE1  7
794
795#define UCSR1C  _SFR_MEM8(0xCA)
796#define UCPOL1  0
797#define UCSZ10  1
798#define UCSZ11  2
799#define USBS1   3
800#define UPM10   4
801#define UPM11   5
802#define UMSEL10 6
803#define UMSEL11 7
804
805/* Reserved [0xCB] */
806
807/* Combine UBRR1L and UBRR1H */
808#define UBRR1   _SFR_MEM16(0xCC)
809
810#define UBRR1L  _SFR_MEM8(0xCC)
811#define UBRR1H  _SFR_MEM8(0xCD)
812
813#define UDR1    _SFR_MEM8(0xCE)
814
815
816
817/* Values and associated defines */
818
819
820#define SLEEP_MODE_IDLE (0x00<<1)
821#define SLEEP_MODE_ADC (0x01<<1)
822#define SLEEP_MODE_PWR_DOWN (0x02<<1)
823#define SLEEP_MODE_PWR_SAVE (0x03<<1)
824#define SLEEP_MODE_STANDBY (0x06<<1)
825#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
826
827/* Interrupt vectors */
828/* Vector 0 is the reset vector */
829/* External Interrupt Request 0 */
830#define INT0_vect            _VECTOR(1)
831#define INT0_vect_num        1
832
833/* External Interrupt Request 1 */
834#define INT1_vect            _VECTOR(2)
835#define INT1_vect_num        2
836
837/* External Interrupt Request 2 */
838#define INT2_vect            _VECTOR(3)
839#define INT2_vect_num        3
840
841/* Pin Change Interrupt Request 0 */
842#define PCINT0_vect            _VECTOR(4)
843#define PCINT0_vect_num        4
844
845/* Pin Change Interrupt Request 1 */
846#define PCINT1_vect            _VECTOR(5)
847#define PCINT1_vect_num        5
848
849/* Pin Change Interrupt Request 2 */
850#define PCINT2_vect            _VECTOR(6)
851#define PCINT2_vect_num        6
852
853/* Pin Change Interrupt Request 3 */
854#define PCINT3_vect            _VECTOR(7)
855#define PCINT3_vect_num        7
856
857/* Watchdog Time-out Interrupt */
858#define WDT_vect            _VECTOR(8)
859#define WDT_vect_num        8
860
861/* Timer/Counter2 Compare Match A */
862#define TIMER2_COMPA_vect            _VECTOR(9)
863#define TIMER2_COMPA_vect_num        9
864
865/* Timer/Counter2 Compare Match B */
866#define TIMER2_COMPB_vect            _VECTOR(10)
867#define TIMER2_COMPB_vect_num        10
868
869/* Timer/Counter2 Overflow */
870#define TIMER2_OVF_vect            _VECTOR(11)
871#define TIMER2_OVF_vect_num        11
872
873/* Timer/Counter1 Capture Event */
874#define TIMER1_CAPT_vect            _VECTOR(12)
875#define TIMER1_CAPT_vect_num        12
876
877/* Timer/Counter1 Compare Match A */
878#define TIMER1_COMPA_vect            _VECTOR(13)
879#define TIMER1_COMPA_vect_num        13
880
881/* Timer/Counter1 Compare Match B */
882#define TIMER1_COMPB_vect            _VECTOR(14)
883#define TIMER1_COMPB_vect_num        14
884
885/* Timer/Counter1 Overflow */
886#define TIMER1_OVF_vect            _VECTOR(15)
887#define TIMER1_OVF_vect_num        15
888
889/* Timer/Counter0 Compare Match A */
890#define TIMER0_COMPA_vect            _VECTOR(16)
891#define TIMER0_COMPA_vect_num        16
892
893/* Timer/Counter0 Compare Match B */
894#define TIMER0_COMPB_vect            _VECTOR(17)
895#define TIMER0_COMPB_vect_num        17
896
897/* Timer/Counter0 Overflow */
898#define TIMER0_OVF_vect            _VECTOR(18)
899#define TIMER0_OVF_vect_num        18
900
901/* SPI Serial Transfer Complete */
902#define SPI_STC_vect            _VECTOR(19)
903#define SPI_STC_vect_num        19
904
905/* USART0, Rx Complete */
906#define USART0_RX_vect            _VECTOR(20)
907#define USART0_RX_vect_num        20
908
909/* USART0 Data register Empty */
910#define USART0_UDRE_vect            _VECTOR(21)
911#define USART0_UDRE_vect_num        21
912
913/* USART0, Tx Complete */
914#define USART0_TX_vect            _VECTOR(22)
915#define USART0_TX_vect_num        22
916
917/* Analog Comparator */
918#define ANALOG_COMP_vect            _VECTOR(23)
919#define ANALOG_COMP_vect_num        23
920
921/* ADC Conversion Complete */
922#define ADC_vect            _VECTOR(24)
923#define ADC_vect_num        24
924
925/* EEPROM Ready */
926#define EE_READY_vect            _VECTOR(25)
927#define EE_READY_vect_num        25
928
929/* 2-wire Serial Interface */
930#define TWI_vect            _VECTOR(26)
931#define TWI_vect_num        26
932
933/* Store Program Memory Read */
934#define SPM_READY_vect            _VECTOR(27)
935#define SPM_READY_vect_num        27
936
937/* USART1 RX complete */
938#define USART1_RX_vect            _VECTOR(28)
939#define USART1_RX_vect_num        28
940
941/* USART1 Data Register Empty */
942#define USART1_UDRE_vect            _VECTOR(29)
943#define USART1_UDRE_vect_num        29
944
945/* USART1 TX complete */
946#define USART1_TX_vect            _VECTOR(30)
947#define USART1_TX_vect_num        30
948
949#define _VECTORS_SIZE 124
950
951
952/* Constants */
953
954#define SPM_PAGESIZE 128
955#define FLASHSTART   0x0000
956#define FLASHEND     0x7FFF
957#define RAMSTART     0x0100
958#define RAMSIZE      2048
959#define RAMEND       0x08FF
960#define E2START     0
961#define E2SIZE      1024
962#define E2PAGESIZE  4
963#define E2END       0x03FF
964#define XRAMEND      RAMEND
965
966
967/* Fuses */
968
969#define FUSE_MEMORY_SIZE 3
970
971/* Low Fuse Byte */
972#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
973#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
974#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
975#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
976#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
977#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
978#define FUSE_CKOUT       (unsigned char)~_BV(6)
979#define FUSE_CKDIV8      (unsigned char)~_BV(7)
980#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
981
982
983/* High Fuse Byte */
984#define FUSE_BOOTRST     (unsigned char)~_BV(0)
985#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
986#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
987#define FUSE_EESAVE      (unsigned char)~_BV(3)
988#define FUSE_WDTON       (unsigned char)~_BV(4)
989#define FUSE_SPIEN       (unsigned char)~_BV(5)
990#define FUSE_JTAGEN      (unsigned char)~_BV(6)
991#define FUSE_OCDEN       (unsigned char)~_BV(7)
992#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
993
994
995/* Extended Fuse Byte */
996#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
997#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
998#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
999#define EFUSE_DEFAULT    (0xFF)
1000
1001
1002
1003/* Lock Bits */
1004#define __LOCK_BITS_EXIST
1005#define __BOOT_LOCK_BITS_0_EXIST
1006#define __BOOT_LOCK_BITS_1_EXIST
1007
1008
1009/* Signature */
1010#define SIGNATURE_0 0x1E
1011#define SIGNATURE_1 0x95
1012#define SIGNATURE_2 0x08
1013
1014
1015#endif /* #ifdef _AVR_ATMEGA324P_H_INCLUDED */
1016
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