source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom325pa.h @ 46

Last change on this file since 46 was 46, checked in by jrpelegrina, 4 years ago

First release to Xenial

File size: 17.1 KB
Line 
1/*****************************************************************************
2 *
3 * Copyright (C) 2014 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATMEGA325PA_H_INCLUDED
36#define _AVR_ATMEGA325PA_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "iom325pa.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINA    _SFR_IO8(0x00)
52#define PINA7   7
53#define PINA6   6
54#define PINA5   5
55#define PINA4   4
56#define PINA3   3
57#define PINA2   2
58#define PINA1   1
59#define PINA0   0
60
61#define DDRA    _SFR_IO8(0x01)
62#define DDRA7   7
63#define DDRA6   6
64#define DDRA5   5
65#define DDRA4   4
66#define DDRA3   3
67#define DDRA2   2
68#define DDRA1   1
69#define DDRA0   0
70
71#define PORTA   _SFR_IO8(0x02)
72#define PORTA7  7
73#define PORTA6  6
74#define PORTA5  5
75#define PORTA4  4
76#define PORTA3  3
77#define PORTA2  2
78#define PORTA1  1
79#define PORTA0  0
80
81#define PINB    _SFR_IO8(0x03)
82#define PINB7   7
83#define PINB6   6
84#define PINB5   5
85#define PINB4   4
86#define PINB3   3
87#define PINB2   2
88#define PINB1   1
89#define PINB0   0
90
91#define DDRB    _SFR_IO8(0x04)
92#define DDRB7   7
93#define DDRB6   6
94#define DDRB5   5
95#define DDRB4   4
96#define DDRB3   3
97#define DDRB2   2
98#define DDRB1   1
99#define DDRB0   0
100
101#define PORTB   _SFR_IO8(0x05)
102#define PORTB7  7
103#define PORTB6  6
104#define PORTB5  5
105#define PORTB4  4
106#define PORTB3  3
107#define PORTB2  2
108#define PORTB1  1
109#define PORTB0  0
110
111#define PINC    _SFR_IO8(0x06)
112#define PINC7   7
113#define PINC6   6
114#define PINC5   5
115#define PINC4   4
116#define PINC3   3
117#define PINC2   2
118#define PINC1   1
119#define PINC0   0
120
121#define DDRC    _SFR_IO8(0x07)
122#define DDRC7   7
123#define DDRC6   6
124#define DDRC5   5
125#define DDRC4   4
126#define DDRC3   3
127#define DDRC2   2
128#define DDRC1   1
129#define DDRC0   0
130
131#define PORTC   _SFR_IO8(0x08)
132#define PORTC7  7
133#define PORTC6  6
134#define PORTC5  5
135#define PORTC4  4
136#define PORTC3  3
137#define PORTC2  2
138#define PORTC1  1
139#define PORTC0  0
140
141#define PIND    _SFR_IO8(0x09)
142#define PIND7   7
143#define PIND6   6
144#define PIND5   5
145#define PIND4   4
146#define PIND3   3
147#define PIND2   2
148#define PIND1   1
149#define PIND0   0
150
151#define DDRD    _SFR_IO8(0x0A)
152#define DDRD7   7
153#define DDRD6   6
154#define DDRD5   5
155#define DDRD4   4
156#define DDRD3   3
157#define DDRD2   2
158#define DDRD1   1
159#define DDRD0   0
160
161#define PORTD   _SFR_IO8(0x0B)
162#define PORTD7  7
163#define PORTD6  6
164#define PORTD5  5
165#define PORTD4  4
166#define PORTD3  3
167#define PORTD2  2
168#define PORTD1  1
169#define PORTD0  0
170
171#define PINE    _SFR_IO8(0x0C)
172#define PINE7   7
173#define PINE6   6
174#define PINE5   5
175#define PINE4   4
176#define PINE3   3
177#define PINE2   2
178#define PINE1   1
179#define PINE0   0
180
181#define DDRE    _SFR_IO8(0x0D)
182#define DDRE7   7
183#define DDRE6   6
184#define DDRE5   5
185#define DDRE4   4
186#define DDRE3   3
187#define DDRE2   2
188#define DDRE1   1
189#define DDRE0   0
190
191#define PORTE   _SFR_IO8(0x0E)
192#define PORTE7  7
193#define PORTE6  6
194#define PORTE5  5
195#define PORTE4  4
196#define PORTE3  3
197#define PORTE2  2
198#define PORTE1  1
199#define PORTE0  0
200
201#define PINF    _SFR_IO8(0x0F)
202#define PINF7   7
203#define PINF6   6
204#define PINF5   5
205#define PINF4   4
206#define PINF3   3
207#define PINF2   2
208#define PINF1   1
209#define PINF0   0
210
211#define DDRF    _SFR_IO8(0x10)
212#define DDRF7   7
213#define DDRF6   6
214#define DDRF5   5
215#define DDRF4   4
216#define DDRF3   3
217#define DDRF2   2
218#define DDRF1   1
219#define DDRF0   0
220
221#define PORTF   _SFR_IO8(0x11)
222#define PORTF7  7
223#define PORTF6  6
224#define PORTF5  5
225#define PORTF4  4
226#define PORTF3  3
227#define PORTF2  2
228#define PORTF1  1
229#define PORTF0  0
230
231#define PING    _SFR_IO8(0x12)
232#define PING5   5
233#define PING4   4
234#define PING3   3
235#define PING2   2
236#define PING1   1
237#define PING0   0
238
239#define DDRG    _SFR_IO8(0x13)
240#define DDRG4   4
241#define DDRG3   3
242#define DDRG2   2
243#define DDRG1   1
244#define DDRG0   0
245
246#define PORTG   _SFR_IO8(0x14)
247#define PORTG4  4
248#define PORTG3  3
249#define PORTG2  2
250#define PORTG1  1
251#define PORTG0  0
252
253#define TIFR0   _SFR_IO8(0x15)
254#define TOV0    0
255#define OCF0A   1
256
257#define TIFR1   _SFR_IO8(0x16)
258#define TOV1    0
259#define OCF1A   1
260#define OCF1B   2
261#define ICF1    5
262
263#define TIFR2   _SFR_IO8(0x17)
264#define TOV2    0
265#define OCF2A   1
266
267/* Reserved [0x18..0x1B] */
268
269#define EIFR    _SFR_IO8(0x1C)
270#define INTF0   0
271#define PCIF0   4
272#define PCIF1   5
273#define PCIF2   6
274#define PCIF3   7
275
276#define EIMSK   _SFR_IO8(0x1D)
277#define INT0    0
278#define PCIE0   4
279#define PCIE1   5
280#define PCIE2   6
281#define PCIE3   7
282
283#define GPIOR0  _SFR_IO8(0x1E)
284
285#define EECR    _SFR_IO8(0x1F)
286#define EERE    0
287#define EEWE    1
288#define EEMWE   2
289#define EERIE   3
290
291#define EEDR    _SFR_IO8(0x20)
292
293/* Combine EEARL and EEARH */
294#define EEAR    _SFR_IO16(0x21)
295
296#define EEARL   _SFR_IO8(0x21)
297#define EEARH   _SFR_IO8(0x22)
298
299#define GTCCR   _SFR_IO8(0x23)
300#define PSR310  0
301#define TSM     7
302#define PSR2    1
303
304#define TCCR0A  _SFR_IO8(0x24)
305#define CS00    0
306#define CS01    1
307#define CS02    2
308#define WGM01   3
309#define COM0A0  4
310#define COM0A1  5
311#define WGM00   6
312#define FOC0A   7
313
314/* Reserved [0x25] */
315
316#define TCNT0   _SFR_IO8(0x26)
317
318#define OCR0A   _SFR_IO8(0x27)
319
320/* Reserved [0x28..0x29] */
321
322#define GPIOR1  _SFR_IO8(0x2A)
323
324#define GPIOR2  _SFR_IO8(0x2B)
325
326#define SPCR    _SFR_IO8(0x2C)
327#define SPR0    0
328#define SPR1    1
329#define CPHA    2
330#define CPOL    3
331#define MSTR    4
332#define DORD    5
333#define SPE     6
334#define SPIE    7
335
336#define SPSR    _SFR_IO8(0x2D)
337#define SPI2X   0
338#define WCOL    6
339#define SPIF    7
340
341#define SPDR    _SFR_IO8(0x2E)
342
343/* Reserved [0x2F] */
344
345#define ACSR    _SFR_IO8(0x30)
346#define ACIS0   0
347#define ACIS1   1
348#define ACIC    2
349#define ACIE    3
350#define ACI     4
351#define ACO     5
352#define ACBG    6
353#define ACD     7
354
355#define OCDR    _SFR_IO8(0x31)
356#define OCDR7   7
357#define OCDR6   6
358#define OCDR5   5
359#define OCDR4   4
360#define OCDR3   3
361#define OCDR2   2
362#define OCDR1   1
363#define OCDR0   0
364
365/* Reserved [0x32] */
366
367#define SMCR    _SFR_IO8(0x33)
368#define SE      0
369#define SM0     1
370#define SM1     2
371#define SM2     3
372
373#define MCUSR   _SFR_IO8(0x34)
374#define JTRF    4
375#define PORF    0
376#define EXTRF   1
377#define BORF    2
378#define WDRF    3
379
380#define MCUCR   _SFR_IO8(0x35)
381#define JTD     7
382#define IVCE    0
383#define IVSEL   1
384#define PUD     4
385#define BODSE   5
386#define BODS    6
387
388/* Reserved [0x36] */
389
390#define SPMCSR  _SFR_IO8(0x37)
391#define SPMEN   0
392#define PGERS   1
393#define PGWRT   2
394#define BLBSET  3
395#define RWWSRE  4
396#define RWWSB   6
397#define SPMIE   7
398
399/* Reserved [0x38..0x3C] */
400
401/* SP [0x3D..0x3E] */
402
403/* SREG [0x3F] */
404
405#define WDTCR   _SFR_MEM8(0x60)
406#define WDP0    0
407#define WDP1    1
408#define WDP2    2
409#define WDE     3
410#define WDCE    4
411
412#define CLKPR   _SFR_MEM8(0x61)
413#define CLKPS0  0
414#define CLKPS1  1
415#define CLKPS2  2
416#define CLKPS3  3
417#define CLKPCE  7
418
419/* Reserved [0x62..0x63] */
420
421#define PRR     _SFR_MEM8(0x64)
422#define PRADC   0
423#define PRUSART0 1
424#define PRSPI   2
425#define PRTIM1  3
426#define PRLCD   4
427
428/* Reserved [0x65] */
429
430#define OSCCAL  _SFR_MEM8(0x66)
431#define OSCCAL0 0
432#define OSCCAL1 1
433#define OSCCAL2 2
434#define OSCCAL3 3
435#define OSCCAL4 4
436#define OSCCAL5 5
437#define OSCCAL6 6
438#define OSCCAL7 7
439
440/* Reserved [0x67..0x68] */
441
442#define EICRA   _SFR_MEM8(0x69)
443#define ISC00   0
444#define ISC01   1
445
446/* Reserved [0x6A] */
447
448#define PCMSK0  _SFR_MEM8(0x6B)
449
450#define PCMSK1  _SFR_MEM8(0x6C)
451
452/* Reserved [0x6D] */
453
454#define TIMSK0  _SFR_MEM8(0x6E)
455#define TOIE0   0
456#define OCIE0A  1
457
458#define TIMSK1  _SFR_MEM8(0x6F)
459#define TOIE1   0
460#define OCIE1A  1
461#define OCIE1B  2
462#define ICIE1   5
463
464#define TIMSK2  _SFR_MEM8(0x70)
465#define TOIE2   0
466#define OCIE2A  1
467
468/* Reserved [0x71..0x77] */
469
470/* Combine ADCL and ADCH */
471#ifndef __ASSEMBLER__
472#define ADC     _SFR_MEM16(0x78)
473#endif
474#define ADCW    _SFR_MEM16(0x78)
475
476#define ADCL    _SFR_MEM8(0x78)
477#define ADCH    _SFR_MEM8(0x79)
478
479#define ADCSRA  _SFR_MEM8(0x7A)
480#define ADPS0   0
481#define ADPS1   1
482#define ADPS2   2
483#define ADIE    3
484#define ADIF    4
485#define ADATE   5
486#define ADSC    6
487#define ADEN    7
488
489#define ADCSRB  _SFR_MEM8(0x7B)
490#define ADTS0   0
491#define ADTS1   1
492#define ADTS2   2
493#define ACME    6
494
495#define ADMUX   _SFR_MEM8(0x7C)
496#define MUX0    0
497#define MUX1    1
498#define MUX2    2
499#define MUX3    3
500#define MUX4    4
501#define ADLAR   5
502#define REFS0   6
503#define REFS1   7
504
505/* Reserved [0x7D] */
506
507#define DIDR0   _SFR_MEM8(0x7E)
508#define ADC0D   0
509#define ADC1D   1
510#define ADC2D   2
511#define ADC3D   3
512#define ADC4D   4
513#define ADC5D   5
514#define ADC6D   6
515#define ADC7D   7
516
517#define DIDR1   _SFR_MEM8(0x7F)
518#define AIN0D   0
519#define AIN1D   1
520
521#define TCCR1A  _SFR_MEM8(0x80)
522#define WGM10   0
523#define WGM11   1
524#define COM1B0  4
525#define COM1B1  5
526#define COM1A0  6
527#define COM1A1  7
528
529#define TCCR1B  _SFR_MEM8(0x81)
530#define CS10    0
531#define CS11    1
532#define CS12    2
533#define WGM12   3
534#define WGM13   4
535#define ICES1   6
536#define ICNC1   7
537
538#define TCCR1C  _SFR_MEM8(0x82)
539#define FOC1B   6
540#define FOC1A   7
541
542/* Reserved [0x83] */
543
544/* Combine TCNT1L and TCNT1H */
545#define TCNT1   _SFR_MEM16(0x84)
546
547#define TCNT1L  _SFR_MEM8(0x84)
548#define TCNT1H  _SFR_MEM8(0x85)
549
550/* Combine ICR1L and ICR1H */
551#define ICR1    _SFR_MEM16(0x86)
552
553#define ICR1L   _SFR_MEM8(0x86)
554#define ICR1H   _SFR_MEM8(0x87)
555
556/* Combine OCR1AL and OCR1AH */
557#define OCR1A   _SFR_MEM16(0x88)
558
559#define OCR1AL  _SFR_MEM8(0x88)
560#define OCR1AH  _SFR_MEM8(0x89)
561
562/* Combine OCR1BL and OCR1BH */
563#define OCR1B   _SFR_MEM16(0x8A)
564
565#define OCR1BL  _SFR_MEM8(0x8A)
566#define OCR1BH  _SFR_MEM8(0x8B)
567
568/* Reserved [0x8C..0xAF] */
569
570#define TCCR2A  _SFR_MEM8(0xB0)
571#define CS20    0
572#define CS21    1
573#define CS22    2
574#define WGM21   3
575#define COM2A0  4
576#define COM2A1  5
577#define WGM20   6
578#define FOC2A   7
579
580/* Reserved [0xB1] */
581
582#define TCNT2   _SFR_MEM8(0xB2)
583
584#define OCR2A   _SFR_MEM8(0xB3)
585
586/* Reserved [0xB4..0xB5] */
587
588#define ASSR    _SFR_MEM8(0xB6)
589#define TCR2UB  0
590#define OCR2UB  1
591#define TCN2UB  2
592#define AS2     3
593#define EXCLK   4
594
595/* Reserved [0xB7] */
596
597#define USICR   _SFR_MEM8(0xB8)
598#define USITC   0
599#define USICLK  1
600#define USICS0  2
601#define USICS1  3
602#define USIWM0  4
603#define USIWM1  5
604#define USIOIE  6
605#define USISIE  7
606
607#define USISR   _SFR_MEM8(0xB9)
608#define USICNT0 0
609#define USICNT1 1
610#define USICNT2 2
611#define USICNT3 3
612#define USIDC   4
613#define USIPF   5
614#define USIOIF  6
615#define USISIF  7
616
617#define USIDR   _SFR_MEM8(0xBA)
618
619/* Reserved [0xBB..0xBF] */
620
621#define UCSR0A  _SFR_MEM8(0xC0)
622#define MPCM0   0
623#define U2X0    1
624#define UPE0    2
625#define DOR0    3
626#define FE0     4
627#define UDRE0   5
628#define TXC0    6
629#define RXC0    7
630
631#define UCSR0B  _SFR_MEM8(0xC1)
632#define TXB80   0
633#define RXB80   1
634#define UCSZ02  2
635#define TXEN0   3
636#define RXEN0   4
637#define UDRIE0  5
638#define TXCIE0  6
639#define RXCIE0  7
640
641#define UCSR0C  _SFR_MEM8(0xC2)
642#define UCPOL0  0
643#define UCSZ00  1
644#define UCSZ01  2
645#define USBS0   3
646#define UPM00   4
647#define UPM01   5
648#define UMSEL0  6
649
650/* Reserved [0xC3] */
651
652/* Combine UBRR0L and UBRR0H */
653#define UBRR0   _SFR_MEM16(0xC4)
654
655#define UBRR0L  _SFR_MEM8(0xC4)
656#define UBRR0H  _SFR_MEM8(0xC5)
657
658#define UDR0    _SFR_MEM8(0xC6)
659
660
661
662/* Interrupt vectors */
663/* Vector 0 is the reset vector */
664/* External Interrupt Request 0 */
665#define INT0_vect            _VECTOR(1)
666#define INT0_vect_num        1
667
668/* Pin Change Interrupt Request 0 */
669#define PCINT0_vect            _VECTOR(2)
670#define PCINT0_vect_num        2
671
672/* Pin Change Interrupt Request 1 */
673#define PCINT1_vect            _VECTOR(3)
674#define PCINT1_vect_num        3
675
676/* Timer/Counter2 Compare Match */
677#define TIMER2_COMP_vect            _VECTOR(4)
678#define TIMER2_COMP_vect_num        4
679
680/* Timer/Counter2 Overflow */
681#define TIMER2_OVF_vect            _VECTOR(5)
682#define TIMER2_OVF_vect_num        5
683
684/* Timer/Counter1 Capture Event */
685#define TIMER1_CAPT_vect            _VECTOR(6)
686#define TIMER1_CAPT_vect_num        6
687
688/* Timer/Counter1 Compare Match A */
689#define TIMER1_COMPA_vect            _VECTOR(7)
690#define TIMER1_COMPA_vect_num        7
691
692/* Timer/Counter Compare Match B */
693#define TIMER1_COMPB_vect            _VECTOR(8)
694#define TIMER1_COMPB_vect_num        8
695
696/* Timer/Counter1 Overflow */
697#define TIMER1_OVF_vect            _VECTOR(9)
698#define TIMER1_OVF_vect_num        9
699
700/* Timer/Counter0 Compare Match */
701#define TIMER0_COMP_vect            _VECTOR(10)
702#define TIMER0_COMP_vect_num        10
703
704/* Timer/Counter0 Overflow */
705#define TIMER0_OVF_vect            _VECTOR(11)
706#define TIMER0_OVF_vect_num        11
707
708/* SPI Serial Transfer Complete */
709#define SPI_STC_vect            _VECTOR(12)
710#define SPI_STC_vect_num        12
711
712/* USART0, Rx Complete */
713#define USART0_RX_vect            _VECTOR(13)
714#define USART0_RX_vect_num        13
715
716/* USART0 Data register Empty */
717#define USART0_UDRE_vect            _VECTOR(14)
718#define USART0_UDRE_vect_num        14
719
720/* USART0, Tx Complete */
721#define USART0_TX_vect            _VECTOR(15)
722#define USART0_TX_vect_num        15
723
724/* USI Start Condition */
725#define USI_START_vect            _VECTOR(16)
726#define USI_START_vect_num        16
727
728/* USI Overflow */
729#define USI_OVERFLOW_vect            _VECTOR(17)
730#define USI_OVERFLOW_vect_num        17
731
732/* Analog Comparator */
733#define ANALOG_COMP_vect            _VECTOR(18)
734#define ANALOG_COMP_vect_num        18
735
736/* ADC Conversion Complete */
737#define ADC_vect            _VECTOR(19)
738#define ADC_vect_num        19
739
740/* EEPROM Ready */
741#define EE_READY_vect            _VECTOR(20)
742#define EE_READY_vect_num        20
743
744/* Store Program Memory Read */
745#define SPM_READY_vect            _VECTOR(21)
746#define SPM_READY_vect_num        21
747
748#define _VECTORS_SIZE 88
749
750
751/* Constants */
752
753#define SPM_PAGESIZE 128
754#define FLASHSTART   0x0000
755#define FLASHEND     0x7FFF
756#define RAMSTART     0x0100
757#define RAMSIZE      2048
758#define RAMEND       0x08FF
759#define E2START     0
760#define E2SIZE      1024
761#define E2PAGESIZE  4
762#define E2END       0x03FF
763#define XRAMEND      RAMEND
764
765
766/* Fuses */
767
768#define FUSE_MEMORY_SIZE 3
769
770/* Low Fuse Byte */
771#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
772#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
773#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
774#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
775#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
776#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
777#define FUSE_CKOUT       (unsigned char)~_BV(6)
778#define FUSE_CKDIV8      (unsigned char)~_BV(7)
779
780/* High Fuse Byte */
781#define FUSE_BOOTRST     (unsigned char)~_BV(0)
782#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
783#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
784#define FUSE_EESAVE      (unsigned char)~_BV(3)
785#define FUSE_WDTON       (unsigned char)~_BV(4)
786#define FUSE_SPIEN       (unsigned char)~_BV(5)
787#define FUSE_JTAGEN      (unsigned char)~_BV(6)
788#define FUSE_OCDEN       (unsigned char)~_BV(7)
789
790/* Extended Fuse Byte */
791#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
792#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
793#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
794
795
796/* Lock Bits */
797#define __LOCK_BITS_EXIST
798#define __BOOT_LOCK_BITS_0_EXIST
799#define __BOOT_LOCK_BITS_1_EXIST
800
801
802/* Signature */
803#define SIGNATURE_0 0x1E
804#define SIGNATURE_1 0x95
805#define SIGNATURE_2 0x0D
806
807
808#endif /* #ifdef _AVR_ATMEGA325PA_H_INCLUDED */
809
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