source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom32a.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

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1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATMEGA32A_H_INCLUDED
36#define _AVR_ATMEGA32A_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "iom32a.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define TWBR    _SFR_IO8(0x00)
52
53#define TWSR    _SFR_IO8(0x01)
54#define TWPS0   0
55#define TWPS1   1
56#define TWS3    3
57#define TWS4    4
58#define TWS5    5
59#define TWS6    6
60#define TWS7    7
61
62#define TWAR    _SFR_IO8(0x02)
63
64#define TWDR    _SFR_IO8(0x03)
65
66/* Combine ADCL and ADCH */
67#ifndef __ASSEMBLER__
68#define ADC     _SFR_IO16(0x04)
69#endif
70#define ADCW    _SFR_IO16(0x04)
71
72#define ADCL    _SFR_IO8(0x04)
73#define ADCH    _SFR_IO8(0x05)
74
75#define ADCSRA  _SFR_IO8(0x06)
76#define ADPS0   0
77#define ADPS1   1
78#define ADPS2   2
79#define ADIE    3
80#define ADIF    4
81#define ADATE   5
82#define ADSC    6
83#define ADEN    7
84
85#define ADMUX   _SFR_IO8(0x07)
86#define MUX0    0
87#define MUX1    1
88#define MUX2    2
89#define MUX3    3
90#define MUX4    4
91#define ADLAR   5
92#define REFS0   6
93#define REFS1   7
94
95#define ACSR    _SFR_IO8(0x08)
96#define ACIS0   0
97#define ACIS1   1
98#define ACIC    2
99#define ACIE    3
100#define ACI     4
101#define ACO     5
102#define ACBG    6
103#define ACD     7
104
105#define UBRRL   _SFR_IO8(0x09)
106
107#define UCSRB   _SFR_IO8(0x0A)
108#define TXB8    0
109#define RXB8    1
110#define UCSZ2   2
111#define TXEN    3
112#define RXEN    4
113#define UDRIE   5
114#define TXCIE   6
115#define RXCIE   7
116
117#define UCSRA   _SFR_IO8(0x0B)
118#define MPCM    0
119#define U2X     1
120#define UPE     2
121#define DOR     3
122#define FE      4
123#define UDRE    5
124#define TXC     6
125#define RXC     7
126
127#define UDR     _SFR_IO8(0x0C)
128
129#define SPCR    _SFR_IO8(0x0D)
130#define SPR0    0
131#define SPR1    1
132#define CPHA    2
133#define CPOL    3
134#define MSTR    4
135#define DORD    5
136#define SPE     6
137#define SPIE    7
138
139#define SPSR    _SFR_IO8(0x0E)
140#define SPI2X   0
141#define WCOL    6
142#define SPIF    7
143
144#define SPDR    _SFR_IO8(0x0F)
145
146#define PIND    _SFR_IO8(0x10)
147#define PIND7   7
148#define PIND6   6
149#define PIND5   5
150#define PIND4   4
151#define PIND3   3
152#define PIND2   2
153#define PIND1   1
154#define PIND0   0
155
156#define DDRD    _SFR_IO8(0x11)
157#define DDRD7   7
158// Inserted "DDD7" from "DDRD7" due to compatibility
159#define DDD7    7
160#define DDRD6   6
161// Inserted "DDD6" from "DDRD6" due to compatibility
162#define DDD6    6
163#define DDRD5   5
164// Inserted "DDD5" from "DDRD5" due to compatibility
165#define DDD5    5
166#define DDRD4   4
167// Inserted "DDD4" from "DDRD4" due to compatibility
168#define DDD4    4
169#define DDRD3   3
170// Inserted "DDD3" from "DDRD3" due to compatibility
171#define DDD3    3
172#define DDRD2   2
173// Inserted "DDD2" from "DDRD2" due to compatibility
174#define DDD2    2
175#define DDRD1   1
176// Inserted "DDD1" from "DDRD1" due to compatibility
177#define DDD1    1
178#define DDRD0   0
179// Inserted "DDD0" from "DDRD0" due to compatibility
180#define DDD0    0
181
182#define PORTD   _SFR_IO8(0x12)
183#define PORTD7  7
184#define PORTD6  6
185#define PORTD5  5
186#define PORTD4  4
187#define PORTD3  3
188#define PORTD2  2
189#define PORTD1  1
190#define PORTD0  0
191
192#define PINC    _SFR_IO8(0x13)
193#define PINC7   7
194#define PINC6   6
195#define PINC5   5
196#define PINC4   4
197#define PINC3   3
198#define PINC2   2
199#define PINC1   1
200#define PINC0   0
201
202#define DDRC    _SFR_IO8(0x14)
203#define DDRC7   7
204// Inserted "DDC7" from "DDRC7" due to compatibility
205#define DDC7    7
206#define DDRC6   6
207// Inserted "DDC6" from "DDRC6" due to compatibility
208#define DDC6    6
209#define DDRC5   5
210// Inserted "DDC5" from "DDRC5" due to compatibility
211#define DDC5    5
212#define DDRC4   4
213// Inserted "DDC4" from "DDRC4" due to compatibility
214#define DDC4    4
215#define DDRC3   3
216// Inserted "DDC3" from "DDRC3" due to compatibility
217#define DDC3    3
218#define DDRC2   2
219// Inserted "DDC2" from "DDRC2" due to compatibility
220#define DDC2    2
221#define DDRC1   1
222// Inserted "DDC1" from "DDRC1" due to compatibility
223#define DDC1    1
224#define DDRC0   0
225// Inserted "DDC0" from "DDRC0" due to compatibility
226#define DDC0    0
227
228#define PORTC   _SFR_IO8(0x15)
229#define PORTC7  7
230#define PORTC6  6
231#define PORTC5  5
232#define PORTC4  4
233#define PORTC3  3
234#define PORTC2  2
235#define PORTC1  1
236#define PORTC0  0
237
238#define PINB    _SFR_IO8(0x16)
239#define PINB7   7
240#define PINB6   6
241#define PINB5   5
242#define PINB4   4
243#define PINB3   3
244#define PINB2   2
245#define PINB1   1
246#define PINB0   0
247
248#define DDRB    _SFR_IO8(0x17)
249#define DDRB7   7
250// Inserted "DDB7" from "DDRB7" due to compatibility
251#define DDB7    7
252#define DDRB6   6
253// Inserted "DDB6" from "DDRB6" due to compatibility
254#define DDB6    6
255#define DDRB5   5
256// Inserted "DDB5" from "DDRB5" due to compatibility
257#define DDB5    5
258#define DDRB4   4
259// Inserted "DDB4" from "DDRB4" due to compatibility
260#define DDB4    4
261#define DDRB3   3
262// Inserted "DDB3" from "DDRB3" due to compatibility
263#define DDB3    3
264#define DDRB2   2
265// Inserted "DDB2" from "DDRB2" due to compatibility
266#define DDB2    2
267#define DDRB1   1
268// Inserted "DDB1" from "DDRB1" due to compatibility
269#define DDB1    1
270#define DDRB0   0
271// Inserted "DDB0" from "DDRB0" due to compatibility
272#define DDB0    0
273
274#define PORTB   _SFR_IO8(0x18)
275#define PORTB7  7
276#define PORTB6  6
277#define PORTB5  5
278#define PORTB4  4
279#define PORTB3  3
280#define PORTB2  2
281#define PORTB1  1
282#define PORTB0  0
283
284#define PINA    _SFR_IO8(0x19)
285#define PINA7   7
286#define PINA6   6
287#define PINA5   5
288#define PINA4   4
289#define PINA3   3
290#define PINA2   2
291#define PINA1   1
292#define PINA0   0
293
294#define DDRA    _SFR_IO8(0x1A)
295#define DDRA7   7
296// Inserted "DDA7" from "DDRA7" due to compatibility
297#define DDA7    7
298#define DDRA6   6
299// Inserted "DDA6" from "DDRA6" due to compatibility
300#define DDA6    6
301#define DDRA5   5
302// Inserted "DDA5" from "DDRA5" due to compatibility
303#define DDA5    5
304#define DDRA4   4
305// Inserted "DDA4" from "DDRA4" due to compatibility
306#define DDA4    4
307#define DDRA3   3
308// Inserted "DDA3" from "DDRA3" due to compatibility
309#define DDA3    3
310#define DDRA2   2
311// Inserted "DDA2" from "DDRA2" due to compatibility
312#define DDA2    2
313#define DDRA1   1
314// Inserted "DDA1" from "DDRA1" due to compatibility
315#define DDA1    1
316#define DDRA0   0
317// Inserted "DDA0" from "DDRA0" due to compatibility
318#define DDA0    0
319
320#define PORTA   _SFR_IO8(0x1B)
321#define PORTA7  7
322#define PORTA6  6
323#define PORTA5  5
324#define PORTA4  4
325#define PORTA3  3
326#define PORTA2  2
327#define PORTA1  1
328#define PORTA0  0
329
330#define EECR    _SFR_IO8(0x1C)
331#define EERE    0
332#define EEWE    1
333#define EEMWE   2
334#define EERIE   3
335
336#define EEDR    _SFR_IO8(0x1D)
337
338/* Combine EEARL and EEARH */
339#define EEAR    _SFR_IO16(0x1E)
340
341#define EEARL   _SFR_IO8(0x1E)
342#define EEARH   _SFR_IO8(0x1F)
343
344#define UCSRC   _SFR_IO8(0x20)
345#define UCPOL   0
346#define UCSZ0   1
347#define UCSZ1   2
348#define USBS    3
349#define UPM0    4
350#define UPM1    5
351#define UMSEL   6
352#define URSEL   7
353
354#define UBRRH   _SFR_IO8(0x20)
355
356#define WDTCR   _SFR_IO8(0x21)
357#define WDP0    0
358#define WDP1    1
359#define WDP2    2
360#define WDE     3
361#define WDTOE   4
362
363#define ASSR    _SFR_IO8(0x22)
364#define TCR2UB  0
365#define OCR2UB  1
366#define TCN2UB  2
367#define AS2     3
368
369#define OCR2    _SFR_IO8(0x23)
370
371#define TCNT2   _SFR_IO8(0x24)
372
373#define TCCR2   _SFR_IO8(0x25)
374#define CS20    0
375#define CS21    1
376#define CS22    2
377#define WGM21   3
378#define COM20   4
379#define COM21   5
380#define WGM20   6
381#define FOC2    7
382
383/* Combine ICR1L and ICR1H */
384#define ICR1    _SFR_IO16(0x26)
385
386#define ICR1L   _SFR_IO8(0x26)
387#define ICR1H   _SFR_IO8(0x27)
388
389/* Combine OCR1BL and OCR1BH */
390#define OCR1B   _SFR_IO16(0x28)
391
392#define OCR1BL  _SFR_IO8(0x28)
393#define OCR1BH  _SFR_IO8(0x29)
394
395/* Combine OCR1AL and OCR1AH */
396#define OCR1A   _SFR_IO16(0x2A)
397
398#define OCR1AL  _SFR_IO8(0x2A)
399#define OCR1AH  _SFR_IO8(0x2B)
400
401/* Combine TCNT1L and TCNT1H */
402#define TCNT1   _SFR_IO16(0x2C)
403
404#define TCNT1L  _SFR_IO8(0x2C)
405#define TCNT1H  _SFR_IO8(0x2D)
406
407#define TCCR1B  _SFR_IO8(0x2E)
408#define CS10    0
409#define CS11    1
410#define CS12    2
411#define WGM12   3
412#define WGM13   4
413#define ICES1   6
414#define ICNC1   7
415
416#define TCCR1A  _SFR_IO8(0x2F)
417#define WGM10   0
418#define WGM11   1
419#define FOC1B   2
420#define FOC1A   3
421#define COM1B0  4
422#define COM1B1  5
423#define COM1A0  6
424#define COM1A1  7
425
426#define SFIOR   _SFR_IO8(0x30)
427#define PSR2    0
428#define PSR10   0
429#define PUD     2
430#define ACME    3
431#define ADTS0   5
432#define ADTS1   6
433#define ADTS2   7
434
435#define OSCCAL  _SFR_IO8(0x31)
436#define OSCCAL0 0
437#define OSCCAL1 1
438#define OSCCAL2 2
439#define OSCCAL3 3
440#define OSCCAL4 4
441#define OSCCAL5 5
442#define OSCCAL6 6
443#define OSCCAL7 7
444
445#define TCNT0   _SFR_IO8(0x32)
446
447#define TCCR0   _SFR_IO8(0x33)
448#define CS00    0
449#define CS01    1
450#define CS02    2
451#define WGM01   3
452#define COM00   4
453#define COM01   5
454#define WGM00   6
455#define FOC0    7
456
457#define MCUCSR  _SFR_IO8(0x34)
458#define ISC2    6
459#define PORF    0
460#define EXTRF   1
461#define BORF    2
462#define WDRF    3
463#define JTRF    4
464#define JTD     7
465
466#define MCUCR   _SFR_IO8(0x35)
467#define ISC00   0
468#define ISC01   1
469#define ISC10   2
470#define ISC11   3
471#define SM0     4
472#define SM1     5
473#define SM2     6
474#define SE      7
475
476#define TWCR    _SFR_IO8(0x36)
477#define TWIE    0
478#define TWEN    2
479#define TWWC    3
480#define TWSTO   4
481#define TWSTA   5
482#define TWEA    6
483#define TWINT   7
484
485#define SPMCR   _SFR_IO8(0x37)
486#define SPMEN   0
487#define PGERS   1
488#define PGWRT   2
489#define BLBSET  3
490#define RWWSRE  4
491#define RWWSB   6
492#define SPMIE   7
493
494#define TIFR    _SFR_IO8(0x38)
495#define TOV0    0
496#define OCF0    1
497#define TOV2    6
498#define OCF2    7
499#define TOV1    2
500#define OCF1B   3
501#define OCF1A   4
502#define ICF1    5
503
504#define TIMSK   _SFR_IO8(0x39)
505#define TOIE0   0
506#define OCIE0   1
507#define TOIE2   6
508#define OCIE2   7
509#define TOIE1   2
510#define OCIE1B  3
511#define OCIE1A  4
512#define TICIE1  5
513
514#define GIFR    _SFR_IO8(0x3A)
515#define INTF2   5
516#define INTF0   6
517#define INTF1   7
518
519#define GICR    _SFR_IO8(0x3B)
520#define IVCE    0
521#define IVSEL   1
522#define INT2    5
523#define INT0    6
524#define INT1    7
525
526#define OCR0    _SFR_IO8(0x3C)
527
528/* SP [0x3D..0x3E] */
529
530/* SREG [0x3F] */
531
532
533
534/* Values and associated defines */
535
536
537#define SLEEP_MODE_IDLE (0x00<<4)
538#define SLEEP_MODE_ADC (0x01<<4)
539#define SLEEP_MODE_PWR_DOWN (0x02<<4)
540#define SLEEP_MODE_PWR_SAVE (0x03<<4)
541#define SLEEP_MODE_STANDBY (0x06<<4)
542#define SLEEP_MODE_EXT_STANDBY (0x07<<4)
543
544/* Interrupt vectors */
545/* Vector 0 is the reset vector */
546/* External Interrupt Request 0 */
547#define INT0_vect            _VECTOR(1)
548#define INT0_vect_num        1
549
550/* External Interrupt Request 1 */
551#define INT1_vect            _VECTOR(2)
552#define INT1_vect_num        2
553
554/* External Interrupt Request 2 */
555#define INT2_vect            _VECTOR(3)
556#define INT2_vect_num        3
557
558/* Timer/Counter2 Compare Match */
559#define TIMER2_COMP_vect            _VECTOR(4)
560#define TIMER2_COMP_vect_num        4
561
562/* Timer/Counter2 Overflow */
563#define TIMER2_OVF_vect            _VECTOR(5)
564#define TIMER2_OVF_vect_num        5
565
566/* Timer/Counter1 Capture Event */
567#define TIMER1_CAPT_vect            _VECTOR(6)
568#define TIMER1_CAPT_vect_num        6
569
570/* Timer/Counter1 Compare Match A */
571#define TIMER1_COMPA_vect            _VECTOR(7)
572#define TIMER1_COMPA_vect_num        7
573
574/* Timer/Counter1 Compare Match B */
575#define TIMER1_COMPB_vect            _VECTOR(8)
576#define TIMER1_COMPB_vect_num        8
577
578/* Timer/Counter1 Overflow */
579#define TIMER1_OVF_vect            _VECTOR(9)
580#define TIMER1_OVF_vect_num        9
581
582/* Timer/Counter0 Compare Match */
583#define TIMER0_COMP_vect            _VECTOR(10)
584#define TIMER0_COMP_vect_num        10
585
586/* Timer/Counter0 Overflow */
587#define TIMER0_OVF_vect            _VECTOR(11)
588#define TIMER0_OVF_vect_num        11
589
590/* Serial Transfer Complete */
591#define SPI_STC_vect            _VECTOR(12)
592#define SPI_STC_vect_num        12
593
594/* USART, Rx Complete */
595#define USART_RXC_vect            _VECTOR(13)
596#define USART_RXC_vect_num        13
597
598/* USART Data Register Empty */
599#define USART_UDRE_vect            _VECTOR(14)
600#define USART_UDRE_vect_num        14
601
602/* USART, Tx Complete */
603#define USART_TXC_vect            _VECTOR(15)
604#define USART_TXC_vect_num        15
605
606/* ADC Conversion Complete */
607#define ADC_vect            _VECTOR(16)
608#define ADC_vect_num        16
609
610/* EEPROM Ready */
611#define EE_RDY_vect            _VECTOR(17)
612#define EE_RDY_vect_num        17
613
614/* Analog Comparator */
615#define ANA_COMP_vect            _VECTOR(18)
616#define ANA_COMP_vect_num        18
617
618/* 2-wire Serial Interface */
619#define TWI_vect            _VECTOR(19)
620#define TWI_vect_num        19
621
622/* Store Program Memory Ready */
623#define SPM_RDY_vect            _VECTOR(20)
624#define SPM_RDY_vect_num        20
625
626#define _VECTORS_SIZE 84
627
628
629/* Constants */
630
631#define SPM_PAGESIZE 128
632#define FLASHSTART   0x0000
633#define FLASHEND     0x7FFF
634#define RAMSTART     0x0060
635#define RAMSIZE      2048
636#define RAMEND       0x085F
637#define E2START     0
638#define E2SIZE      1024
639#define E2PAGESIZE  4
640#define E2END       0x03FF
641#define XRAMEND      RAMEND
642
643
644/* Fuses */
645
646#define FUSE_MEMORY_SIZE 2
647
648/* Low Fuse Byte */
649#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
650#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
651#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
652#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
653#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
654#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
655#define FUSE_BODEN       (unsigned char)~_BV(6)
656#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
657#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL1 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4)
658
659
660/* High Fuse Byte */
661#define FUSE_BOOTRST     (unsigned char)~_BV(0)
662#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
663#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
664#define FUSE_EESAVE      (unsigned char)~_BV(3)
665#define FUSE_CKOPT       (unsigned char)~_BV(4)
666#define FUSE_SPIEN       (unsigned char)~_BV(5)
667#define FUSE_JTAGEN      (unsigned char)~_BV(6)
668#define FUSE_OCDEN       (unsigned char)~_BV(7)
669#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
670
671
672
673/* Lock Bits */
674#define __LOCK_BITS_EXIST
675#define __BOOT_LOCK_BITS_0_EXIST
676#define __BOOT_LOCK_BITS_1_EXIST
677
678
679/* Signature */
680#define SIGNATURE_0 0x1E
681#define SIGNATURE_1 0x95
682#define SIGNATURE_2 0x02
683
684
685#endif /* #ifdef _AVR_ATMEGA32A_H_INCLUDED */
686
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