source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom48pa.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

File size: 18.9 KB
Line 
1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATMEGA48PA_H_INCLUDED
36#define _AVR_ATMEGA48PA_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "iom48pa.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINB    _SFR_IO8(0x03)
52#define PINB7   7
53#define PINB6   6
54#define PINB5   5
55#define PINB4   4
56#define PINB3   3
57#define PINB2   2
58#define PINB1   1
59#define PINB0   0
60
61#define DDRB    _SFR_IO8(0x04)
62#define DDRB7   7
63// Inserted "DDB7" from "DDRB7" due to compatibility
64#define DDB7    7
65#define DDRB6   6
66// Inserted "DDB6" from "DDRB6" due to compatibility
67#define DDB6    6
68#define DDRB5   5
69// Inserted "DDB5" from "DDRB5" due to compatibility
70#define DDB5    5
71#define DDRB4   4
72// Inserted "DDB4" from "DDRB4" due to compatibility
73#define DDB4    4
74#define DDRB3   3
75// Inserted "DDB3" from "DDRB3" due to compatibility
76#define DDB3    3
77#define DDRB2   2
78// Inserted "DDB2" from "DDRB2" due to compatibility
79#define DDB2    2
80#define DDRB1   1
81// Inserted "DDB1" from "DDRB1" due to compatibility
82#define DDB1    1
83#define DDRB0   0
84// Inserted "DDB0" from "DDRB0" due to compatibility
85#define DDB0    0
86
87#define PORTB   _SFR_IO8(0x05)
88#define PORTB7  7
89#define PORTB6  6
90#define PORTB5  5
91#define PORTB4  4
92#define PORTB3  3
93#define PORTB2  2
94#define PORTB1  1
95#define PORTB0  0
96
97#define PINC    _SFR_IO8(0x06)
98#define PINC6   6
99#define PINC5   5
100#define PINC4   4
101#define PINC3   3
102#define PINC2   2
103#define PINC1   1
104#define PINC0   0
105
106#define DDRC    _SFR_IO8(0x07)
107#define DDRC6   6
108// Inserted "DDC6" from "DDRC6" due to compatibility
109#define DDC6    6
110#define DDRC5   5
111// Inserted "DDC5" from "DDRC5" due to compatibility
112#define DDC5    5
113#define DDRC4   4
114// Inserted "DDC4" from "DDRC4" due to compatibility
115#define DDC4    4
116#define DDRC3   3
117// Inserted "DDC3" from "DDRC3" due to compatibility
118#define DDC3    3
119#define DDRC2   2
120// Inserted "DDC2" from "DDRC2" due to compatibility
121#define DDC2    2
122#define DDRC1   1
123// Inserted "DDC1" from "DDRC1" due to compatibility
124#define DDC1    1
125#define DDRC0   0
126// Inserted "DDC0" from "DDRC0" due to compatibility
127#define DDC0    0
128
129#define PORTC   _SFR_IO8(0x08)
130#define PORTC6  6
131#define PORTC5  5
132#define PORTC4  4
133#define PORTC3  3
134#define PORTC2  2
135#define PORTC1  1
136#define PORTC0  0
137
138#define PIND    _SFR_IO8(0x09)
139#define PIND7   7
140#define PIND6   6
141#define PIND5   5
142#define PIND4   4
143#define PIND3   3
144#define PIND2   2
145#define PIND1   1
146#define PIND0   0
147
148#define DDRD    _SFR_IO8(0x0A)
149#define DDRD7   7
150// Inserted "DDD7" from "DDRD7" due to compatibility
151#define DDD7    7
152#define DDRD6   6
153// Inserted "DDD6" from "DDRD6" due to compatibility
154#define DDD6    6
155#define DDRD5   5
156// Inserted "DDD5" from "DDRD5" due to compatibility
157#define DDD5    5
158#define DDRD4   4
159// Inserted "DDD4" from "DDRD4" due to compatibility
160#define DDD4    4
161#define DDRD3   3
162// Inserted "DDD3" from "DDRD3" due to compatibility
163#define DDD3    3
164#define DDRD2   2
165// Inserted "DDD2" from "DDRD2" due to compatibility
166#define DDD2    2
167#define DDRD1   1
168// Inserted "DDD1" from "DDRD1" due to compatibility
169#define DDD1    1
170#define DDRD0   0
171// Inserted "DDD0" from "DDRD0" due to compatibility
172#define DDD0    0
173
174#define PORTD   _SFR_IO8(0x0B)
175#define PORTD7  7
176#define PORTD6  6
177#define PORTD5  5
178#define PORTD4  4
179#define PORTD3  3
180#define PORTD2  2
181#define PORTD1  1
182#define PORTD0  0
183
184/* Reserved [0x0C..0x14] */
185
186#define TIFR0   _SFR_IO8(0x15)
187#define TOV0    0
188#define OCF0A   1
189#define OCF0B   2
190
191#define TIFR1   _SFR_IO8(0x16)
192#define TOV1    0
193#define OCF1A   1
194#define OCF1B   2
195#define ICF1    5
196
197#define TIFR2   _SFR_IO8(0x17)
198#define TOV2    0
199#define OCF2A   1
200#define OCF2B   2
201
202/* Reserved [0x18..0x1A] */
203
204#define PCIFR   _SFR_IO8(0x1B)
205#define PCIF0   0
206#define PCIF1   1
207#define PCIF2   2
208
209#define EIFR    _SFR_IO8(0x1C)
210#define INTF0   0
211#define INTF1   1
212
213#define EIMSK   _SFR_IO8(0x1D)
214#define INT0    0
215#define INT1    1
216
217#define GPIOR0  _SFR_IO8(0x1E)
218
219#define EECR    _SFR_IO8(0x1F)
220#define EERE    0
221#define EEPE    1
222#define EEMPE   2
223#define EERIE   3
224#define EEPM0   4
225#define EEPM1   5
226
227#define EEDR    _SFR_IO8(0x20)
228
229#define EEARL   _SFR_IO8(0x21)
230
231#define EEARH   _SFR_IO8(0x22)
232#define EEAR8   0
233#define EEAR9   1
234
235#define GTCCR   _SFR_IO8(0x23)
236#define PSRSYNC 0
237#define TSM     7
238#define PSRASY  1
239
240#define TCCR0A  _SFR_IO8(0x24)
241#define WGM00   0
242#define WGM01   1
243#define COM0B0  4
244#define COM0B1  5
245#define COM0A0  6
246#define COM0A1  7
247
248#define TCCR0B  _SFR_IO8(0x25)
249#define CS00    0
250#define CS01    1
251#define CS02    2
252#define WGM02   3
253#define FOC0B   6
254#define FOC0A   7
255
256#define TCNT0   _SFR_IO8(0x26)
257
258#define OCR0A   _SFR_IO8(0x27)
259
260#define OCR0B   _SFR_IO8(0x28)
261
262/* Reserved [0x29] */
263
264#define GPIOR1  _SFR_IO8(0x2A)
265
266#define GPIOR2  _SFR_IO8(0x2B)
267
268#define SPCR    _SFR_IO8(0x2C)
269#define SPR0    0
270#define SPR1    1
271#define CPHA    2
272#define CPOL    3
273#define MSTR    4
274#define DORD    5
275#define SPE     6
276#define SPIE    7
277
278#define SPSR    _SFR_IO8(0x2D)
279#define SPI2X   0
280#define WCOL    6
281#define SPIF    7
282
283#define SPDR    _SFR_IO8(0x2E)
284
285/* Reserved [0x2F] */
286
287#define ACSR    _SFR_IO8(0x30)
288#define ACIS0   0
289#define ACIS1   1
290#define ACIC    2
291#define ACIE    3
292#define ACI     4
293#define ACO     5
294#define ACBG    6
295#define ACD     7
296
297/* Reserved [0x31..0x32] */
298
299#define SMCR    _SFR_IO8(0x33)
300#define SE      0
301#define SM0     1
302#define SM1     2
303#define SM2     3
304
305#define MCUSR   _SFR_IO8(0x34)
306#define PORF    0
307#define EXTRF   1
308#define BORF    2
309#define WDRF    3
310
311#define MCUCR   _SFR_IO8(0x35)
312#define IVCE    0
313#define IVSEL   1
314#define PUD     4
315#define BODSE   5
316#define BODS    6
317
318/* Reserved [0x36] */
319
320#define SPMCSR  _SFR_IO8(0x37)
321#define SPMEN   0
322#define PGERS   1
323#define PGWRT   2
324#define BLBSET  3
325#define RWWSRE  4
326#define SIGRD   5
327#define RWWSB   6
328#define SPMIE   7
329
330/* Reserved [0x38..0x3C] */
331
332/* SP [0x3D..0x3E] */
333
334/* SREG [0x3F] */
335
336#define WDTCSR  _SFR_MEM8(0x60)
337#define WDE     3
338#define WDCE    4
339#define WDP0    0
340#define WDP1    1
341#define WDP2    2
342#define WDP3    5
343#define WDIE    6
344#define WDIF    7
345
346#define CLKPR   _SFR_MEM8(0x61)
347#define CLKPS0  0
348#define CLKPS1  1
349#define CLKPS2  2
350#define CLKPS3  3
351#define CLKPCE  7
352
353/* Reserved [0x62..0x63] */
354
355#define PRR     _SFR_MEM8(0x64)
356#define PRADC   0
357#define PRUSART0 1
358#define PRSPI   2
359#define PRTIM1  3
360#define PRTIM0  5
361#define PRTIM2  6
362#define PRTWI   7
363
364#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
365#define __AVR_HAVE_PRR_PRADC
366#define __AVR_HAVE_PRR_PRUSART0
367#define __AVR_HAVE_PRR_PRSPI
368#define __AVR_HAVE_PRR_PRTIM1
369#define __AVR_HAVE_PRR_PRTIM0
370#define __AVR_HAVE_PRR_PRTIM2
371#define __AVR_HAVE_PRR_PRTWI
372
373/* Reserved [0x65] */
374
375#define OSCCAL  _SFR_MEM8(0x66)
376#define OSCCAL0 0
377#define OSCCAL1 1
378#define OSCCAL2 2
379#define OSCCAL3 3
380#define OSCCAL4 4
381#define OSCCAL5 5
382#define OSCCAL6 6
383#define OSCCAL7 7
384
385/* Reserved [0x67] */
386
387#define PCICR   _SFR_MEM8(0x68)
388#define PCIE0   0
389#define PCIE1   1
390#define PCIE2   2
391
392#define EICRA   _SFR_MEM8(0x69)
393#define ISC00   0
394#define ISC01   1
395#define ISC10   2
396#define ISC11   3
397
398/* Reserved [0x6A] */
399
400#define PCMSK0  _SFR_MEM8(0x6B)
401#define PCINT0  0
402#define PCINT1  1
403#define PCINT2  2
404#define PCINT3  3
405#define PCINT4  4
406#define PCINT5  5
407#define PCINT6  6
408#define PCINT7  7
409
410#define PCMSK1  _SFR_MEM8(0x6C)
411#define PCINT8  0
412#define PCINT9  1
413#define PCINT10 2
414#define PCINT11 3
415#define PCINT12 4
416#define PCINT13 5
417#define PCINT14 6
418
419#define PCMSK2  _SFR_MEM8(0x6D)
420#define PCINT16 0
421#define PCINT17 1
422#define PCINT18 2
423#define PCINT19 3
424#define PCINT20 4
425#define PCINT21 5
426#define PCINT22 6
427#define PCINT23 7
428
429#define TIMSK0  _SFR_MEM8(0x6E)
430#define TOIE0   0
431#define OCIE0A  1
432#define OCIE0B  2
433
434#define TIMSK1  _SFR_MEM8(0x6F)
435#define TOIE1   0
436#define OCIE1A  1
437#define OCIE1B  2
438#define ICIE1   5
439
440#define TIMSK2  _SFR_MEM8(0x70)
441#define TOIE2   0
442#define OCIE2A  1
443#define OCIE2B  2
444
445/* Reserved [0x71..0x77] */
446
447/* Combine ADCL and ADCH */
448#ifndef __ASSEMBLER__
449#define ADC     _SFR_MEM16(0x78)
450#endif
451#define ADCW    _SFR_MEM16(0x78)
452
453#define ADCL    _SFR_MEM8(0x78)
454#define ADCH    _SFR_MEM8(0x79)
455
456#define ADCSRA  _SFR_MEM8(0x7A)
457#define ADPS0   0
458#define ADPS1   1
459#define ADPS2   2
460#define ADIE    3
461#define ADIF    4
462#define ADATE   5
463#define ADSC    6
464#define ADEN    7
465
466#define ADCSRB  _SFR_MEM8(0x7B)
467#define ADTS0   0
468#define ADTS1   1
469#define ADTS2   2
470#define ACME    6
471
472#define ADMUX   _SFR_MEM8(0x7C)
473#define MUX0    0
474#define MUX1    1
475#define MUX2    2
476#define MUX3    3
477#define ADLAR   5
478#define REFS0   6
479#define REFS1   7
480
481/* Reserved [0x7D] */
482
483#define DIDR0   _SFR_MEM8(0x7E)
484#define ADC0D   0
485#define ADC1D   1
486#define ADC2D   2
487#define ADC3D   3
488#define ADC4D   4
489#define ADC5D   5
490
491#define DIDR1   _SFR_MEM8(0x7F)
492#define AIN0D   0
493#define AIN1D   1
494
495#define TCCR1A  _SFR_MEM8(0x80)
496#define WGM10   0
497#define WGM11   1
498#define COM1B0  4
499#define COM1B1  5
500#define COM1A0  6
501#define COM1A1  7
502
503#define TCCR1B  _SFR_MEM8(0x81)
504#define CS10    0
505#define CS11    1
506#define CS12    2
507#define WGM12   3
508#define WGM13   4
509#define ICES1   6
510#define ICNC1   7
511
512#define TCCR1C  _SFR_MEM8(0x82)
513#define FOC1B   6
514#define FOC1A   7
515
516/* Reserved [0x83] */
517
518/* Combine TCNT1L and TCNT1H */
519#define TCNT1   _SFR_MEM16(0x84)
520
521#define TCNT1L  _SFR_MEM8(0x84)
522#define TCNT1H  _SFR_MEM8(0x85)
523
524/* Combine ICR1L and ICR1H */
525#define ICR1    _SFR_MEM16(0x86)
526
527#define ICR1L   _SFR_MEM8(0x86)
528#define ICR1H   _SFR_MEM8(0x87)
529
530/* Combine OCR1AL and OCR1AH */
531#define OCR1A   _SFR_MEM16(0x88)
532
533#define OCR1AL  _SFR_MEM8(0x88)
534#define OCR1AH  _SFR_MEM8(0x89)
535
536/* Combine OCR1BL and OCR1BH */
537#define OCR1B   _SFR_MEM16(0x8A)
538
539#define OCR1BL  _SFR_MEM8(0x8A)
540#define OCR1BH  _SFR_MEM8(0x8B)
541
542/* Reserved [0x8C..0xAF] */
543
544#define TCCR2A  _SFR_MEM8(0xB0)
545#define WGM20   0
546#define WGM21   1
547#define COM2B0  4
548#define COM2B1  5
549#define COM2A0  6
550#define COM2A1  7
551
552#define TCCR2B  _SFR_MEM8(0xB1)
553#define CS20    0
554#define CS21    1
555#define CS22    2
556#define WGM22   3
557#define FOC2B   6
558#define FOC2A   7
559
560#define TCNT2   _SFR_MEM8(0xB2)
561
562#define OCR2A   _SFR_MEM8(0xB3)
563
564#define OCR2B   _SFR_MEM8(0xB4)
565
566/* Reserved [0xB5] */
567
568#define ASSR    _SFR_MEM8(0xB6)
569#define TCR2BUB 0
570#define TCR2AUB 1
571#define OCR2BUB 2
572#define OCR2AUB 3
573#define TCN2UB  4
574#define AS2     5
575#define EXCLK   6
576
577/* Reserved [0xB7] */
578
579#define TWBR    _SFR_MEM8(0xB8)
580
581#define TWSR    _SFR_MEM8(0xB9)
582#define TWPS0   0
583#define TWPS1   1
584#define TWS3    3
585#define TWS4    4
586#define TWS5    5
587#define TWS6    6
588#define TWS7    7
589
590#define TWAR    _SFR_MEM8(0xBA)
591#define TWGCE   0
592#define TWA0    1
593#define TWA1    2
594#define TWA2    3
595#define TWA3    4
596#define TWA4    5
597#define TWA5    6
598#define TWA6    7
599
600#define TWDR    _SFR_MEM8(0xBB)
601
602#define TWCR    _SFR_MEM8(0xBC)
603#define TWIE    0
604#define TWEN    2
605#define TWWC    3
606#define TWSTO   4
607#define TWSTA   5
608#define TWEA    6
609#define TWINT   7
610
611#define TWAMR   _SFR_MEM8(0xBD)
612#define TWAM0   1
613#define TWAM1   2
614#define TWAM2   3
615#define TWAM3   4
616#define TWAM4   5
617#define TWAM5   6
618#define TWAM6   7
619
620/* Reserved [0xBE..0xBF] */
621
622#define UCSR0A  _SFR_MEM8(0xC0)
623#define MPCM0   0
624#define U2X0    1
625#define UPE0    2
626#define DOR0    3
627#define FE0     4
628#define UDRE0   5
629#define TXC0    6
630#define RXC0    7
631
632#define UCSR0B  _SFR_MEM8(0xC1)
633#define TXB80   0
634#define RXB80   1
635#define UCSZ02  2
636#define TXEN0   3
637#define RXEN0   4
638#define UDRIE0  5
639#define TXCIE0  6
640#define RXCIE0  7
641
642#define UCSR0C  _SFR_MEM8(0xC2)
643#define UCPOL0  0
644#define UCSZ00  1
645#define UCSZ01  2
646#define USBS0   3
647#define UPM00   4
648#define UPM01   5
649#define UMSEL00 6
650#define UMSEL01 7
651
652/* Reserved [0xC3] */
653
654/* Combine UBRR0L and UBRR0H */
655#define UBRR0   _SFR_MEM16(0xC4)
656
657#define UBRR0L  _SFR_MEM8(0xC4)
658#define UBRR0H  _SFR_MEM8(0xC5)
659
660#define UDR0    _SFR_MEM8(0xC6)
661
662
663
664/* Values and associated defines */
665
666
667#define SLEEP_MODE_IDLE (0x00<<1)
668#define SLEEP_MODE_ADC (0x01<<1)
669#define SLEEP_MODE_PWR_DOWN (0x02<<1)
670#define SLEEP_MODE_PWR_SAVE (0x03<<1)
671#define SLEEP_MODE_STANDBY (0x06<<1)
672#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
673
674/* Interrupt vectors */
675/* Vector 0 is the reset vector */
676/* External Interrupt Request 0 */
677#define INT0_vect            _VECTOR(1)
678#define INT0_vect_num        1
679
680/* External Interrupt Request 1 */
681#define INT1_vect            _VECTOR(2)
682#define INT1_vect_num        2
683
684/* Pin Change Interrupt Request 0 */
685#define PCINT0_vect            _VECTOR(3)
686#define PCINT0_vect_num        3
687
688/* Pin Change Interrupt Request 0 */
689#define PCINT1_vect            _VECTOR(4)
690#define PCINT1_vect_num        4
691
692/* Pin Change Interrupt Request 1 */
693#define PCINT2_vect            _VECTOR(5)
694#define PCINT2_vect_num        5
695
696/* Watchdog Time-out Interrupt */
697#define WDT_vect            _VECTOR(6)
698#define WDT_vect_num        6
699
700/* Timer/Counter2 Compare Match A */
701#define TIMER2_COMPA_vect            _VECTOR(7)
702#define TIMER2_COMPA_vect_num        7
703
704/* Timer/Counter2 Compare Match A */
705#define TIMER2_COMPB_vect            _VECTOR(8)
706#define TIMER2_COMPB_vect_num        8
707
708/* Timer/Counter2 Overflow */
709#define TIMER2_OVF_vect            _VECTOR(9)
710#define TIMER2_OVF_vect_num        9
711
712/* Timer/Counter1 Capture Event */
713#define TIMER1_CAPT_vect            _VECTOR(10)
714#define TIMER1_CAPT_vect_num        10
715
716/* Timer/Counter1 Compare Match A */
717#define TIMER1_COMPA_vect            _VECTOR(11)
718#define TIMER1_COMPA_vect_num        11
719
720/* Timer/Counter1 Compare Match B */
721#define TIMER1_COMPB_vect            _VECTOR(12)
722#define TIMER1_COMPB_vect_num        12
723
724/* Timer/Counter1 Overflow */
725#define TIMER1_OVF_vect            _VECTOR(13)
726#define TIMER1_OVF_vect_num        13
727
728/* TimerCounter0 Compare Match A */
729#define TIMER0_COMPA_vect            _VECTOR(14)
730#define TIMER0_COMPA_vect_num        14
731
732/* TimerCounter0 Compare Match B */
733#define TIMER0_COMPB_vect            _VECTOR(15)
734#define TIMER0_COMPB_vect_num        15
735
736/* Timer/Couner0 Overflow */
737#define TIMER0_OVF_vect            _VECTOR(16)
738#define TIMER0_OVF_vect_num        16
739
740/* SPI Serial Transfer Complete */
741#define SPI_STC_vect            _VECTOR(17)
742#define SPI_STC_vect_num        17
743
744/* USART Rx Complete */
745#define USART_RX_vect            _VECTOR(18)
746#define USART_RX_vect_num        18
747
748/* USART, Data Register Empty */
749#define USART_UDRE_vect            _VECTOR(19)
750#define USART_UDRE_vect_num        19
751
752/* USART Tx Complete */
753#define USART_TX_vect            _VECTOR(20)
754#define USART_TX_vect_num        20
755
756/* ADC Conversion Complete */
757#define ADC_vect            _VECTOR(21)
758#define ADC_vect_num        21
759
760/* EEPROM Ready */
761#define EE_READY_vect            _VECTOR(22)
762#define EE_READY_vect_num        22
763
764/* Analog Comparator */
765#define ANALOG_COMP_vect            _VECTOR(23)
766#define ANALOG_COMP_vect_num        23
767
768/* Two-wire Serial Interface */
769#define TWI_vect            _VECTOR(24)
770#define TWI_vect_num        24
771
772/* Store Program Memory Read */
773#define SPM_Ready_vect            _VECTOR(25)
774#define SPM_Ready_vect_num        25
775
776#define _VECTORS_SIZE 52
777
778
779/* Constants */
780
781#define SPM_PAGESIZE 64
782#define FLASHSTART   0x0000
783#define FLASHEND     0x0FFF
784#define RAMSTART     0x0100
785#define RAMSIZE      512
786#define RAMEND       0x02FF
787#define E2START     0
788#define E2SIZE      256
789#define E2PAGESIZE  4
790#define E2END       0x00FF
791#define XRAMEND      RAMEND
792
793
794/* Fuses */
795
796#define FUSE_MEMORY_SIZE 3
797
798/* Low Fuse Byte */
799#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
800#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
801#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
802#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
803#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
804#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
805#define FUSE_CKOUT       (unsigned char)~_BV(6)
806#define FUSE_CKDIV8      (unsigned char)~_BV(7)
807#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
808
809
810/* High Fuse Byte */
811#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
812#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
813#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
814#define FUSE_EESAVE      (unsigned char)~_BV(3)
815#define FUSE_WDTON       (unsigned char)~_BV(4)
816#define FUSE_SPIEN       (unsigned char)~_BV(5)
817#define FUSE_DWEN        (unsigned char)~_BV(6)
818#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
819#define HFUSE_DEFAULT    (FUSE_SPIEN)
820
821
822/* Extended Fuse Byte */
823#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
824#define EFUSE_DEFAULT    (0xFF)
825
826
827
828/* Lock Bits */
829#define __LOCK_BITS_EXIST
830
831
832/* Signature */
833#define SIGNATURE_0 0x1E
834#define SIGNATURE_1 0x92
835#define SIGNATURE_2 0x0A
836
837
838#endif /* #ifdef _AVR_ATMEGA48PA_H_INCLUDED */
839
Note: See TracBrowser for help on using the repository browser.