source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom48pb.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

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1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATMEGA48PB_H_INCLUDED
36#define _AVR_ATMEGA48PB_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "iom48pb.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINB    _SFR_IO8(0x03)
52#define PINB7   7
53#define PINB6   6
54#define PINB5   5
55#define PINB4   4
56#define PINB3   3
57#define PINB2   2
58#define PINB1   1
59#define PINB0   0
60
61#define DDRB    _SFR_IO8(0x04)
62#define DDRB7   7
63// Inserted "DDB7" from "DDRB7" due to compatibility
64#define DDB7    7
65#define DDRB6   6
66// Inserted "DDB6" from "DDRB6" due to compatibility
67#define DDB6    6
68#define DDRB5   5
69// Inserted "DDB5" from "DDRB5" due to compatibility
70#define DDB5    5
71#define DDRB4   4
72// Inserted "DDB4" from "DDRB4" due to compatibility
73#define DDB4    4
74#define DDRB3   3
75// Inserted "DDB3" from "DDRB3" due to compatibility
76#define DDB3    3
77#define DDRB2   2
78// Inserted "DDB2" from "DDRB2" due to compatibility
79#define DDB2    2
80#define DDRB1   1
81// Inserted "DDB1" from "DDRB1" due to compatibility
82#define DDB1    1
83#define DDRB0   0
84// Inserted "DDB0" from "DDRB0" due to compatibility
85#define DDB0    0
86
87#define PORTB   _SFR_IO8(0x05)
88#define PORTB7  7
89#define PORTB6  6
90#define PORTB5  5
91#define PORTB4  4
92#define PORTB3  3
93#define PORTB2  2
94#define PORTB1  1
95#define PORTB0  0
96
97#define PINC    _SFR_IO8(0x06)
98#define PINC6   6
99#define PINC5   5
100#define PINC4   4
101#define PINC3   3
102#define PINC2   2
103#define PINC1   1
104#define PINC0   0
105
106#define DDRC    _SFR_IO8(0x07)
107#define DDRC6   6
108// Inserted "DDC6" from "DDRC6" due to compatibility
109#define DDC6    6
110#define DDRC5   5
111// Inserted "DDC5" from "DDRC5" due to compatibility
112#define DDC5    5
113#define DDRC4   4
114// Inserted "DDC4" from "DDRC4" due to compatibility
115#define DDC4    4
116#define DDRC3   3
117// Inserted "DDC3" from "DDRC3" due to compatibility
118#define DDC3    3
119#define DDRC2   2
120// Inserted "DDC2" from "DDRC2" due to compatibility
121#define DDC2    2
122#define DDRC1   1
123// Inserted "DDC1" from "DDRC1" due to compatibility
124#define DDC1    1
125#define DDRC0   0
126// Inserted "DDC0" from "DDRC0" due to compatibility
127#define DDC0    0
128
129#define PORTC   _SFR_IO8(0x08)
130#define PORTC6  6
131#define PORTC5  5
132#define PORTC4  4
133#define PORTC3  3
134#define PORTC2  2
135#define PORTC1  1
136#define PORTC0  0
137
138#define PIND    _SFR_IO8(0x09)
139#define PIND7   7
140#define PIND6   6
141#define PIND5   5
142#define PIND4   4
143#define PIND3   3
144#define PIND2   2
145#define PIND1   1
146#define PIND0   0
147
148#define DDRD    _SFR_IO8(0x0A)
149#define DDRD7   7
150// Inserted "DDD7" from "DDRD7" due to compatibility
151#define DDD7    7
152#define DDRD6   6
153// Inserted "DDD6" from "DDRD6" due to compatibility
154#define DDD6    6
155#define DDRD5   5
156// Inserted "DDD5" from "DDRD5" due to compatibility
157#define DDD5    5
158#define DDRD4   4
159// Inserted "DDD4" from "DDRD4" due to compatibility
160#define DDD4    4
161#define DDRD3   3
162// Inserted "DDD3" from "DDRD3" due to compatibility
163#define DDD3    3
164#define DDRD2   2
165// Inserted "DDD2" from "DDRD2" due to compatibility
166#define DDD2    2
167#define DDRD1   1
168// Inserted "DDD1" from "DDRD1" due to compatibility
169#define DDD1    1
170#define DDRD0   0
171// Inserted "DDD0" from "DDRD0" due to compatibility
172#define DDD0    0
173
174#define PORTD   _SFR_IO8(0x0B)
175#define PORTD7  7
176#define PORTD6  6
177#define PORTD5  5
178#define PORTD4  4
179#define PORTD3  3
180#define PORTD2  2
181#define PORTD1  1
182#define PORTD0  0
183
184#define PINE    _SFR_IO8(0x0C)
185#define PINE3   3
186#define PINE2   2
187#define PINE1   1
188#define PINE0   0
189
190#define DDRE    _SFR_IO8(0x0D)
191#define DDRE3   3
192// Inserted "DDE3" from "DDRE3" due to compatibility
193#define DDE3    3
194#define DDRE2   2
195// Inserted "DDE2" from "DDRE2" due to compatibility
196#define DDE2    2
197#define DDRE1   1
198// Inserted "DDE1" from "DDRE1" due to compatibility
199#define DDE1    1
200#define DDRE0   0
201// Inserted "DDE0" from "DDRE0" due to compatibility
202#define DDE0    0
203
204#define PORTE   _SFR_IO8(0x0E)
205#define PORTE3  3
206#define PORTE2  2
207#define PORTE1  1
208#define PORTE0  0
209
210#define ACSRB   _SFR_IO8(0x0F)
211#define ACOE    0
212
213/* Reserved [0x10..0x14] */
214
215#define TIFR0   _SFR_IO8(0x15)
216#define TOV0    0
217#define OCF0A   1
218#define OCF0B   2
219
220#define TIFR1   _SFR_IO8(0x16)
221#define TOV1    0
222#define OCF1A   1
223#define OCF1B   2
224#define ICF1    5
225
226#define TIFR2   _SFR_IO8(0x17)
227#define TOV2    0
228#define OCF2A   1
229#define OCF2B   2
230
231/* Reserved [0x18..0x1A] */
232
233#define PCIFR   _SFR_IO8(0x1B)
234#define PCIF0   0
235#define PCIF1   1
236#define PCIF2   2
237
238#define EIFR    _SFR_IO8(0x1C)
239#define INTF0   0
240#define INTF1   1
241
242#define EIMSK   _SFR_IO8(0x1D)
243#define INT0    0
244#define INT1    1
245
246#define GPIOR0  _SFR_IO8(0x1E)
247
248#define EECR    _SFR_IO8(0x1F)
249#define EERE    0
250#define EEPE    1
251#define EEMPE   2
252#define EERIE   3
253#define EEPM0   4
254#define EEPM1   5
255
256#define EEDR    _SFR_IO8(0x20)
257
258#define EEARL   _SFR_IO8(0x21)
259
260/* Reserved [0x22] */
261
262#define GTCCR   _SFR_IO8(0x23)
263#define PSRSYNC 0
264#define TSM     7
265#define PSRASY  1
266
267#define TCCR0A  _SFR_IO8(0x24)
268#define WGM00   0
269#define WGM01   1
270#define COM0B0  4
271#define COM0B1  5
272#define COM0A0  6
273#define COM0A1  7
274
275#define TCCR0B  _SFR_IO8(0x25)
276#define CS00    0
277#define CS01    1
278#define CS02    2
279#define WGM02   3
280#define FOC0B   6
281#define FOC0A   7
282
283#define TCNT0   _SFR_IO8(0x26)
284
285#define OCR0A   _SFR_IO8(0x27)
286
287#define OCR0B   _SFR_IO8(0x28)
288
289/* Reserved [0x29] */
290
291#define GPIOR1  _SFR_IO8(0x2A)
292
293#define GPIOR2  _SFR_IO8(0x2B)
294
295#define SPCR    _SFR_IO8(0x2C)
296#define SPR0    0
297#define SPR1    1
298#define CPHA    2
299#define CPOL    3
300#define MSTR    4
301#define DORD    5
302#define SPE     6
303#define SPIE    7
304
305#define SPSR    _SFR_IO8(0x2D)
306#define SPI2X   0
307#define WCOL    6
308#define SPIF    7
309
310#define SPDR    _SFR_IO8(0x2E)
311
312/* Reserved [0x2F] */
313
314#define ACSR    _SFR_IO8(0x30)
315#define ACIS0   0
316#define ACIS1   1
317#define ACIC    2
318#define ACIE    3
319#define ACI     4
320#define ACO     5
321#define ACBG    6
322#define ACD     7
323
324/* Reserved [0x31..0x32] */
325
326#define SMCR    _SFR_IO8(0x33)
327#define SE      0
328#define SM0     1
329#define SM1     2
330#define SM2     3
331
332#define MCUSR   _SFR_IO8(0x34)
333#define PORF    0
334#define EXTRF   1
335#define BORF    2
336#define WDRF    3
337
338#define MCUCR   _SFR_IO8(0x35)
339#define PUD     4
340#define BODSE   5
341#define BODS    6
342
343/* Reserved [0x36] */
344
345#define SPMCSR  _SFR_IO8(0x37)
346#define SELFPRGEN 0
347#define PGERS   1
348#define PGWRT   2
349#define BLBSET  3
350#define RWWSRE  4
351#define RWWSB   6
352#define SPMIE   7
353
354/* Reserved [0x38..0x3C] */
355
356/* SP [0x3D..0x3E] */
357
358/* SREG [0x3F] */
359
360#define WDTCSR  _SFR_MEM8(0x60)
361#define WDE     3
362#define WDCE    4
363#define WDP0    0
364#define WDP1    1
365#define WDP2    2
366#define WDP3    5
367#define WDIE    6
368#define WDIF    7
369
370#define CLKPR   _SFR_MEM8(0x61)
371#define CLKPS0  0
372#define CLKPS1  1
373#define CLKPS2  2
374#define CLKPS3  3
375#define CLKPCE  7
376
377/* Reserved [0x62..0x63] */
378
379#define PRR     _SFR_MEM8(0x64)
380#define PRADC   0
381#define PRUSART0 1
382#define PRSPI   2
383#define PRTIM1  3
384#define PRTIM0  5
385#define PRTIM2  6
386#define PRTWI   7
387
388#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
389#define __AVR_HAVE_PRR_PRADC
390#define __AVR_HAVE_PRR_PRUSART0
391#define __AVR_HAVE_PRR_PRSPI
392#define __AVR_HAVE_PRR_PRTIM1
393#define __AVR_HAVE_PRR_PRTIM0
394#define __AVR_HAVE_PRR_PRTIM2
395#define __AVR_HAVE_PRR_PRTWI
396
397/* Reserved [0x65] */
398
399#define OSCCAL  _SFR_MEM8(0x66)
400#define OSCCAL0 0
401#define OSCCAL1 1
402#define OSCCAL2 2
403#define OSCCAL3 3
404#define OSCCAL4 4
405#define OSCCAL5 5
406#define OSCCAL6 6
407#define OSCCAL7 7
408
409/* Reserved [0x67] */
410
411#define PCICR   _SFR_MEM8(0x68)
412#define PCIE0   0
413#define PCIE1   1
414#define PCIE2   2
415
416#define EICRA   _SFR_MEM8(0x69)
417#define ISC00   0
418#define ISC01   1
419#define ISC10   2
420#define ISC11   3
421
422/* Reserved [0x6A] */
423
424#define PCMSK0  _SFR_MEM8(0x6B)
425#define PCINT0  0
426#define PCINT1  1
427#define PCINT2  2
428#define PCINT3  3
429#define PCINT4  4
430#define PCINT5  5
431#define PCINT6  6
432#define PCINT7  7
433
434#define PCMSK1  _SFR_MEM8(0x6C)
435#define PCINT8  0
436#define PCINT9  1
437#define PCINT10 2
438#define PCINT11 3
439#define PCINT12 4
440#define PCINT13 5
441#define PCINT14 6
442
443#define PCMSK2  _SFR_MEM8(0x6D)
444#define PCINT16 0
445#define PCINT17 1
446#define PCINT18 2
447#define PCINT19 3
448#define PCINT20 4
449#define PCINT21 5
450#define PCINT22 6
451#define PCINT23 7
452
453#define TIMSK0  _SFR_MEM8(0x6E)
454#define TOIE0   0
455#define OCIE0A  1
456#define OCIE0B  2
457
458#define TIMSK1  _SFR_MEM8(0x6F)
459#define TOIE1   0
460#define OCIE1A  1
461#define OCIE1B  2
462#define ICIE1   5
463
464#define TIMSK2  _SFR_MEM8(0x70)
465#define TOIE2   0
466#define OCIE2A  1
467#define OCIE2B  2
468
469/* Reserved [0x71..0x77] */
470
471/* Combine ADCL and ADCH */
472#ifndef __ASSEMBLER__
473#define ADC     _SFR_MEM16(0x78)
474#endif
475#define ADCW    _SFR_MEM16(0x78)
476
477#define ADCL    _SFR_MEM8(0x78)
478#define ADCH    _SFR_MEM8(0x79)
479
480#define ADCSRA  _SFR_MEM8(0x7A)
481#define ADPS0   0
482#define ADPS1   1
483#define ADPS2   2
484#define ADIE    3
485#define ADIF    4
486#define ADATE   5
487#define ADSC    6
488#define ADEN    7
489
490#define ADCSRB  _SFR_MEM8(0x7B)
491#define ADTS0   0
492#define ADTS1   1
493#define ADTS2   2
494#define ACME    6
495
496#define ADMUX   _SFR_MEM8(0x7C)
497#define MUX0    0
498#define MUX1    1
499#define MUX2    2
500#define MUX3    3
501#define ADLAR   5
502#define REFS0   6
503#define REFS1   7
504
505/* Reserved [0x7D] */
506
507#define DIDR0   _SFR_MEM8(0x7E)
508#define ADC0D   0
509#define ADC1D   1
510#define ADC2D   2
511#define ADC3D   3
512#define ADC4D   4
513#define ADC5D   5
514
515#define DIDR1   _SFR_MEM8(0x7F)
516#define AIN0D   0
517#define AIN1D   1
518
519#define TCCR1A  _SFR_MEM8(0x80)
520#define WGM10   0
521#define WGM11   1
522#define COM1B0  4
523#define COM1B1  5
524#define COM1A0  6
525#define COM1A1  7
526
527#define TCCR1B  _SFR_MEM8(0x81)
528#define CS10    0
529#define CS11    1
530#define CS12    2
531#define WGM12   3
532#define WGM13   4
533#define ICES1   6
534#define ICNC1   7
535
536#define TCCR1C  _SFR_MEM8(0x82)
537#define FOC1B   6
538#define FOC1A   7
539
540/* Reserved [0x83] */
541
542/* Combine TCNT1L and TCNT1H */
543#define TCNT1   _SFR_MEM16(0x84)
544
545#define TCNT1L  _SFR_MEM8(0x84)
546#define TCNT1H  _SFR_MEM8(0x85)
547
548/* Combine ICR1L and ICR1H */
549#define ICR1    _SFR_MEM16(0x86)
550
551#define ICR1L   _SFR_MEM8(0x86)
552#define ICR1H   _SFR_MEM8(0x87)
553
554/* Combine OCR1AL and OCR1AH */
555#define OCR1A   _SFR_MEM16(0x88)
556
557#define OCR1AL  _SFR_MEM8(0x88)
558#define OCR1AH  _SFR_MEM8(0x89)
559
560/* Combine OCR1BL and OCR1BH */
561#define OCR1B   _SFR_MEM16(0x8A)
562
563#define OCR1BL  _SFR_MEM8(0x8A)
564#define OCR1BH  _SFR_MEM8(0x8B)
565
566/* Reserved [0x8C..0xAF] */
567
568#define TCCR2A  _SFR_MEM8(0xB0)
569#define WGM20   0
570#define WGM21   1
571#define COM2B0  4
572#define COM2B1  5
573#define COM2A0  6
574#define COM2A1  7
575
576#define TCCR2B  _SFR_MEM8(0xB1)
577#define CS20    0
578#define CS21    1
579#define CS22    2
580#define WGM22   3
581#define FOC2B   6
582#define FOC2A   7
583
584#define TCNT2   _SFR_MEM8(0xB2)
585
586#define OCR2A   _SFR_MEM8(0xB3)
587
588#define OCR2B   _SFR_MEM8(0xB4)
589
590/* Reserved [0xB5] */
591
592#define ASSR    _SFR_MEM8(0xB6)
593#define TCR2BUB 0
594#define TCR2AUB 1
595#define OCR2BUB 2
596#define OCR2AUB 3
597#define TCN2UB  4
598#define AS2     5
599#define EXCLK   6
600
601/* Reserved [0xB7] */
602
603#define TWBR    _SFR_MEM8(0xB8)
604
605#define TWSR    _SFR_MEM8(0xB9)
606#define TWPS0   0
607#define TWPS1   1
608#define TWS3    3
609#define TWS4    4
610#define TWS5    5
611#define TWS6    6
612#define TWS7    7
613
614#define TWAR    _SFR_MEM8(0xBA)
615#define TWGCE   0
616#define TWA0    1
617#define TWA1    2
618#define TWA2    3
619#define TWA3    4
620#define TWA4    5
621#define TWA5    6
622#define TWA6    7
623
624#define TWDR    _SFR_MEM8(0xBB)
625
626#define TWCR    _SFR_MEM8(0xBC)
627#define TWIE    0
628#define TWEN    2
629#define TWWC    3
630#define TWSTO   4
631#define TWSTA   5
632#define TWEA    6
633#define TWINT   7
634
635#define TWAMR   _SFR_MEM8(0xBD)
636#define TWAM0   1
637#define TWAM1   2
638#define TWAM2   3
639#define TWAM3   4
640#define TWAM4   5
641#define TWAM5   6
642#define TWAM6   7
643
644/* Reserved [0xBE..0xBF] */
645
646#define UCSR0A  _SFR_MEM8(0xC0)
647#define MPCM0   0
648#define U2X0    1
649#define UPE0    2
650#define DOR0    3
651#define FE0     4
652#define UDRE0   5
653#define TXC0    6
654#define RXC0    7
655
656#define UCSR0B  _SFR_MEM8(0xC1)
657#define TXB80   0
658#define RXB80   1
659#define UCSZ02  2
660#define TXEN0   3
661#define RXEN0   4
662#define UDRIE0  5
663#define TXCIE0  6
664#define RXCIE0  7
665
666#define UCSR0C  _SFR_MEM8(0xC2)
667#define UCPOL0  0
668#define UCSZ00  1
669#define UCSZ01  2
670#define USBS0   3
671#define UPM00   4
672#define UPM01   5
673#define UMSEL00 6
674#define UMSEL01 7
675
676#define UCSR0D  _SFR_MEM8(0xC3)
677#define SFDE    5
678#define RXS     6
679#define RXSIE   7
680
681/* Combine UBRR0L and UBRR0H */
682#define UBRR0   _SFR_MEM16(0xC4)
683
684#define UBRR0L  _SFR_MEM8(0xC4)
685#define UBRR0H  _SFR_MEM8(0xC5)
686
687#define UDR0    _SFR_MEM8(0xC6)
688
689/* Reserved [0xC7..0xEF] */
690
691#define DEVID0  _SFR_MEM8(0xF0)
692
693#define DEVID1  _SFR_MEM8(0xF1)
694
695#define DEVID2  _SFR_MEM8(0xF2)
696
697#define DEVID3  _SFR_MEM8(0xF3)
698
699#define DEVID4  _SFR_MEM8(0xF4)
700
701#define DEVID5  _SFR_MEM8(0xF5)
702
703#define DEVID6  _SFR_MEM8(0xF6)
704
705#define DEVID7  _SFR_MEM8(0xF7)
706
707#define DEVID8  _SFR_MEM8(0xF8)
708
709
710
711/* Values and associated defines */
712
713
714#define SLEEP_MODE_IDLE (0x00<<1)
715#define SLEEP_MODE_ADC (0x01<<1)
716#define SLEEP_MODE_PWR_DOWN (0x02<<1)
717#define SLEEP_MODE_PWR_SAVE (0x03<<1)
718#define SLEEP_MODE_STANDBY (0x06<<1)
719#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
720
721/* Interrupt vectors */
722/* Vector 0 is the reset vector */
723/* External Interrupt Request 0 */
724#define INT0_vect            _VECTOR(1)
725#define INT0_vect_num        1
726
727/* External Interrupt Request 1 */
728#define INT1_vect            _VECTOR(2)
729#define INT1_vect_num        2
730
731/* Pin Change Interrupt Request 0 */
732#define PCINT0_vect            _VECTOR(3)
733#define PCINT0_vect_num        3
734
735/* Pin Change Interrupt Request 0 */
736#define PCINT1_vect            _VECTOR(4)
737#define PCINT1_vect_num        4
738
739/* Pin Change Interrupt Request 1 */
740#define PCINT2_vect            _VECTOR(5)
741#define PCINT2_vect_num        5
742
743/* Watchdog Time-out Interrupt */
744#define WDT_vect            _VECTOR(6)
745#define WDT_vect_num        6
746
747/* Timer/Counter2 Compare Match A */
748#define TIMER2_COMPA_vect            _VECTOR(7)
749#define TIMER2_COMPA_vect_num        7
750
751/* Timer/Counter2 Compare Match A */
752#define TIMER2_COMPB_vect            _VECTOR(8)
753#define TIMER2_COMPB_vect_num        8
754
755/* Timer/Counter2 Overflow */
756#define TIMER2_OVF_vect            _VECTOR(9)
757#define TIMER2_OVF_vect_num        9
758
759/* Timer/Counter1 Capture Event */
760#define TIMER1_CAPT_vect            _VECTOR(10)
761#define TIMER1_CAPT_vect_num        10
762
763/* Timer/Counter1 Compare Match A */
764#define TIMER1_COMPA_vect            _VECTOR(11)
765#define TIMER1_COMPA_vect_num        11
766
767/* Timer/Counter1 Compare Match B */
768#define TIMER1_COMPB_vect            _VECTOR(12)
769#define TIMER1_COMPB_vect_num        12
770
771/* Timer/Counter1 Overflow */
772#define TIMER1_OVF_vect            _VECTOR(13)
773#define TIMER1_OVF_vect_num        13
774
775/* TimerCounter0 Compare Match A */
776#define TIMER0_COMPA_vect            _VECTOR(14)
777#define TIMER0_COMPA_vect_num        14
778
779/* TimerCounter0 Compare Match B */
780#define TIMER0_COMPB_vect            _VECTOR(15)
781#define TIMER0_COMPB_vect_num        15
782
783/* Timer/Couner0 Overflow */
784#define TIMER0_OVF_vect            _VECTOR(16)
785#define TIMER0_OVF_vect_num        16
786
787/* SPI Serial Transfer Complete */
788#define SPI_STC_vect            _VECTOR(17)
789#define SPI_STC_vect_num        17
790
791/* USART Rx Complete */
792#define USART_RX_vect            _VECTOR(18)
793#define USART_RX_vect_num        18
794
795/* USART, Data Register Empty */
796#define USART_UDRE_vect            _VECTOR(19)
797#define USART_UDRE_vect_num        19
798
799/* USART Tx Complete */
800#define USART_TX_vect            _VECTOR(20)
801#define USART_TX_vect_num        20
802
803/* ADC Conversion Complete */
804#define ADC_vect            _VECTOR(21)
805#define ADC_vect_num        21
806
807/* EEPROM Ready */
808#define EE_READY_vect            _VECTOR(22)
809#define EE_READY_vect_num        22
810
811/* Analog Comparator */
812#define ANALOG_COMP_vect            _VECTOR(23)
813#define ANALOG_COMP_vect_num        23
814
815/* Two-wire Serial Interface */
816#define TWI_vect            _VECTOR(24)
817#define TWI_vect_num        24
818
819/* Store Program Memory Read */
820#define SPM_Ready_vect            _VECTOR(25)
821#define SPM_Ready_vect_num        25
822
823/* USART Start Edge Interrupt */
824#define USART_START_vect            _VECTOR(26)
825#define USART_START_vect_num        26
826
827#define _VECTORS_SIZE 54
828
829
830/* Constants */
831
832#define SPM_PAGESIZE 64
833#define FLASHSTART   0x0000
834#define FLASHEND     0x0FFF
835#define RAMSTART     0x0100
836#define RAMSIZE      512
837#define RAMEND       0x02FF
838#define E2START     0
839#define E2SIZE      256
840#define E2PAGESIZE  4
841#define E2END       0x00FF
842#define XRAMEND      RAMEND
843
844
845/* Fuses */
846
847#define FUSE_MEMORY_SIZE 3
848
849/* Low Fuse Byte */
850#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
851#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
852#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
853#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
854#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
855#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
856#define FUSE_CKOUT       (unsigned char)~_BV(6)
857#define FUSE_CKDIV8      (unsigned char)~_BV(7)
858#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
859
860
861/* High Fuse Byte */
862#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
863#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
864#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
865#define FUSE_EESAVE      (unsigned char)~_BV(3)
866#define FUSE_WDTON       (unsigned char)~_BV(4)
867#define FUSE_SPIEN       (unsigned char)~_BV(5)
868#define FUSE_DWEN        (unsigned char)~_BV(6)
869#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
870#define HFUSE_DEFAULT    (FUSE_SPIEN)
871
872
873/* Extended Fuse Byte */
874#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
875#define EFUSE_DEFAULT    (0xFF)
876
877
878
879/* Lock Bits */
880#define __LOCK_BITS_EXIST
881
882
883/* Signature */
884#define SIGNATURE_0 0x1E
885#define SIGNATURE_1 0x92
886#define SIGNATURE_2 0x10
887
888
889#endif /* #ifdef _AVR_ATMEGA48PB_H_INCLUDED */
890
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