source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom644rfr2.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

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1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATMEGA644RFR2_H_INCLUDED
36#define _AVR_ATMEGA644RFR2_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "iom644rfr2.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINA    _SFR_IO8(0x00)
52#define PINA7   7
53#define PINA6   6
54#define PINA5   5
55#define PINA4   4
56#define PINA3   3
57#define PINA2   2
58#define PINA1   1
59#define PINA0   0
60
61#define DDRA    _SFR_IO8(0x01)
62#define DDRA7   7
63// Inserted "DDA7" from "DDRA7" due to compatibility
64#define DDA7    7
65#define DDRA6   6
66// Inserted "DDA6" from "DDRA6" due to compatibility
67#define DDA6    6
68#define DDRA5   5
69// Inserted "DDA5" from "DDRA5" due to compatibility
70#define DDA5    5
71#define DDRA4   4
72// Inserted "DDA4" from "DDRA4" due to compatibility
73#define DDA4    4
74#define DDRA3   3
75// Inserted "DDA3" from "DDRA3" due to compatibility
76#define DDA3    3
77#define DDRA2   2
78// Inserted "DDA2" from "DDRA2" due to compatibility
79#define DDA2    2
80#define DDRA1   1
81// Inserted "DDA1" from "DDRA1" due to compatibility
82#define DDA1    1
83#define DDRA0   0
84// Inserted "DDA0" from "DDRA0" due to compatibility
85#define DDA0    0
86
87#define PORTA   _SFR_IO8(0x02)
88#define PORTA7  7
89#define PORTA6  6
90#define PORTA5  5
91#define PORTA4  4
92#define PORTA3  3
93#define PORTA2  2
94#define PORTA1  1
95#define PORTA0  0
96
97#define PINB    _SFR_IO8(0x03)
98#define PINB7   7
99#define PINB6   6
100#define PINB5   5
101#define PINB4   4
102#define PINB3   3
103#define PINB2   2
104#define PINB1   1
105#define PINB0   0
106
107#define DDRB    _SFR_IO8(0x04)
108#define DDRB7   7
109// Inserted "DDB7" from "DDRB7" due to compatibility
110#define DDB7    7
111#define DDRB6   6
112// Inserted "DDB6" from "DDRB6" due to compatibility
113#define DDB6    6
114#define DDRB5   5
115// Inserted "DDB5" from "DDRB5" due to compatibility
116#define DDB5    5
117#define DDRB4   4
118// Inserted "DDB4" from "DDRB4" due to compatibility
119#define DDB4    4
120#define DDRB3   3
121// Inserted "DDB3" from "DDRB3" due to compatibility
122#define DDB3    3
123#define DDRB2   2
124// Inserted "DDB2" from "DDRB2" due to compatibility
125#define DDB2    2
126#define DDRB1   1
127// Inserted "DDB1" from "DDRB1" due to compatibility
128#define DDB1    1
129#define DDRB0   0
130// Inserted "DDB0" from "DDRB0" due to compatibility
131#define DDB0    0
132
133#define PORTB   _SFR_IO8(0x05)
134#define PORTB7  7
135#define PORTB6  6
136#define PORTB5  5
137#define PORTB4  4
138#define PORTB3  3
139#define PORTB2  2
140#define PORTB1  1
141#define PORTB0  0
142
143#define PINC    _SFR_IO8(0x06)
144#define PINC7   7
145#define PINC6   6
146#define PINC5   5
147#define PINC4   4
148#define PINC3   3
149#define PINC2   2
150#define PINC1   1
151#define PINC0   0
152
153#define DDRC    _SFR_IO8(0x07)
154#define DDRC7   7
155// Inserted "DDC7" from "DDRC7" due to compatibility
156#define DDC7    7
157#define DDRC6   6
158// Inserted "DDC6" from "DDRC6" due to compatibility
159#define DDC6    6
160#define DDRC5   5
161// Inserted "DDC5" from "DDRC5" due to compatibility
162#define DDC5    5
163#define DDRC4   4
164// Inserted "DDC4" from "DDRC4" due to compatibility
165#define DDC4    4
166#define DDRC3   3
167// Inserted "DDC3" from "DDRC3" due to compatibility
168#define DDC3    3
169#define DDRC2   2
170// Inserted "DDC2" from "DDRC2" due to compatibility
171#define DDC2    2
172#define DDRC1   1
173// Inserted "DDC1" from "DDRC1" due to compatibility
174#define DDC1    1
175#define DDRC0   0
176// Inserted "DDC0" from "DDRC0" due to compatibility
177#define DDC0    0
178
179#define PORTC   _SFR_IO8(0x08)
180#define PORTC7  7
181#define PORTC6  6
182#define PORTC5  5
183#define PORTC4  4
184#define PORTC3  3
185#define PORTC2  2
186#define PORTC1  1
187#define PORTC0  0
188
189#define PIND    _SFR_IO8(0x09)
190#define PIND7   7
191#define PIND6   6
192#define PIND5   5
193#define PIND4   4
194#define PIND3   3
195#define PIND2   2
196#define PIND1   1
197#define PIND0   0
198
199#define DDRD    _SFR_IO8(0x0A)
200#define DDRD7   7
201// Inserted "DDD7" from "DDRD7" due to compatibility
202#define DDD7    7
203#define DDRD6   6
204// Inserted "DDD6" from "DDRD6" due to compatibility
205#define DDD6    6
206#define DDRD5   5
207// Inserted "DDD5" from "DDRD5" due to compatibility
208#define DDD5    5
209#define DDRD4   4
210// Inserted "DDD4" from "DDRD4" due to compatibility
211#define DDD4    4
212#define DDRD3   3
213// Inserted "DDD3" from "DDRD3" due to compatibility
214#define DDD3    3
215#define DDRD2   2
216// Inserted "DDD2" from "DDRD2" due to compatibility
217#define DDD2    2
218#define DDRD1   1
219// Inserted "DDD1" from "DDRD1" due to compatibility
220#define DDD1    1
221#define DDRD0   0
222// Inserted "DDD0" from "DDRD0" due to compatibility
223#define DDD0    0
224
225#define PORTD   _SFR_IO8(0x0B)
226#define PORTD7  7
227#define PORTD6  6
228#define PORTD5  5
229#define PORTD4  4
230#define PORTD3  3
231#define PORTD2  2
232#define PORTD1  1
233#define PORTD0  0
234
235#define PINE    _SFR_IO8(0x0C)
236#define PINE7   7
237#define PINE6   6
238#define PINE5   5
239#define PINE4   4
240#define PINE3   3
241#define PINE2   2
242#define PINE1   1
243#define PINE0   0
244
245#define DDRE    _SFR_IO8(0x0D)
246#define DDRE7   7
247// Inserted "DDE7" from "DDRE7" due to compatibility
248#define DDE7    7
249#define DDRE6   6
250// Inserted "DDE6" from "DDRE6" due to compatibility
251#define DDE6    6
252#define DDRE5   5
253// Inserted "DDE5" from "DDRE5" due to compatibility
254#define DDE5    5
255#define DDRE4   4
256// Inserted "DDE4" from "DDRE4" due to compatibility
257#define DDE4    4
258#define DDRE3   3
259// Inserted "DDE3" from "DDRE3" due to compatibility
260#define DDE3    3
261#define DDRE2   2
262// Inserted "DDE2" from "DDRE2" due to compatibility
263#define DDE2    2
264#define DDRE1   1
265// Inserted "DDE1" from "DDRE1" due to compatibility
266#define DDE1    1
267#define DDRE0   0
268// Inserted "DDE0" from "DDRE0" due to compatibility
269#define DDE0    0
270
271#define PORTE   _SFR_IO8(0x0E)
272#define PORTE7  7
273#define PORTE6  6
274#define PORTE5  5
275#define PORTE4  4
276#define PORTE3  3
277#define PORTE2  2
278#define PORTE1  1
279#define PORTE0  0
280
281#define PINF    _SFR_IO8(0x0F)
282#define PINF7   7
283#define PINF6   6
284#define PINF5   5
285#define PINF4   4
286#define PINF3   3
287#define PINF2   2
288#define PINF1   1
289#define PINF0   0
290
291#define DDRF    _SFR_IO8(0x10)
292#define DDRF7   7
293// Inserted "DDF7" from "DDRF7" due to compatibility
294#define DDF7    7
295#define DDRF6   6
296// Inserted "DDF6" from "DDRF6" due to compatibility
297#define DDF6    6
298#define DDRF5   5
299// Inserted "DDF5" from "DDRF5" due to compatibility
300#define DDF5    5
301#define DDRF4   4
302// Inserted "DDF4" from "DDRF4" due to compatibility
303#define DDF4    4
304#define DDRF3   3
305// Inserted "DDF3" from "DDRF3" due to compatibility
306#define DDF3    3
307#define DDRF2   2
308// Inserted "DDF2" from "DDRF2" due to compatibility
309#define DDF2    2
310#define DDRF1   1
311// Inserted "DDF1" from "DDRF1" due to compatibility
312#define DDF1    1
313#define DDRF0   0
314// Inserted "DDF0" from "DDRF0" due to compatibility
315#define DDF0    0
316
317#define PORTF   _SFR_IO8(0x11)
318#define PORTF7  7
319#define PORTF6  6
320#define PORTF5  5
321#define PORTF4  4
322#define PORTF3  3
323#define PORTF2  2
324#define PORTF1  1
325#define PORTF0  0
326
327#define PING    _SFR_IO8(0x12)
328#define PING7   7
329#define PING6   6
330#define PING5   5
331#define PING4   4
332#define PING3   3
333#define PING2   2
334#define PING1   1
335#define PING0   0
336
337#define DDRG    _SFR_IO8(0x13)
338#define DDRG7   7
339// Inserted "DDG7" from "DDRG7" due to compatibility
340#define DDG7    7
341#define DDRG6   6
342// Inserted "DDG6" from "DDRG6" due to compatibility
343#define DDG6    6
344#define DDRG5   5
345// Inserted "DDG5" from "DDRG5" due to compatibility
346#define DDG5    5
347#define DDRG4   4
348// Inserted "DDG4" from "DDRG4" due to compatibility
349#define DDG4    4
350#define DDRG3   3
351// Inserted "DDG3" from "DDRG3" due to compatibility
352#define DDG3    3
353#define DDRG2   2
354// Inserted "DDG2" from "DDRG2" due to compatibility
355#define DDG2    2
356#define DDRG1   1
357// Inserted "DDG1" from "DDRG1" due to compatibility
358#define DDG1    1
359#define DDRG0   0
360// Inserted "DDG0" from "DDRG0" due to compatibility
361#define DDG0    0
362
363#define PORTG   _SFR_IO8(0x14)
364#define PORTG7  7
365#define PORTG6  6
366#define PORTG5  5
367#define PORTG4  4
368#define PORTG3  3
369#define PORTG2  2
370#define PORTG1  1
371#define PORTG0  0
372
373#define TIFR0   _SFR_IO8(0x15)
374#define TOV0    0
375#define OCF0A   1
376#define OCF0B   2
377#define Res0    3
378#define Res1    4
379#define Res2    5
380#define Res3    6
381#define Res4    7
382
383#define TIFR1   _SFR_IO8(0x16)
384#define TOV1    0
385#define OCF1A   1
386#define OCF1B   2
387#define OCF1C   3
388#define ICF1    5
389
390#define TIFR2   _SFR_IO8(0x17)
391#define TOV2    0
392#define OCF2A   1
393#define OCF2B   2
394
395#define TIFR3   _SFR_IO8(0x18)
396#define TOV3    0
397#define OCF3A   1
398#define OCF3B   2
399#define OCF3C   3
400#define ICF3    5
401
402#define TIFR4   _SFR_IO8(0x19)
403#define TOV4    0
404#define OCF4A   1
405#define OCF4B   2
406#define OCF4C   3
407#define ICF4    5
408
409#define TIFR5   _SFR_IO8(0x1A)
410#define TOV5    0
411#define OCF5A   1
412#define OCF5B   2
413#define OCF5C   3
414#define ICF5    5
415
416#define PCIFR   _SFR_IO8(0x1B)
417#define PCIF0   0
418#define PCIF1   1
419#define PCIF2   2
420
421#define EIFR    _SFR_IO8(0x1C)
422#define INTF0   0
423#define INTF1   1
424#define INTF2   2
425#define INTF3   3
426#define INTF4   4
427#define INTF5   5
428#define INTF6   6
429#define INTF7   7
430
431#define EIMSK   _SFR_IO8(0x1D)
432#define INT0    0
433#define INT1    1
434#define INT2    2
435#define INT3    3
436#define INT4    4
437#define INT5    5
438#define INT6    6
439#define INT7    7
440
441#define GPIOR0  _SFR_IO8(0x1E)
442#define GPIOR00 0
443#define GPIOR01 1
444#define GPIOR02 2
445#define GPIOR03 3
446#define GPIOR04 4
447#define GPIOR05 5
448#define GPIOR06 6
449#define GPIOR07 7
450
451#define EECR    _SFR_IO8(0x1F)
452#define EERE    0
453#define EEPE    1
454#define EEMPE   2
455#define EERIE   3
456#define EEPM0   4
457#define EEPM1   5
458
459#define EEDR    _SFR_IO8(0x20)
460
461/* Combine EEARL and EEARH */
462#define EEAR    _SFR_IO16(0x21)
463
464#define EEARL   _SFR_IO8(0x21)
465#define EEARH   _SFR_IO8(0x22)
466
467#define GTCCR   _SFR_IO8(0x23)
468#define PSRSYNC 0
469#define PSRASY  1
470#define TSM     7
471
472#define TCCR0A  _SFR_IO8(0x24)
473#define WGM00   0
474#define WGM01   1
475#define COM0B0  4
476#define COM0B1  5
477#define COM0A0  6
478#define COM0A1  7
479
480#define TCCR0B  _SFR_IO8(0x25)
481#define CS00    0
482#define CS01    1
483#define CS02    2
484#define WGM02   3
485#define FOC0B   6
486#define FOC0A   7
487
488#define TCNT0   _SFR_IO8(0x26)
489
490#define OCR0A   _SFR_IO8(0x27)
491
492#define OCR0B   _SFR_IO8(0x28)
493
494/* Reserved [0x29] */
495
496#define GPIOR1  _SFR_IO8(0x2A)
497#define GPIOR10 0
498#define GPIOR11 1
499#define GPIOR12 2
500#define GPIOR13 3
501#define GPIOR14 4
502#define GPIOR15 5
503#define GPIOR16 6
504#define GPIOR17 7
505
506#define GPIOR2  _SFR_IO8(0x2B)
507#define GPIOR20 0
508#define GPIOR21 1
509#define GPIOR22 2
510#define GPIOR23 3
511#define GPIOR24 4
512#define GPIOR25 5
513#define GPIOR26 6
514#define GPIOR27 7
515
516#define SPCR    _SFR_IO8(0x2C)
517#define SPR0    0
518#define SPR1    1
519#define CPHA    2
520#define CPOL    3
521#define MSTR    4
522#define DORD    5
523#define SPE     6
524#define SPIE    7
525
526#define SPSR    _SFR_IO8(0x2D)
527#define SPI2X   0
528#define WCOL    6
529#define SPIF    7
530
531#define SPDR    _SFR_IO8(0x2E)
532
533/* Reserved [0x2F] */
534
535#define ACSR    _SFR_IO8(0x30)
536#define ACIS0   0
537#define ACIS1   1
538#define ACIC    2
539#define ACIE    3
540#define ACI     4
541#define ACO     5
542#define ACBG    6
543#define ACD     7
544
545#define OCDR    _SFR_IO8(0x31)
546#define OCDR0   0
547#define OCDR1   1
548#define OCDR2   2
549#define OCDR3   3
550#define OCDR4   4
551#define OCDR5   5
552#define OCDR6   6
553#define OCDR7   7
554
555/* Reserved [0x32] */
556
557#define SMCR    _SFR_IO8(0x33)
558#define SE      0
559#define SM0     1
560#define SM1     2
561#define SM2     3
562
563#define MCUSR   _SFR_IO8(0x34)
564#define JTRF    4
565#define PORF    0
566#define EXTRF   1
567#define BORF    2
568#define WDRF    3
569
570#define MCUCR   _SFR_IO8(0x35)
571#define JTD     7
572#define IVCE    0
573#define IVSEL   1
574#define PUD     4
575
576/* Reserved [0x36] */
577
578#define SPMCSR  _SFR_IO8(0x37)
579#define SPMEN   0
580#define PGERS   1
581#define PGWRT   2
582#define BLBSET  3
583#define RWWSRE  4
584#define SIGRD   5
585#define RWWSB   6
586#define SPMIE   7
587
588/* Reserved [0x38..0x3C] */
589
590/* SP [0x3D..0x3E] */
591
592/* SREG [0x3F] */
593
594#define WDTCSR  _SFR_MEM8(0x60)
595#define WDE     3
596#define WDCE    4
597#define WDP0    0
598#define WDP1    1
599#define WDP2    2
600#define WDP3    5
601#define WDIE    6
602#define WDIF    7
603
604#define CLKPR   _SFR_MEM8(0x61)
605#define CLKPS0  0
606#define CLKPS1  1
607#define CLKPS2  2
608#define CLKPS3  3
609#define CLKPCE  7
610
611/* Reserved [0x62] */
612
613#define PRR2    _SFR_MEM8(0x63)
614#define PRRAM0  0
615#define PRRAM1  1
616#define PRRAM2  2
617#define PRRAM3  3
618
619#define __AVR_HAVE_PRR2 ((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3))
620#define __AVR_HAVE_PRR2_PRRAM0
621#define __AVR_HAVE_PRR2_PRRAM1
622#define __AVR_HAVE_PRR2_PRRAM2
623#define __AVR_HAVE_PRR2_PRRAM3
624
625#define PRR0    _SFR_MEM8(0x64)
626#define PRADC   0
627#define PRUSART0 1
628#define PRSPI   2
629#define PRTIM1  3
630#define PRPGA   4
631#define PRTIM0  5
632#define PRTIM2  6
633#define PRTWI   7
634
635#define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPGA)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
636#define __AVR_HAVE_PRR0_PRADC
637#define __AVR_HAVE_PRR0_PRUSART0
638#define __AVR_HAVE_PRR0_PRSPI
639#define __AVR_HAVE_PRR0_PRTIM1
640#define __AVR_HAVE_PRR0_PRPGA
641#define __AVR_HAVE_PRR0_PRTIM0
642#define __AVR_HAVE_PRR0_PRTIM2
643#define __AVR_HAVE_PRR0_PRTWI
644
645#define PRR1    _SFR_MEM8(0x65)
646#define PRUSART1 0
647#define PRTIM3  3
648#define PRTIM4  4
649#define PRTIM5  5
650#define PRTRX24 6
651#define Res     7
652
653#define __AVR_HAVE_PRR1 ((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24))
654#define __AVR_HAVE_PRR1_PRUSART1
655#define __AVR_HAVE_PRR1_PRTIM3
656#define __AVR_HAVE_PRR1_PRTIM4
657#define __AVR_HAVE_PRR1_PRTIM5
658#define __AVR_HAVE_PRR1_PRTRX24
659
660#define OSCCAL  _SFR_MEM8(0x66)
661#define CAL0    0
662#define CAL1    1
663#define CAL2    2
664#define CAL3    3
665#define CAL4    4
666#define CAL5    5
667#define CAL6    6
668#define CAL7    7
669
670#define BGCR    _SFR_MEM8(0x67)
671#define BGCAL0  0
672#define BGCAL1  1
673#define BGCAL2  2
674#define BGCAL_FINE0 3
675#define BGCAL_FINE1 4
676#define BGCAL_FINE2 5
677#define BGCAL_FINE3 6
678
679#define PCICR   _SFR_MEM8(0x68)
680#define PCIE0   0
681#define PCIE1   1
682#define PCIE2   2
683
684#define EICRA   _SFR_MEM8(0x69)
685#define ISC00   0
686#define ISC01   1
687#define ISC10   2
688#define ISC11   3
689#define ISC20   4
690#define ISC21   5
691#define ISC30   6
692#define ISC31   7
693
694#define EICRB   _SFR_MEM8(0x6A)
695#define ISC40   0
696#define ISC41   1
697#define ISC50   2
698#define ISC51   3
699#define ISC60   4
700#define ISC61   5
701#define ISC70   6
702#define ISC71   7
703
704#define PCMSK0  _SFR_MEM8(0x6B)
705
706#define PCMSK1  _SFR_MEM8(0x6C)
707#define PCINT8  0
708#define PCINT9  1
709#define PCINT10 2
710#define PCINT11 3
711#define PCINT12 4
712#define PCINT13 5
713#define PCINT14 6
714#define PCINT15 7
715
716#define PCMSK2  _SFR_MEM8(0x6D)
717#define PCINT16 0
718#define PCINT17 1
719#define PCINT18 2
720#define PCINT19 3
721#define PCINT20 4
722#define PCINT21 5
723#define PCINT22 6
724#define PCINT23 7
725
726#define TIMSK0  _SFR_MEM8(0x6E)
727#define TOIE0   0
728#define OCIE0A  1
729#define OCIE0B  2
730
731#define TIMSK1  _SFR_MEM8(0x6F)
732#define TOIE1   0
733#define OCIE1A  1
734#define OCIE1B  2
735#define OCIE1C  3
736#define ICIE1   5
737
738#define TIMSK2  _SFR_MEM8(0x70)
739#define TOIE2   0
740#define OCIE2A  1
741#define OCIE2B  2
742
743#define TIMSK3  _SFR_MEM8(0x71)
744#define TOIE3   0
745#define OCIE3A  1
746#define OCIE3B  2
747#define OCIE3C  3
748#define ICIE3   5
749
750#define TIMSK4  _SFR_MEM8(0x72)
751#define TOIE4   0
752#define OCIE4A  1
753#define OCIE4B  2
754#define OCIE4C  3
755#define ICIE4   5
756
757#define TIMSK5  _SFR_MEM8(0x73)
758#define TOIE5   0
759#define OCIE5A  1
760#define OCIE5B  2
761#define OCIE5C  3
762#define ICIE5   5
763
764/* Reserved [0x74] */
765
766#define NEMCR   _SFR_MEM8(0x75)
767#define AEAM0   4
768#define AEAM1   5
769#define ENEAM   6
770
771/* Reserved [0x76] */
772
773#define ADCSRC  _SFR_MEM8(0x77)
774#define ADSUT0  0
775#define ADSUT1  1
776#define ADSUT2  2
777#define ADSUT3  3
778#define ADSUT4  4
779#define ADTHT0  6
780#define ADTHT1  7
781
782/* Combine ADCL and ADCH */
783#ifndef __ASSEMBLER__
784#define ADC     _SFR_MEM16(0x78)
785#endif
786#define ADCW    _SFR_MEM16(0x78)
787
788#define ADCL    _SFR_MEM8(0x78)
789#define ADCH    _SFR_MEM8(0x79)
790
791#define ADCSRA  _SFR_MEM8(0x7A)
792#define ADPS0   0
793#define ADPS1   1
794#define ADPS2   2
795#define ADIE    3
796#define ADIF    4
797#define ADATE   5
798#define ADSC    6
799#define ADEN    7
800
801#define ADCSRB  _SFR_MEM8(0x7B)
802#define ACME    6
803#define ADTS0   0
804#define ADTS1   1
805#define ADTS2   2
806#define MUX5    3
807#define ACCH    4
808#define REFOK   5
809#define AVDDOK  7
810
811#define ADMUX   _SFR_MEM8(0x7C)
812#define MUX0    0
813#define MUX1    1
814#define MUX2    2
815#define MUX3    3
816#define MUX4    4
817#define ADLAR   5
818#define REFS0   6
819#define REFS1   7
820
821#define DIDR2   _SFR_MEM8(0x7D)
822#define ADC8D   0
823#define ADC9D   1
824#define ADC10D  2
825#define ADC11D  3
826#define ADC12D  4
827#define ADC13D  5
828#define ADC14D  6
829#define ADC15D  7
830
831#define DIDR0   _SFR_MEM8(0x7E)
832#define ADC0D   0
833#define ADC1D   1
834#define ADC2D   2
835#define ADC3D   3
836#define ADC4D   4
837#define ADC5D   5
838#define ADC6D   6
839#define ADC7D   7
840
841#define DIDR1   _SFR_MEM8(0x7F)
842#define AIN0D   0
843#define AIN1D   1
844
845#define TCCR1A  _SFR_MEM8(0x80)
846#define WGM10   0
847#define WGM11   1
848#define COM1C0  2
849#define COM1C1  3
850#define COM1B0  4
851#define COM1B1  5
852#define COM1A0  6
853#define COM1A1  7
854
855#define TCCR1B  _SFR_MEM8(0x81)
856#define CS10    0
857#define CS11    1
858#define CS12    2
859#define WGM12   3
860#define WGM13   4
861#define ICES1   6
862#define ICNC1   7
863
864#define TCCR1C  _SFR_MEM8(0x82)
865#define FOC1C   5
866#define FOC1B   6
867#define FOC1A   7
868
869/* Reserved [0x83] */
870
871/* Combine TCNT1L and TCNT1H */
872#define TCNT1   _SFR_MEM16(0x84)
873
874#define TCNT1L  _SFR_MEM8(0x84)
875#define TCNT1H  _SFR_MEM8(0x85)
876
877/* Combine ICR1L and ICR1H */
878#define ICR1    _SFR_MEM16(0x86)
879
880#define ICR1L   _SFR_MEM8(0x86)
881#define ICR1H   _SFR_MEM8(0x87)
882
883/* Combine OCR1AL and OCR1AH */
884#define OCR1A   _SFR_MEM16(0x88)
885
886#define OCR1AL  _SFR_MEM8(0x88)
887#define OCR1AH  _SFR_MEM8(0x89)
888
889/* Combine OCR1BL and OCR1BH */
890#define OCR1B   _SFR_MEM16(0x8A)
891
892#define OCR1BL  _SFR_MEM8(0x8A)
893#define OCR1BH  _SFR_MEM8(0x8B)
894
895/* Combine OCR1CL and OCR1CH */
896#define OCR1C   _SFR_MEM16(0x8C)
897
898#define OCR1CL  _SFR_MEM8(0x8C)
899#define OCR1CH  _SFR_MEM8(0x8D)
900
901/* Reserved [0x8E..0x8F] */
902
903#define TCCR3A  _SFR_MEM8(0x90)
904#define WGM30   0
905#define WGM31   1
906#define COM3C0  2
907#define COM3C1  3
908#define COM3B0  4
909#define COM3B1  5
910#define COM3A0  6
911#define COM3A1  7
912
913#define TCCR3B  _SFR_MEM8(0x91)
914#define CS30    0
915#define CS31    1
916#define CS32    2
917#define WGM32   3
918#define WGM33   4
919#define ICES3   6
920#define ICNC3   7
921
922#define TCCR3C  _SFR_MEM8(0x92)
923#define FOC3C   5
924#define FOC3B   6
925#define FOC3A   7
926
927/* Reserved [0x93] */
928
929/* Combine TCNT3L and TCNT3H */
930#define TCNT3   _SFR_MEM16(0x94)
931
932#define TCNT3L  _SFR_MEM8(0x94)
933#define TCNT3H  _SFR_MEM8(0x95)
934
935/* Combine ICR3L and ICR3H */
936#define ICR3    _SFR_MEM16(0x96)
937
938#define ICR3L   _SFR_MEM8(0x96)
939#define ICR3H   _SFR_MEM8(0x97)
940
941/* Combine OCR3AL and OCR3AH */
942#define OCR3A   _SFR_MEM16(0x98)
943
944#define OCR3AL  _SFR_MEM8(0x98)
945#define OCR3AH  _SFR_MEM8(0x99)
946
947/* Combine OCR3BL and OCR3BH */
948#define OCR3B   _SFR_MEM16(0x9A)
949
950#define OCR3BL  _SFR_MEM8(0x9A)
951#define OCR3BH  _SFR_MEM8(0x9B)
952
953/* Combine OCR3CL and OCR3CH */
954#define OCR3C   _SFR_MEM16(0x9C)
955
956#define OCR3CL  _SFR_MEM8(0x9C)
957#define OCR3CH  _SFR_MEM8(0x9D)
958
959/* Reserved [0x9E..0x9F] */
960
961#define TCCR4A  _SFR_MEM8(0xA0)
962#define WGM40   0
963#define WGM41   1
964#define COM4C0  2
965#define COM4C1  3
966#define COM4B0  4
967#define COM4B1  5
968#define COM4A0  6
969#define COM4A1  7
970
971#define TCCR4B  _SFR_MEM8(0xA1)
972#define CS40    0
973#define CS41    1
974#define CS42    2
975#define WGM42   3
976#define WGM43   4
977#define ICES4   6
978#define ICNC4   7
979
980#define TCCR4C  _SFR_MEM8(0xA2)
981#define FOC4C   5
982#define FOC4B   6
983#define FOC4A   7
984
985/* Reserved [0xA3] */
986
987/* Combine TCNT4L and TCNT4H */
988#define TCNT4   _SFR_MEM16(0xA4)
989
990#define TCNT4L  _SFR_MEM8(0xA4)
991#define TCNT4H  _SFR_MEM8(0xA5)
992
993/* Combine ICR4L and ICR4H */
994#define ICR4    _SFR_MEM16(0xA6)
995
996#define ICR4L   _SFR_MEM8(0xA6)
997#define ICR4H   _SFR_MEM8(0xA7)
998
999/* Combine OCR4AL and OCR4AH */
1000#define OCR4A   _SFR_MEM16(0xA8)
1001
1002#define OCR4AL  _SFR_MEM8(0xA8)
1003#define OCR4AH  _SFR_MEM8(0xA9)
1004
1005/* Combine OCR4BL and OCR4BH */
1006#define OCR4B   _SFR_MEM16(0xAA)
1007
1008#define OCR4BL  _SFR_MEM8(0xAA)
1009#define OCR4BH  _SFR_MEM8(0xAB)
1010
1011/* Combine OCR4CL and OCR4CH */
1012#define OCR4C   _SFR_MEM16(0xAC)
1013
1014#define OCR4CL  _SFR_MEM8(0xAC)
1015#define OCR4CH  _SFR_MEM8(0xAD)
1016
1017/* Reserved [0xAE..0xAF] */
1018
1019#define TCCR2A  _SFR_MEM8(0xB0)
1020#define WGM20   0
1021#define WGM21   1
1022#define COM2B0  4
1023#define COM2B1  5
1024#define COM2A0  6
1025#define COM2A1  7
1026
1027#define TCCR2B  _SFR_MEM8(0xB1)
1028#define CS20    0
1029#define CS21    1
1030#define CS22    2
1031#define WGM22   3
1032#define FOC2B   6
1033#define FOC2A   7
1034
1035#define TCNT2   _SFR_MEM8(0xB2)
1036
1037#define OCR2A   _SFR_MEM8(0xB3)
1038
1039#define OCR2B   _SFR_MEM8(0xB4)
1040
1041/* Reserved [0xB5] */
1042
1043#define ASSR    _SFR_MEM8(0xB6)
1044#define TCR2BUB 0
1045#define TCR2AUB 1
1046#define OCR2BUB 2
1047#define OCR2AUB 3
1048#define TCN2UB  4
1049#define AS2     5
1050#define EXCLK   6
1051#define EXCLKAMR 7
1052
1053/* Reserved [0xB7] */
1054
1055#define TWBR    _SFR_MEM8(0xB8)
1056
1057#define TWSR    _SFR_MEM8(0xB9)
1058#define TWPS0   0
1059#define TWPS1   1
1060#define TWS3    3
1061#define TWS4    4
1062#define TWS5    5
1063#define TWS6    6
1064#define TWS7    7
1065
1066#define TWAR    _SFR_MEM8(0xBA)
1067#define TWGCE   0
1068#define TWA0    1
1069#define TWA1    2
1070#define TWA2    3
1071#define TWA3    4
1072#define TWA4    5
1073#define TWA5    6
1074#define TWA6    7
1075
1076#define TWDR    _SFR_MEM8(0xBB)
1077
1078#define TWCR    _SFR_MEM8(0xBC)
1079#define TWIE    0
1080#define TWEN    2
1081#define TWWC    3
1082#define TWSTO   4
1083#define TWSTA   5
1084#define TWEA    6
1085#define TWINT   7
1086
1087#define TWAMR   _SFR_MEM8(0xBD)
1088#define TWAM0   1
1089#define TWAM1   2
1090#define TWAM2   3
1091#define TWAM3   4
1092#define TWAM4   5
1093#define TWAM5   6
1094#define TWAM6   7
1095
1096#define IRQ_MASK1 _SFR_MEM8(0xBE)
1097#define TX_START_EN 0
1098#define MAF_0_AMI_EN 1
1099#define MAF_1_AMI_EN 2
1100#define MAF_2_AMI_EN 3
1101#define MAF_3_AMI_EN 4
1102
1103#define IRQ_STATUS1 _SFR_MEM8(0xBF)
1104#define TX_START 0
1105#define MAF_0_AMI 1
1106#define MAF_1_AMI 2
1107#define MAF_2_AMI 3
1108#define MAF_3_AMI 4
1109
1110#define UCSR0A  _SFR_MEM8(0xC0)
1111#define MPCM0   0
1112#define U2X0    1
1113#define UPE0    2
1114#define DOR0    3
1115#define FE0     4
1116#define UDRE0   5
1117#define TXC0    6
1118#define RXC0    7
1119
1120#define UCSR0B  _SFR_MEM8(0xC1)
1121#define TXB80   0
1122#define RXB80   1
1123#define UCSZ02  2
1124#define TXEN0   3
1125#define RXEN0   4
1126#define UDRIE0  5
1127#define TXCIE0  6
1128#define RXCIE0  7
1129
1130#define UCSR0C  _SFR_MEM8(0xC2)
1131#define UCPOL0  0
1132#define UCSZ00  1
1133#define UCSZ01  2
1134#define USBS0   3
1135#define UPM00   4
1136#define UPM01   5
1137#define UMSEL00 6
1138#define UMSEL01 7
1139#define UCPHA0  1
1140#define UDORD0  2
1141
1142/* Reserved [0xC3] */
1143
1144/* Combine UBRR0L and UBRR0H */
1145#define UBRR0   _SFR_MEM16(0xC4)
1146
1147#define UBRR0L  _SFR_MEM8(0xC4)
1148#define UBRR0H  _SFR_MEM8(0xC5)
1149
1150#define UDR0    _SFR_MEM8(0xC6)
1151
1152/* Reserved [0xC7] */
1153
1154#define UCSR1A  _SFR_MEM8(0xC8)
1155#define MPCM1   0
1156#define U2X1    1
1157#define UPE1    2
1158#define DOR1    3
1159#define FE1     4
1160#define UDRE1   5
1161#define TXC1    6
1162#define RXC1    7
1163
1164#define UCSR1B  _SFR_MEM8(0xC9)
1165#define TXB81   0
1166#define RXB81   1
1167#define UCSZ12  2
1168#define TXEN1   3
1169#define RXEN1   4
1170#define UDRIE1  5
1171#define TXCIE1  6
1172#define RXCIE1  7
1173
1174#define UCSR1C  _SFR_MEM8(0xCA)
1175#define UCPOL1  0
1176#define UCSZ10  1
1177#define UCSZ11  2
1178#define USBS1   3
1179#define UPM10   4
1180#define UPM11   5
1181#define UMSEL10 6
1182#define UMSEL11 7
1183#define UCPHA1  1
1184#define UDORD1  2
1185
1186/* Reserved [0xCB] */
1187
1188/* Combine UBRR1L and UBRR1H */
1189#define UBRR1   _SFR_MEM16(0xCC)
1190
1191#define UBRR1L  _SFR_MEM8(0xCC)
1192#define UBRR1H  _SFR_MEM8(0xCD)
1193
1194#define UDR1    _SFR_MEM8(0xCE)
1195
1196/* Reserved [0xCF..0xD6] */
1197
1198#define SCRSTRLL _SFR_MEM8(0xD7)
1199#define SCRSTRLL0 0
1200#define SCRSTRLL1 1
1201#define SCRSTRLL2 2
1202#define SCRSTRLL3 3
1203#define SCRSTRLL4 4
1204#define SCRSTRLL5 5
1205#define SCRSTRLL6 6
1206#define SCRSTRLL7 7
1207
1208#define SCRSTRLH _SFR_MEM8(0xD8)
1209#define SCRSTRLH0 0
1210#define SCRSTRLH1 1
1211#define SCRSTRLH2 2
1212#define SCRSTRLH3 3
1213#define SCRSTRLH4 4
1214#define SCRSTRLH5 5
1215#define SCRSTRLH6 6
1216#define SCRSTRLH7 7
1217
1218#define SCRSTRHL _SFR_MEM8(0xD9)
1219#define SCRSTRHL0 0
1220#define SCRSTRHL1 1
1221#define SCRSTRHL2 2
1222#define SCRSTRHL3 3
1223#define SCRSTRHL4 4
1224#define SCRSTRHL5 5
1225#define SCRSTRHL6 6
1226#define SCRSTRHL7 7
1227
1228#define SCRSTRHH _SFR_MEM8(0xDA)
1229#define SCRSTRHH0 0
1230#define SCRSTRHH1 1
1231#define SCRSTRHH2 2
1232#define SCRSTRHH3 3
1233#define SCRSTRHH4 4
1234#define SCRSTRHH5 5
1235#define SCRSTRHH6 6
1236#define SCRSTRHH7 7
1237
1238#define SCCSR   _SFR_MEM8(0xDB)
1239#define SCCS10  0
1240#define SCCS11  1
1241#define SCCS20  2
1242#define SCCS21  3
1243#define SCCS30  4
1244#define SCCS31  5
1245
1246#define SCCR0   _SFR_MEM8(0xDC)
1247#define SCCMP1  0
1248#define SCCMP2  1
1249#define SCCMP3  2
1250#define SCTSE   3
1251#define SCCKSEL 4
1252#define SCEN    5
1253#define SCMBTS  6
1254#define SCRES   7
1255
1256#define SCCR1   _SFR_MEM8(0xDD)
1257#define SCENBO  0
1258#define SCEECLK 1
1259#define SCCKDIV0 2
1260#define SCCKDIV1 3
1261#define SCCKDIV2 4
1262#define SCBTSM  5
1263#define Res5    6
1264#define Res6    7
1265
1266#define SCSR    _SFR_MEM8(0xDE)
1267#define SCBSY   0
1268
1269#define SCIRQM  _SFR_MEM8(0xDF)
1270#define IRQMCP1 0
1271#define IRQMCP2 1
1272#define IRQMCP3 2
1273#define IRQMOF  3
1274#define IRQMBO  4
1275
1276#define SCIRQS  _SFR_MEM8(0xE0)
1277#define IRQSCP1 0
1278#define IRQSCP2 1
1279#define IRQSCP3 2
1280#define IRQSOF  3
1281#define IRQSBO  4
1282
1283#define SCCNTLL _SFR_MEM8(0xE1)
1284#define SCCNTLL0 0
1285#define SCCNTLL1 1
1286#define SCCNTLL2 2
1287#define SCCNTLL3 3
1288#define SCCNTLL4 4
1289#define SCCNTLL5 5
1290#define SCCNTLL6 6
1291#define SCCNTLL7 7
1292
1293#define SCCNTLH _SFR_MEM8(0xE2)
1294#define SCCNTLH0 0
1295#define SCCNTLH1 1
1296#define SCCNTLH2 2
1297#define SCCNTLH3 3
1298#define SCCNTLH4 4
1299#define SCCNTLH5 5
1300#define SCCNTLH6 6
1301#define SCCNTLH7 7
1302
1303#define SCCNTHL _SFR_MEM8(0xE3)
1304#define SCCNTHL0 0
1305#define SCCNTHL1 1
1306#define SCCNTHL2 2
1307#define SCCNTHL3 3
1308#define SCCNTHL4 4
1309#define SCCNTHL5 5
1310#define SCCNTHL6 6
1311#define SCCNTHL7 7
1312
1313#define SCCNTHH _SFR_MEM8(0xE4)
1314#define SCCNTHH0 0
1315#define SCCNTHH1 1
1316#define SCCNTHH2 2
1317#define SCCNTHH3 3
1318#define SCCNTHH4 4
1319#define SCCNTHH5 5
1320#define SCCNTHH6 6
1321#define SCCNTHH7 7
1322
1323#define SCBTSRLL _SFR_MEM8(0xE5)
1324#define SCBTSRLL0 0
1325#define SCBTSRLL1 1
1326#define SCBTSRLL2 2
1327#define SCBTSRLL3 3
1328#define SCBTSRLL4 4
1329#define SCBTSRLL5 5
1330#define SCBTSRLL6 6
1331#define SCBTSRLL7 7
1332
1333#define SCBTSRLH _SFR_MEM8(0xE6)
1334#define SCBTSRLH0 0
1335#define SCBTSRLH1 1
1336#define SCBTSRLH2 2
1337#define SCBTSRLH3 3
1338#define SCBTSRLH4 4
1339#define SCBTSRLH5 5
1340#define SCBTSRLH6 6
1341#define SCBTSRLH7 7
1342
1343#define SCBTSRHL _SFR_MEM8(0xE7)
1344#define SCBTSRHL0 0
1345#define SCBTSRHL1 1
1346#define SCBTSRHL2 2
1347#define SCBTSRHL3 3
1348#define SCBTSRHL4 4
1349#define SCBTSRHL5 5
1350#define SCBTSRHL6 6
1351#define SCBTSRHL7 7
1352
1353#define SCBTSRHH _SFR_MEM8(0xE8)
1354#define SCBTSRHH0 0
1355#define SCBTSRHH1 1
1356#define SCBTSRHH2 2
1357#define SCBTSRHH3 3
1358#define SCBTSRHH4 4
1359#define SCBTSRHH5 5
1360#define SCBTSRHH6 6
1361#define SCBTSRHH7 7
1362
1363#define SCTSRLL _SFR_MEM8(0xE9)
1364#define SCTSRLL0 0
1365#define SCTSRLL1 1
1366#define SCTSRLL2 2
1367#define SCTSRLL3 3
1368#define SCTSRLL4 4
1369#define SCTSRLL5 5
1370#define SCTSRLL6 6
1371#define SCTSRLL7 7
1372
1373#define SCTSRLH _SFR_MEM8(0xEA)
1374#define SCTSRLH0 0
1375#define SCTSRLH1 1
1376#define SCTSRLH2 2
1377#define SCTSRLH3 3
1378#define SCTSRLH4 4
1379#define SCTSRLH5 5
1380#define SCTSRLH6 6
1381#define SCTSRLH7 7
1382
1383#define SCTSRHL _SFR_MEM8(0xEB)
1384#define SCTSRHL0 0
1385#define SCTSRHL1 1
1386#define SCTSRHL2 2
1387#define SCTSRHL3 3
1388#define SCTSRHL4 4
1389#define SCTSRHL5 5
1390#define SCTSRHL6 6
1391#define SCTSRHL7 7
1392
1393#define SCTSRHH _SFR_MEM8(0xEC)
1394#define SCTSRHH0 0
1395#define SCTSRHH1 1
1396#define SCTSRHH2 2
1397#define SCTSRHH3 3
1398#define SCTSRHH4 4
1399#define SCTSRHH5 5
1400#define SCTSRHH6 6
1401#define SCTSRHH7 7
1402
1403#define SCOCR3LL _SFR_MEM8(0xED)
1404#define SCOCR3LL0 0
1405#define SCOCR3LL1 1
1406#define SCOCR3LL2 2
1407#define SCOCR3LL3 3
1408#define SCOCR3LL4 4
1409#define SCOCR3LL5 5
1410#define SCOCR3LL6 6
1411#define SCOCR3LL7 7
1412
1413#define SCOCR3LH _SFR_MEM8(0xEE)
1414#define SCOCR3LH0 0
1415#define SCOCR3LH1 1
1416#define SCOCR3LH2 2
1417#define SCOCR3LH3 3
1418#define SCOCR3LH4 4
1419#define SCOCR3LH5 5
1420#define SCOCR3LH6 6
1421#define SCOCR3LH7 7
1422
1423#define SCOCR3HL _SFR_MEM8(0xEF)
1424#define SCOCR3HL0 0
1425#define SCOCR3HL1 1
1426#define SCOCR3HL2 2
1427#define SCOCR3HL3 3
1428#define SCOCR3HL4 4
1429#define SCOCR3HL5 5
1430#define SCOCR3HL6 6
1431#define SCOCR3HL7 7
1432
1433#define SCOCR3HH _SFR_MEM8(0xF0)
1434#define SCOCR3HH0 0
1435#define SCOCR3HH1 1
1436#define SCOCR3HH2 2
1437#define SCOCR3HH3 3
1438#define SCOCR3HH4 4
1439#define SCOCR3HH5 5
1440#define SCOCR3HH6 6
1441#define SCOCR3HH7 7
1442
1443#define SCOCR2LL _SFR_MEM8(0xF1)
1444#define SCOCR2LL0 0
1445#define SCOCR2LL1 1
1446#define SCOCR2LL2 2
1447#define SCOCR2LL3 3
1448#define SCOCR2LL4 4
1449#define SCOCR2LL5 5
1450#define SCOCR2LL6 6
1451#define SCOCR2LL7 7
1452
1453#define SCOCR2LH _SFR_MEM8(0xF2)
1454#define SCOCR2LH0 0
1455#define SCOCR2LH1 1
1456#define SCOCR2LH2 2
1457#define SCOCR2LH3 3
1458#define SCOCR2LH4 4
1459#define SCOCR2LH5 5
1460#define SCOCR2LH6 6
1461#define SCOCR2LH7 7
1462
1463#define SCOCR2HL _SFR_MEM8(0xF3)
1464#define SCOCR2HL0 0
1465#define SCOCR2HL1 1
1466#define SCOCR2HL2 2
1467#define SCOCR2HL3 3
1468#define SCOCR2HL4 4
1469#define SCOCR2HL5 5
1470#define SCOCR2HL6 6
1471#define SCOCR2HL7 7
1472
1473#define SCOCR2HH _SFR_MEM8(0xF4)
1474#define SCOCR2HH0 0
1475#define SCOCR2HH1 1
1476#define SCOCR2HH2 2
1477#define SCOCR2HH3 3
1478#define SCOCR2HH4 4
1479#define SCOCR2HH5 5
1480#define SCOCR2HH6 6
1481#define SCOCR2HH7 7
1482
1483#define SCOCR1LL _SFR_MEM8(0xF5)
1484#define SCOCR1LL0 0
1485#define SCOCR1LL1 1
1486#define SCOCR1LL2 2
1487#define SCOCR1LL3 3
1488#define SCOCR1LL4 4
1489#define SCOCR1LL5 5
1490#define SCOCR1LL6 6
1491#define SCOCR1LL7 7
1492
1493#define SCOCR1LH _SFR_MEM8(0xF6)
1494#define SCOCR1LH0 0
1495#define SCOCR1LH1 1
1496#define SCOCR1LH2 2
1497#define SCOCR1LH3 3
1498#define SCOCR1LH4 4
1499#define SCOCR1LH5 5
1500#define SCOCR1LH6 6
1501#define SCOCR1LH7 7
1502
1503#define SCOCR1HL _SFR_MEM8(0xF7)
1504#define SCOCR1HL0 0
1505#define SCOCR1HL1 1
1506#define SCOCR1HL2 2
1507#define SCOCR1HL3 3
1508#define SCOCR1HL4 4
1509#define SCOCR1HL5 5
1510#define SCOCR1HL6 6
1511#define SCOCR1HL7 7
1512
1513#define SCOCR1HH _SFR_MEM8(0xF8)
1514#define SCOCR1HH0 0
1515#define SCOCR1HH1 1
1516#define SCOCR1HH2 2
1517#define SCOCR1HH3 3
1518#define SCOCR1HH4 4
1519#define SCOCR1HH5 5
1520#define SCOCR1HH6 6
1521#define SCOCR1HH7 7
1522
1523#define SCTSTRLL _SFR_MEM8(0xF9)
1524#define SCTSTRLL0 0
1525#define SCTSTRLL1 1
1526#define SCTSTRLL2 2
1527#define SCTSTRLL3 3
1528#define SCTSTRLL4 4
1529#define SCTSTRLL5 5
1530#define SCTSTRLL6 6
1531#define SCTSTRLL7 7
1532
1533#define SCTSTRLH _SFR_MEM8(0xFA)
1534#define SCTSTRLH0 0
1535#define SCTSTRLH1 1
1536#define SCTSTRLH2 2
1537#define SCTSTRLH3 3
1538#define SCTSTRLH4 4
1539#define SCTSTRLH5 5
1540#define SCTSTRLH6 6
1541#define SCTSTRLH7 7
1542
1543#define SCTSTRHL _SFR_MEM8(0xFB)
1544#define SCTSTRHL0 0
1545#define SCTSTRHL1 1
1546#define SCTSTRHL2 2
1547#define SCTSTRHL3 3
1548#define SCTSTRHL4 4
1549#define SCTSTRHL5 5
1550#define SCTSTRHL6 6
1551#define SCTSTRHL7 7
1552
1553#define SCTSTRHH _SFR_MEM8(0xFC)
1554#define SCTSTRHH0 0
1555#define SCTSTRHH1 1
1556#define SCTSTRHH2 2
1557#define SCTSTRHH3 3
1558#define SCTSTRHH4 4
1559#define SCTSTRHH5 5
1560#define SCTSTRHH6 6
1561#define SCTSTRHH7 7
1562
1563/* Reserved [0xFD..0x10B] */
1564
1565#define MAFCR0  _SFR_MEM8(0x10C)
1566#define MAF0EN  0
1567#define MAF1EN  1
1568#define MAF2EN  2
1569#define MAF3EN  3
1570
1571#define MAFCR1  _SFR_MEM8(0x10D)
1572#define AACK_0_I_AM_COORD 0
1573#define AACK_0_SET_PD 1
1574#define AACK_1_I_AM_COORD 2
1575#define AACK_1_SET_PD 3
1576#define AACK_2_I_AM_COORD 4
1577#define AACK_2_SET_PD 5
1578#define AACK_3_I_AM_COORD 6
1579#define AACK_3_SET_PD 7
1580
1581#define MAFSA0L _SFR_MEM8(0x10E)
1582#define MAFSA0L0 0
1583#define MAFSA0L1 1
1584#define MAFSA0L2 2
1585#define MAFSA0L3 3
1586#define MAFSA0L4 4
1587#define MAFSA0L5 5
1588#define MAFSA0L6 6
1589#define MAFSA0L7 7
1590
1591#define MAFSA0H _SFR_MEM8(0x10F)
1592#define MAFSA0H0 0
1593#define MAFSA0H1 1
1594#define MAFSA0H2 2
1595#define MAFSA0H3 3
1596#define MAFSA0H4 4
1597#define MAFSA0H5 5
1598#define MAFSA0H6 6
1599#define MAFSA0H7 7
1600
1601#define MAFPA0L _SFR_MEM8(0x110)
1602#define MAFPA0L0 0
1603#define MAFPA0L1 1
1604#define MAFPA0L2 2
1605#define MAFPA0L3 3
1606#define MAFPA0L4 4
1607#define MAFPA0L5 5
1608#define MAFPA0L6 6
1609#define MAFPA0L7 7
1610
1611#define MAFPA0H _SFR_MEM8(0x111)
1612#define MAFPA0H0 0
1613#define MAFPA0H1 1
1614#define MAFPA0H2 2
1615#define MAFPA0H3 3
1616#define MAFPA0H4 4
1617#define MAFPA0H5 5
1618#define MAFPA0H6 6
1619#define MAFPA0H7 7
1620
1621#define MAFSA1L _SFR_MEM8(0x112)
1622#define MAFSA1L0 0
1623#define MAFSA1L1 1
1624#define MAFSA1L2 2
1625#define MAFSA1L3 3
1626#define MAFSA1L4 4
1627#define MAFSA1L5 5
1628#define MAFSA1L6 6
1629#define MAFSA1L7 7
1630
1631#define MAFSA1H _SFR_MEM8(0x113)
1632#define MAFSA1H0 0
1633#define MAFSA1H1 1
1634#define MAFSA1H2 2
1635#define MAFSA1H3 3
1636#define MAFSA1H4 4
1637#define MAFSA1H5 5
1638#define MAFSA1H6 6
1639#define MAFSA1H7 7
1640
1641#define MAFPA1L _SFR_MEM8(0x114)
1642#define MAFPA1L0 0
1643#define MAFPA1L1 1
1644#define MAFPA1L2 2
1645#define MAFPA1L3 3
1646#define MAFPA1L4 4
1647#define MAFPA1L5 5
1648#define MAFPA1L6 6
1649#define MAFPA1L7 7
1650
1651#define MAFPA1H _SFR_MEM8(0x115)
1652#define MAFPA1H0 0
1653#define MAFPA1H1 1
1654#define MAFPA1H2 2
1655#define MAFPA1H3 3
1656#define MAFPA1H4 4
1657#define MAFPA1H5 5
1658#define MAFPA1H6 6
1659#define MAFPA1H7 7
1660
1661#define MAFSA2L _SFR_MEM8(0x116)
1662#define MAFSA2L0 0
1663#define MAFSA2L1 1
1664#define MAFSA2L2 2
1665#define MAFSA2L3 3
1666#define MAFSA2L4 4
1667#define MAFSA2L5 5
1668#define MAFSA2L6 6
1669#define MAFSA2L7 7
1670
1671#define MAFSA2H _SFR_MEM8(0x117)
1672#define MAFSA2H0 0
1673#define MAFSA2H1 1
1674#define MAFSA2H2 2
1675#define MAFSA2H3 3
1676#define MAFSA2H4 4
1677#define MAFSA2H5 5
1678#define MAFSA2H6 6
1679#define MAFSA2H7 7
1680
1681#define MAFPA2L _SFR_MEM8(0x118)
1682#define MAFPA2L0 0
1683#define MAFPA2L1 1
1684#define MAFPA2L2 2
1685#define MAFPA2L3 3
1686#define MAFPA2L4 4
1687#define MAFPA2L5 5
1688#define MAFPA2L6 6
1689#define MAFPA2L7 7
1690
1691#define MAFPA2H _SFR_MEM8(0x119)
1692#define MAFPA2H0 0
1693#define MAFPA2H1 1
1694#define MAFPA2H2 2
1695#define MAFPA2H3 3
1696#define MAFPA2H4 4
1697#define MAFPA2H5 5
1698#define MAFPA2H6 6
1699#define MAFPA2H7 7
1700
1701#define MAFSA3L _SFR_MEM8(0x11A)
1702#define MAFSA3L0 0
1703#define MAFSA3L1 1
1704#define MAFSA3L2 2
1705#define MAFSA3L3 3
1706#define MAFSA3L4 4
1707#define MAFSA3L5 5
1708#define MAFSA3L6 6
1709#define MAFSA3L7 7
1710
1711#define MAFSA3H _SFR_MEM8(0x11B)
1712#define MAFSA3H0 0
1713#define MAFSA3H1 1
1714#define MAFSA3H2 2
1715#define MAFSA3H3 3
1716#define MAFSA3H4 4
1717#define MAFSA3H5 5
1718#define MAFSA3H6 6
1719#define MAFSA3H7 7
1720
1721#define MAFPA3L _SFR_MEM8(0x11C)
1722#define MAFPA3L0 0
1723#define MAFPA3L1 1
1724#define MAFPA3L2 2
1725#define MAFPA3L3 3
1726#define MAFPA3L4 4
1727#define MAFPA3L5 5
1728#define MAFPA3L6 6
1729#define MAFPA3L7 7
1730
1731#define MAFPA3H _SFR_MEM8(0x11D)
1732#define MAFPA3H0 0
1733#define MAFPA3H1 1
1734#define MAFPA3H2 2
1735#define MAFPA3H3 3
1736#define MAFPA3H4 4
1737#define MAFPA3H5 5
1738#define MAFPA3H6 6
1739#define MAFPA3H7 7
1740
1741/* Reserved [0x11E..0x11F] */
1742
1743#define TCCR5A  _SFR_MEM8(0x120)
1744#define WGM50   0
1745#define WGM51   1
1746#define COM5C0  2
1747#define COM5C1  3
1748#define COM5B0  4
1749#define COM5B1  5
1750#define COM5A0  6
1751#define COM5A1  7
1752
1753#define TCCR5B  _SFR_MEM8(0x121)
1754#define CS50    0
1755#define CS51    1
1756#define CS52    2
1757#define WGM52   3
1758#define WGM53   4
1759#define ICES5   6
1760#define ICNC5   7
1761
1762#define TCCR5C  _SFR_MEM8(0x122)
1763#define FOC5C   5
1764#define FOC5B   6
1765#define FOC5A   7
1766
1767/* Reserved [0x123] */
1768
1769/* Combine TCNT5L and TCNT5H */
1770#define TCNT5   _SFR_MEM16(0x124)
1771
1772#define TCNT5L  _SFR_MEM8(0x124)
1773#define TCNT5H  _SFR_MEM8(0x125)
1774
1775/* Combine ICR5L and ICR5H */
1776#define ICR5    _SFR_MEM16(0x126)
1777
1778#define ICR5L   _SFR_MEM8(0x126)
1779#define ICR5H   _SFR_MEM8(0x127)
1780
1781/* Combine OCR5AL and OCR5AH */
1782#define OCR5A   _SFR_MEM16(0x128)
1783
1784#define OCR5AL  _SFR_MEM8(0x128)
1785#define OCR5AH  _SFR_MEM8(0x129)
1786
1787/* Combine OCR5BL and OCR5BH */
1788#define OCR5B   _SFR_MEM16(0x12A)
1789
1790#define OCR5BL  _SFR_MEM8(0x12A)
1791#define OCR5BH  _SFR_MEM8(0x12B)
1792
1793/* Combine OCR5CL and OCR5CH */
1794#define OCR5C   _SFR_MEM16(0x12C)
1795
1796#define OCR5CL  _SFR_MEM8(0x12C)
1797#define OCR5CH  _SFR_MEM8(0x12D)
1798
1799/* Reserved [0x12E] */
1800
1801#define LLCR    _SFR_MEM8(0x12F)
1802#define LLENCAL 0
1803#define LLSHORT 1
1804#define LLTCO   2
1805#define LLCAL   3
1806#define LLCOMP  4
1807#define LLDONE  5
1808
1809#define LLDRL   _SFR_MEM8(0x130)
1810#define LLDRL0  0
1811#define LLDRL1  1
1812#define LLDRL2  2
1813#define LLDRL3  3
1814
1815#define LLDRH   _SFR_MEM8(0x131)
1816#define LLDRH0  0
1817#define LLDRH1  1
1818#define LLDRH2  2
1819#define LLDRH3  3
1820#define LLDRH4  4
1821
1822#define DRTRAM3 _SFR_MEM8(0x132)
1823#define ENDRT   4
1824#define DRTSWOK 5
1825
1826#define DRTRAM2 _SFR_MEM8(0x133)
1827
1828#define DRTRAM1 _SFR_MEM8(0x134)
1829
1830#define DRTRAM0 _SFR_MEM8(0x135)
1831
1832#define DPDS0   _SFR_MEM8(0x136)
1833#define PBDRV0  0
1834#define PBDRV1  1
1835#define PDDRV0  2
1836#define PDDRV1  3
1837#define PEDRV0  4
1838#define PEDRV1  5
1839#define PFDRV0  6
1840#define PFDRV1  7
1841
1842#define DPDS1   _SFR_MEM8(0x137)
1843#define PGDRV0  0
1844#define PGDRV1  1
1845
1846#define PARCR   _SFR_MEM8(0x138)
1847#define PARUFI  0
1848#define PARDFI  1
1849#define PALTU0  2
1850#define PALTU1  3
1851#define PALTU2  4
1852#define PALTD0  5
1853#define PALTD1  6
1854#define PALTD2  7
1855
1856#define TRXPR   _SFR_MEM8(0x139)
1857#define TRXRST  0
1858#define SLPTR   1
1859
1860/* Reserved [0x13A..0x13B] */
1861
1862#define AES_CTRL _SFR_MEM8(0x13C)
1863#define AES_IM  2
1864#define AES_DIR 3
1865#define AES_MODE 5
1866#define AES_REQUEST 7
1867
1868#define AES_STATUS _SFR_MEM8(0x13D)
1869#define AES_DONE 0
1870#define AES_ER  7
1871
1872#define AES_STATE _SFR_MEM8(0x13E)
1873#define AES_STATE0 0
1874#define AES_STATE1 1
1875#define AES_STATE2 2
1876#define AES_STATE3 3
1877#define AES_STATE4 4
1878#define AES_STATE5 5
1879#define AES_STATE6 6
1880#define AES_STATE7 7
1881
1882#define AES_KEY _SFR_MEM8(0x13F)
1883#define AES_KEY0 0
1884#define AES_KEY1 1
1885#define AES_KEY2 2
1886#define AES_KEY3 3
1887#define AES_KEY4 4
1888#define AES_KEY5 5
1889#define AES_KEY6 6
1890#define AES_KEY7 7
1891
1892/* Reserved [0x140] */
1893
1894#define TRX_STATUS _SFR_MEM8(0x141)
1895#define TRX_STATUS0 0
1896#define TRX_STATUS1 1
1897#define TRX_STATUS2 2
1898#define TRX_STATUS3 3
1899#define TRX_STATUS4 4
1900#define TST_STATUS 5
1901#define CCA_STATUS 6
1902#define CCA_DONE 7
1903
1904#define TRX_STATE _SFR_MEM8(0x142)
1905#define TRX_CMD0 0
1906#define TRX_CMD1 1
1907#define TRX_CMD2 2
1908#define TRX_CMD3 3
1909#define TRX_CMD4 4
1910#define TRAC_STATUS0 5
1911#define TRAC_STATUS1 6
1912#define TRAC_STATUS2 7
1913
1914#define TRX_CTRL_0 _SFR_MEM8(0x143)
1915#define PMU_IF_INV 4
1916#define PMU_START 5
1917#define PMU_EN  6
1918#define Res7    7
1919
1920#define TRX_CTRL_1 _SFR_MEM8(0x144)
1921#define PLL_TX_FLT 4
1922#define TX_AUTO_CRC_ON 5
1923#define IRQ_2_EXT_EN 6
1924#define PA_EXT_EN 7
1925
1926#define PHY_TX_PWR _SFR_MEM8(0x145)
1927#define TX_PWR0 0
1928#define TX_PWR1 1
1929#define TX_PWR2 2
1930#define TX_PWR3 3
1931
1932#define PHY_RSSI _SFR_MEM8(0x146)
1933#define RSSI0   0
1934#define RSSI1   1
1935#define RSSI2   2
1936#define RSSI3   3
1937#define RSSI4   4
1938#define RND_VALUE0 5
1939#define RND_VALUE1 6
1940#define RX_CRC_VALID 7
1941
1942#define PHY_ED_LEVEL _SFR_MEM8(0x147)
1943#define ED_LEVEL0 0
1944#define ED_LEVEL1 1
1945#define ED_LEVEL2 2
1946#define ED_LEVEL3 3
1947#define ED_LEVEL4 4
1948#define ED_LEVEL5 5
1949#define ED_LEVEL6 6
1950#define ED_LEVEL7 7
1951
1952#define PHY_CC_CCA _SFR_MEM8(0x148)
1953#define CHANNEL0 0
1954#define CHANNEL1 1
1955#define CHANNEL2 2
1956#define CHANNEL3 3
1957#define CHANNEL4 4
1958#define CCA_MODE0 5
1959#define CCA_MODE1 6
1960#define CCA_REQUEST 7
1961
1962#define CCA_THRES _SFR_MEM8(0x149)
1963#define CCA_ED_THRES0 0
1964#define CCA_ED_THRES1 1
1965#define CCA_ED_THRES2 2
1966#define CCA_ED_THRES3 3
1967#define CCA_CS_THRES0 4
1968#define CCA_CS_THRES1 5
1969#define CCA_CS_THRES2 6
1970#define CCA_CS_THRES3 7
1971
1972#define RX_CTRL _SFR_MEM8(0x14A)
1973#define PDT_THRES0 0
1974#define PDT_THRES1 1
1975#define PDT_THRES2 2
1976#define PDT_THRES3 3
1977
1978#define SFD_VALUE _SFR_MEM8(0x14B)
1979#define SFD_VALUE0 0
1980#define SFD_VALUE1 1
1981#define SFD_VALUE2 2
1982#define SFD_VALUE3 3
1983#define SFD_VALUE4 4
1984#define SFD_VALUE5 5
1985#define SFD_VALUE6 6
1986#define SFD_VALUE7 7
1987
1988#define TRX_CTRL_2 _SFR_MEM8(0x14C)
1989#define OQPSK_DATA_RATE0 0
1990#define OQPSK_DATA_RATE1 1
1991#define RX_SAFE_MODE 7
1992
1993#define ANT_DIV _SFR_MEM8(0x14D)
1994#define ANT_CTRL0 0
1995#define ANT_CTRL1 1
1996#define ANT_EXT_SW_EN 2
1997#define ANT_DIV_EN 3
1998#define ANT_SEL 7
1999
2000#define IRQ_MASK _SFR_MEM8(0x14E)
2001#define PLL_LOCK_EN 0
2002#define PLL_UNLOCK_EN 1
2003#define RX_START_EN 2
2004#define RX_END_EN 3
2005#define CCA_ED_DONE_EN 4
2006#define AMI_EN  5
2007#define TX_END_EN 6
2008#define AWAKE_EN 7
2009
2010#define IRQ_STATUS _SFR_MEM8(0x14F)
2011#define PLL_LOCK 0
2012#define PLL_UNLOCK 1
2013#define RX_START 2
2014#define RX_END  3
2015#define CCA_ED_DONE 4
2016#define AMI     5
2017#define TX_END  6
2018#define AWAKE   7
2019
2020#define VREG_CTRL _SFR_MEM8(0x150)
2021#define DVDD_OK 2
2022#define DVREG_EXT 3
2023#define AVDD_OK 6
2024#define AVREG_EXT 7
2025
2026#define BATMON  _SFR_MEM8(0x151)
2027#define BATMON_VTH0 0
2028#define BATMON_VTH1 1
2029#define BATMON_VTH2 2
2030#define BATMON_VTH3 3
2031#define BATMON_HR 4
2032#define BATMON_OK 5
2033#define BAT_LOW_EN 6
2034#define BAT_LOW 7
2035
2036#define XOSC_CTRL _SFR_MEM8(0x152)
2037#define XTAL_TRIM0 0
2038#define XTAL_TRIM1 1
2039#define XTAL_TRIM2 2
2040#define XTAL_TRIM3 3
2041#define XTAL_MODE0 4
2042#define XTAL_MODE1 5
2043#define XTAL_MODE2 6
2044#define XTAL_MODE3 7
2045
2046#define CC_CTRL_0 _SFR_MEM8(0x153)
2047#define CC_NUMBER0 0
2048#define CC_NUMBER1 1
2049#define CC_NUMBER2 2
2050#define CC_NUMBER3 3
2051#define CC_NUMBER4 4
2052#define CC_NUMBER5 5
2053#define CC_NUMBER6 6
2054#define CC_NUMBER7 7
2055
2056#define CC_CTRL_1 _SFR_MEM8(0x154)
2057#define CC_BAND0 0
2058#define CC_BAND1 1
2059#define CC_BAND2 2
2060#define CC_BAND3 3
2061
2062#define RX_SYN  _SFR_MEM8(0x155)
2063#define RX_PDT_LEVEL0 0
2064#define RX_PDT_LEVEL1 1
2065#define RX_PDT_LEVEL2 2
2066#define RX_PDT_LEVEL3 3
2067#define RX_OVERRIDE 6
2068#define RX_PDT_DIS 7
2069
2070#define TRX_RPC _SFR_MEM8(0x156)
2071#define XAH_RPC_EN 0
2072#define IPAN_RPC_EN 1
2073#define PLL_RPC_EN 3
2074#define PDT_RPC_EN 4
2075#define RX_RPC_EN 5
2076#define RX_RPC_CTRL0 6
2077#define RX_RPC_CTRL1 7
2078
2079#define XAH_CTRL_1 _SFR_MEM8(0x157)
2080#define AACK_PROM_MODE 1
2081#define AACK_ACK_TIME 2
2082#define AACK_UPLD_RES_FT 4
2083#define AACK_FLTR_RES_FT 5
2084
2085#define FTN_CTRL _SFR_MEM8(0x158)
2086#define FTN_START 7
2087
2088/* Reserved [0x159] */
2089
2090#define PLL_CF  _SFR_MEM8(0x15A)
2091#define PLL_CF_START 7
2092
2093#define PLL_DCU _SFR_MEM8(0x15B)
2094#define PLL_DCU_START 7
2095
2096#define PART_NUM _SFR_MEM8(0x15C)
2097#define PART_NUM0 0
2098#define PART_NUM1 1
2099#define PART_NUM2 2
2100#define PART_NUM3 3
2101#define PART_NUM4 4
2102#define PART_NUM5 5
2103#define PART_NUM6 6
2104#define PART_NUM7 7
2105
2106#define VERSION_NUM _SFR_MEM8(0x15D)
2107#define VERSION_NUM0 0
2108#define VERSION_NUM1 1
2109#define VERSION_NUM2 2
2110#define VERSION_NUM3 3
2111#define VERSION_NUM4 4
2112#define VERSION_NUM5 5
2113#define VERSION_NUM6 6
2114#define VERSION_NUM7 7
2115
2116#define MAN_ID_0 _SFR_MEM8(0x15E)
2117#define MAN_ID_00 0
2118#define MAN_ID_01 1
2119#define MAN_ID_02 2
2120#define MAN_ID_03 3
2121#define MAN_ID_04 4
2122#define MAN_ID_05 5
2123#define MAN_ID_06 6
2124#define MAN_ID_07 7
2125
2126#define MAN_ID_1 _SFR_MEM8(0x15F)
2127#define MAN_ID_10 0
2128#define MAN_ID_11 1
2129#define MAN_ID_12 2
2130#define MAN_ID_13 3
2131#define MAN_ID_14 4
2132#define MAN_ID_15 5
2133#define MAN_ID_16 6
2134#define MAN_ID_17 7
2135
2136#define SHORT_ADDR_0 _SFR_MEM8(0x160)
2137#define SHORT_ADDR_00 0
2138#define SHORT_ADDR_01 1
2139#define SHORT_ADDR_02 2
2140#define SHORT_ADDR_03 3
2141#define SHORT_ADDR_04 4
2142#define SHORT_ADDR_05 5
2143#define SHORT_ADDR_06 6
2144#define SHORT_ADDR_07 7
2145
2146#define SHORT_ADDR_1 _SFR_MEM8(0x161)
2147#define SHORT_ADDR_10 0
2148#define SHORT_ADDR_11 1
2149#define SHORT_ADDR_12 2
2150#define SHORT_ADDR_13 3
2151#define SHORT_ADDR_14 4
2152#define SHORT_ADDR_15 5
2153#define SHORT_ADDR_16 6
2154#define SHORT_ADDR_17 7
2155
2156#define PAN_ID_0 _SFR_MEM8(0x162)
2157#define PAN_ID_00 0
2158#define PAN_ID_01 1
2159#define PAN_ID_02 2
2160#define PAN_ID_03 3
2161#define PAN_ID_04 4
2162#define PAN_ID_05 5
2163#define PAN_ID_06 6
2164#define PAN_ID_07 7
2165
2166#define PAN_ID_1 _SFR_MEM8(0x163)
2167#define PAN_ID_10 0
2168#define PAN_ID_11 1
2169#define PAN_ID_12 2
2170#define PAN_ID_13 3
2171#define PAN_ID_14 4
2172#define PAN_ID_15 5
2173#define PAN_ID_16 6
2174#define PAN_ID_17 7
2175
2176#define IEEE_ADDR_0 _SFR_MEM8(0x164)
2177#define IEEE_ADDR_00 0
2178#define IEEE_ADDR_01 1
2179#define IEEE_ADDR_02 2
2180#define IEEE_ADDR_03 3
2181#define IEEE_ADDR_04 4
2182#define IEEE_ADDR_05 5
2183#define IEEE_ADDR_06 6
2184#define IEEE_ADDR_07 7
2185
2186#define IEEE_ADDR_1 _SFR_MEM8(0x165)
2187#define IEEE_ADDR_10 0
2188#define IEEE_ADDR_11 1
2189#define IEEE_ADDR_12 2
2190#define IEEE_ADDR_13 3
2191#define IEEE_ADDR_14 4
2192#define IEEE_ADDR_15 5
2193#define IEEE_ADDR_16 6
2194#define IEEE_ADDR_17 7
2195
2196#define IEEE_ADDR_2 _SFR_MEM8(0x166)
2197#define IEEE_ADDR_20 0
2198#define IEEE_ADDR_21 1
2199#define IEEE_ADDR_22 2
2200#define IEEE_ADDR_23 3
2201#define IEEE_ADDR_24 4
2202#define IEEE_ADDR_25 5
2203#define IEEE_ADDR_26 6
2204#define IEEE_ADDR_27 7
2205
2206#define IEEE_ADDR_3 _SFR_MEM8(0x167)
2207#define IEEE_ADDR_30 0
2208#define IEEE_ADDR_31 1
2209#define IEEE_ADDR_32 2
2210#define IEEE_ADDR_33 3
2211#define IEEE_ADDR_34 4
2212#define IEEE_ADDR_35 5
2213#define IEEE_ADDR_36 6
2214#define IEEE_ADDR_37 7
2215
2216#define IEEE_ADDR_4 _SFR_MEM8(0x168)
2217#define IEEE_ADDR_40 0
2218#define IEEE_ADDR_41 1
2219#define IEEE_ADDR_42 2
2220#define IEEE_ADDR_43 3
2221#define IEEE_ADDR_44 4
2222#define IEEE_ADDR_45 5
2223#define IEEE_ADDR_46 6
2224#define IEEE_ADDR_47 7
2225
2226#define IEEE_ADDR_5 _SFR_MEM8(0x169)
2227#define IEEE_ADDR_50 0
2228#define IEEE_ADDR_51 1
2229#define IEEE_ADDR_52 2
2230#define IEEE_ADDR_53 3
2231#define IEEE_ADDR_54 4
2232#define IEEE_ADDR_55 5
2233#define IEEE_ADDR_56 6
2234#define IEEE_ADDR_57 7
2235
2236#define IEEE_ADDR_6 _SFR_MEM8(0x16A)
2237#define IEEE_ADDR_60 0
2238#define IEEE_ADDR_61 1
2239#define IEEE_ADDR_62 2
2240#define IEEE_ADDR_63 3
2241#define IEEE_ADDR_64 4
2242#define IEEE_ADDR_65 5
2243#define IEEE_ADDR_66 6
2244#define IEEE_ADDR_67 7
2245
2246#define IEEE_ADDR_7 _SFR_MEM8(0x16B)
2247#define IEEE_ADDR_70 0
2248#define IEEE_ADDR_71 1
2249#define IEEE_ADDR_72 2
2250#define IEEE_ADDR_73 3
2251#define IEEE_ADDR_74 4
2252#define IEEE_ADDR_75 5
2253#define IEEE_ADDR_76 6
2254#define IEEE_ADDR_77 7
2255
2256#define XAH_CTRL_0 _SFR_MEM8(0x16C)
2257#define SLOTTED_OPERATION 0
2258#define MAX_CSMA_RETRIES0 1
2259#define MAX_CSMA_RETRIES1 2
2260#define MAX_CSMA_RETRIES2 3
2261#define MAX_FRAME_RETRIES0 4
2262#define MAX_FRAME_RETRIES1 5
2263#define MAX_FRAME_RETRIES2 6
2264#define MAX_FRAME_RETRIES3 7
2265
2266#define CSMA_SEED_0 _SFR_MEM8(0x16D)
2267#define CSMA_SEED_00 0
2268#define CSMA_SEED_01 1
2269#define CSMA_SEED_02 2
2270#define CSMA_SEED_03 3
2271#define CSMA_SEED_04 4
2272#define CSMA_SEED_05 5
2273#define CSMA_SEED_06 6
2274#define CSMA_SEED_07 7
2275
2276#define CSMA_SEED_1 _SFR_MEM8(0x16E)
2277#define CSMA_SEED_10 0
2278#define CSMA_SEED_11 1
2279#define CSMA_SEED_12 2
2280#define AACK_I_AM_COORD 3
2281#define AACK_DIS_ACK 4
2282#define AACK_SET_PD 5
2283#define AACK_FVN_MODE0 6
2284#define AACK_FVN_MODE1 7
2285
2286#define CSMA_BE _SFR_MEM8(0x16F)
2287#define MIN_BE0 0
2288#define MIN_BE1 1
2289#define MIN_BE2 2
2290#define MIN_BE3 3
2291#define MAX_BE0 4
2292#define MAX_BE1 5
2293#define MAX_BE2 6
2294#define MAX_BE3 7
2295
2296/* Reserved [0x170..0x175] */
2297
2298#define TST_CTRL_DIGI _SFR_MEM8(0x176)
2299#define TST_CTRL_DIG0 0
2300#define TST_CTRL_DIG1 1
2301#define TST_CTRL_DIG2 2
2302#define TST_CTRL_DIG3 3
2303
2304/* Reserved [0x177..0x17A] */
2305
2306#define TST_RX_LENGTH _SFR_MEM8(0x17B)
2307#define RX_LENGTH0 0
2308#define RX_LENGTH1 1
2309#define RX_LENGTH2 2
2310#define RX_LENGTH3 3
2311#define RX_LENGTH4 4
2312#define RX_LENGTH5 5
2313#define RX_LENGTH6 6
2314#define RX_LENGTH7 7
2315
2316/* Reserved [0x17C..0x17F] */
2317
2318#define TRXFBST _SFR_MEM8(0x180)
2319
2320/* Reserved [0x181..0x1FE] */
2321
2322#define TRXFBEND _SFR_MEM8(0x1FF)
2323
2324
2325
2326/* Values and associated defines */
2327
2328
2329#define SLEEP_MODE_IDLE (0x00<<1)
2330#define SLEEP_MODE_ADC (0x01<<1)
2331#define SLEEP_MODE_PWR_DOWN (0x02<<1)
2332#define SLEEP_MODE_PWR_SAVE (0x03<<1)
2333#define SLEEP_MODE_STANDBY (0x06<<1)
2334#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
2335
2336/* Interrupt vectors */
2337/* Vector 0 is the reset vector */
2338/* External Interrupt Request 0 */
2339#define INT0_vect            _VECTOR(1)
2340#define INT0_vect_num        1
2341
2342/* External Interrupt Request 1 */
2343#define INT1_vect            _VECTOR(2)
2344#define INT1_vect_num        2
2345
2346/* External Interrupt Request 2 */
2347#define INT2_vect            _VECTOR(3)
2348#define INT2_vect_num        3
2349
2350/* External Interrupt Request 3 */
2351#define INT3_vect            _VECTOR(4)
2352#define INT3_vect_num        4
2353
2354/* External Interrupt Request 4 */
2355#define INT4_vect            _VECTOR(5)
2356#define INT4_vect_num        5
2357
2358/* External Interrupt Request 5 */
2359#define INT5_vect            _VECTOR(6)
2360#define INT5_vect_num        6
2361
2362/* External Interrupt Request 6 */
2363#define INT6_vect            _VECTOR(7)
2364#define INT6_vect_num        7
2365
2366/* External Interrupt Request 7 */
2367#define INT7_vect            _VECTOR(8)
2368#define INT7_vect_num        8
2369
2370/* Pin Change Interrupt Request 0 */
2371#define PCINT0_vect            _VECTOR(9)
2372#define PCINT0_vect_num        9
2373
2374/* Pin Change Interrupt Request 1 */
2375#define PCINT1_vect            _VECTOR(10)
2376#define PCINT1_vect_num        10
2377
2378/* Pin Change Interrupt Request 2 */
2379#define PCINT2_vect            _VECTOR(11)
2380#define PCINT2_vect_num        11
2381
2382/* Watchdog Time-out Interrupt */
2383#define WDT_vect            _VECTOR(12)
2384#define WDT_vect_num        12
2385
2386/* Timer/Counter2 Compare Match A */
2387#define TIMER2_COMPA_vect            _VECTOR(13)
2388#define TIMER2_COMPA_vect_num        13
2389
2390/* Timer/Counter2 Compare Match B */
2391#define TIMER2_COMPB_vect            _VECTOR(14)
2392#define TIMER2_COMPB_vect_num        14
2393
2394/* Timer/Counter2 Overflow */
2395#define TIMER2_OVF_vect            _VECTOR(15)
2396#define TIMER2_OVF_vect_num        15
2397
2398/* Timer/Counter1 Capture Event */
2399#define TIMER1_CAPT_vect            _VECTOR(16)
2400#define TIMER1_CAPT_vect_num        16
2401
2402/* Timer/Counter1 Compare Match A */
2403#define TIMER1_COMPA_vect            _VECTOR(17)
2404#define TIMER1_COMPA_vect_num        17
2405
2406/* Timer/Counter1 Compare Match B */
2407#define TIMER1_COMPB_vect            _VECTOR(18)
2408#define TIMER1_COMPB_vect_num        18
2409
2410/* Timer/Counter1 Compare Match C */
2411#define TIMER1_COMPC_vect            _VECTOR(19)
2412#define TIMER1_COMPC_vect_num        19
2413
2414/* Timer/Counter1 Overflow */
2415#define TIMER1_OVF_vect            _VECTOR(20)
2416#define TIMER1_OVF_vect_num        20
2417
2418/* Timer/Counter0 Compare Match A */
2419#define TIMER0_COMPA_vect            _VECTOR(21)
2420#define TIMER0_COMPA_vect_num        21
2421
2422/* Timer/Counter0 Compare Match B */
2423#define TIMER0_COMPB_vect            _VECTOR(22)
2424#define TIMER0_COMPB_vect_num        22
2425
2426/* Timer/Counter0 Overflow */
2427#define TIMER0_OVF_vect            _VECTOR(23)
2428#define TIMER0_OVF_vect_num        23
2429
2430/* SPI Serial Transfer Complete */
2431#define SPI_STC_vect            _VECTOR(24)
2432#define SPI_STC_vect_num        24
2433
2434/* USART0, Rx Complete */
2435#define USART0_RX_vect            _VECTOR(25)
2436#define USART0_RX_vect_num        25
2437
2438/* USART0 Data register Empty */
2439#define USART0_UDRE_vect            _VECTOR(26)
2440#define USART0_UDRE_vect_num        26
2441
2442/* USART0, Tx Complete */
2443#define USART0_TX_vect            _VECTOR(27)
2444#define USART0_TX_vect_num        27
2445
2446/* Analog Comparator */
2447#define ANALOG_COMP_vect            _VECTOR(28)
2448#define ANALOG_COMP_vect_num        28
2449
2450/* ADC Conversion Complete */
2451#define ADC_vect            _VECTOR(29)
2452#define ADC_vect_num        29
2453
2454/* EEPROM Ready */
2455#define EE_READY_vect            _VECTOR(30)
2456#define EE_READY_vect_num        30
2457
2458/* Timer/Counter3 Capture Event */
2459#define TIMER3_CAPT_vect            _VECTOR(31)
2460#define TIMER3_CAPT_vect_num        31
2461
2462/* Timer/Counter3 Compare Match A */
2463#define TIMER3_COMPA_vect            _VECTOR(32)
2464#define TIMER3_COMPA_vect_num        32
2465
2466/* Timer/Counter3 Compare Match B */
2467#define TIMER3_COMPB_vect            _VECTOR(33)
2468#define TIMER3_COMPB_vect_num        33
2469
2470/* Timer/Counter3 Compare Match C */
2471#define TIMER3_COMPC_vect            _VECTOR(34)
2472#define TIMER3_COMPC_vect_num        34
2473
2474/* Timer/Counter3 Overflow */
2475#define TIMER3_OVF_vect            _VECTOR(35)
2476#define TIMER3_OVF_vect_num        35
2477
2478/* USART1, Rx Complete */
2479#define USART1_RX_vect            _VECTOR(36)
2480#define USART1_RX_vect_num        36
2481
2482/* USART1 Data register Empty */
2483#define USART1_UDRE_vect            _VECTOR(37)
2484#define USART1_UDRE_vect_num        37
2485
2486/* USART1, Tx Complete */
2487#define USART1_TX_vect            _VECTOR(38)
2488#define USART1_TX_vect_num        38
2489
2490/* 2-wire Serial Interface */
2491#define TWI_vect            _VECTOR(39)
2492#define TWI_vect_num        39
2493
2494/* Store Program Memory Read */
2495#define SPM_READY_vect            _VECTOR(40)
2496#define SPM_READY_vect_num        40
2497
2498/* Timer/Counter4 Capture Event */
2499#define TIMER4_CAPT_vect            _VECTOR(41)
2500#define TIMER4_CAPT_vect_num        41
2501
2502/* Timer/Counter4 Compare Match A */
2503#define TIMER4_COMPA_vect            _VECTOR(42)
2504#define TIMER4_COMPA_vect_num        42
2505
2506/* Timer/Counter4 Compare Match B */
2507#define TIMER4_COMPB_vect            _VECTOR(43)
2508#define TIMER4_COMPB_vect_num        43
2509
2510/* Timer/Counter4 Compare Match C */
2511#define TIMER4_COMPC_vect            _VECTOR(44)
2512#define TIMER4_COMPC_vect_num        44
2513
2514/* Timer/Counter4 Overflow */
2515#define TIMER4_OVF_vect            _VECTOR(45)
2516#define TIMER4_OVF_vect_num        45
2517
2518/* Timer/Counter5 Capture Event */
2519#define TIMER5_CAPT_vect            _VECTOR(46)
2520#define TIMER5_CAPT_vect_num        46
2521
2522/* Timer/Counter5 Compare Match A */
2523#define TIMER5_COMPA_vect            _VECTOR(47)
2524#define TIMER5_COMPA_vect_num        47
2525
2526/* Timer/Counter5 Compare Match B */
2527#define TIMER5_COMPB_vect            _VECTOR(48)
2528#define TIMER5_COMPB_vect_num        48
2529
2530/* Timer/Counter5 Compare Match C */
2531#define TIMER5_COMPC_vect            _VECTOR(49)
2532#define TIMER5_COMPC_vect_num        49
2533
2534/* Timer/Counter5 Overflow */
2535#define TIMER5_OVF_vect            _VECTOR(50)
2536#define TIMER5_OVF_vect_num        50
2537
2538/* TRX24 - PLL lock interrupt */
2539#define TRX24_PLL_LOCK_vect            _VECTOR(57)
2540#define TRX24_PLL_LOCK_vect_num        57
2541
2542/* TRX24 - PLL unlock interrupt */
2543#define TRX24_PLL_UNLOCK_vect            _VECTOR(58)
2544#define TRX24_PLL_UNLOCK_vect_num        58
2545
2546/* TRX24 - Receive start interrupt */
2547#define TRX24_RX_START_vect            _VECTOR(59)
2548#define TRX24_RX_START_vect_num        59
2549
2550/* TRX24 - RX_END interrupt */
2551#define TRX24_RX_END_vect            _VECTOR(60)
2552#define TRX24_RX_END_vect_num        60
2553
2554/* TRX24 - CCA/ED done interrupt */
2555#define TRX24_CCA_ED_DONE_vect            _VECTOR(61)
2556#define TRX24_CCA_ED_DONE_vect_num        61
2557
2558/* TRX24 - XAH - AMI */
2559#define TRX24_XAH_AMI_vect            _VECTOR(62)
2560#define TRX24_XAH_AMI_vect_num        62
2561
2562/* TRX24 - TX_END interrupt */
2563#define TRX24_TX_END_vect            _VECTOR(63)
2564#define TRX24_TX_END_vect_num        63
2565
2566/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
2567#define TRX24_AWAKE_vect            _VECTOR(64)
2568#define TRX24_AWAKE_vect_num        64
2569
2570/* Symbol counter - compare match 1 interrupt */
2571#define SCNT_CMP1_vect            _VECTOR(65)
2572#define SCNT_CMP1_vect_num        65
2573
2574/* Symbol counter - compare match 2 interrupt */
2575#define SCNT_CMP2_vect            _VECTOR(66)
2576#define SCNT_CMP2_vect_num        66
2577
2578/* Symbol counter - compare match 3 interrupt */
2579#define SCNT_CMP3_vect            _VECTOR(67)
2580#define SCNT_CMP3_vect_num        67
2581
2582/* Symbol counter - overflow interrupt */
2583#define SCNT_OVFL_vect            _VECTOR(68)
2584#define SCNT_OVFL_vect_num        68
2585
2586/* Symbol counter - backoff interrupt */
2587#define SCNT_BACKOFF_vect            _VECTOR(69)
2588#define SCNT_BACKOFF_vect_num        69
2589
2590/* AES engine ready interrupt */
2591#define AES_READY_vect            _VECTOR(70)
2592#define AES_READY_vect_num        70
2593
2594/* Battery monitor indicates supply voltage below threshold */
2595#define BAT_LOW_vect            _VECTOR(71)
2596#define BAT_LOW_vect_num        71
2597
2598/* TRX24 TX start interrupt */
2599#define TRX24_TX_START_vect            _VECTOR(72)
2600#define TRX24_TX_START_vect_num        72
2601
2602/* Address match interrupt of address filter 0 */
2603#define TRX24_AMI0_vect            _VECTOR(73)
2604#define TRX24_AMI0_vect_num        73
2605
2606/* Address match interrupt of address filter 1 */
2607#define TRX24_AMI1_vect            _VECTOR(74)
2608#define TRX24_AMI1_vect_num        74
2609
2610/* Address match interrupt of address filter 2 */
2611#define TRX24_AMI2_vect            _VECTOR(75)
2612#define TRX24_AMI2_vect_num        75
2613
2614/* Address match interrupt of address filter 3 */
2615#define TRX24_AMI3_vect            _VECTOR(76)
2616#define TRX24_AMI3_vect_num        76
2617
2618#define _VECTORS_SIZE 308
2619
2620
2621/* Constants */
2622
2623#define SPM_PAGESIZE 256
2624#define FLASHSTART   0x0000
2625#define FLASHEND     0xFFFF
2626#define RAMSTART     0x0200
2627#define RAMSIZE      8192
2628#define RAMEND       0x21FF
2629#define E2START     0
2630#define E2SIZE      2048
2631#define E2PAGESIZE  8
2632#define E2END       0x07FF
2633#define XRAMEND      RAMEND
2634
2635
2636/* Fuses */
2637
2638#define FUSE_MEMORY_SIZE 3
2639
2640/* Low Fuse Byte */
2641#define FUSE_CKSEL_SUT0  (unsigned char)~_BV(0)
2642#define FUSE_CKSEL_SUT1  (unsigned char)~_BV(1)
2643#define FUSE_CKSEL_SUT2  (unsigned char)~_BV(2)
2644#define FUSE_CKSEL_SUT3  (unsigned char)~_BV(3)
2645#define FUSE_CKSEL_SUT4  (unsigned char)~_BV(4)
2646#define FUSE_CKSEL_SUT5  (unsigned char)~_BV(5)
2647#define FUSE_CKOUT       (unsigned char)~_BV(6)
2648#define FUSE_CKDIV8      (unsigned char)~_BV(7)
2649#define LFUSE_DEFAULT    (FUSE_CKSEL_SUT0 & FUSE_CKSEL_SUT2 & FUSE_CKSEL_SUT3 & FUSE_CKSEL_SUT4 & FUSE_CKDIV8)
2650
2651
2652/* High Fuse Byte */
2653#define FUSE_BOOTRST     (unsigned char)~_BV(0)
2654#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
2655#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
2656#define FUSE_EESAVE      (unsigned char)~_BV(3)
2657#define FUSE_WDTON       (unsigned char)~_BV(4)
2658#define FUSE_SPIEN       (unsigned char)~_BV(5)
2659#define FUSE_JTAGEN      (unsigned char)~_BV(6)
2660#define FUSE_OCDEN       (unsigned char)~_BV(7)
2661#define HFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
2662
2663
2664/* Extended Fuse Byte */
2665#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
2666#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
2667#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
2668#define EFUSE_DEFAULT    (FUSE_BODLEVEL0)
2669
2670
2671
2672/* Lock Bits */
2673#define __LOCK_BITS_EXIST
2674#define __BOOT_LOCK_BITS_0_EXIST
2675#define __BOOT_LOCK_BITS_1_EXIST
2676
2677
2678/* Signature */
2679#define SIGNATURE_0 0x1E
2680#define SIGNATURE_1 0xA6
2681#define SIGNATURE_2 0x03
2682
2683
2684#endif /* #ifdef _AVR_ATMEGA644RFR2_H_INCLUDED */
2685
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