source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom6450.h @ 4837

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1/* Copyright (c) 2004,2005,2006 Eric B. Weddington
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iom6450.h 2235 2011-03-17 04:13:14Z arcanum $ */
32
33/* avr/iom6450.h - definitions for ATmega6450 */
34
35#ifndef _AVR_IOM6450_H_
36#define _AVR_IOM6450_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iom6450.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* Registers and associated bit numbers */
51
52#define PINA    _SFR_IO8(0x00)
53#define PINA7   7
54#define PINA6   6
55#define PINA5   5
56#define PINA4   4
57#define PINA3   3
58#define PINA2   2
59#define PINA1   1
60#define PINA0   0
61
62#define DDRA    _SFR_IO8(0x01)
63#define DDA7    7
64#define DDA6    6
65#define DDA5    5
66#define DDA4    4
67#define DDA3    3
68#define DDA2    2
69#define DDA1    1
70#define DDA0    0
71
72#define PORTA   _SFR_IO8(0x02)
73#define PA7     7
74#define PA6     6
75#define PA5     5
76#define PA4     4
77#define PA3     3
78#define PA2     2
79#define PA1     1
80#define PA0     0
81
82#define PINB    _SFR_IO8(0x03)
83#define PINB7   7
84#define PINB6   6
85#define PINB5   5
86#define PINB4   4
87#define PINB3   3
88#define PINB2   2
89#define PINB1   1
90#define PINB0   0
91
92#define DDRB    _SFR_IO8(0x04)
93#define DDB7    7
94#define DDB6    6
95#define DDB5    5
96#define DDB4    4
97#define DDB3    3
98#define DDB2    2
99#define DDB1    1
100#define DDB0    0
101
102#define PORTB   _SFR_IO8(0x05)
103#define PB7     7
104#define PB6     6
105#define PB5     5
106#define PB4     4
107#define PB3     3
108#define PB2     2
109#define PB1     1
110#define PB0     0
111
112#define PINC    _SFR_IO8(0x06)
113#define PINC7   7
114#define PINC6   6
115#define PINC5   5
116#define PINC4   4
117#define PINC3   3
118#define PINC2   2
119#define PINC1   1
120#define PINC0   0
121
122#define DDRC    _SFR_IO8(0x07)
123#define DDC7    7
124#define DDC6    6
125#define DDC5    5
126#define DDC4    4
127#define DDC3    3
128#define DDC2    2
129#define DDC1    1
130#define DDC0    0
131
132#define PORTC   _SFR_IO8(0x08)
133#define PC7     7
134#define PC6     6
135#define PC5     5
136#define PC4     4
137#define PC3     3
138#define PC2     2
139#define PC1     1
140#define PC0     0
141
142#define PIND    _SFR_IO8(0x09)
143#define PIND7   7
144#define PIND6   6
145#define PIND5   5
146#define PIND4   4
147#define PIND3   3
148#define PIND2   2
149#define PIND1   1
150#define PIND0   0
151
152#define DDRD    _SFR_IO8(0x0A)
153#define DDD7    7
154#define DDD6    6
155#define DDD5    5
156#define DDD4    4
157#define DDD3    3
158#define DDD2    2
159#define DDD1    1
160#define DDD0    0
161
162#define PORTD   _SFR_IO8(0x0B)
163#define PD7     7
164#define PD6     6
165#define PD5     5
166#define PD4     4
167#define PD3     3
168#define PD2     2
169#define PD1     1
170#define PD0     0
171
172#define PINE    _SFR_IO8(0x0C)
173#define PINE7   7
174#define PINE6   6
175#define PINE5   5
176#define PINE4   4
177#define PINE3   3
178#define PINE2   2
179#define PINE1   1
180#define PINE0   0
181
182#define DDRE    _SFR_IO8(0x0D)
183#define DDE7    7
184#define DDE6    6
185#define DDE5    5
186#define DDE4    4
187#define DDE3    3
188#define DDE2    2
189#define DDE1    1
190#define DDE0    0
191
192#define PORTE   _SFR_IO8(0x0E)
193#define PE7     7
194#define PE6     6
195#define PE5     5
196#define PE4     4
197#define PE3     3
198#define PE2     2
199#define PE1     1
200#define PE0     0
201
202#define PINF    _SFR_IO8(0x0F)
203#define PINF7   7
204#define PINF6   6
205#define PINF5   5
206#define PINF4   4
207#define PINF3   3
208#define PINF2   2
209#define PINF1   1
210#define PINF0   0
211
212#define DDRF    _SFR_IO8(0x10)
213#define DDF7    7
214#define DDF6    6
215#define DDF5    5
216#define DDF4    4
217#define DDF3    3
218#define DDF2    2
219#define DDF1    1
220#define DDF0    0
221
222#define PORTF   _SFR_IO8(0x11)
223#define PF7     7
224#define PF6     6
225#define PF5     5
226#define PF4     4
227#define PF3     3
228#define PF2     2
229#define PF1     1
230#define PF0     0
231
232#define PING    _SFR_IO8(0x12)
233#define PING5   5
234#define PING4   4
235#define PING3   3
236#define PING2   2
237#define PING1   1
238#define PING0   0
239
240#define DDRG    _SFR_IO8(0x13)
241#define DDG4    4
242#define DDG3    3
243#define DDG2    2
244#define DDG1    1
245#define DDG0    0
246
247#define PORTG   _SFR_IO8(0x14)
248#define PG4     4
249#define PG3     3
250#define PG2     2
251#define PG1     1
252#define PG0     0
253
254#define TIFR0   _SFR_IO8(0x15)
255#define TOV0    0
256#define OCF0A   1
257
258#define TIFR1   _SFR_IO8(0x16)
259#define TOV1    0
260#define OCF1A   1
261#define OCF1B   2
262#define ICF1    5
263
264#define TIFR2   _SFR_IO8(0x17)
265#define TOV2    0
266#define OCF2A   1
267
268/* Reserved [0x18..0x1B] */
269
270#define EIFR    _SFR_IO8(0x1C)
271#define INTF0   0
272#define PCIF0   4
273#define PCIF1   5
274#define PCIF2   6
275#define PCIF3   7
276
277#define EIMSK   _SFR_IO8(0x1D)
278#define INT0    0
279#define PCIE0   4
280#define PCIE1   5
281#define PCIE2   6
282#define PCIE3   7
283
284#define GPIOR0  _SFR_IO8(0x1E)
285
286#define EECR    _SFR_IO8(0x1F)
287#define EERE    0
288#define EEWE    1
289#define EEMWE   2
290#define EERIE   3
291
292#define EEDR    _SFR_IO8(0X20)
293
294/* Combine EEARL and EEARH */
295#define EEAR    _SFR_IO16(0x21)
296#define EEARL   _SFR_IO8(0x21)
297#define EEARH   _SFR_IO8(0X22)
298
299/* 6-char sequence denoting where to find the EEPROM registers in memory space.
300   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
301   subroutines.
302   First two letters:  EECR address.
303   Second two letters: EEDR address.
304   Last two letters:   EEAR address.  */
305#define __EEPROM_REG_LOCATIONS__ 1F2021
306
307#define GTCCR   _SFR_IO8(0x23)
308#define PSR10   0
309#define PSR2    1
310#define TSM     7
311
312#define TCCR0A  _SFR_IO8(0x24)
313#define CS00    0
314#define CS01    1
315#define CS02    2
316#define WGM01   3
317#define COM0A0  4
318#define COM0A1  5
319#define WGM00   6
320#define FOC0A   7
321
322/* Reserved [0x25] */
323
324#define TCNT0   _SFR_IO8(0X26)
325
326#define OCR0A   _SFR_IO8(0X27)
327
328/* Reserved [0x28..0x29] */
329
330#define GPIOR1  _SFR_IO8(0x2A)
331
332#define GPIOR2  _SFR_IO8(0x2B)
333
334#define SPCR    _SFR_IO8(0x2C)
335#define SPR0    0
336#define SPR1    1
337#define CPHA    2
338#define CPOL    3
339#define MSTR    4
340#define DORD    5
341#define SPE     6
342#define SPIE    7
343
344#define SPSR    _SFR_IO8(0x2D)
345#define SPI2X   0
346#define WCOL    6
347#define SPIF    7
348
349#define SPDR    _SFR_IO8(0X2E)
350
351/* Reserved [0x2F] */
352
353#define ACSR    _SFR_IO8(0x30)
354#define ACIS0   0
355#define ACIS1   1
356#define ACIC    2
357#define ACIE    3
358#define ACI     4
359#define ACO     5
360#define ACBG    6
361#define ACD     7
362
363#define OCDR    _SFR_IO8(0x31)
364#define OCDR0   0
365#define OCDR1   1
366#define OCDR2   2
367#define OCDR3   3
368#define OCDR4   4
369#define OCDR5   5
370#define OCDR6   6
371#define OCDR7   7
372#define IDRD    7
373
374/* Reserved [0x32] */
375
376#define SMCR    _SFR_IO8(0x33)
377#define SE      0
378#define SM0     1
379#define SM1     2
380#define SM2     3
381
382#define MCUSR   _SFR_IO8(0x34)
383#define PORF    0
384#define EXTRF   1
385#define BORF    2
386#define WDRF    3
387#define JTRF    4
388
389#define MCUCR   _SFR_IO8(0X35)
390#define IVCE    0
391#define IVSEL   1
392#define PUD     4
393#define JTD     7
394
395/* Reserved [0x36] */
396
397#define SPMCSR  _SFR_IO8(0x37)
398#define SPMEN   0
399#define PGERS   1
400#define PGWRT   2
401#define BLBSET  3
402#define RWWSRE  4
403#define RWWSB   6
404#define SPMIE   7
405
406/* Reserved [0x38..0x3C] */
407
408/* SP [0x3D..0x3E] */
409/* SREG [0x3F] */
410
411#define WDTCR   _SFR_MEM8(0x60)
412#define WDP0    0
413#define WDP1    1
414#define WDP2    2
415#define WDE     3
416#define WDCE    4
417
418#define CLKPR   _SFR_MEM8(0x61)
419#define CLKPS0  0
420#define CLKPS1  1
421#define CLKPS2  2
422#define CLKPS3  3
423#define CLKPCE  7
424
425/* Reserved [0x62..0x63] */
426
427#define PRR     _SFR_MEM8(0x64)
428#define PRADC       0
429#define PRUSART0    1
430#define PRSPI       2
431#define PRTIM1      3
432
433#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1))
434#define __AVR_HAVE_PRR_PRADC
435#define __AVR_HAVE_PRR_PRUSART0
436#define __AVR_HAVE_PRR_PRSPI
437#define __AVR_HAVE_PRR_PRTIM1
438
439/* Reserved [0x65] */
440
441#define OSCCAL  _SFR_MEM8(0x66)
442
443/* Reserved [0x67..0x68] */
444
445#define EICRA   _SFR_MEM8(0x69)
446#define ISC00   0
447#define ISC01   1
448
449/* Reserved [0x6A] */
450
451#define PCMSK0  _SFR_MEM8(0x6B)
452#define PCINT0  0
453#define PCINT1  1
454#define PCINT2  2
455#define PCINT3  3
456#define PCINT4  4
457#define PCINT5  5
458#define PCINT6  6
459#define PCINT7  7
460
461#define PCMSK1  _SFR_MEM8(0x6C)
462#define PCINT8  0
463#define PCINT9  1
464#define PCINT10 2
465#define PCINT11 3
466#define PCINT12 4
467#define PCINT13 5
468#define PCINT14 6
469#define PCINT15 7
470
471#define PCMSK2  _SFR_MEM8(0x6D)
472#define PCINT16 0
473#define PCINT17 1
474#define PCINT18 2
475#define PCINT19 3
476#define PCINT20 4
477#define PCINT21 5
478#define PCINT22 6
479#define PCINT23 7
480
481#define TIMSK0  _SFR_MEM8(0x6E)
482#define TOIE0   0
483#define OCIE0A  1
484
485#define TIMSK1  _SFR_MEM8(0x6F)
486#define TOIE1   0
487#define OCIE1A  1
488#define OCIE1B  2
489#define ICIE1   5
490
491#define TIMSK2  _SFR_MEM8(0x70)
492#define TOIE2   0
493#define OCIE2A  1
494
495/* Reserved [0x71..0x72] */
496
497#define PCMSK3  _SFR_MEM8(0x73)
498#define PCINT24 0
499#define PCINT25 1
500#define PCINT26 2
501#define PCINT27 3
502#define PCINT28 4
503#define PCINT29 5
504#define PCINT30 6
505
506/* Reserved [0x74..0x77] */
507
508/* Combine ADCL and ADCH */
509#ifndef __ASSEMBLER__
510#define ADC     _SFR_MEM16(0x78)
511#endif
512#define ADCW    _SFR_MEM16(0x78)
513#define ADCL    _SFR_MEM8(0x78)
514#define ADCH    _SFR_MEM8(0x79)
515
516#define ADCSRA  _SFR_MEM8(0x7A)
517#define ADPS0   0
518#define ADPS1   1
519#define ADPS2   2
520#define ADIE    3
521#define ADIF    4
522#define ADATE   5
523#define ADSC    6
524#define ADEN    7
525
526#define ADCSRB  _SFR_MEM8(0x7B)
527#define ADTS0   0
528#define ADTS1   1
529#define ADTS2   2
530#define ACME    6
531
532#define ADMUX   _SFR_MEM8(0x7C)
533#define MUX0    0
534#define MUX1    1
535#define MUX2    2
536#define MUX3    3
537#define MUX4    4
538#define ADLAR   5
539#define REFS0   6
540#define REFS1   7
541
542/* Reserved [0x7D] */
543
544#define DIDR0   _SFR_MEM8(0x7E)
545#define ADC0D   0
546#define ADC1D   1
547#define ADC2D   2
548#define ADC3D   3
549#define ADC4D   4
550#define ADC5D   5
551#define ADC6D   6
552#define ADC7D   7
553
554#define DIDR1   _SFR_MEM8(0x7F)
555#define AIN0D   0
556#define AIN1D   1
557
558#define TCCR1A  _SFR_MEM8(0X80)
559#define WGM10   0
560#define WGM11   1
561#define COM1B0  4
562#define COM1B1  5
563#define COM1A0  6
564#define COM1A1  7
565
566#define TCCR1B  _SFR_MEM8(0X81)
567#define CS10    0
568#define CS11    1
569#define CS12    2
570#define WGM12   3
571#define WGM13   4
572#define ICES1   6
573#define ICNC1   7
574
575#define TCCR1C  _SFR_MEM8(0x82)
576#define FOC1B   6
577#define FOC1A   7
578
579/* Reserved [0x83] */
580
581/* Combine TCNT1L and TCNT1H */
582#define TCNT1   _SFR_MEM16(0x84)
583
584#define TCNT1L  _SFR_MEM8(0x84)
585#define TCNT1H  _SFR_MEM8(0x85)
586
587/* Combine ICR1L and ICR1H */
588#define ICR1    _SFR_MEM16(0x86)
589
590#define ICR1L   _SFR_MEM8(0x86)
591#define ICR1H   _SFR_MEM8(0x87)
592
593/* Combine OCR1AL and OCR1AH */
594#define OCR1A   _SFR_MEM16(0x88)
595
596#define OCR1AL  _SFR_MEM8(0x88)
597#define OCR1AH  _SFR_MEM8(0x89)
598
599/* Combine OCR1BL and OCR1BH */
600#define OCR1B   _SFR_MEM16(0x8A)
601
602#define OCR1BL  _SFR_MEM8(0x8A)
603#define OCR1BH  _SFR_MEM8(0x8B)
604
605/* Reserved [0x8C..0xAF] */
606
607#define TCCR2A  _SFR_MEM8(0xB0)
608#define CS20    0
609#define CS21    1
610#define CS22    2
611#define WGM21   3
612#define COM2A0  4
613#define COM2A1  5
614#define WGM20   6
615#define FOC2A   7
616
617/* Reserved [0xB1] */
618
619#define TCNT2   _SFR_MEM8(0xB2)
620
621#define OCR2A   _SFR_MEM8(0xB3)
622
623/* Reserved [0xB4..0xB5] */
624
625#define ASSR    _SFR_MEM8(0xB6)
626#define TCR2UB  0
627#define OCR2UB  1
628#define TCN2UB  2
629#define AS2     3
630#define EXCLK   4
631
632/* Reserved [0xB7] */
633
634#define USICR   _SFR_MEM8(0xB8)
635#define USITC   0
636#define USICLK  1
637#define USICS0  2
638#define USICS1  3
639#define USIWM0  4
640#define USIWM1  5
641#define USIOIE  6
642#define USISIE  7
643
644#define USISR   _SFR_MEM8(0xB9)
645#define USICNT0 0
646#define USICNT1 1
647#define USICNT2 2
648#define USICNT3 3
649#define USIDC   4
650#define USIPF   5
651#define USIOIF  6
652#define USISIF  7
653
654#define USIDR   _SFR_MEM8(0xBA)
655
656/* Reserved [0xBB..0xBF] */
657
658#define UCSR0A  _SFR_MEM8(0xC0)
659#define MPCM0   0
660#define U2X0    1
661#define UPE0    2
662#define DOR0    3
663#define FE0     4
664#define UDRE0   5
665#define TXC0    6
666#define RXC0    7
667
668#define UCSR0B  _SFR_MEM8(0XC1)
669#define TXB80   0
670#define RXB80   1
671#define UCSZ02  2
672#define TXEN0   3
673#define RXEN0   4
674#define UDRIE0  5
675#define TXCIE0  6
676#define RXCIE0  7
677
678#define UCSR0C  _SFR_MEM8(0xC2)
679#define UCPOL0  0
680#define UCSZ00  1
681#define UCSZ01  2
682#define USBS0   3
683#define UPM00   4
684#define UPM01   5
685#define UMSEL0  6
686
687/* Reserved [0xC3] */
688
689/* Combine UBRR0L and UBRR0H */
690#define UBRR0   _SFR_MEM16(0xC4)
691
692#define UBRR0L  _SFR_MEM8(0xC4)
693#define UBRR0H  _SFR_MEM8(0xC5)
694
695#define UDR0    _SFR_MEM8(0XC6)
696
697/* Reserved [0xC7..0xD7] */
698
699#define PINH    _SFR_MEM8(0xD8)
700#define PINH7   7
701#define PINH6   6
702#define PINH5   5
703#define PINH4   4
704#define PINH3   3
705#define PINH2   2
706#define PINH1   1
707#define PINH0   0
708
709#define DDRH    _SFR_MEM8(0xD9)
710#define DDH7    7
711#define DDH6    6
712#define DDH5    5
713#define DDH4    4
714#define DDH3    3
715#define DDH2    2
716#define DDH1    1
717#define DDH0    0
718
719#define PORTH   _SFR_MEM8(0xDA)
720#define PH7     7
721#define PH6     6
722#define PH5     5
723#define PH4     4
724#define PH3     3
725#define PH2     2
726#define PH1     1
727#define PH0     0
728
729#define PINJ    _SFR_MEM8(0xDB)
730#define PINJ6   6
731#define PINJ5   5
732#define PINJ4   4
733#define PINJ3   3
734#define PINJ2   2
735#define PINJ1   1
736#define PINJ0   0
737
738#define DDRJ    _SFR_MEM8(0xDC)
739#define DDJ6    6
740#define DDJ5    5
741#define DDJ4    4
742#define DDJ3    3
743#define DDJ2    2
744#define DDJ1    1
745#define DDJ0    0
746
747#define PORTJ   _SFR_MEM8(0xDD)
748#define PJ6     6
749#define PJ5     5
750#define PJ4     4
751#define PJ3     3
752#define PJ2     2
753#define PJ1     1
754#define PJ0     0
755
756/* Reserved [0xDE..0xFF] */
757
758
759/* Interrupt vectors */
760/* Vector 0 is the reset vector */
761
762/* External Interrupt Request 0 */
763#define INT0_vect_num           1
764#define INT0_vect                       _VECTOR(1)
765#define SIG_INTERRUPT0                  _VECTOR(1)
766
767/* Pin Change Interrupt Request 0 */
768#define PCINT0_vect_num         2
769#define PCINT0_vect                     _VECTOR(2)
770#define SIG_PIN_CHANGE0                 _VECTOR(2)
771
772/* Pin Change Interrupt Request 1 */
773#define PCINT1_vect_num         3
774#define PCINT1_vect                     _VECTOR(3)
775#define SIG_PIN_CHANGE1                 _VECTOR(3)
776
777/* Timer/Counter2 Compare Match */
778#define TIMER2_COMP_vect_num    4
779#define TIMER2_COMP_vect                _VECTOR(4)
780#define SIG_OUTPUT_COMPARE2             _VECTOR(4)
781
782/* Timer/Counter2 Overflow */
783#define TIMER2_OVF_vect_num             5
784#define TIMER2_OVF_vect                 _VECTOR(5)
785#define SIG_OVERFLOW2                   _VECTOR(5)
786
787/* Timer/Counter1 Capture Event */
788#define TIMER1_CAPT_vect_num    6
789#define TIMER1_CAPT_vect                _VECTOR(6)
790#define SIG_INPUT_CAPTURE1              _VECTOR(6)
791
792/* Timer/Counter1 Compare Match A */
793#define TIMER1_COMPA_vect_num   7
794#define TIMER1_COMPA_vect               _VECTOR(7)
795#define SIG_OUTPUT_COMPARE1A    _VECTOR(7)
796
797/* Timer/Counter Compare Match B */
798#define TIMER1_COMPB_vect_num   8
799#define TIMER1_COMPB_vect               _VECTOR(8)
800#define SIG_OUTPUT_COMPARE1B    _VECTOR(8)
801
802/* Timer/Counter1 Overflow */
803#define TIMER1_OVF_vect_num             9
804#define TIMER1_OVF_vect                 _VECTOR(9)
805#define SIG_OVERFLOW1                   _VECTOR(9)
806
807/* Timer/Counter0 Compare Match */
808#define TIMER0_COMP_vect_num    10
809#define TIMER0_COMP_vect                _VECTOR(10)
810#define SIG_OUTPUT_COMPARE0             _VECTOR(10)
811
812/* Timer/Counter0 Overflow */
813#define TIMER0_OVF_vect_num             11
814#define TIMER0_OVF_vect                 _VECTOR(11)
815#define SIG_OVERFLOW0                   _VECTOR(11)
816
817/* SPI Serial Transfer Complete */
818#define SPI_STC_vect_num                12
819#define SPI_STC_vect                    _VECTOR(12)
820#define SIG_SPI                             _VECTOR(12)
821
822/* USART, Rx Complete */
823#define USART_RX_vect_num               13
824#define USART_RX_vect                   _VECTOR(13)
825#define USART0_RX_vect                  _VECTOR(13)  /* Alias */
826#define SIG_UART_RECV                   _VECTOR(13)
827
828/* USART Data register Empty */
829#define USART_UDRE_vect_num             14
830#define USART_UDRE_vect                 _VECTOR(14)
831#define USART0_UDRE_vect                _VECTOR(14)  /* Alias */
832#define SIG_UART_DATA                   _VECTOR(14)
833
834/* USART0, Tx Complete */
835#define USART0_TX_vect_num              15
836#define USART0_TX_vect                  _VECTOR(15)
837#define USART_TX_vect                   _VECTOR(15)  /* Alias */
838#define SIG_UART_TRANS                  _VECTOR(15)
839
840/* USI Start Condition */
841#define USI_START_vect_num              16
842#define USI_START_vect                  _VECTOR(16)
843#define SIG_USI_START                   _VECTOR(16)
844
845/* USI Overflow */
846#define USI_OVERFLOW_vect_num   17
847#define USI_OVERFLOW_vect               _VECTOR(17)
848#define SIG_USI_OVERFLOW                _VECTOR(17)
849
850/* Analog Comparator */
851#define ANALOG_COMP_vect_num    18
852#define ANALOG_COMP_vect                _VECTOR(18)
853#define SIG_COMPARATOR                  _VECTOR(18)
854
855/* ADC Conversion Complete */
856#define ADC_vect_num            19
857#define ADC_vect                        _VECTOR(19)
858#define SIG_ADC                         _VECTOR(19)
859
860/* EEPROM Ready */
861#define EE_READY_vect_num               20
862#define EE_READY_vect                   _VECTOR(20)
863#define SIG_EEPROM_READY                _VECTOR(20)
864
865/* Store Program Memory Read */
866#define SPM_READY_vect_num              21
867#define SPM_READY_vect                  _VECTOR(21)
868#define SIG_SPM_READY                   _VECTOR(21)
869
870/* Pin Change Interrupt Request 2 */
871#define PCINT2_vect_num         23
872#define PCINT2_vect                     _VECTOR(23)
873#define SIG_PIN_CHANGE2                 _VECTOR(23)
874
875/* Pin Change Interrupt Request 3 */
876#define PCINT3_vect_num         24
877#define PCINT3_vect                     _VECTOR(24)
878#define SIG_PIN_CHANGE3                 _VECTOR(24)
879
880#define _VECTORS_SIZE 100
881
882
883/* Constants */
884#define SPM_PAGESIZE 256
885#define RAMSTART     (0x100)
886#define RAMEND       0x10FF
887#define XRAMEND      RAMEND
888#define E2END        0x7FF
889#define E2PAGESIZE   8
890#define FLASHEND     0xFFFF
891
892
893/* Fuses */
894
895#define FUSE_MEMORY_SIZE 3
896
897/* Low Fuse Byte */
898#define FUSE_CKSEL0      (unsigned char)~_BV(0)
899#define FUSE_CKSEL1      (unsigned char)~_BV(1)
900#define FUSE_CKSEL2      (unsigned char)~_BV(2)
901#define FUSE_CKSEL3      (unsigned char)~_BV(3)
902#define FUSE_SUT0        (unsigned char)~_BV(4)
903#define FUSE_SUT1        (unsigned char)~_BV(5)
904#define FUSE_CKOUT       (unsigned char)~_BV(6)
905#define FUSE_CKDIV8      (unsigned char)~_BV(7)
906#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
907
908/* High Fuse Byte */
909#define FUSE_BOOTRST     (unsigned char)~_BV(0)
910#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
911#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
912#define FUSE_EESAVE      (unsigned char)~_BV(3)
913#define FUSE_WDTON       (unsigned char)~_BV(4)
914#define FUSE_SPIEN       (unsigned char)~_BV(5)
915#define FUSE_JTAGEN      (unsigned char)~_BV(6)
916#define FUSE_OCDEN       (unsigned char)~_BV(7)
917#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
918
919/* Extended Fuse Byte */
920#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
921#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
922#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
923#define EFUSE_DEFAULT (0xFF)
924
925
926/* Lock Bits */
927#define __LOCK_BITS_EXIST
928#define __BOOT_LOCK_BITS_0_EXIST
929#define __BOOT_LOCK_BITS_1_EXIST
930
931
932/* Signature */
933#define SIGNATURE_0 0x1E
934#define SIGNATURE_1 0x96
935#define SIGNATURE_2 0x06
936
937
938/* Deprecated items */
939#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
940
941#pragma GCC system_header
942
943#pragma GCC poison SIG_INTERRUPT0
944#pragma GCC poison SIG_PIN_CHANGE0
945#pragma GCC poison SIG_PIN_CHANGE1
946#pragma GCC poison SIG_OUTPUT_COMPARE2
947#pragma GCC poison SIG_OVERFLOW2
948#pragma GCC poison SIG_INPUT_CAPTURE1
949#pragma GCC poison SIG_OUTPUT_COMPARE1A
950#pragma GCC poison SIG_OUTPUT_COMPARE1B
951#pragma GCC poison SIG_OVERFLOW1
952#pragma GCC poison SIG_OUTPUT_COMPARE0
953#pragma GCC poison SIG_OVERFLOW0
954#pragma GCC poison SIG_SPI
955#pragma GCC poison USART0_RX_vect
956#pragma GCC poison SIG_UART_RECV
957#pragma GCC poison USART0_UDRE_vect
958#pragma GCC poison SIG_UART_DATA
959#pragma GCC poison USART_TX_vect
960#pragma GCC poison SIG_UART_TRANS
961#pragma GCC poison SIG_USI_START
962#pragma GCC poison SIG_USI_OVERFLOW
963#pragma GCC poison SIG_COMPARATOR
964#pragma GCC poison SIG_ADC
965#pragma GCC poison SIG_EEPROM_READY
966#pragma GCC poison SIG_SPM_READY
967#pragma GCC poison SIG_PIN_CHANGE2
968#pragma GCC poison SIG_PIN_CHANGE3
969
970#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
971
972#define SLEEP_MODE_IDLE (0x00<<1)
973#define SLEEP_MODE_ADC (0x01<<1)
974#define SLEEP_MODE_PWR_DOWN (0x02<<1)
975#define SLEEP_MODE_PWR_SAVE (0x03<<1)
976#define SLEEP_MODE_STANDBY (0x06<<1)
977
978#endif /* _AVR_IOM6450_H_ */
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