source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom64hve.h @ 4837

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1/* Copyright (c) 2009 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iom64hve.h 2086 2009-12-15 03:24:16Z arcanum $ */
32
33/* avr/iom64hve.h - definitions for ATmega64HVE */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iom64hve.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_ATmega64HVE_H_
49#define _AVR_ATmega64HVE_H_ 1
50
51
52/* Registers and associated bit numbers. */
53
54#define PINA _SFR_IO8(0x00)
55#define PINA0 0
56#define PINA1 1
57
58#define DDRA _SFR_IO8(0x01)
59#define DDA0 0
60#define DDA1 1
61
62#define PORTA _SFR_IO8(0x02)
63#define PORTA0 0
64#define PORTA1 1
65
66#define PINB _SFR_IO8(0x03)
67#define PINB0 0
68#define PINB1 1
69#define PINB2 2
70#define PINB3 3
71#define PINB4 4
72#define PINB5 5
73#define PINB6 6
74#define PINB7 7
75
76#define DDRB _SFR_IO8(0x04)
77#define DDB0 0
78#define DDB1 1
79#define DDB2 2
80#define DDB3 3
81#define DDB4 4
82#define DDB5 5
83#define DDB6 6
84#define DDB7 7
85
86#define PORTB _SFR_IO8(0x05)
87#define PORTB0 0
88#define PORTB1 1
89#define PORTB2 2
90#define PORTB3 3
91#define PORTB4 4
92#define PORTB5 5
93#define PORTB6 6
94#define PORTB7 7
95
96#define TIFR0 _SFR_IO8(0x15)
97#define TOV0 0
98#define OCF0A 1
99#define OCF0B 2
100#define ICF0 3
101
102#define TIFR1 _SFR_IO8(0x16)
103#define TOV1 0
104#define OCF1A 1
105#define OCF1B 2
106#define ICF1 3
107
108#define PCIFR _SFR_IO8(0x1B)
109#define PCIF0 0
110#define PCIF1 1
111
112#define EIFR _SFR_IO8(0x1C)
113#define INTF0 0
114
115#define EIMSK _SFR_IO8(0x1D)
116#define INT0 0
117
118#define GPIOR0 _SFR_IO8(0x1E)
119#define GPIOR00 0
120#define GPIOR01 1
121#define GPIOR02 2
122#define GPIOR03 3
123#define GPIOR04 4
124#define GPIOR05 5
125#define GPIOR06 6
126#define GPIOR07 7
127
128#define EECR _SFR_IO8(0x1F)
129#define EERE 0
130#define EEPE 1
131#define EEMPE 2
132#define EERIE 3
133#define EEPM0 4
134#define EEPM1 5
135
136#define EEDR _SFR_IO8(0x20)
137#define EEDR0 0
138#define EEDR1 1
139#define EEDR2 2
140#define EEDR3 3
141#define EEDR4 4
142#define EEDR5 5
143#define EEDR6 6
144#define EEDR7 7
145
146#define EEAR _SFR_IO16(0x21)
147
148#define EEARL _SFR_IO8(0x21)
149#define EEAR0 0
150#define EEAR1 1
151#define EEAR2 2
152#define EEAR3 3
153#define EEAR4 4
154#define EEAR5 5
155#define EEAR6 6
156#define EEAR7 7
157
158#define EEARH _SFR_IO8(0x22)
159#define EEAR8 0
160#define EEAR9 1
161
162#define GTCCR _SFR_IO8(0x23)
163#define PSRSYNC 0
164#define TSM 7
165
166#define TCCR0A _SFR_IO8(0x24)
167#define WGM00 0
168#define ICS0 3
169#define ICES0 4
170#define ICNC0 5
171#define ICEN0 6
172#define TCW0 7
173
174#define TCCR0B _SFR_IO8(0x25)
175#define CS00 0
176#define CS01 1
177#define CS02 2
178
179#define TCNT0 _SFR_IO16(0x26)
180
181#define TCNT0L _SFR_IO8(0x26)
182#define TCNT0L0 0
183#define TCNT0L1 1
184#define TCNT0L2 2
185#define TCNT0L3 3
186#define TCNT0L4 4
187#define TCNT0L5 5
188#define TCNT0L6 6
189#define TCNT0L7 7
190
191#define TCNT0H _SFR_IO8(0x27)
192#define TCNT0H0 0
193#define TCNT0H1 1
194#define TCNT0H2 2
195#define TCNT0H3 3
196#define TCNT0H4 4
197#define TCNT0H5 5
198#define TCNT0H6 6
199#define TCNT0H7 7
200
201#define OCR0A _SFR_IO8(0x28)
202#define OCR0A0 0
203#define OCR0A1 1
204#define OCR0A2 2
205#define OCR0A3 3
206#define OCR0A4 4
207#define OCR0A5 5
208#define OCR0A6 6
209#define OCR0A7 7
210
211#define OCR0B _SFR_IO8(0x29)
212#define OCR0B0 0
213#define OCR0B1 1
214#define OCR0B2 2
215#define OCR0B3 3
216#define OCR0B4 4
217#define OCR0B5 5
218#define OCR0B6 6
219#define OCR0B7 7
220
221#define GPIOR1 _SFR_IO8(0x2A)
222#define GPIOR10 0
223#define GPIOR11 1
224#define GPIOR12 2
225#define GPIOR13 3
226#define GPIOR14 4
227#define GPIOR15 5
228#define GPIOR16 6
229#define GPIOR17 7
230
231#define GPIOR2 _SFR_IO8(0x2B)
232#define GPIOR20 0
233#define GPIOR21 1
234#define GPIOR22 2
235#define GPIOR23 3
236#define GPIOR24 4
237#define GPIOR25 5
238#define GPIOR26 6
239#define GPIOR27 7
240
241#define SPCR _SFR_IO8(0x2C)
242#define SPR0 0
243#define SPR1 1
244#define CPHA 2
245#define CPOL 3
246#define MSTR 4
247#define DORD 5
248#define SPE 6
249#define SPIE 7
250
251#define SPSR _SFR_IO8(0x2D)
252#define SPI2X 0
253#define WCOL 6
254#define SPIF 7
255
256#define SPDR _SFR_IO8(0x2E)
257#define SPDR0 0
258#define SPDR1 1
259#define SPDR2 2
260#define SPDR3 3
261#define SPDR4 4
262#define SPDR5 5
263#define SPDR6 6
264#define SPDR7 7
265
266#define TCCR0C _SFR_IO8(0x2F)
267
268#define OCDR _SFR_IO8(0x31)
269
270#define SMCR _SFR_IO8(0x33)
271#define SE 0
272#define SM0 1
273#define SM1 2
274#define SM2 3
275
276#define MCUSR _SFR_IO8(0x34)
277#define PORF 0
278#define EXTRF 1
279#define BODRF 2
280#define WDRF 3
281#define OCDRF 4
282
283#define MCUCR _SFR_IO8(0x35)
284#define IVCE 0
285#define IVSEL 1
286#define PUD 4
287#define CKOE 5
288
289#define SPMCSR _SFR_IO8(0x37)
290#define SPMEN 0
291#define PGERS 1
292#define PGWRT 2
293#define LBSET 3
294#define RWWSRE 4
295#define SIGRD 5
296#define RWWSB 6
297#define SPMIE 7
298
299#define WDTCSR _SFR_MEM8(0x60)
300#define WDP0 0
301#define WDP1 1
302#define WDP2 2
303#define WDE 3
304#define WDCE 4
305#define WDP3 5
306#define WDIE 6
307#define WDIF 7
308
309#define CLKPR _SFR_MEM8(0x61)
310#define CLKPS0 0
311#define CLKPS1 1
312#define CLKPCE 7
313
314#define WUTCSR _SFR_MEM8(0x62)
315#define WUTP0 0
316#define WUTP1 1
317#define WUTP2 2
318#define WUTE 3
319#define WUTR 4
320#define WUTIE 6
321#define WUTIF 7
322
323#define WDTCLR _SFR_MEM8(0x63)
324#define WDCLE 0
325#define WDCL0 1
326#define WDCL1 2
327
328#define PRR0 _SFR_MEM8(0x64)
329#define PRTIM0 0
330#define PRTIM1 1
331#define PRSPI 2
332#define PRLIN 3
333
334#define __AVR_HAVE_PRR0 ((1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN))
335#define __AVR_HAVE_PRR0_PRTIM0
336#define __AVR_HAVE_PRR0_PRTIM1
337#define __AVR_HAVE_PRR0_PRSPI
338#define __AVR_HAVE_PRR0_PRLIN
339
340#define SOSCCALA _SFR_MEM8(0x66)
341#define SCALA0 0
342#define SCALA1 1
343#define SCALA2 2
344#define SCALA3 3
345#define SCALA4 4
346#define SCALA5 5
347#define SCALA6 6
348#define SCALA7 7
349
350#define SOSCCALB _SFR_MEM8(0x67)
351#define SCALB0 0
352#define SCALB1 1
353#define SCALB2 2
354#define SCALB3 3
355#define SCALB4 4
356#define SCALB5 5
357#define SCALB6 6
358#define SCALB7 7
359
360#define PCICR _SFR_MEM8(0x68)
361#define PCIE0 0
362#define PCIE1 1
363
364#define EICRA _SFR_MEM8(0x69)
365#define ISC00 0
366#define ISC01 1
367
368#define PCMSK0 _SFR_MEM8(0x6B)
369#define PCINT0 0
370#define PCINT1 1
371
372#define PCMSK1 _SFR_MEM8(0x6C)
373#define PCINT2 0
374#define PCINT3 1
375#define PCINT4 2
376#define PCINT5 3
377#define PCINT6 4
378#define PCINT7 5
379#define PCINT8 6
380#define PCINT9 7
381
382#define TIMSK0 _SFR_MEM8(0x6E)
383#define TOIE0 0
384#define OCIE0A 1
385#define OCIE0B 2
386#define ICIE0 3
387
388#define TIMSK1 _SFR_MEM8(0x6F)
389#define TOIE1 0
390#define OCIE1A 1
391#define OCIE1B 2
392#define ICIE1 3
393
394#define DIDR0 _SFR_MEM8(0x7E)
395#define PA0DID 0
396#define PA1DID 1
397
398#define TCCR1A _SFR_MEM8(0x80)
399#define WGM10 0
400#define ICS1 3
401#define ICES1 4
402#define ICNC1 5
403#define ICEN1 6
404#define TCW1 7
405
406#define TCCR1B _SFR_MEM8(0x81)
407#define CS10 0
408#define CS11 1
409#define CS12 2
410
411#define TCCR1C _SFR_MEM8(0x82)
412
413#define TCNT1 _SFR_MEM16(0x84)
414
415#define TCNT1L _SFR_MEM8(0x84)
416#define TCNT1L0 0
417#define TCNT1L1 1
418#define TCNT1L2 2
419#define TCNT1L3 3
420#define TCNT1L4 4
421#define TCNT1L5 5
422#define TCNT1L6 6
423#define TCNT1L7 7
424
425#define TCNT1H _SFR_MEM8(0x85)
426#define TCNT1H0 0
427#define TCNT1H1 1
428#define TCNT1H2 2
429#define TCNT1H3 3
430#define TCNT1H4 4
431#define TCNT1H5 5
432#define TCNT1H6 6
433#define TCNT1H7 7
434
435#define OCR1A _SFR_MEM8(0x88)
436#define OCR1A0 0
437#define OCR1A1 1
438#define OCR1A2 2
439#define OCR1A3 3
440#define OCR1A4 4
441#define OCR1A5 5
442#define OCR1A6 6
443#define OCR1A7 7
444
445#define OCR1B _SFR_MEM8(0x89)
446#define OCR1B0 0
447#define OCR1B1 1
448#define OCR1B2 2
449#define OCR1B3 3
450#define OCR1B4 4
451#define OCR1B5 5
452#define OCR1B6 6
453#define OCR1B7 7
454
455#define LINCR _SFR_MEM8(0xC0)
456#define LCMD0 0
457#define LCMD1 1
458#define LCMD2 2
459#define LENA 3
460#define LCONF0 4
461#define LCONF1 5
462#define LIN13 6
463#define LSWRES 7
464
465#define LINSIR _SFR_MEM8(0xC1)
466#define LRXOK 0
467#define LTXOK 1
468#define LIDOK 2
469#define LERR 3
470#define LBUSY 4
471#define LIDST0 5
472#define LIDST1 6
473#define LIDST2 7
474
475#define LINENIR _SFR_MEM8(0xC2)
476#define LENRXOK 0
477#define LENTXOK 1
478#define LENIDOK 2
479#define LENERR 3
480
481#define LINERR _SFR_MEM8(0xC3)
482#define LBERR 0
483#define LCERR 1
484#define LPERR 2
485#define LSERR 3
486#define LFERR 4
487#define LOVERR 5
488#define LTOERR 6
489#define LABORT 7
490
491#define LINBTR _SFR_MEM8(0xC4)
492#define LBT0 0
493#define LBT1 1
494#define LBT2 2
495#define LBT3 3
496#define LBT4 4
497#define LBT5 5
498#define LDISR 7
499
500#define LINBRR _SFR_MEM16(0xC5)
501
502#define LINBRRL _SFR_MEM8(0xC5)
503#define LDIV0 0
504#define LDIV1 1
505#define LDIV2 2
506#define LDIV3 3
507#define LDIV4 4
508#define LDIV5 5
509#define LDIV6 6
510#define LDIV7 7
511
512#define LINBRRH _SFR_MEM8(0xC6)
513#define LDIV8 0
514#define LDIV9 1
515#define LDIV10 2
516#define LDIV11 3
517
518#define LINDLR _SFR_MEM8(0xC7)
519#define LRXDL0 0
520#define LRXDL1 1
521#define LRXDL2 2
522#define LRXDL3 3
523#define LTXDL0 4
524#define LTXDL1 5
525#define LTXDL2 6
526#define LTXDL3 7
527
528#define LINIDR _SFR_MEM8(0xC8)
529#define LID0 0
530#define LID1 1
531#define LID2 2
532#define LID3 3
533#define LID4 4
534#define LID5 5
535#define LP0 6
536#define LP1 7
537
538#define LINSEL _SFR_MEM8(0xC9)
539#define LINDX0 0
540#define LINDX1 1
541#define LINDX2 2
542#define LAINC 3
543
544#define LINDAT _SFR_MEM8(0xCA)
545#define LDATA0 0
546#define LDATA1 1
547#define LDATA2 2
548#define LDATA3 3
549#define LDATA4 4
550#define LDATA5 5
551#define LDATA6 6
552#define LDATA7 7
553
554#define BGCSRA _SFR_MEM8(0xD1)
555#define BGSC0 0
556#define BGSC1 1
557#define BGSC2 2
558
559#define BGCRB _SFR_MEM8(0xD2)
560#define BGCL0 0
561#define BGCL1 1
562#define BGCL2 2
563#define BGCL3 3
564#define BGCL4 4
565#define BGCL5 5
566#define BGCL6 6
567#define BGCL7 7
568
569#define BGCRA _SFR_MEM8(0xD3)
570#define BGCN0 0
571#define BGCN1 1
572#define BGCN2 2
573#define BGCN3 3
574#define BGCN4 4
575#define BGCN5 5
576#define BGCN6 6
577#define BGCN7 7
578
579#define BGLR _SFR_MEM8(0xD4)
580#define BGPL 0
581#define BGPLE 1
582
583#define PLLCSR _SFR_MEM8(0xD8)
584#define PLLCIE 0
585#define PLLCIF 1
586#define LOCK 4
587#define SWEN 5
588
589#define PBOV _SFR_MEM8(0xDC)
590#define PBOE0 0
591#define PBOE3 3
592#define PBOVCE 7
593
594#define ADSCSRA _SFR_MEM8(0xE0)
595#define SCMD0 0
596#define SCMD1 1
597#define SBSY 2
598
599#define ADSCSRB _SFR_MEM8(0xE1)
600#define CADICRB 0
601#define CADACRB 1
602#define CADICPS 2
603#define VADICRB 4
604#define VADACRB 5
605#define VADICPS 6
606
607#define ADCRA _SFR_MEM8(0xE2)
608#define CKSEL 0
609#define ADCMS0 1
610#define ADCMS1 2
611#define ADPSEL 3
612
613#define ADCRB _SFR_MEM8(0xE3)
614#define ADADES0 0
615#define ADADES1 1
616#define ADADES2 2
617#define ADIDES0 3
618#define ADIDES1 4
619
620#define ADCRC _SFR_MEM8(0xE4)
621#define CADRCT0 0
622#define CADRCT1 1
623#define CADRCT2 2
624#define CADRCT3 3
625#define CADRCM0 4
626#define CADRCM1 5
627#define CADEN 7
628
629#define ADCRD _SFR_MEM8(0xE5)
630#define CADDSEL 0
631#define CADPDM0 1
632#define CADPDM1 2
633#define CADG0 3
634#define CADG1 4
635#define CADG2 5
636
637#define ADCRE _SFR_MEM8(0xE6)
638#define VADMUX0 0
639#define VADMUX1 1
640#define VADMUX2 2
641#define VADPDM0 3
642#define VADPDM1 4
643#define VADREFS 5
644#define VADEN 7
645
646#define ADIFR _SFR_MEM8(0xE7)
647#define CADICIF 0
648#define CADACIF 1
649#define CADRCIF 2
650#define VADICIF 4
651#define VADACIF 5
652
653#define ADIMR _SFR_MEM8(0xE8)
654#define CADICIE 0
655#define CADACIE 1
656#define CADRCIE 2
657#define VADICIE 4
658#define VADACIE 5
659
660#define CADRCL _SFR_MEM16(0xE9)
661
662#define CADRCLL _SFR_MEM8(0xE9)
663#define CADRCL0 0
664#define CADRCL1 1
665#define CADRCL2 2
666#define CADRCL3 3
667#define CADRCL4 4
668#define CADRCL5 5
669#define CADRCL6 6
670#define CADRCL7 7
671
672#define CADRCLH _SFR_MEM8(0xEA)
673#define CADRCL8 0
674#define CADRCL9 1
675#define CADRCL10 2
676#define CADRCL11 3
677#define CADRCL12 4
678#define CADRCL13 5
679#define CADRCL14 6
680#define CADRCL15 7
681
682#define CADIC _SFR_MEM16(0xEB)
683
684#define CADICL _SFR_MEM8(0xEB)
685#define CADIC0 0
686#define CADIC1 1
687#define CADIC2 2
688#define CADIC3 3
689#define CADIC4 4
690#define CADIC5 5
691#define CADIC6 6
692#define CADIC7 7
693
694#define CADICH _SFR_MEM8(0xEC)
695#define CADIC8 0
696#define CADIC9 1
697#define CADIC10 2
698#define CADIC11 3
699#define CADIC12 4
700#define CADIC13 5
701#define CADIC14 6
702#define CADIC15 7
703
704#define CADAC0 _SFR_MEM8(0xED)
705#define CADAC00 0
706#define CADAC01 1
707#define CADAC02 2
708#define CADAC03 3
709#define CADAC04 4
710#define CADAC05 5
711#define CADAC06 6
712#define CADAC07 7
713
714#define CADAC1 _SFR_MEM8(0xEE)
715#define CADAC08 0
716#define CADAC09 1
717#define CADAC10 2
718#define CADAC11 3
719#define CADAC12 4
720#define CADAC13 5
721#define CADAC14 6
722#define CADAC15 7
723
724#define CADAC2 _SFR_MEM8(0xEF)
725#define CADAC16 0
726#define CADAC17 1
727#define CADAC18 2
728#define CADAC19 3
729#define CADAC20 4
730#define CADAC21 5
731#define CADAC22 6
732#define CADAC23 7
733
734#define CADAC3 _SFR_MEM8(0xF0)
735#define CADAC24 0
736#define CADAC25 1
737#define CADAC26 2
738#define CADAC27 3
739#define CADAC28 4
740#define CADAC29 5
741#define CADAC30 6
742#define CADAC31 7
743
744#define VADIC _SFR_MEM16(0xF1)
745
746#define VADICL _SFR_MEM8(0xF1)
747#define VADIC0 0
748#define VADIC1 1
749#define VADIC2 2
750#define VADIC3 3
751#define VADIC4 4
752#define VADIC5 5
753#define VADIC6 6
754#define VADIC7 7
755
756#define VADICH _SFR_MEM8(0xF2)
757#define VADIC8 0
758#define VADIC9 1
759#define VADIC10 2
760#define VADIC11 3
761#define VADIC12 4
762#define VADIC13 5
763#define VADIC14 6
764#define VADIC15 7
765
766#define VADAC0 _SFR_MEM8(0xF3)
767#define VADAC00 0
768#define VADAC01 1
769#define VADAC02 2
770#define VADAC03 3
771#define VADAC04 4
772#define VADAC05 5
773#define VADAC06 6
774#define VADAC07 7
775
776#define VADAC1 _SFR_MEM8(0xF4)
777#define VADAC08 0
778#define VADAC09 1
779#define VADAC10 2
780#define VADAC11 3
781#define VADAC12 4
782#define VADAC13 5
783#define VADAC14 6
784#define VADAC15 7
785
786#define VADAC2 _SFR_MEM8(0xF5)
787#define VADAC16 0
788#define VADAC17 1
789#define VADAC18 2
790#define VADAC19 3
791#define VADAC20 4
792#define VADAC21 5
793#define VADAC22 6
794#define VADAC23 7
795
796#define VADAC3 _SFR_MEM8(0xF6)
797#define VADAC24 0
798#define VADAC25 1
799#define VADAC26 2
800#define VADAC27 3
801#define VADAC28 4
802#define VADAC29 5
803#define VADAC30 6
804#define VADAC31 7
805
806
807/* Interrupt vectors */
808/* Vector 0 is the reset vector */
809#define INT0_vect_num  1
810#define INT0_vect      _VECTOR(1)  /* External Interrupt 0 */
811#define PCINT0_vect_num  2
812#define PCINT0_vect      _VECTOR(2)  /* Pin Change Interrupt 0 */
813#define PCINT1_vect_num  3
814#define PCINT1_vect      _VECTOR(3)  /* Pin Change Interrupt 1 */
815#define WDT_vect_num  4
816#define WDT_vect      _VECTOR(4)  /* Watchdog Timeout Interrupt */
817#define WAKEUP_vect_num  5
818#define WAKEUP_vect      _VECTOR(5)  /* Wakeup Timer Overflow */
819#define TIMER1_IC_vect_num  6
820#define TIMER1_IC_vect      _VECTOR(6)  /* Timer 1 Input capture */
821#define TIMER1_COMPA_vect_num  7
822#define TIMER1_COMPA_vect      _VECTOR(7)  /* Timer 1 Compare Match A */
823#define TIMER1_COMPB_vect_num  8
824#define TIMER1_COMPB_vect      _VECTOR(8)  /* Timer 1 Compare Match B */
825#define TIMER1_OVF_vect_num  9
826#define TIMER1_OVF_vect      _VECTOR(9)  /* Timer 1 overflow */
827#define TIMER0_IC_vect_num  10
828#define TIMER0_IC_vect      _VECTOR(10)  /* Timer 0 Input Capture */
829#define TIMER0_COMPA_vect_num  11
830#define TIMER0_COMPA_vect      _VECTOR(11)  /* Timer 0 Comapre Match A */
831#define TIMER0_COMPB_vect_num  12
832#define TIMER0_COMPB_vect      _VECTOR(12)  /* Timer 0 Compare Match B */
833#define TIMER0_OVF_vect_num  13
834#define TIMER0_OVF_vect      _VECTOR(13)  /* Timer 0 Overflow */
835#define LIN_STATUS_vect_num  14
836#define LIN_STATUS_vect      _VECTOR(14)  /* LIN Status Interrupt */
837#define LIN_ERROR_vect_num  15
838#define LIN_ERROR_vect      _VECTOR(15)  /* LIN Error Interrupt */
839#define SPI_STC_vect_num  16
840#define SPI_STC_vect      _VECTOR(16)  /* SPI Serial transfer complete */
841#define VADC_CONV_vect_num  17
842#define VADC_CONV_vect      _VECTOR(17)  /* Voltage ADC Instantaneous Conversion Complete */
843#define VADC_ACC_vect_num  18
844#define VADC_ACC_vect      _VECTOR(18)  /* Voltage ADC Accumulated Conversion Complete */
845#define CADC_CONV_vect_num  19
846#define CADC_CONV_vect      _VECTOR(19)  /* C-ADC Instantaneous Conversion Complete */
847#define CADC_REG_CUR_vect_num  20
848#define CADC_REG_CUR_vect      _VECTOR(20)  /* C-ADC Regular Current */
849#define CADC_ACC_vect_num  21
850#define CADC_ACC_vect      _VECTOR(21)  /* C-ADC Accumulated Conversion Complete */
851#define EE_READY_vect_num  22
852#define EE_READY_vect      _VECTOR(22)  /* EEPROM Ready */
853#define SPM_vect_num  23
854#define SPM_vect      _VECTOR(23)  /* SPM Ready */
855#define PLL_vect_num  24
856#define PLL_vect      _VECTOR(24)  /* PLL Lock Change Interrupt */
857
858#define _VECTOR_SIZE 4 /* Size of individual vector. */
859#define _VECTORS_SIZE (25 * _VECTOR_SIZE)
860
861
862/* Constants */
863#define SPM_PAGESIZE (128)
864#define RAMSTART     (0x100)
865#define RAMSIZE      (4096)
866#define RAMEND       (RAMSTART + RAMSIZE - 1)
867#define XRAMSTART    (NA)
868#define XRAMSIZE     (NA)
869#define XRAMEND      (RAMEND)
870#define E2END        (0x3FF)
871#define E2PAGESIZE   (4)
872#define FLASHEND     (0xFFFF)
873
874
875/* Fuses */
876#define FUSE_MEMORY_SIZE 2
877
878/* Low Fuse Byte */
879#define FUSE_OSCSEL0  (unsigned char)~_BV(0)  /* Oscillator Select */
880#define FUSE_SUT0  (unsigned char)~_BV(1)  /* Select start-up time */
881#define FUSE_SUT1  (unsigned char)~_BV(2)  /* Select start-up time */
882#define FUSE_CKDIV8  (unsigned char)~_BV(3)  /* Divide clock by 8 */
883#define FUSE_BODEN  (unsigned char)~_BV(4)  /* Enable BOD */
884#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
885#define FUSE_EESAVE  (unsigned char)~_BV(6)  /* EEPROM memory is preserved through chip erase */
886#define FUSE_WDTON  (unsigned char)~_BV(7)  /* Watchdog Timer Always On */
887#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_CKDIV8 & FUSE_OSCSEL0)
888
889/* High Fuse Byte */
890#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
891#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
892#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
893#define FUSE_DWEN  (unsigned char)~_BV(3)  /* Enable debugWire */
894#define HFUSE_DEFAULT (FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
895
896
897/* Lock Bits */
898#define __LOCK_BITS_EXIST
899#define __BOOT_LOCK_BITS_0_EXIST
900#define __BOOT_LOCK_BITS_1_EXIST
901
902
903/* Signature */
904#define SIGNATURE_0 0x1E
905#define SIGNATURE_1 0x96
906#define SIGNATURE_2 0x10
907
908
909/* Device Pin Definitions */
910#define PV2_DDR   DDRV
911#define PV2_PORT  PORTV
912#define PV2_PIN   PINV
913#define PV2_BIT   2
914
915#define PV1_DDR   DDRV
916#define PV1_PORT  PORTV
917#define PV1_PIN   PINV
918#define PV1_BIT   1
919
920#define NV_DDR   DDRNV
921#define NV_PORT  PORTNV
922#define NV_PIN   PINNV
923#define NV_BIT   NV
924
925#define VFET_DDR   DDRVFET
926#define VFET_PORT  PORTVFET
927#define VFET_PIN   PINVFET
928#define VFET_BIT   VFET
929
930#define CF1P_DDR   DDRCF1P
931#define CF1P_PORT  PORTCF1P
932#define CF1P_PIN   PINCF1P
933#define CF1P_BIT   CF1P
934
935#define CF1N_DDR   DDRCF1N
936#define CF1N_PORT  PORTCF1N
937#define CF1N_PIN   PINCF1N
938#define CF1N_BIT   CF1N
939
940#define CF2P_DDR   DDRCF2P
941#define CF2P_PORT  PORTCF2P
942#define CF2P_PIN   PINCF2P
943#define CF2P_BIT   CF2P
944
945#define CF2N_DDR   DDRCF2N
946#define CF2N_PORT  PORTCF2N
947#define CF2N_PIN   PINCF2N
948#define CF2N_BIT   CF2N
949
950#define VREG_DDR   DDRVREG
951#define VREG_PORT  PORTVREG
952#define VREG_PIN   PINVREG
953#define VREG_BIT   VREG
954
955#define VREF_DDR   DDRVREF
956#define VREF_PORT  PORTVREF
957#define VREF_PIN   PINVREF
958#define VREF_BIT   VREF
959
960#define VREFGND_DDR   DDRVREFGND
961#define VREFGND_PORT  PORTVREFGND
962#define VREFGND_PIN   PINVREFGND
963#define VREFGND_BIT   VREFGND
964
965#define PI_DDR   DDRI
966#define PI_PORT  PORTI
967#define PI_PIN   PINI
968#define PI_BIT   
969
970#define NI_DDR   DDRNI
971#define NI_PORT  PORTNI
972#define NI_PIN   PINNI
973#define NI_BIT   NI
974
975#define PA0_DDR   DDRA
976#define PA0_PORT  PORTA
977#define PA0_PIN   PINA
978#define PA0_BIT   0
979
980#define PA1_DDR   DDRA
981#define PA1_PORT  PORTA
982#define PA1_PIN   PINA
983#define PA1_BIT   1
984
985#define PA2_DDR   DDRA
986#define PA2_PORT  PORTA
987#define PA2_PIN   PINA
988#define PA2_BIT   2
989
990#define PB0_DDR   DDRB
991#define PB0_PORT  PORTB
992#define PB0_PIN   PINB
993#define PB0_BIT   0
994
995#define PB1_DDR   DDRB
996#define PB1_PORT  PORTB
997#define PB1_PIN   PINB
998#define PB1_BIT   1
999
1000#define PB2_DDR   DDRB
1001#define PB2_PORT  PORTB
1002#define PB2_PIN   PINB
1003#define PB2_BIT   2
1004
1005#define PB3_DDR   DDRB
1006#define PB3_PORT  PORTB
1007#define PB3_PIN   PINB
1008#define PB3_BIT   3
1009
1010#define PC0_DDR   DDRC
1011#define PC0_PORT  PORTC
1012#define PC0_PIN   PINC
1013#define PC0_BIT   0
1014
1015#define BATT_DDR   DDRBATT
1016#define BATT_PORT  PORTBATT
1017#define BATT_PIN   PINBATT
1018#define BATT_BIT   BATT
1019
1020#define OC_DDR   DDROC
1021#define OC_PORT  PORTOC
1022#define OC_PIN   PINOC
1023#define OC_BIT   OC
1024
1025
1026#define SLEEP_MODE_IDLE (0x00<<1)
1027#define SLEEP_MODE_ADC (0x01<<1)
1028#define SLEEP_MODE_PWR_DOWN (0x02<<1)
1029#define SLEEP_MODE_PWR_SAVE (0x03<<1)
1030#define SLEEP_MODE_STANDBY (0x06<<1)
1031#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
1032
1033#endif /* _AVR_ATmega64HVE_H_ */
1034
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