source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom88pa.h @ 4837

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1/* Copyright (c) 2009 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iom88pa.h 2035 2009-11-02 02:44:17Z arcanum $ */
32
33/* avr/iom88pa.h - definitions for ATmega88PA */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iom88pa.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_ATmega88PA_H_
49#define _AVR_ATmega88PA_H_ 1
50
51
52/* Registers and associated bit numbers. */
53
54#define PINB _SFR_IO8(0x03)
55#define PINB0 0
56#define PINB1 1
57#define PINB2 2
58#define PINB3 3
59#define PINB4 4
60#define PINB5 5
61#define PINB6 6
62#define PINB7 7
63
64#define DDRB _SFR_IO8(0x04)
65#define DDB0 0
66#define DDB1 1
67#define DDB2 2
68#define DDB3 3
69#define DDB4 4
70#define DDB5 5
71#define DDB6 6
72#define DDB7 7
73
74#define PORTB _SFR_IO8(0x05)
75#define PORTB0 0
76#define PORTB1 1
77#define PORTB2 2
78#define PORTB3 3
79#define PORTB4 4
80#define PORTB5 5
81#define PORTB6 6
82#define PORTB7 7
83
84#define PINC _SFR_IO8(0x06)
85#define PINC0 0
86#define PINC1 1
87#define PINC2 2
88#define PINC3 3
89#define PINC4 4
90#define PINC5 5
91#define PINC6 6
92
93#define DDRC _SFR_IO8(0x07)
94#define DDC0 0
95#define DDC1 1
96#define DDC2 2
97#define DDC3 3
98#define DDC4 4
99#define DDC5 5
100#define DDC6 6
101
102#define PORTC _SFR_IO8(0x08)
103#define PORTC0 0
104#define PORTC1 1
105#define PORTC2 2
106#define PORTC3 3
107#define PORTC4 4
108#define PORTC5 5
109#define PORTC6 6
110
111#define PIND _SFR_IO8(0x09)
112#define PIND0 0
113#define PIND1 1
114#define PIND2 2
115#define PIND3 3
116#define PIND4 4
117#define PIND5 5
118#define PIND6 6
119#define PIND7 7
120
121#define DDRD _SFR_IO8(0x0A)
122#define DDD0 0
123#define DDD1 1
124#define DDD2 2
125#define DDD3 3
126#define DDD4 4
127#define DDD5 5
128#define DDD6 6
129#define DDD7 7
130
131#define PORTD _SFR_IO8(0x0B)
132#define PORTD0 0
133#define PORTD1 1
134#define PORTD2 2
135#define PORTD3 3
136#define PORTD4 4
137#define PORTD5 5
138#define PORTD6 6
139#define PORTD7 7
140
141#define TIFR0 _SFR_IO8(0x15)
142#define TOV0 0
143#define OCF0A 1
144#define OCF0B 2
145
146#define TIFR1 _SFR_IO8(0x16)
147#define TOV1 0
148#define OCF1A 1
149#define OCF1B 2
150#define ICF1 5
151
152#define TIFR2 _SFR_IO8(0x17)
153#define TOV2 0
154#define OCF2A 1
155#define OCF2B 2
156
157#define PCIFR _SFR_IO8(0x1B)
158#define PCIF0 0
159#define PCIF1 1
160#define PCIF2 2
161
162#define EIFR _SFR_IO8(0x1C)
163#define INTF0 0
164#define INTF1 1
165
166#define EIMSK _SFR_IO8(0x1D)
167#define INT0 0
168#define INT1 1
169
170#define GPIOR0 _SFR_IO8(0x1E)
171#define GPIOR00 0
172#define GPIOR01 1
173#define GPIOR02 2
174#define GPIOR03 3
175#define GPIOR04 4
176#define GPIOR05 5
177#define GPIOR06 6
178#define GPIOR07 7
179
180#define EECR _SFR_IO8(0x1F)
181#define EERE 0
182#define EEPE 1
183#define EEMPE 2
184#define EERIE 3
185#define EEPM0 4
186#define EEPM1 5
187
188#define EEDR _SFR_IO8(0x20)
189#define EEDR0 0
190#define EEDR1 1
191#define EEDR2 2
192#define EEDR3 3
193#define EEDR4 4
194#define EEDR5 5
195#define EEDR6 6
196#define EEDR7 7
197
198#define EEAR _SFR_IO16(0x21)
199
200#define EEARL _SFR_IO8(0x21)
201#define EEAR0 0
202#define EEAR1 1
203#define EEAR2 2
204#define EEAR3 3
205#define EEAR4 4
206#define EEAR5 5
207#define EEAR6 6
208#define EEAR7 7
209
210#define EEARH _SFR_IO8(0x22)
211#define EEAR8 0
212
213#define GTCCR _SFR_IO8(0x23)
214#define PSRSYNC 0
215#define PSRASY 1
216#define TSM 7
217
218#define TCCR0A _SFR_IO8(0x24)
219#define WGM00 0
220#define WGM01 1
221#define COM0B0 4
222#define COM0B1 5
223#define COM0A0 6
224#define COM0A1 7
225
226#define TCCR0B _SFR_IO8(0x25)
227#define CS00 0
228#define CS01 1
229#define CS02 2
230#define WGM02 3
231#define FOC0B 6
232#define FOC0A 7
233
234#define TCNT0 _SFR_IO8(0x26)
235#define TCNT0_0 0
236#define TCNT0_1 1
237#define TCNT0_2 2
238#define TCNT0_3 3
239#define TCNT0_4 4
240#define TCNT0_5 5
241#define TCNT0_6 6
242#define TCNT0_7 7
243
244#define OCR0A _SFR_IO8(0x27)
245#define OCR0A_0 0
246#define OCR0A_1 1
247#define OCR0A_2 2
248#define OCR0A_3 3
249#define OCR0A_4 4
250#define OCR0A_5 5
251#define OCR0A_6 6
252#define OCR0A_7 7
253
254#define OCR0B _SFR_IO8(0x28)
255#define OCR0B_0 0
256#define OCR0B_1 1
257#define OCR0B_2 2
258#define OCR0B_3 3
259#define OCR0B_4 4
260#define OCR0B_5 5
261#define OCR0B_6 6
262#define OCR0B_7 7
263
264#define GPIOR1 _SFR_IO8(0x2A)
265#define GPIOR10 0
266#define GPIOR11 1
267#define GPIOR12 2
268#define GPIOR13 3
269#define GPIOR14 4
270#define GPIOR15 5
271#define GPIOR16 6
272#define GPIOR17 7
273
274#define GPIOR2 _SFR_IO8(0x2B)
275#define GPIOR20 0
276#define GPIOR21 1
277#define GPIOR22 2
278#define GPIOR23 3
279#define GPIOR24 4
280#define GPIOR25 5
281#define GPIOR26 6
282#define GPIOR27 7
283
284#define SPCR _SFR_IO8(0x2C)
285#define SPR0 0
286#define SPR1 1
287#define CPHA 2
288#define CPOL 3
289#define MSTR 4
290#define DORD 5
291#define SPE 6
292#define SPIE 7
293
294#define SPSR _SFR_IO8(0x2D)
295#define SPI2X 0
296#define WCOL 6
297#define SPIF 7
298
299#define SPDR _SFR_IO8(0x2E)
300#define SPDR0 0
301#define SPDR1 1
302#define SPDR2 2
303#define SPDR3 3
304#define SPDR4 4
305#define SPDR5 5
306#define SPDR6 6
307#define SPDR7 7
308
309#define ACSR _SFR_IO8(0x30)
310#define ACIS0 0
311#define ACIS1 1
312#define ACIC 2
313#define ACIE 3
314#define ACI 4
315#define ACO 5
316#define ACBG 6
317#define ACD 7
318
319#define SMCR _SFR_IO8(0x33)
320#define SE 0
321#define SM0 1
322#define SM1 2
323#define SM2 3
324
325#define MCUSR _SFR_IO8(0x34)
326#define PORF 0
327#define EXTRF 1
328#define BORF 2
329#define WDRF 3
330
331#define MCUCR _SFR_IO8(0x35)
332#define IVCE 0
333#define IVSEL 1
334#define PUD 4
335#define BODSE 5
336#define BODS 6
337
338#define SPMCSR _SFR_IO8(0x37)
339#define SELFPRGEN 0
340#define SPMEN 0
341#define PGERS 1
342#define PGWRT 2
343#define BLBSET 3
344#define RWWSRE 4
345#define SIGRD 5
346#define RWWSB 6
347#define SPMIE 7
348
349#define WDTCSR _SFR_MEM8(0x60)
350#define WDP0 0
351#define WDP1 1
352#define WDP2 2
353#define WDE 3
354#define WDCE 4
355#define WDP3 5
356#define WDIE 6
357#define WDIF 7
358
359#define CLKPR _SFR_MEM8(0x61)
360#define CLKPS0 0
361#define CLKPS1 1
362#define CLKPS2 2
363#define CLKPS3 3
364#define CLKPCE 7
365
366#define PRR _SFR_MEM8(0x64)
367#define PRADC 0
368#define PRUSART0 1
369#define PRSPI 2
370#define PRTIM1 3
371#define PRTIM0 5
372#define PRTIM2 6
373#define PRTWI 7
374
375#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
376#define __AVR_HAVE_PRR_PRADC
377#define __AVR_HAVE_PRR_PRUSART0
378#define __AVR_HAVE_PRR_PRSPI
379#define __AVR_HAVE_PRR_PRTIM1
380#define __AVR_HAVE_PRR_PRTIM0
381#define __AVR_HAVE_PRR_PRTIM2
382#define __AVR_HAVE_PRR_PRTWI
383
384#define OSCCAL _SFR_MEM8(0x66)
385#define CAL0 0
386#define CAL1 1
387#define CAL2 2
388#define CAL3 3
389#define CAL4 4
390#define CAL5 5
391#define CAL6 6
392#define CAL7 7
393
394#define PCICR _SFR_MEM8(0x68)
395#define PCIE0 0
396#define PCIE1 1
397#define PCIE2 2
398
399#define EICRA _SFR_MEM8(0x69)
400#define ISC00 0
401#define ISC01 1
402#define ISC10 2
403#define ISC11 3
404
405#define PCMSK0 _SFR_MEM8(0x6B)
406#define PCINT0 0
407#define PCINT1 1
408#define PCINT2 2
409#define PCINT3 3
410#define PCINT4 4
411#define PCINT5 5
412#define PCINT6 6
413#define PCINT7 7
414
415#define PCMSK1 _SFR_MEM8(0x6C)
416#define PCINT8 0
417#define PCINT9 1
418#define PCINT10 2
419#define PCINT11 3
420#define PCINT12 4
421#define PCINT13 5
422#define PCINT14 6
423
424#define PCMSK2 _SFR_MEM8(0x6D)
425#define PCINT16 0
426#define PCINT17 1
427#define PCINT18 2
428#define PCINT19 3
429#define PCINT20 4
430#define PCINT21 5
431#define PCINT22 6
432#define PCINT23 7
433
434#define TIMSK0 _SFR_MEM8(0x6E)
435#define TOIE0 0
436#define OCIE0A 1
437#define OCIE0B 2
438
439#define TIMSK1 _SFR_MEM8(0x6F)
440#define TOIE1 0
441#define OCIE1A 1
442#define OCIE1B 2
443#define ICIE1 5
444
445#define TIMSK2 _SFR_MEM8(0x70)
446#define TOIE2 0
447#define OCIE2A 1
448#define OCIE2B 2
449
450#ifndef __ASSEMBLER__
451#define ADC _SFR_MEM16(0x78)
452#endif
453#define ADCW _SFR_MEM16(0x78)
454
455#define ADCL _SFR_MEM8(0x78)
456#define ADCL0 0
457#define ADCL1 1
458#define ADCL2 2
459#define ADCL3 3
460#define ADCL4 4
461#define ADCL5 5
462#define ADCL6 6
463#define ADCL7 7
464
465#define ADCH _SFR_MEM8(0x79)
466#define ADCH0 0
467#define ADCH1 1
468#define ADCH2 2
469#define ADCH3 3
470#define ADCH4 4
471#define ADCH5 5
472#define ADCH6 6
473#define ADCH7 7
474
475#define ADCSRA _SFR_MEM8(0x7A)
476#define ADPS0 0
477#define ADPS1 1
478#define ADPS2 2
479#define ADIE 3
480#define ADIF 4
481#define ADATE 5
482#define ADSC 6
483#define ADEN 7
484
485#define ADCSRB _SFR_MEM8(0x7B)
486#define ADTS0 0
487#define ADTS1 1
488#define ADTS2 2
489#define ACME 6
490
491#define ADMUX _SFR_MEM8(0x7C)
492#define MUX0 0
493#define MUX1 1
494#define MUX2 2
495#define MUX3 3
496#define ADLAR 5
497#define REFS0 6
498#define REFS1 7
499
500#define DIDR0 _SFR_MEM8(0x7E)
501#define ADC0D 0
502#define ADC1D 1
503#define ADC2D 2
504#define ADC3D 3
505#define ADC4D 4
506#define ADC5D 5
507
508#define DIDR1 _SFR_MEM8(0x7F)
509#define AIN0D 0
510#define AIN1D 1
511
512#define TCCR1A _SFR_MEM8(0x80)
513#define WGM10 0
514#define WGM11 1
515#define COM1B0 4
516#define COM1B1 5
517#define COM1A0 6
518#define COM1A1 7
519
520#define TCCR1B _SFR_MEM8(0x81)
521#define CS10 0
522#define CS11 1
523#define CS12 2
524#define WGM12 3
525#define WGM13 4
526#define ICES1 6
527#define ICNC1 7
528
529#define TCCR1C _SFR_MEM8(0x82)
530#define FOC1B 6
531#define FOC1A 7
532
533#define TCNT1 _SFR_MEM16(0x84)
534
535#define TCNT1L _SFR_MEM8(0x84)
536#define TCNT1L0 0
537#define TCNT1L1 1
538#define TCNT1L2 2
539#define TCNT1L3 3
540#define TCNT1L4 4
541#define TCNT1L5 5
542#define TCNT1L6 6
543#define TCNT1L7 7
544
545#define TCNT1H _SFR_MEM8(0x85)
546#define TCNT1H0 0
547#define TCNT1H1 1
548#define TCNT1H2 2
549#define TCNT1H3 3
550#define TCNT1H4 4
551#define TCNT1H5 5
552#define TCNT1H6 6
553#define TCNT1H7 7
554
555#define ICR1 _SFR_MEM16(0x86)
556
557#define ICR1L _SFR_MEM8(0x86)
558#define ICR1L0 0
559#define ICR1L1 1
560#define ICR1L2 2
561#define ICR1L3 3
562#define ICR1L4 4
563#define ICR1L5 5
564#define ICR1L6 6
565#define ICR1L7 7
566
567#define ICR1H _SFR_MEM8(0x87)
568#define ICR1H0 0
569#define ICR1H1 1
570#define ICR1H2 2
571#define ICR1H3 3
572#define ICR1H4 4
573#define ICR1H5 5
574#define ICR1H6 6
575#define ICR1H7 7
576
577#define OCR1A _SFR_MEM16(0x88)
578
579#define OCR1AL _SFR_MEM8(0x88)
580#define OCR1AL0 0
581#define OCR1AL1 1
582#define OCR1AL2 2
583#define OCR1AL3 3
584#define OCR1AL4 4
585#define OCR1AL5 5
586#define OCR1AL6 6
587#define OCR1AL7 7
588
589#define OCR1AH _SFR_MEM8(0x89)
590#define OCR1AH0 0
591#define OCR1AH1 1
592#define OCR1AH2 2
593#define OCR1AH3 3
594#define OCR1AH4 4
595#define OCR1AH5 5
596#define OCR1AH6 6
597#define OCR1AH7 7
598
599#define OCR1B _SFR_MEM16(0x8A)
600
601#define OCR1BL _SFR_MEM8(0x8A)
602#define OCR1BL0 0
603#define OCR1BL1 1
604#define OCR1BL2 2
605#define OCR1BL3 3
606#define OCR1BL4 4
607#define OCR1BL5 5
608#define OCR1BL6 6
609#define OCR1BL7 7
610
611#define OCR1BH _SFR_MEM8(0x8B)
612#define OCR1BH0 0
613#define OCR1BH1 1
614#define OCR1BH2 2
615#define OCR1BH3 3
616#define OCR1BH4 4
617#define OCR1BH5 5
618#define OCR1BH6 6
619#define OCR1BH7 7
620
621#define TCCR2A _SFR_MEM8(0xB0)
622#define WGM20 0
623#define WGM21 1
624#define COM2B0 4
625#define COM2B1 5
626#define COM2A0 6
627#define COM2A1 7
628
629#define TCCR2B _SFR_MEM8(0xB1)
630#define CS20 0
631#define CS21 1
632#define CS22 2
633#define WGM22 3
634#define FOC2B 6
635#define FOC2A 7
636
637#define TCNT2 _SFR_MEM8(0xB2)
638#define TCNT2_0 0
639#define TCNT2_1 1
640#define TCNT2_2 2
641#define TCNT2_3 3
642#define TCNT2_4 4
643#define TCNT2_5 5
644#define TCNT2_6 6
645#define TCNT2_7 7
646
647#define OCR2A _SFR_MEM8(0xB3)
648#define OCR2A_0 0
649#define OCR2A_1 1
650#define OCR2A_2 2
651#define OCR2A_3 3
652#define OCR2A_4 4
653#define OCR2A_5 5
654#define OCR2A_6 6
655#define OCR2A_7 7
656
657#define OCR2B _SFR_MEM8(0xB4)
658#define OCR2B_0 0
659#define OCR2B_1 1
660#define OCR2B_2 2
661#define OCR2B_3 3
662#define OCR2B_4 4
663#define OCR2B_5 5
664#define OCR2B_6 6
665#define OCR2B_7 7
666
667#define ASSR _SFR_MEM8(0xB6)
668#define TCR2BUB 0
669#define TCR2AUB 1
670#define OCR2BUB 2
671#define OCR2AUB 3
672#define TCN2UB 4
673#define AS2 5
674#define EXCLK 6
675
676#define TWBR _SFR_MEM8(0xB8)
677#define TWBR0 0
678#define TWBR1 1
679#define TWBR2 2
680#define TWBR3 3
681#define TWBR4 4
682#define TWBR5 5
683#define TWBR6 6
684#define TWBR7 7
685
686#define TWSR _SFR_MEM8(0xB9)
687#define TWPS0 0
688#define TWPS1 1
689#define TWS3 3
690#define TWS4 4
691#define TWS5 5
692#define TWS6 6
693#define TWS7 7
694
695#define TWAR _SFR_MEM8(0xBA)
696#define TWGCE 0
697#define TWA0 1
698#define TWA1 2
699#define TWA2 3
700#define TWA3 4
701#define TWA4 5
702#define TWA5 6
703#define TWA6 7
704
705#define TWDR _SFR_MEM8(0xBB)
706#define TWD0 0
707#define TWD1 1
708#define TWD2 2
709#define TWD3 3
710#define TWD4 4
711#define TWD5 5
712#define TWD6 6
713#define TWD7 7
714
715#define TWCR _SFR_MEM8(0xBC)
716#define TWIE 0
717#define TWEN 2
718#define TWWC 3
719#define TWSTO 4
720#define TWSTA 5
721#define TWEA 6
722#define TWINT 7
723
724#define TWAMR _SFR_MEM8(0xBD)
725#define TWAM0 1
726#define TWAM1 2
727#define TWAM2 3
728#define TWAM3 4
729#define TWAM4 5
730#define TWAM5 6
731#define TWAM6 7
732
733#define UCSR0A _SFR_MEM8(0xC0)
734#define MPCM0 0
735#define U2X0 1
736#define UPE0 2
737#define DOR0 3
738#define FE0 4
739#define UDRE0 5
740#define TXC0 6
741#define RXC0 7
742
743#define UCSR0B _SFR_MEM8(0xC1)
744#define TXB80 0
745#define RXB80 1
746#define UCSZ02 2
747#define TXEN0 3
748#define RXEN0 4
749#define UDRIE0 5
750#define TXCIE0 6
751#define RXCIE0 7
752
753#define UCSR0C _SFR_MEM8(0xC2)
754#define UCPOL0 0
755#define UCSZ00 1
756#define UCSZ01 2
757#define USBS0 3
758#define UPM00 4
759#define UPM01 5
760#define UMSEL00 6
761#define UMSEL01 7
762
763#define UBRR0 _SFR_MEM16(0xC4)
764
765#define UBRR0L _SFR_MEM8(0xC4)
766#define _UBRR0 0
767#define _UBRR1 1
768#define UBRR2 2
769#define UBRR3 3
770#define UBRR4 4
771#define UBRR5 5
772#define UBRR6 6
773#define UBRR7 7
774
775#define UBRR0H _SFR_MEM8(0xC5)
776#define UBRR8 0
777#define UBRR9 1
778#define UBRR10 2
779#define UBRR11 3
780
781#define UDR0 _SFR_MEM8(0xC6)
782#define UDR0_0 0
783#define UDR0_1 1
784#define UDR0_2 2
785#define UDR0_3 3
786#define UDR0_4 4
787#define UDR0_5 5
788#define UDR0_6 6
789#define UDR0_7 7
790
791
792/* Interrupt vectors */
793/* Vector 0 is the reset vector */
794#define INT0_vect_num  1
795#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
796#define INT1_vect_num  2
797#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
798#define PCINT0_vect_num  3
799#define PCINT0_vect      _VECTOR(3)  /* Pin Change Interrupt Request 0 */
800#define PCINT1_vect_num  4
801#define PCINT1_vect      _VECTOR(4)  /* Pin Change Interrupt Request 0 */
802#define PCINT2_vect_num  5
803#define PCINT2_vect      _VECTOR(5)  /* Pin Change Interrupt Request 1 */
804#define WDT_vect_num  6
805#define WDT_vect      _VECTOR(6)  /* Watchdog Time-out Interrupt */
806#define TIMER2_COMPA_vect_num  7
807#define TIMER2_COMPA_vect      _VECTOR(7)  /* Timer/Counter2 Compare Match A */
808#define TIMER2_COMPB_vect_num  8
809#define TIMER2_COMPB_vect      _VECTOR(8)  /* Timer/Counter2 Compare Match A */
810#define TIMER2_OVF_vect_num  9
811#define TIMER2_OVF_vect      _VECTOR(9)  /* Timer/Counter2 Overflow */
812#define TIMER1_CAPT_vect_num  10
813#define TIMER1_CAPT_vect      _VECTOR(10)  /* Timer/Counter1 Capture Event */
814#define TIMER1_COMPA_vect_num  11
815#define TIMER1_COMPA_vect      _VECTOR(11)  /* Timer/Counter1 Compare Match A */
816#define TIMER1_COMPB_vect_num  12
817#define TIMER1_COMPB_vect      _VECTOR(12)  /* Timer/Counter1 Compare Match B */
818#define TIMER1_OVF_vect_num  13
819#define TIMER1_OVF_vect      _VECTOR(13)  /* Timer/Counter1 Overflow */
820#define TIMER0_COMPA_vect_num  14
821#define TIMER0_COMPA_vect      _VECTOR(14)  /* TimerCounter0 Compare Match A */
822#define TIMER0_COMPB_vect_num  15
823#define TIMER0_COMPB_vect      _VECTOR(15)  /* TimerCounter0 Compare Match B */
824#define TIMER0_OVF_vect_num  16
825#define TIMER0_OVF_vect      _VECTOR(16)  /* Timer/Couner0 Overflow */
826#define SPI_STC_vect_num  17
827#define SPI_STC_vect      _VECTOR(17)  /* SPI Serial Transfer Complete */
828#define USART_RX_vect_num  18
829#define USART_RX_vect      _VECTOR(18)  /* USART Rx Complete */
830#define USART_UDRE_vect_num  19
831#define USART_UDRE_vect      _VECTOR(19)  /* USART, Data Register Empty */
832#define USART_TX_vect_num  20
833#define USART_TX_vect      _VECTOR(20)  /* USART Tx Complete */
834#define ADC_vect_num  21
835#define ADC_vect      _VECTOR(21)  /* ADC Conversion Complete */
836#define EE_READY_vect_num  22
837#define EE_READY_vect      _VECTOR(22)  /* EEPROM Ready */
838#define ANALOG_COMP_vect_num  23
839#define ANALOG_COMP_vect      _VECTOR(23)  /* Analog Comparator */
840#define TWI_vect_num  24
841#define TWI_vect      _VECTOR(24)  /* Two-wire Serial Interface */
842#define SPM_Ready_vect_num  25
843#define SPM_Ready_vect      _VECTOR(25)  /* Store Program Memory Read */
844
845#define _VECTOR_SIZE 2 /* Size of individual vector. */
846#define _VECTORS_SIZE (26 * _VECTOR_SIZE)
847
848
849/* Constants */
850#define SPM_PAGESIZE (64)
851#define RAMSTART     (0x100)
852#define RAMSIZE      (1024)
853#define RAMEND       (RAMSTART + RAMSIZE - 1)
854#define XRAMSTART    (NA)
855#define XRAMSIZE     (0)
856#define XRAMEND      (RAMEND)
857#define E2END        (0x1FF)
858#define E2PAGESIZE   (4)
859#define FLASHEND     (0x1FFF)
860
861
862/* Fuses */
863#define FUSE_MEMORY_SIZE 3
864
865/* Low Fuse Byte */
866#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
867#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
868#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
869#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
870#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
871#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
872#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
873#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
874#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
875
876/* High Fuse Byte */
877#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
878#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
879#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
880#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
881#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog Timer Always On */
882#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
883#define FUSE_DWEN  (unsigned char)~_BV(6)  /* debugWIRE Enable */
884#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External reset disable */
885#define HFUSE_DEFAULT (FUSE_SPIEN)
886
887/* Extended Fuse Byte */
888#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select reset vector */
889#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select boot size */
890#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select boot size */
891#define EFUSE_DEFAULT (FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
892
893
894/* Lock Bits */
895#define __LOCK_BITS_EXIST
896#define __BOOT_LOCK_BITS_0_EXIST
897#define __BOOT_LOCK_BITS_1_EXIST
898
899
900/* Signature */
901#define SIGNATURE_0 0x1E
902#define SIGNATURE_1 0x93
903#define SIGNATURE_2 0x0F
904
905
906/* Device Pin Definitions */
907#define PCINT19_DDR   DDRD
908#define PCINT19_PORT  PORTD
909#define PCINT19_PIN   PIND
910#define PCINT19_BIT   3
911
912#define OC2B_DDR   DDRD
913#define OC2B_PORT  PORTD
914#define OC2B_PIN   PIND
915#define OC2B_BIT   3
916
917#define INT1_DDR   DDRD
918#define INT1_PORT  PORTD
919#define INT1_PIN   PIND
920#define INT1_BIT   3
921
922#define XCK_DDR   DDRD
923#define XCK_PORT  PORTD
924#define XCK_PIN   PIND
925#define XCK_BIT   4
926
927#define T0_DDR   DDRD
928#define T0_PORT  PORTD
929#define T0_PIN   PIND
930#define T0_BIT   4
931
932#define PCINT20_DDR   DDRD
933#define PCINT20_PORT  PORTD
934#define PCINT20_PIN   PIND
935#define PCINT20_BIT   4
936
937#define PCINT6_DDR   DDRB
938#define PCINT6_PORT  PORTB
939#define PCINT6_PIN   PINB
940#define PCINT6_BIT   6
941
942#define PCINT7_DDR   DDRB
943#define PCINT7_PORT  PORTB
944#define PCINT7_PIN   PINB
945#define PCINT7_BIT   7
946
947#define T1_DDR   DDRD
948#define T1_PORT  PORTD
949#define T1_PIN   PIND
950#define T1_BIT   5
951
952#define OC0B_DDR   DDRD
953#define OC0B_PORT  PORTD
954#define OC0B_PIN   PIND
955#define OC0B_BIT   5
956
957#define PCINT21_DDR   DDRD
958#define PCINT21_PORT  PORTD
959#define PCINT21_PIN   PIND
960#define PCINT21_BIT   5
961
962#define AIN0_DDR   DDRD
963#define AIN0_PORT  PORTD
964#define AIN0_PIN   PIND
965#define AIN0_BIT   6
966
967#define OC0A_DDR   DDRD
968#define OC0A_PORT  PORTD
969#define OC0A_PIN   PIND
970#define OC0A_BIT   6
971
972#define PCINT22_DDR   DDRD
973#define PCINT22_PORT  PORTD
974#define PCINT22_PIN   PIND
975#define PCINT22_BIT   6
976
977#define AIN1_DDR   DDRD
978#define AIN1_PORT  PORTD
979#define AIN1_PIN   PIND
980#define AIN1_BIT   7
981
982#define PCINT23_DDR   DDRD
983#define PCINT23_PORT  PORTD
984#define PCINT23_PIN   PIND
985#define PCINT23_BIT   7
986
987#define ICP1_DDR   DDRB
988#define ICP1_PORT  PORTB
989#define ICP1_PIN   PINB
990#define ICP1_BIT   0
991
992#define CLKO_DDR   DDRB
993#define CLKO_PORT  PORTB
994#define CLKO_PIN   PINB
995#define CLKO_BIT   0
996
997#define PCINT0_DDR   DDRB
998#define PCINT0_PORT  PORTB
999#define PCINT0_PIN   PINB
1000#define PCINT0_BIT   0
1001
1002#define OC1A_DDR   DDRB
1003#define OC1A_PORT  PORTB
1004#define OC1A_PIN   PINB
1005#define OC1A_BIT   1
1006
1007#define PCINT1_DDR   DDRB
1008#define PCINT1_PORT  PORTB
1009#define PCINT1_PIN   PINB
1010#define PCINT1_BIT   1
1011
1012#define SS_DDR   DDRB
1013#define SS_PORT  PORTB
1014#define SS_PIN   PINB
1015#define SS_BIT   2
1016
1017#define OC1B_DDR   DDRB
1018#define OC1B_PORT  PORTB
1019#define OC1B_PIN   PINB
1020#define OC1B_BIT   2
1021
1022#define PCINT2_DDR   DDRB
1023#define PCINT2_PORT  PORTB
1024#define PCINT2_PIN   PINB
1025#define PCINT2_BIT   2
1026
1027#define MOSI_DDR   DDRB
1028#define MOSI_PORT  PORTB
1029#define MOSI_PIN   PINB
1030#define MOSI_BIT   3
1031
1032#define OC2A_DDR   DDRB
1033#define OC2A_PORT  PORTB
1034#define OC2A_PIN   PINB
1035#define OC2A_BIT   3
1036
1037#define PCINT3_DDR   DDRB
1038#define PCINT3_PORT  PORTB
1039#define PCINT3_PIN   PINB
1040#define PCINT3_BIT   3
1041
1042#define MISO_DDR   DDRB
1043#define MISO_PORT  PORTB
1044#define MISO_PIN   PINB
1045#define MISO_BIT   4
1046
1047#define PCINT4_DDR   DDRB
1048#define PCINT4_PORT  PORTB
1049#define PCINT4_PIN   PINB
1050#define PCINT4_BIT   4
1051
1052#define SCK_DDR   DDRB
1053#define SCK_PORT  PORTB
1054#define SCK_PIN   PINB
1055#define SCK_BIT   5
1056
1057#define PCINT5_DDR   DDRB
1058#define PCINT5_PORT  PORTB
1059#define PCINT5_PIN   PINB
1060#define PCINT5_BIT   5
1061
1062#define ADC6_DDR   DDRADC
1063#define ADC6_PORT  PORTADC
1064#define ADC6_PIN   PINADC
1065#define ADC6_BIT   ADC6
1066
1067#define ADC7_DDR   DDRADC
1068#define ADC7_PORT  PORTADC
1069#define ADC7_PIN   PINADC
1070#define ADC7_BIT   ADC7
1071
1072#define ADC0_DDR   DDRC
1073#define ADC0_PORT  PORTC
1074#define ADC0_PIN   PINC
1075#define ADC0_BIT   0
1076
1077#define PCINT8_DDR   DDRC
1078#define PCINT8_PORT  PORTC
1079#define PCINT8_PIN   PINC
1080#define PCINT8_BIT   0
1081
1082#define ADC1_DDR   DDRC
1083#define ADC1_PORT  PORTC
1084#define ADC1_PIN   PINC
1085#define ADC1_BIT   1
1086
1087#define PCINT9_DDR   DDRC
1088#define PCINT9_PORT  PORTC
1089#define PCINT9_PIN   PINC
1090#define PCINT9_BIT   1
1091
1092#define ADC2_DDR   DDRC
1093#define ADC2_PORT  PORTC
1094#define ADC2_PIN   PINC
1095#define ADC2_BIT   2
1096
1097#define PCINT10_DDR   DDRC
1098#define PCINT10_PORT  PORTC
1099#define PCINT10_PIN   PINC
1100#define PCINT10_BIT   2
1101
1102#define ADC3_DDR   DDRC
1103#define ADC3_PORT  PORTC
1104#define ADC3_PIN   PINC
1105#define ADC3_BIT   3
1106
1107#define PCINT11_DDR   DDRC
1108#define PCINT11_PORT  PORTC
1109#define PCINT11_PIN   PINC
1110#define PCINT11_BIT   3
1111
1112#define ADC4_DDR   DDRC
1113#define ADC4_PORT  PORTC
1114#define ADC4_PIN   PINC
1115#define ADC4_BIT   4
1116
1117#define SDA_DDR   DDRC
1118#define SDA_PORT  PORTC
1119#define SDA_PIN   PINC
1120#define SDA_BIT   4
1121
1122#define PCINT12_DDR   DDRC
1123#define PCINT12_PORT  PORTC
1124#define PCINT12_PIN   PINC
1125#define PCINT12_BIT   4
1126
1127#define ADC5_DDR   DDRC
1128#define ADC5_PORT  PORTC
1129#define ADC5_PIN   PINC
1130#define ADC5_BIT   5
1131
1132#define SCL_DDR   DDRC
1133#define SCL_PORT  PORTC
1134#define SCL_PIN   PINC
1135#define SCL_BIT   5
1136
1137#define PCINT13_DDR   DDRC
1138#define PCINT13_PORT  PORTC
1139#define PCINT13_PIN   PINC
1140#define PCINT13_BIT   5
1141
1142#define PCINT14_DDR   DDRC
1143#define PCINT14_PORT  PORTC
1144#define PCINT14_PIN   PINC
1145#define PCINT14_BIT   6
1146
1147#define RXD_DDR   DDRD
1148#define RXD_PORT  PORTD
1149#define RXD_PIN   PIND
1150#define RXD_BIT   0
1151
1152#define PCINT16_DDR   DDRD
1153#define PCINT16_PORT  PORTD
1154#define PCINT16_PIN   PIND
1155#define PCINT16_BIT   0
1156
1157#define TXD_DDR   DDRD
1158#define TXD_PORT  PORTD
1159#define TXD_PIN   PIND
1160#define TXD_BIT   1
1161
1162#define PCINT17_DDR   DDRD
1163#define PCINT17_PORT  PORTD
1164#define PCINT17_PIN   PIND
1165#define PCINT17_BIT   1
1166
1167#define INT0_DDR   DDRD
1168#define INT0_PORT  PORTD
1169#define INT0_PIN   PIND
1170#define INT0_BIT   2
1171
1172#define PCINT18_DDR   DDRD
1173#define PCINT18_PORT  PORTD
1174#define PCINT18_PIN   PIND
1175#define PCINT18_BIT   2
1176
1177#define SLEEP_MODE_IDLE (0x00<<1)
1178#define SLEEP_MODE_ADC (0x01<<1)
1179#define SLEEP_MODE_PWR_DOWN (0x02<<1)
1180#define SLEEP_MODE_PWR_SAVE (0x03<<1)
1181#define SLEEP_MODE_STANDBY (0x06<<1)
1182#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
1183
1184#endif /* _AVR_ATmega88PA_H_ */
1185
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