source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom88pb.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

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1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATMEGA88PB_H_INCLUDED
36#define _AVR_ATMEGA88PB_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "iom88pb.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINB    _SFR_IO8(0x03)
52#define PINB7   7
53#define PINB6   6
54#define PINB5   5
55#define PINB4   4
56#define PINB3   3
57#define PINB2   2
58#define PINB1   1
59#define PINB0   0
60
61#define DDRB    _SFR_IO8(0x04)
62#define DDRB7   7
63// Inserted "DDB7" from "DDRB7" due to compatibility
64#define DDB7    7
65#define DDRB6   6
66// Inserted "DDB6" from "DDRB6" due to compatibility
67#define DDB6    6
68#define DDRB5   5
69// Inserted "DDB5" from "DDRB5" due to compatibility
70#define DDB5    5
71#define DDRB4   4
72// Inserted "DDB4" from "DDRB4" due to compatibility
73#define DDB4    4
74#define DDRB3   3
75// Inserted "DDB3" from "DDRB3" due to compatibility
76#define DDB3    3
77#define DDRB2   2
78// Inserted "DDB2" from "DDRB2" due to compatibility
79#define DDB2    2
80#define DDRB1   1
81// Inserted "DDB1" from "DDRB1" due to compatibility
82#define DDB1    1
83#define DDRB0   0
84// Inserted "DDB0" from "DDRB0" due to compatibility
85#define DDB0    0
86
87#define PORTB   _SFR_IO8(0x05)
88#define PORTB7  7
89#define PORTB6  6
90#define PORTB5  5
91#define PORTB4  4
92#define PORTB3  3
93#define PORTB2  2
94#define PORTB1  1
95#define PORTB0  0
96
97#define PINC    _SFR_IO8(0x06)
98#define PINC6   6
99#define PINC5   5
100#define PINC4   4
101#define PINC3   3
102#define PINC2   2
103#define PINC1   1
104#define PINC0   0
105
106#define DDRC    _SFR_IO8(0x07)
107#define DDRC6   6
108// Inserted "DDC6" from "DDRC6" due to compatibility
109#define DDC6    6
110#define DDRC5   5
111// Inserted "DDC5" from "DDRC5" due to compatibility
112#define DDC5    5
113#define DDRC4   4
114// Inserted "DDC4" from "DDRC4" due to compatibility
115#define DDC4    4
116#define DDRC3   3
117// Inserted "DDC3" from "DDRC3" due to compatibility
118#define DDC3    3
119#define DDRC2   2
120// Inserted "DDC2" from "DDRC2" due to compatibility
121#define DDC2    2
122#define DDRC1   1
123// Inserted "DDC1" from "DDRC1" due to compatibility
124#define DDC1    1
125#define DDRC0   0
126// Inserted "DDC0" from "DDRC0" due to compatibility
127#define DDC0    0
128
129#define PORTC   _SFR_IO8(0x08)
130#define PORTC6  6
131#define PORTC5  5
132#define PORTC4  4
133#define PORTC3  3
134#define PORTC2  2
135#define PORTC1  1
136#define PORTC0  0
137
138#define PIND    _SFR_IO8(0x09)
139#define PIND7   7
140#define PIND6   6
141#define PIND5   5
142#define PIND4   4
143#define PIND3   3
144#define PIND2   2
145#define PIND1   1
146#define PIND0   0
147
148#define DDRD    _SFR_IO8(0x0A)
149#define DDRD7   7
150// Inserted "DDD7" from "DDRD7" due to compatibility
151#define DDD7    7
152#define DDRD6   6
153// Inserted "DDD6" from "DDRD6" due to compatibility
154#define DDD6    6
155#define DDRD5   5
156// Inserted "DDD5" from "DDRD5" due to compatibility
157#define DDD5    5
158#define DDRD4   4
159// Inserted "DDD4" from "DDRD4" due to compatibility
160#define DDD4    4
161#define DDRD3   3
162// Inserted "DDD3" from "DDRD3" due to compatibility
163#define DDD3    3
164#define DDRD2   2
165// Inserted "DDD2" from "DDRD2" due to compatibility
166#define DDD2    2
167#define DDRD1   1
168// Inserted "DDD1" from "DDRD1" due to compatibility
169#define DDD1    1
170#define DDRD0   0
171// Inserted "DDD0" from "DDRD0" due to compatibility
172#define DDD0    0
173
174#define PORTD   _SFR_IO8(0x0B)
175#define PORTD7  7
176#define PORTD6  6
177#define PORTD5  5
178#define PORTD4  4
179#define PORTD3  3
180#define PORTD2  2
181#define PORTD1  1
182#define PORTD0  0
183
184#define PINE    _SFR_IO8(0x0C)
185#define PINE3   3
186#define PINE2   2
187#define PINE1   1
188#define PINE0   0
189
190#define DDRE    _SFR_IO8(0x0D)
191#define DDRE3   3
192// Inserted "DDE3" from "DDRE3" due to compatibility
193#define DDE3    3
194#define DDRE2   2
195// Inserted "DDE2" from "DDRE2" due to compatibility
196#define DDE2    2
197#define DDRE1   1
198// Inserted "DDE1" from "DDRE1" due to compatibility
199#define DDE1    1
200#define DDRE0   0
201// Inserted "DDE0" from "DDRE0" due to compatibility
202#define DDE0    0
203
204#define PORTE   _SFR_IO8(0x0E)
205#define PORTE3  3
206#define PORTE2  2
207#define PORTE1  1
208#define PORTE0  0
209
210#define ACSRB   _SFR_IO8(0x0F)
211#define ACOE    0
212
213/* Reserved [0x10..0x14] */
214
215#define TIFR0   _SFR_IO8(0x15)
216#define TOV0    0
217#define OCF0A   1
218#define OCF0B   2
219
220#define TIFR1   _SFR_IO8(0x16)
221#define TOV1    0
222#define OCF1A   1
223#define OCF1B   2
224#define ICF1    5
225
226#define TIFR2   _SFR_IO8(0x17)
227#define TOV2    0
228#define OCF2A   1
229#define OCF2B   2
230
231/* Reserved [0x18..0x1A] */
232
233#define PCIFR   _SFR_IO8(0x1B)
234#define PCIF0   0
235#define PCIF1   1
236#define PCIF2   2
237
238#define EIFR    _SFR_IO8(0x1C)
239#define INTF0   0
240#define INTF1   1
241
242#define EIMSK   _SFR_IO8(0x1D)
243#define INT0    0
244#define INT1    1
245
246#define GPIOR0  _SFR_IO8(0x1E)
247
248#define EECR    _SFR_IO8(0x1F)
249#define EERE    0
250#define EEPE    1
251#define EEMPE   2
252#define EERIE   3
253#define EEPM0   4
254#define EEPM1   5
255
256#define EEDR    _SFR_IO8(0x20)
257
258/* Combine EEARL and EEARH */
259#define EEAR    _SFR_IO16(0x21)
260
261#define EEARL   _SFR_IO8(0x21)
262#define EEARH   _SFR_IO8(0x22)
263
264#define GTCCR   _SFR_IO8(0x23)
265#define PSRSYNC 0
266#define TSM     7
267#define PSRASY  1
268
269#define TCCR0A  _SFR_IO8(0x24)
270#define WGM00   0
271#define WGM01   1
272#define COM0B0  4
273#define COM0B1  5
274#define COM0A0  6
275#define COM0A1  7
276
277#define TCCR0B  _SFR_IO8(0x25)
278#define CS00    0
279#define CS01    1
280#define CS02    2
281#define WGM02   3
282#define FOC0B   6
283#define FOC0A   7
284
285#define TCNT0   _SFR_IO8(0x26)
286
287#define OCR0A   _SFR_IO8(0x27)
288
289#define OCR0B   _SFR_IO8(0x28)
290
291/* Reserved [0x29] */
292
293#define GPIOR1  _SFR_IO8(0x2A)
294
295#define GPIOR2  _SFR_IO8(0x2B)
296
297#define SPCR    _SFR_IO8(0x2C)
298#define SPR0    0
299#define SPR1    1
300#define CPHA    2
301#define CPOL    3
302#define MSTR    4
303#define DORD    5
304#define SPE     6
305#define SPIE    7
306
307#define SPSR    _SFR_IO8(0x2D)
308#define SPI2X   0
309#define WCOL    6
310#define SPIF    7
311
312#define SPDR    _SFR_IO8(0x2E)
313
314/* Reserved [0x2F] */
315
316#define ACSR    _SFR_IO8(0x30)
317#define ACIS0   0
318#define ACIS1   1
319#define ACIC    2
320#define ACIE    3
321#define ACI     4
322#define ACO     5
323#define ACBG    6
324#define ACD     7
325
326/* Reserved [0x31..0x32] */
327
328#define SMCR    _SFR_IO8(0x33)
329#define SE      0
330#define SM0     1
331#define SM1     2
332#define SM2     3
333
334#define MCUSR   _SFR_IO8(0x34)
335#define PORF    0
336#define EXTRF   1
337#define BORF    2
338#define WDRF    3
339
340#define MCUCR   _SFR_IO8(0x35)
341#define IVCE    0
342#define IVSEL   1
343#define PUD     4
344#define BODSE   5
345#define BODS    6
346
347/* Reserved [0x36] */
348
349#define SPMCSR  _SFR_IO8(0x37)
350#define SPMEN   0
351#define PGERS   1
352#define PGWRT   2
353#define BLBSET  3
354#define RWWSRE  4
355#define SIGRD   5
356#define RWWSB   6
357#define SPMIE   7
358
359/* Reserved [0x38..0x3C] */
360
361/* SP [0x3D..0x3E] */
362
363/* SREG [0x3F] */
364
365#define WDTCSR  _SFR_MEM8(0x60)
366#define WDE     3
367#define WDCE    4
368#define WDP0    0
369#define WDP1    1
370#define WDP2    2
371#define WDP3    5
372#define WDIE    6
373#define WDIF    7
374
375#define CLKPR   _SFR_MEM8(0x61)
376#define CLKPS0  0
377#define CLKPS1  1
378#define CLKPS2  2
379#define CLKPS3  3
380#define CLKPCE  7
381
382/* Reserved [0x62..0x63] */
383
384#define PRR     _SFR_MEM8(0x64)
385#define PRADC   0
386#define PRUSART0 1
387#define PRSPI   2
388#define PRTIM1  3
389#define PRTIM0  5
390#define PRTIM2  6
391#define PRTWI   7
392
393#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
394#define __AVR_HAVE_PRR_PRADC
395#define __AVR_HAVE_PRR_PRUSART0
396#define __AVR_HAVE_PRR_PRSPI
397#define __AVR_HAVE_PRR_PRTIM1
398#define __AVR_HAVE_PRR_PRTIM0
399#define __AVR_HAVE_PRR_PRTIM2
400#define __AVR_HAVE_PRR_PRTWI
401
402/* Reserved [0x65] */
403
404#define OSCCAL  _SFR_MEM8(0x66)
405#define OSCCAL0 0
406#define OSCCAL1 1
407#define OSCCAL2 2
408#define OSCCAL3 3
409#define OSCCAL4 4
410#define OSCCAL5 5
411#define OSCCAL6 6
412#define OSCCAL7 7
413
414/* Reserved [0x67] */
415
416#define PCICR   _SFR_MEM8(0x68)
417#define PCIE0   0
418#define PCIE1   1
419#define PCIE2   2
420
421#define EICRA   _SFR_MEM8(0x69)
422#define ISC00   0
423#define ISC01   1
424#define ISC10   2
425#define ISC11   3
426
427/* Reserved [0x6A] */
428
429#define PCMSK0  _SFR_MEM8(0x6B)
430#define PCINT0  0
431#define PCINT1  1
432#define PCINT2  2
433#define PCINT3  3
434#define PCINT4  4
435#define PCINT5  5
436#define PCINT6  6
437#define PCINT7  7
438
439#define PCMSK1  _SFR_MEM8(0x6C)
440#define PCINT8  0
441#define PCINT9  1
442#define PCINT10 2
443#define PCINT11 3
444#define PCINT12 4
445#define PCINT13 5
446#define PCINT14 6
447
448#define PCMSK2  _SFR_MEM8(0x6D)
449#define PCINT16 0
450#define PCINT17 1
451#define PCINT18 2
452#define PCINT19 3
453#define PCINT20 4
454#define PCINT21 5
455#define PCINT22 6
456#define PCINT23 7
457
458#define TIMSK0  _SFR_MEM8(0x6E)
459#define TOIE0   0
460#define OCIE0A  1
461#define OCIE0B  2
462
463#define TIMSK1  _SFR_MEM8(0x6F)
464#define TOIE1   0
465#define OCIE1A  1
466#define OCIE1B  2
467#define ICIE1   5
468
469#define TIMSK2  _SFR_MEM8(0x70)
470#define TOIE2   0
471#define OCIE2A  1
472#define OCIE2B  2
473
474/* Reserved [0x71..0x77] */
475
476/* Combine ADCL and ADCH */
477#ifndef __ASSEMBLER__
478#define ADC     _SFR_MEM16(0x78)
479#endif
480#define ADCW    _SFR_MEM16(0x78)
481
482#define ADCL    _SFR_MEM8(0x78)
483#define ADCH    _SFR_MEM8(0x79)
484
485#define ADCSRA  _SFR_MEM8(0x7A)
486#define ADPS0   0
487#define ADPS1   1
488#define ADPS2   2
489#define ADIE    3
490#define ADIF    4
491#define ADATE   5
492#define ADSC    6
493#define ADEN    7
494
495#define ADCSRB  _SFR_MEM8(0x7B)
496#define ADTS0   0
497#define ADTS1   1
498#define ADTS2   2
499#define ACME    6
500
501#define ADMUX   _SFR_MEM8(0x7C)
502#define MUX0    0
503#define MUX1    1
504#define MUX2    2
505#define MUX3    3
506#define ADLAR   5
507#define REFS0   6
508#define REFS1   7
509
510/* Reserved [0x7D] */
511
512#define DIDR0   _SFR_MEM8(0x7E)
513#define ADC0D   0
514#define ADC1D   1
515#define ADC2D   2
516#define ADC3D   3
517#define ADC4D   4
518#define ADC5D   5
519
520#define DIDR1   _SFR_MEM8(0x7F)
521#define AIN0D   0
522#define AIN1D   1
523
524#define TCCR1A  _SFR_MEM8(0x80)
525#define WGM10   0
526#define WGM11   1
527#define COM1B0  4
528#define COM1B1  5
529#define COM1A0  6
530#define COM1A1  7
531
532#define TCCR1B  _SFR_MEM8(0x81)
533#define CS10    0
534#define CS11    1
535#define CS12    2
536#define WGM12   3
537#define WGM13   4
538#define ICES1   6
539#define ICNC1   7
540
541#define TCCR1C  _SFR_MEM8(0x82)
542#define FOC1B   6
543#define FOC1A   7
544
545/* Reserved [0x83] */
546
547/* Combine TCNT1L and TCNT1H */
548#define TCNT1   _SFR_MEM16(0x84)
549
550#define TCNT1L  _SFR_MEM8(0x84)
551#define TCNT1H  _SFR_MEM8(0x85)
552
553/* Combine ICR1L and ICR1H */
554#define ICR1    _SFR_MEM16(0x86)
555
556#define ICR1L   _SFR_MEM8(0x86)
557#define ICR1H   _SFR_MEM8(0x87)
558
559/* Combine OCR1AL and OCR1AH */
560#define OCR1A   _SFR_MEM16(0x88)
561
562#define OCR1AL  _SFR_MEM8(0x88)
563#define OCR1AH  _SFR_MEM8(0x89)
564
565/* Combine OCR1BL and OCR1BH */
566#define OCR1B   _SFR_MEM16(0x8A)
567
568#define OCR1BL  _SFR_MEM8(0x8A)
569#define OCR1BH  _SFR_MEM8(0x8B)
570
571/* Reserved [0x8C..0xAF] */
572
573#define TCCR2A  _SFR_MEM8(0xB0)
574#define WGM20   0
575#define WGM21   1
576#define COM2B0  4
577#define COM2B1  5
578#define COM2A0  6
579#define COM2A1  7
580
581#define TCCR2B  _SFR_MEM8(0xB1)
582#define CS20    0
583#define CS21    1
584#define CS22    2
585#define WGM22   3
586#define FOC2B   6
587#define FOC2A   7
588
589#define TCNT2   _SFR_MEM8(0xB2)
590
591#define OCR2A   _SFR_MEM8(0xB3)
592
593#define OCR2B   _SFR_MEM8(0xB4)
594
595/* Reserved [0xB5] */
596
597#define ASSR    _SFR_MEM8(0xB6)
598#define TCR2BUB 0
599#define TCR2AUB 1
600#define OCR2BUB 2
601#define OCR2AUB 3
602#define TCN2UB  4
603#define AS2     5
604#define EXCLK   6
605
606/* Reserved [0xB7] */
607
608#define TWBR    _SFR_MEM8(0xB8)
609
610#define TWSR    _SFR_MEM8(0xB9)
611#define TWPS0   0
612#define TWPS1   1
613#define TWS3    3
614#define TWS4    4
615#define TWS5    5
616#define TWS6    6
617#define TWS7    7
618
619#define TWAR    _SFR_MEM8(0xBA)
620#define TWGCE   0
621#define TWA0    1
622#define TWA1    2
623#define TWA2    3
624#define TWA3    4
625#define TWA4    5
626#define TWA5    6
627#define TWA6    7
628
629#define TWDR    _SFR_MEM8(0xBB)
630
631#define TWCR    _SFR_MEM8(0xBC)
632#define TWIE    0
633#define TWEN    2
634#define TWWC    3
635#define TWSTO   4
636#define TWSTA   5
637#define TWEA    6
638#define TWINT   7
639
640#define TWAMR   _SFR_MEM8(0xBD)
641#define TWAM0   1
642#define TWAM1   2
643#define TWAM2   3
644#define TWAM3   4
645#define TWAM4   5
646#define TWAM5   6
647#define TWAM6   7
648
649/* Reserved [0xBE..0xBF] */
650
651#define UCSR0A  _SFR_MEM8(0xC0)
652#define MPCM0   0
653#define U2X0    1
654#define UPE0    2
655#define DOR0    3
656#define FE0     4
657#define UDRE0   5
658#define TXC0    6
659#define RXC0    7
660
661#define UCSR0B  _SFR_MEM8(0xC1)
662#define TXB80   0
663#define RXB80   1
664#define UCSZ02  2
665#define TXEN0   3
666#define RXEN0   4
667#define UDRIE0  5
668#define TXCIE0  6
669#define RXCIE0  7
670
671#define UCSR0C  _SFR_MEM8(0xC2)
672#define UCPOL0  0
673#define UCSZ00  1
674#define UCSZ01  2
675#define USBS0   3
676#define UPM00   4
677#define UPM01   5
678#define UMSEL00 6
679#define UMSEL01 7
680
681#define UCSR0D  _SFR_MEM8(0xC3)
682#define SFDE    5
683#define RXS     6
684#define RXSIE   7
685
686/* Combine UBRR0L and UBRR0H */
687#define UBRR0   _SFR_MEM16(0xC4)
688
689#define UBRR0L  _SFR_MEM8(0xC4)
690#define UBRR0H  _SFR_MEM8(0xC5)
691
692#define UDR0    _SFR_MEM8(0xC6)
693
694/* Reserved [0xC7..0xEF] */
695
696#define DEVID0  _SFR_MEM8(0xF0)
697
698#define DEVID1  _SFR_MEM8(0xF1)
699
700#define DEVID2  _SFR_MEM8(0xF2)
701
702#define DEVID3  _SFR_MEM8(0xF3)
703
704#define DEVID4  _SFR_MEM8(0xF4)
705
706#define DEVID5  _SFR_MEM8(0xF5)
707
708#define DEVID6  _SFR_MEM8(0xF6)
709
710#define DEVID7  _SFR_MEM8(0xF7)
711
712#define DEVID8  _SFR_MEM8(0xF8)
713
714
715
716/* Values and associated defines */
717
718
719#define SLEEP_MODE_IDLE (0x00<<1)
720#define SLEEP_MODE_ADC (0x01<<1)
721#define SLEEP_MODE_PWR_DOWN (0x02<<1)
722#define SLEEP_MODE_PWR_SAVE (0x03<<1)
723#define SLEEP_MODE_STANDBY (0x06<<1)
724#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
725
726/* Interrupt vectors */
727/* Vector 0 is the reset vector */
728/* External Interrupt Request 0 */
729#define INT0_vect            _VECTOR(1)
730#define INT0_vect_num        1
731
732/* External Interrupt Request 1 */
733#define INT1_vect            _VECTOR(2)
734#define INT1_vect_num        2
735
736/* Pin Change Interrupt Request 0 */
737#define PCINT0_vect            _VECTOR(3)
738#define PCINT0_vect_num        3
739
740/* Pin Change Interrupt Request 0 */
741#define PCINT1_vect            _VECTOR(4)
742#define PCINT1_vect_num        4
743
744/* Pin Change Interrupt Request 1 */
745#define PCINT2_vect            _VECTOR(5)
746#define PCINT2_vect_num        5
747
748/* Watchdog Time-out Interrupt */
749#define WDT_vect            _VECTOR(6)
750#define WDT_vect_num        6
751
752/* Timer/Counter2 Compare Match A */
753#define TIMER2_COMPA_vect            _VECTOR(7)
754#define TIMER2_COMPA_vect_num        7
755
756/* Timer/Counter2 Compare Match A */
757#define TIMER2_COMPB_vect            _VECTOR(8)
758#define TIMER2_COMPB_vect_num        8
759
760/* Timer/Counter2 Overflow */
761#define TIMER2_OVF_vect            _VECTOR(9)
762#define TIMER2_OVF_vect_num        9
763
764/* Timer/Counter1 Capture Event */
765#define TIMER1_CAPT_vect            _VECTOR(10)
766#define TIMER1_CAPT_vect_num        10
767
768/* Timer/Counter1 Compare Match A */
769#define TIMER1_COMPA_vect            _VECTOR(11)
770#define TIMER1_COMPA_vect_num        11
771
772/* Timer/Counter1 Compare Match B */
773#define TIMER1_COMPB_vect            _VECTOR(12)
774#define TIMER1_COMPB_vect_num        12
775
776/* Timer/Counter1 Overflow */
777#define TIMER1_OVF_vect            _VECTOR(13)
778#define TIMER1_OVF_vect_num        13
779
780/* TimerCounter0 Compare Match A */
781#define TIMER0_COMPA_vect            _VECTOR(14)
782#define TIMER0_COMPA_vect_num        14
783
784/* TimerCounter0 Compare Match B */
785#define TIMER0_COMPB_vect            _VECTOR(15)
786#define TIMER0_COMPB_vect_num        15
787
788/* Timer/Couner0 Overflow */
789#define TIMER0_OVF_vect            _VECTOR(16)
790#define TIMER0_OVF_vect_num        16
791
792/* SPI Serial Transfer Complete */
793#define SPI_STC_vect            _VECTOR(17)
794#define SPI_STC_vect_num        17
795
796/* USART Rx Complete */
797#define USART_RX_vect            _VECTOR(18)
798#define USART_RX_vect_num        18
799
800/* USART, Data Register Empty */
801#define USART_UDRE_vect            _VECTOR(19)
802#define USART_UDRE_vect_num        19
803
804/* USART Tx Complete */
805#define USART_TX_vect            _VECTOR(20)
806#define USART_TX_vect_num        20
807
808/* ADC Conversion Complete */
809#define ADC_vect            _VECTOR(21)
810#define ADC_vect_num        21
811
812/* EEPROM Ready */
813#define EE_READY_vect            _VECTOR(22)
814#define EE_READY_vect_num        22
815
816/* Analog Comparator */
817#define ANALOG_COMP_vect            _VECTOR(23)
818#define ANALOG_COMP_vect_num        23
819
820/* Two-wire Serial Interface */
821#define TWI_vect            _VECTOR(24)
822#define TWI_vect_num        24
823
824/* Store Program Memory Read */
825#define SPM_Ready_vect            _VECTOR(25)
826#define SPM_Ready_vect_num        25
827
828/* USART Start Edge Interrupt */
829#define USART_START_vect            _VECTOR(26)
830#define USART_START_vect_num        26
831
832#define _VECTORS_SIZE 54
833
834
835/* Constants */
836
837#define SPM_PAGESIZE 64
838#define FLASHSTART   0x0000
839#define FLASHEND     0x1FFF
840#define RAMSTART     0x0100
841#define RAMSIZE      1024
842#define RAMEND       0x04FF
843#define E2START     0
844#define E2SIZE      512
845#define E2PAGESIZE  4
846#define E2END       0x01FF
847#define XRAMEND      RAMEND
848
849
850/* Fuses */
851
852#define FUSE_MEMORY_SIZE 3
853
854/* Low Fuse Byte */
855#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
856#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
857#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
858#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
859#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
860#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
861#define FUSE_CKOUT       (unsigned char)~_BV(6)
862#define FUSE_CKDIV8      (unsigned char)~_BV(7)
863#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
864
865
866/* High Fuse Byte */
867#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
868#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
869#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
870#define FUSE_EESAVE      (unsigned char)~_BV(3)
871#define FUSE_WDTON       (unsigned char)~_BV(4)
872#define FUSE_SPIEN       (unsigned char)~_BV(5)
873#define FUSE_DWEN        (unsigned char)~_BV(6)
874#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
875#define HFUSE_DEFAULT    (FUSE_SPIEN)
876
877
878/* Extended Fuse Byte */
879#define FUSE_BOOTRST     (unsigned char)~_BV(0)
880#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
881#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
882#define EFUSE_DEFAULT    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
883
884
885
886/* Lock Bits */
887#define __LOCK_BITS_EXIST
888#define __BOOT_LOCK_BITS_0_EXIST
889#define __BOOT_LOCK_BITS_1_EXIST
890
891
892/* Signature */
893#define SIGNATURE_0 0x1E
894#define SIGNATURE_1 0x93
895#define SIGNATURE_2 0x16
896
897
898#endif /* #ifdef _AVR_ATMEGA88PB_H_INCLUDED */
899
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