source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iom8u2.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 3 years ago

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1/* Copyright (c) 2009 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iom8u2.h 2245 2011-05-12 22:42:21Z arcanum $ */
32
33/* avr/iom8u2.h - definitions for ATmega8U2 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iom8u2.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_ATmega8U2_H_
49#define _AVR_ATmega8U2_H_ 1
50
51
52/* Registers and associated bit numbers. */
53
54#define PINB _SFR_IO8(0x03)
55#define PINB0 0
56#define PINB1 1
57#define PINB2 2
58#define PINB3 3
59#define PINB4 4
60#define PINB5 5
61#define PINB6 6
62#define PINB7 7
63
64#define DDRB _SFR_IO8(0x04)
65#define DDB0 0
66#define DDB1 1
67#define DDB2 2
68#define DDB3 3
69#define DDB4 4
70#define DDB5 5
71#define DDB6 6
72#define DDB7 7
73
74#define PORTB _SFR_IO8(0x05)
75#define PORTB0 0
76#define PORTB1 1
77#define PORTB2 2
78#define PORTB3 3
79#define PORTB4 4
80#define PORTB5 5
81#define PORTB6 6
82#define PORTB7 7
83
84#define PINC _SFR_IO8(0x06)
85#define PINC0 0
86#define PINC1 1
87#define PINC2 2
88#define PINC4 4
89#define PINC5 5
90#define PINC6 6
91#define PINC7 7
92
93#define DDRC _SFR_IO8(0x07)
94#define DDC0 0
95#define DDC1 1
96#define DDC2 2
97#define DDC4 4
98#define DDC5 5
99#define DDC6 6
100#define DDC7 7
101
102#define PORTC _SFR_IO8(0x08)
103#define PORTC0 0
104#define PORTC1 1
105#define PORTC2 2
106#define PORTC4 4
107#define PORTC5 5
108#define PORTC6 6
109#define PORTC7 7
110
111#define PIND _SFR_IO8(0x09)
112#define PIND0 0
113#define PIND1 1
114#define PIND2 2
115#define PIND3 3
116#define PIND4 4
117#define PIND5 5
118#define PIND6 6
119#define PIND7 7
120
121#define DDRD _SFR_IO8(0x0A)
122#define DDD0 0
123#define DDD1 1
124#define DDD2 2
125#define DDD3 3
126#define DDD4 4
127#define DDD5 5
128#define DDD6 6
129#define DDD7 7
130
131#define PORTD _SFR_IO8(0x0B)
132#define PORTD0 0
133#define PORTD1 1
134#define PORTD2 2
135#define PORTD3 3
136#define PORTD4 4
137#define PORTD5 5
138#define PORTD6 6
139#define PORTD7 7
140
141#define TIFR0 _SFR_IO8(0x15)
142#define TOV0 0
143#define OCF0A 1
144#define OCF0B 2
145
146#define TIFR1 _SFR_IO8(0x16)
147#define TOV1 0
148#define OCF1A 1
149#define OCF1B 2
150#define OCF1C 3
151#define ICF1 5
152
153#define PCIFR _SFR_IO8(0x1B)
154#define PCIF0 0
155#define PCIF1 1
156
157#define EIFR _SFR_IO8(0x1C)
158#define INTF0 0
159#define INTF1 1
160#define INTF2 2
161#define INTF3 3
162#define INTF4 4
163#define INTF5 5
164#define INTF6 6
165#define INTF7 7
166
167#define EIMSK _SFR_IO8(0x1D)
168#define INT0 0
169#define INT1 1
170#define INT2 2
171#define INT3 3
172#define INT4 4
173#define INT5 5
174#define INT6 6
175#define INT7 7
176
177#define GPIOR0 _SFR_IO8(0x1E)
178#define GPIOR00 0
179#define GPIOR01 1
180#define GPIOR02 2
181#define GPIOR03 3
182#define GPIOR04 4
183#define GPIOR05 5
184#define GPIOR06 6
185#define GPIOR07 7
186
187#define EECR _SFR_IO8(0x1F)
188#define EERE 0
189#define EEPE 1
190#define EEMPE 2
191#define EERIE 3
192#define EEPM0 4
193#define EEPM1 5
194
195#define EEDR _SFR_IO8(0x20)
196#define EEDR0 0
197#define EEDR1 1
198#define EEDR2 2
199#define EEDR3 3
200#define EEDR4 4
201#define EEDR5 5
202#define EEDR6 6
203#define EEDR7 7
204
205#define EEAR _SFR_IO16(0x21)
206
207#define EEARL _SFR_IO8(0x21)
208#define EEAR0 0
209#define EEAR1 1
210#define EEAR2 2
211#define EEAR3 3
212#define EEAR4 4
213#define EEAR5 5
214#define EEAR6 6
215#define EEAR7 7
216
217#define EEARH _SFR_IO8(0x22)
218#define EEAR8 0
219#define EEAR9 1
220#define EEAR10 2
221#define EEAR11 3
222
223#define GTCCR _SFR_IO8(0x23)
224#define PSRSYNC 0
225#define TSM 7
226
227#define TCCR0A _SFR_IO8(0x24)
228#define WGM00 0
229#define WGM01 1
230#define COM0B0 4
231#define COM0B1 5
232#define COM0A0 6
233#define COM0A1 7
234
235#define TCCR0B _SFR_IO8(0x25)
236#define CS00 0
237#define CS01 1
238#define CS02 2
239#define WGM02 3
240#define FOC0B 6
241#define FOC0A 7
242
243#define TCNT0 _SFR_IO8(0x26)
244#define TCNT0_0 0
245#define TCNT0_1 1
246#define TCNT0_2 2
247#define TCNT0_3 3
248#define TCNT0_4 4
249#define TCNT0_5 5
250#define TCNT0_6 6
251#define TCNT0_7 7
252
253#define OCR0A _SFR_IO8(0x27)
254#define OCR0A_0 0
255#define OCR0A_1 1
256#define OCR0A_2 2
257#define OCR0A_3 3
258#define OCR0A_4 4
259#define OCR0A_5 5
260#define OCR0A_6 6
261#define OCR0A_7 7
262
263#define OCR0B _SFR_IO8(0x28)
264#define OCR0B_0 0
265#define OCR0B_1 1
266#define OCR0B_2 2
267#define OCR0B_3 3
268#define OCR0B_4 4
269#define OCR0B_5 5
270#define OCR0B_6 6
271#define OCR0B_7 7
272
273#define PLLCSR _SFR_IO8(0x29)
274#define PLOCK 0
275#define PLLE 1
276#define PLLP0 2
277#define PLLP1 3
278#define PLLP2 4
279
280#define GPIOR1 _SFR_IO8(0x2A)
281#define GPIOR10 0
282#define GPIOR11 1
283#define GPIOR12 2
284#define GPIOR13 3
285#define GPIOR14 4
286#define GPIOR15 5
287#define GPIOR16 6
288#define GPIOR17 7
289
290#define GPIOR2 _SFR_IO8(0x2B)
291#define GPIOR20 0
292#define GPIOR21 1
293#define GPIOR22 2
294#define GPIOR23 3
295#define GPIOR24 4
296#define GPIOR25 5
297#define GPIOR26 6
298#define GPIOR27 7
299
300#define SPCR _SFR_IO8(0x2C)
301#define SPR0 0
302#define SPR1 1
303#define CPHA 2
304#define CPOL 3
305#define MSTR 4
306#define DORD 5
307#define SPE 6
308#define SPIE 7
309
310#define SPSR _SFR_IO8(0x2D)
311#define SPI2X 0
312#define WCOL 6
313#define SPIF 7
314
315#define SPDR _SFR_IO8(0x2E)
316#define SPDR0 0
317#define SPDR1 1
318#define SPDR2 2
319#define SPDR3 3
320#define SPDR4 4
321#define SPDR5 5
322#define SPDR6 6
323#define SPDR7 7
324
325#define ACSR _SFR_IO8(0x30)
326#define ACIS0 0
327#define ACIS1 1
328#define ACIC 2
329#define ACIE 3
330#define ACI 4
331#define ACO 5
332#define ACBG 6
333#define ACD 7
334
335#define DWDR _SFR_IO8(0x31)
336#define DWDR0 0
337#define DWDR1 1
338#define DWDR2 2
339#define DWDR3 3
340#define DWDR4 4
341#define DWDR5 5
342#define DWDR6 6
343#define DWDR7 7
344
345#define SMCR _SFR_IO8(0x33)
346#define SE 0
347#define SM0 1
348#define SM1 2
349#define SM2 3
350
351#define MCUSR _SFR_IO8(0x34)
352#define PORF 0
353#define EXTRF 1
354#define BORF 2
355#define WDRF 3
356#define USBRF 5
357
358#define MCUCR _SFR_IO8(0x35)
359#define IVCE 0
360#define IVSEL 1
361#define PUD 4
362
363#define SPMCSR _SFR_IO8(0x37)
364#define SPMEN 0
365#define PGERS 1
366#define PGWRT 2
367#define BLBSET 3
368#define RWWSRE 4
369#define SIGRD 5
370#define RWWSB 6
371#define SPMIE 7
372
373#define EIND _SFR_IO8(0x3C)
374#define EIND0 0
375
376#define WDTCSR _SFR_MEM8(0x60)
377#define WDP0 0
378#define WDP1 1
379#define WDP2 2
380#define WDE 3
381#define WDCE 4
382#define WDP3 5
383#define WDIE 6
384#define WDIF 7
385
386#define CLKPR _SFR_MEM8(0x61)
387#define CLKPS0 0
388#define CLKPS1 1
389#define CLKPS2 2
390#define CLKPS3 3
391#define CLKPCE 7
392
393#define WDTCKD _SFR_MEM8(0x62)
394#define WCLKD0 0
395#define WCLKD1 1
396#define WDEWIE 2
397#define WDEWIF 3
398
399#define REGCR _SFR_MEM8(0x63)
400#define REGDIS 0
401
402#define PRR0 _SFR_MEM8(0x64)
403#define PRSPI 2
404#define PRTIM1 3
405#define PRTIM0 5
406
407#define __AVR_HAVE_PRR0 ((1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0))
408#define __AVR_HAVE_PRR0_PRSPI
409#define __AVR_HAVE_PRR0_PRTIM1
410#define __AVR_HAVE_PRR0_PRTIM0
411
412#define PRR1 _SFR_MEM8(0x65)
413#define PRUSART1 0
414#define PRUSB 7
415
416#define __AVR_HAVE_PRR1 ((1<<PRUSART1)|(1<<PRUSB))
417#define __AVR_HAVE_PRR1_PRUSART1
418#define __AVR_HAVE_PRR1_PRUSB
419
420#define OSCCAL _SFR_MEM8(0x66)
421#define CAL0 0
422#define CAL1 1
423#define CAL2 2
424#define CAL3 3
425#define CAL4 4
426#define CAL5 5
427#define CAL6 6
428#define CAL7 7
429
430#define PCICR _SFR_MEM8(0x68)
431#define PCIE0 0
432#define PCIE1 1
433
434#define EICRA _SFR_MEM8(0x69)
435#define ISC00 0
436#define ISC01 1
437#define ISC10 2
438#define ISC11 3
439#define ISC20 4
440#define ISC21 5
441#define ISC30 6
442#define ISC31 7
443
444#define EICRB _SFR_MEM8(0x6A)
445#define ISC40 0
446#define ISC41 1
447#define ISC50 2
448#define ISC51 3
449#define ISC60 4
450#define ISC61 5
451#define ISC70 6
452#define ISC71 7
453
454#define PCMSK0 _SFR_MEM8(0x6B)
455#define PCINT0 0
456#define PCINT1 1
457#define PCINT2 2
458#define PCINT3 3
459#define PCINT4 4
460#define PCINT5 5
461#define PCINT6 6
462#define PCINT7 7
463
464#define PCMSK1 _SFR_MEM8(0x6C)
465#define PCINT8 0
466#define PCINT9 1
467#define PCINT10 2
468#define PCINT11 3
469#define PCINT12 4
470
471#define TIMSK0 _SFR_MEM8(0x6E)
472#define TOIE0 0
473#define OCIE0A 1
474#define OCIE0B 2
475
476#define TIMSK1 _SFR_MEM8(0x6F)
477#define TOIE1 0
478#define OCIE1A 1
479#define OCIE1B 2
480#define OCIE1C 3
481#define ICIE1 5
482
483#define DIDR1 _SFR_MEM8(0x7F)
484#define AIN0D 0
485#define AIN1D 1
486#define AIN2D 2
487#define AIN3D 3
488#define AIN4D 4
489#define AIN5D 5
490#define AIN6D 6
491#define AIN7D 7
492
493#define TCCR1A _SFR_MEM8(0x80)
494#define WGM10 0
495#define WGM11 1
496#define COM1C0 2
497#define COM1C1 3
498#define COM1B0 4
499#define COM1B1 5
500#define COM1A0 6
501#define COM1A1 7
502
503#define TCCR1B _SFR_MEM8(0x81)
504#define CS10 0
505#define CS11 1
506#define CS12 2
507#define WGM12 3
508#define WGM13 4
509#define ICES1 6
510#define ICNC1 7
511
512#define TCCR1C _SFR_MEM8(0x82)
513#define FOC1C 5
514#define FOC1B 6
515#define FOC1A 7
516
517#define TCNT1 _SFR_MEM16(0x84)
518
519#define TCNT1L _SFR_MEM8(0x84)
520#define TCNT1L0 0
521#define TCNT1L1 1
522#define TCNT1L2 2
523#define TCNT1L3 3
524#define TCNT1L4 4
525#define TCNT1L5 5
526#define TCNT1L6 6
527#define TCNT1L7 7
528
529#define TCNT1H _SFR_MEM8(0x85)
530#define TCNT1H0 0
531#define TCNT1H1 1
532#define TCNT1H2 2
533#define TCNT1H3 3
534#define TCNT1H4 4
535#define TCNT1H5 5
536#define TCNT1H6 6
537#define TCNT1H7 7
538
539#define ICR1 _SFR_MEM16(0x86)
540
541#define ICR1L _SFR_MEM8(0x86)
542#define ICR1L0 0
543#define ICR1L1 1
544#define ICR1L2 2
545#define ICR1L3 3
546#define ICR1L4 4
547#define ICR1L5 5
548#define ICR1L6 6
549#define ICR1L7 7
550
551#define ICR1H _SFR_MEM8(0x87)
552#define ICR1H0 0
553#define ICR1H1 1
554#define ICR1H2 2
555#define ICR1H3 3
556#define ICR1H4 4
557#define ICR1H5 5
558#define ICR1H6 6
559#define ICR1H7 7
560
561#define OCR1A _SFR_MEM16(0x88)
562
563#define OCR1AL _SFR_MEM8(0x88)
564#define OCR1AL0 0
565#define OCR1AL1 1
566#define OCR1AL2 2
567#define OCR1AL3 3
568#define OCR1AL4 4
569#define OCR1AL5 5
570#define OCR1AL6 6
571#define OCR1AL7 7
572
573#define OCR1AH _SFR_MEM8(0x89)
574#define OCR1AH0 0
575#define OCR1AH1 1
576#define OCR1AH2 2
577#define OCR1AH3 3
578#define OCR1AH4 4
579#define OCR1AH5 5
580#define OCR1AH6 6
581#define OCR1AH7 7
582
583#define OCR1B _SFR_MEM16(0x8A)
584
585#define OCR1BL _SFR_MEM8(0x8A)
586#define OCR1BL0 0
587#define OCR1BL1 1
588#define OCR1BL2 2
589#define OCR1BL3 3
590#define OCR1BL4 4
591#define OCR1BL5 5
592#define OCR1BL6 6
593#define OCR1BL7 7
594
595#define OCR1BH _SFR_MEM8(0x8B)
596#define OCR1BH0 0
597#define OCR1BH1 1
598#define OCR1BH2 2
599#define OCR1BH3 3
600#define OCR1BH4 4
601#define OCR1BH5 5
602#define OCR1BH6 6
603#define OCR1BH7 7
604
605#define OCR1C _SFR_MEM16(0x8C)
606
607#define OCR1CL _SFR_MEM8(0x8C)
608#define OCR1CL0 0
609#define OCR1CL1 1
610#define OCR1CL2 2
611#define OCR1CL3 3
612#define OCR1CL4 4
613#define OCR1CL5 5
614#define OCR1CL6 6
615#define OCR1CL7 7
616
617#define OCR1CH _SFR_MEM8(0x8D)
618#define OCR1CH0 0
619#define OCR1CH1 1
620#define OCR1CH2 2
621#define OCR1CH3 3
622#define OCR1CH4 4
623#define OCR1CH5 5
624#define OCR1CH6 6
625#define OCR1CH7 7
626
627#define UCSR1A _SFR_MEM8(0xC8)
628#define MPCM1 0
629#define U2X1 1
630#define UPE1 2
631#define DOR1 3
632#define FE1 4
633#define UDRE1 5
634#define TXC1 6
635#define RXC1 7
636
637#define UCSR1B _SFR_MEM8(0xC9)
638#define TXB81 0
639#define RXB81 1
640#define UCSZ12 2
641#define TXEN1 3
642#define RXEN1 4
643#define UDRIE1 5
644#define TXCIE1 6
645#define RXCIE1 7
646
647#define UCSR1C _SFR_MEM8(0xCA)
648#define UCPOL1 0
649#define UCSZ10 1
650#define UCSZ11 2
651#define USBS1 3
652#define UPM10 4
653#define UPM11 5
654#define UMSEL10 6
655#define UMSEL11 7
656
657#define UCSR1D _SFR_MEM8(0xCB)
658#define RTSEN 0
659#define CTSEN 1
660
661#define UBRR1 _SFR_MEM16(0xCC)
662
663#define UBRR1L _SFR_MEM8(0xCC)
664#define UBRR1_0 0
665#define UBRR1_1 1
666#define UBRR1_2 2
667#define UBRR1_3 3
668#define UBRR1_4 4
669#define UBRR1_5 5
670#define UBRR1_6 6
671#define UBRR1_7 7
672
673#define UBRR1H _SFR_MEM8(0xCD)
674#define UBRR1_8 0
675#define UBRR1_9 1
676#define UBRR1_10 2
677#define UBRR1_11 3
678
679#define UDR1 _SFR_MEM8(0xCE)
680#define UDR1_0 0
681#define UDR1_1 1
682#define UDR1_2 2
683#define UDR1_3 3
684#define UDR1_4 4
685#define UDR1_5 5
686#define UDR1_6 6
687#define UDR1_7 7
688
689#define CLKSEL0 _SFR_MEM8(0xD0)
690#define CLKS 0
691#define EXTE 2
692#define RCE 3
693#define EXSUT0 4
694#define EXSUT1 5
695#define RCSUT0 6
696#define RCSUT1 7
697
698#define CLKSEL1 _SFR_MEM8(0xD1)
699#define EXCKSEL0 0
700#define EXCKSEL1 1
701#define EXCKSEL2 2
702#define EXCKSEL3 3
703#define RCCKSEL0 4
704#define RCCKSEL1 5
705#define RCCKSEL2 6
706#define RCCKSEL3 7
707
708#define CLKSTA _SFR_MEM8(0xD2)
709#define EXTON 0
710#define RCON 1
711
712#define USBCON _SFR_MEM8(0xD8)
713#define FRZCLK 5
714#define USBE 7
715
716#define UDCON _SFR_MEM8(0xE0)
717#define DETACH 0
718#define RMWKUP 1
719#define RSTCPU 2
720
721#define UDINT _SFR_MEM8(0xE1)
722#define SUSPI 0
723#define SOFI 2
724#define EORSTI 3
725#define WAKEUPI 4
726#define EORSMI 5
727#define UPRSMI 6
728
729#define UDIEN _SFR_MEM8(0xE2)
730#define SUSPE 0
731#define SOFE 2
732#define EORSTE 3
733#define WAKEUPE 4
734#define EORSME 5
735#define UPRSME 6
736
737#define UDADDR _SFR_MEM8(0xE3)
738#define UADD0 0
739#define UADD1 1
740#define UADD2 2
741#define UADD3 3
742#define UADD4 4
743#define UADD5 5
744#define UADD6 6
745#define ADDEN 7
746
747#define UDFNUM _SFR_MEM16(0xE4)
748
749#define UDFNUML _SFR_MEM8(0xE4)
750#define FNUM0 0
751#define FNUM1 1
752#define FNUM2 2
753#define FNUM3 3
754#define FNUM4 4
755#define FNUM5 5
756#define FNUM6 6
757#define FNUM7 7
758
759#define UDFNUMH _SFR_MEM8(0xE5)
760#define FNUM8 0
761#define FNUM9 1
762#define FNUM10 2
763
764#define UDMFN _SFR_MEM8(0xE6)
765#define FNCERR 4
766
767#define UEINTX _SFR_MEM8(0xE8)
768#define TXINI 0
769#define STALLEDI 1
770#define RXOUTI 2
771#define RXSTPI 3
772#define NAKOUTI 4
773#define RWAL 5
774#define NAKINI 6
775#define FIFOCON 7
776
777#define UENUM _SFR_MEM8(0xE9)
778#define EPNUM0 0
779#define EPNUM1 1
780#define EPNUM2 2
781
782#define UERST _SFR_MEM8(0xEA)
783#define EPRST0 0
784#define EPRST1 1
785#define EPRST2 2
786#define EPRST3 3
787#define EPRST4 4
788
789#define UECONX _SFR_MEM8(0xEB)
790#define EPEN 0
791#define RSTDT 3
792#define STALLRQC 4
793#define STALLRQ 5
794
795#define UECFG0X _SFR_MEM8(0xEC)
796#define EPDIR 0
797#define EPTYPE0 6
798#define EPTYPE1 7
799
800#define UECFG1X _SFR_MEM8(0xED)
801#define ALLOC 1
802#define EPBK0 2
803#define EPBK1 3
804#define EPSIZE0 4
805#define EPSIZE1 5
806#define EPSIZE2 6
807
808#define UESTA0X _SFR_MEM8(0xEE)
809#define NBUSYBK0 0
810#define NBUSYBK1 1
811#define DTSEQ0 2
812#define DTSEQ1 3
813#define UNDERFI 5
814#define OVERFI 6
815#define CFGOK 7
816
817#define UESTA1X _SFR_MEM8(0xEF)
818#define CURRBK0 0
819#define CURRBK1 1
820#define CTRLDIR 2
821
822#define UEIENX _SFR_MEM8(0xF0)
823#define TXINE 0
824#define STALLEDE 1
825#define RXOUTE 2
826#define RXSTPE 3
827#define NAKOUTE 4
828#define NAKINE 6
829#define FLERRE 7
830
831#define UEDATX _SFR_MEM8(0xF1)
832#define DAT0 0
833#define DAT1 1
834#define DAT2 2
835#define DAT3 3
836#define DAT4 4
837#define DAT5 5
838#define DAT6 6
839#define DAT7 7
840
841#define UEBCLX _SFR_MEM8(0xF2)
842#define BYCT0 0
843#define BYCT1 1
844#define BYCT2 2
845#define BYCT3 3
846#define BYCT4 4
847#define BYCT5 5
848#define BYCT6 6
849#define BYCT7 7
850
851#define UEINT _SFR_MEM8(0xF4)
852#define EPINT0 0
853#define EPINT1 1
854#define EPINT2 2
855#define EPINT3 3
856#define EPINT4 4
857
858#define UPOE    _SFR_MEM8(0XFB)
859#define UPWE1   7
860#define UPWE0   6
861#define UPDRV1  5
862#define UPDRV0  4
863#define SCKI    3
864#define DATAI   2
865#define DPI     1
866#define DMI     0
867
868
869/* Interrupt vectors */
870/* Vector 0 is the reset vector */
871#define INT0_vect_num  1
872#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
873#define INT1_vect_num  2
874#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
875#define INT2_vect_num  3
876#define INT2_vect      _VECTOR(3)  /* External Interrupt Request 2 */
877#define INT3_vect_num  4
878#define INT3_vect      _VECTOR(4)  /* External Interrupt Request 3 */
879#define INT4_vect_num  5
880#define INT4_vect      _VECTOR(5)  /* External Interrupt Request 4 */
881#define INT5_vect_num  6
882#define INT5_vect      _VECTOR(6)  /* External Interrupt Request 5 */
883#define INT6_vect_num  7
884#define INT6_vect      _VECTOR(7)  /* External Interrupt Request 6 */
885#define INT7_vect_num  8
886#define INT7_vect      _VECTOR(8)  /* External Interrupt Request 7 */
887#define PCINT0_vect_num  9
888#define PCINT0_vect      _VECTOR(9)  /* Pin Change Interrupt Request 0 */
889#define PCINT1_vect_num  10
890#define PCINT1_vect      _VECTOR(10)  /* Pin Change Interrupt Request 1 */
891#define USB_GEN_vect_num  11
892#define USB_GEN_vect      _VECTOR(11)  /* USB General Interrupt Request */
893#define USB_COM_vect_num  12
894#define USB_COM_vect      _VECTOR(12)  /* USB Endpoint/Pipe Interrupt Communication Request */
895#define WDT_vect_num  13
896#define WDT_vect      _VECTOR(13)  /* Watchdog Time-out Interrupt */
897#define TIMER1_CAPT_vect_num  14
898#define TIMER1_CAPT_vect      _VECTOR(14)  /* Timer/Counter2 Capture Event */
899#define TIMER1_COMPA_vect_num  15
900#define TIMER1_COMPA_vect      _VECTOR(15)  /* Timer/Counter2 Compare Match B */
901#define TIMER0_COMPA_vect_num  19
902#define TIMER0_COMPA_vect      _VECTOR(19)  /* Timer/Counter0 Compare Match A */
903#define TIMER0_COMPB_vect_num  20
904#define TIMER0_COMPB_vect      _VECTOR(20)  /* Timer/Counter0 Compare Match B */
905#define TIMER0_OVF_vect_num  21
906#define TIMER0_OVF_vect      _VECTOR(21)  /* Timer/Counter0 Overflow */
907#define SPI_STC_vect_num  22
908#define SPI_STC_vect      _VECTOR(22)  /* SPI Serial Transfer Complete */
909#define USART1_RX_vect_num  23
910#define USART1_RX_vect      _VECTOR(23)  /* USART1, Rx Complete */
911#define USART1_UDRE_vect_num  24
912#define USART1_UDRE_vect      _VECTOR(24)  /* USART1 Data register Empty */
913#define USART1_TX_vect_num  25
914#define USART1_TX_vect      _VECTOR(25)  /* USART1, Tx Complete */
915#define ANALOG_COMP_vect_num  26
916#define ANALOG_COMP_vect      _VECTOR(26)  /* Analog Comparator */
917#define EE_READY_vect_num  27
918#define EE_READY_vect      _VECTOR(27)  /* EEPROM Ready */
919#define SPM_READY_vect_num  28
920#define SPM_READY_vect      _VECTOR(28)  /* Store Program Memory Read */
921#define TIMER1_COMPB_vect_num  16
922#define TIMER1_COMPB_vect      _VECTOR(16)  /* Timer/Counter2 Compare Match B */
923#define TIMER1_COMPC_vect_num  17
924#define TIMER1_COMPC_vect      _VECTOR(17)  /* Timer/Counter2 Compare Match C */
925#define TIMER1_OVF_vect_num  18
926#define TIMER1_OVF_vect      _VECTOR(18)  /* Timer/Counter1 Overflow */
927
928#define _VECTOR_SIZE 4 /* Size of individual vector. */
929#define _VECTORS_SIZE (29 * _VECTOR_SIZE)
930
931
932/* Constants */
933#define SPM_PAGESIZE (128)
934#define RAMSTART     (0x100)
935#define RAMSIZE      (512)
936#define RAMEND       (RAMSTART + RAMSIZE - 1)
937#define XRAMSTART    (NA)
938#define XRAMSIZE     (0)
939#define XRAMEND      (RAMEND)
940#define E2END        (0x1FF)
941#define E2PAGESIZE   (4)
942#define FLASHEND     (0x1FFF)
943
944
945/* Fuses */
946#define FUSE_MEMORY_SIZE 3
947
948/* Low Fuse Byte */
949#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
950#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
951#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
952#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
953#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
954#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
955#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator options */
956#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
957#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
958
959/* High Fuse Byte */
960#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
961#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
962#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
963#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
964#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
965#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
966#define FUSE_RSTDISBL  (unsigned char)~_BV(6)  /* External Reset Disable */
967#define FUSE_DWEN  (unsigned char)~_BV(7)  /* dwbugWIRE Enable */
968#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
969
970/* Extended Fuse Byte */
971#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
972#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
973#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
974#define FUSE_HWBE  (unsigned char)~_BV(3)  /* Hardware Boot Enable */
975#define EFUSE_DEFAULT (0xFF)
976
977
978/* Lock Bits */
979#define __LOCK_BITS_EXIST
980#define __BOOT_LOCK_BITS_0_EXIST
981#define __BOOT_LOCK_BITS_1_EXIST
982
983
984/* Signature */
985#define SIGNATURE_0 0x1E
986#define SIGNATURE_1 0x93
987#define SIGNATURE_2 0x89
988
989
990#define SLEEP_MODE_IDLE (0x00<<1)
991#define SLEEP_MODE_PWR_DOWN (0x02<<1)
992#define SLEEP_MODE_PWR_SAVE (0x03<<1)
993#define SLEEP_MODE_STANDBY (0x06<<1)
994#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
995
996#endif /* _AVR_ATmega8U2_H_ */
997
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