source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iomx8.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

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1/* Copyright (c) 2004,2005, Theodore A. Roth
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iomx8.h 2235 2011-03-17 04:13:14Z arcanum $ */
32
33/* avr/iomx8.h - definitions for ATmega48, ATmega88 and ATmega168 */
34
35#ifndef _AVR_IOMX8_H_
36#define _AVR_IOMX8_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iomx8.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* I/O registers */
51
52/* Port B */
53
54#define PINB    _SFR_IO8 (0x03)
55/* PINB */
56#define PINB7   7
57#define PINB6   6
58#define PINB5   5
59#define PINB4   4
60#define PINB3   3
61#define PINB2   2
62#define PINB1   1
63#define PINB0   0
64
65#define DDRB    _SFR_IO8 (0x04)
66/* DDRB */
67#define DDB7    7
68#define DDB6    6
69#define DDB5    5
70#define DDB4    4
71#define DDB3    3
72#define DDB2    2
73#define DDB1    1
74#define DDB0    0
75
76#define PORTB   _SFR_IO8 (0x05)
77/* PORTB */
78#define PB7     7
79#define PB6     6
80#define PB5     5
81#define PB4     4
82#define PB3     3
83#define PB2     2
84#define PB1     1
85#define PB0     0
86
87/* Port C */
88
89#define PINC    _SFR_IO8 (0x06)
90/* PINC */
91#define PINC6   6
92#define PINC5   5
93#define PINC4   4
94#define PINC3   3
95#define PINC2   2
96#define PINC1   1
97#define PINC0   0
98
99#define DDRC    _SFR_IO8 (0x07)
100/* DDRC */
101#define DDC6    6
102#define DDC5    5
103#define DDC4    4
104#define DDC3    3
105#define DDC2    2
106#define DDC1    1
107#define DDC0    0
108
109#define PORTC   _SFR_IO8 (0x08)
110/* PORTC */
111#define PC6     6
112#define PC5     5
113#define PC4     4
114#define PC3     3
115#define PC2     2
116#define PC1     1
117#define PC0     0
118
119/* Port D */
120
121#define PIND    _SFR_IO8 (0x09)
122/* PIND */
123#define PIND7   7
124#define PIND6   6
125#define PIND5   5
126#define PIND4   4
127#define PIND3   3
128#define PIND2   2
129#define PIND1   1
130#define PIND0   0
131
132#define DDRD    _SFR_IO8 (0x0A)
133/* DDRD */
134#define DDD7    7
135#define DDD6    6
136#define DDD5    5
137#define DDD4    4
138#define DDD3    3
139#define DDD2    2
140#define DDD1    1
141#define DDD0    0
142
143#define PORTD   _SFR_IO8 (0x0B)
144/* PORTD */
145#define PD7     7
146#define PD6     6
147#define PD5     5
148#define PD4     4
149#define PD3     3
150#define PD2     2
151#define PD1     1
152#define PD0     0
153
154#define TIFR0   _SFR_IO8 (0x15)
155/* TIFR0 */
156#define OCF0B   2
157#define OCF0A   1
158#define TOV0    0
159
160#define TIFR1   _SFR_IO8 (0x16)
161/* TIFR1 */
162#define ICF1    5
163#define OCF1B   2
164#define OCF1A   1
165#define TOV1    0
166
167#define TIFR2   _SFR_IO8 (0x17)
168/* TIFR2 */
169#define OCF2B   2
170#define OCF2A   1
171#define TOV2    0
172
173#define PCIFR   _SFR_IO8 (0x1B)
174/* PCIFR */
175#define PCIF2   2
176#define PCIF1   1
177#define PCIF0   0
178
179#define EIFR    _SFR_IO8 (0x1C)
180/* EIFR */
181#define INTF1   1
182#define INTF0   0
183
184#define EIMSK   _SFR_IO8 (0x1D)
185/* EIMSK */
186#define INT1    1
187#define INT0    0
188
189#define GPIOR0  _SFR_IO8 (0x1E)
190
191#define EECR    _SFR_IO8(0x1F)
192/* EECT - EEPROM Control Register */
193#define EEPM1   5
194#define EEPM0   4
195#define EERIE   3
196#define EEMPE   2
197#define EEPE    1
198#define EERE    0
199
200#define EEDR    _SFR_IO8(0X20)
201
202/* Combine EEARL and EEARH */
203#define EEAR    _SFR_IO16(0x21)
204#define EEARL   _SFR_IO8(0x21)
205#define EEARH   _SFR_IO8(0X22)
206/*
207Even though EEARH is not used by the mega48, the EEAR8 bit in the register
208must be written to 0, according to the datasheet, hence the EEARH register
209must be defined for the mega48.
210*/
211/* 6-char sequence denoting where to find the EEPROM registers in memory space.
212   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
213   subroutines.
214   First two letters:  EECR address.
215   Second two letters: EEDR address.
216   Last two letters:   EEAR address.  */
217#define __EEPROM_REG_LOCATIONS__ 1F2021
218
219
220#define GTCCR   _SFR_IO8 (0x23)
221/* GTCCR */
222#define TSM     7
223#define PSRASY  1
224#define PSRSYNC 0
225
226#define TCCR0A  _SFR_IO8 (0x24)
227/* TCCR0A */
228#define COM0A1  7
229#define COM0A0  6
230#define COM0B1  5
231#define COM0B0  4
232#define WGM01   1
233#define WGM00   0
234
235#define TCCR0B  _SFR_IO8 (0x25)
236/* TCCR0A */
237#define FOC0A   7
238#define FOC0B   6
239#define WGM02   3
240#define CS02    2
241#define CS01    1
242#define CS00    0
243
244#define TCNT0   _SFR_IO8 (0x26)
245#define OCR0A   _SFR_IO8 (0x27)
246#define OCR0B   _SFR_IO8 (0x28)
247
248#define GPIOR1  _SFR_IO8 (0x2A)
249#define GPIOR2  _SFR_IO8 (0x2B)
250
251#define SPCR    _SFR_IO8 (0x2C)
252/* SPCR */
253#define SPIE    7
254#define SPE     6
255#define DORD    5
256#define MSTR    4
257#define CPOL    3
258#define CPHA    2
259#define SPR1    1
260#define SPR0    0
261
262#define SPSR    _SFR_IO8 (0x2D)
263/* SPSR */
264#define SPIF    7
265#define WCOL    6
266#define SPI2X   0
267
268#define SPDR    _SFR_IO8 (0x2E)
269
270#define ACSR    _SFR_IO8 (0x30)
271/* ACSR */
272#define ACD     7
273#define ACBG    6
274#define ACO     5
275#define ACI     4
276#define ACIE    3
277#define ACIC    2
278#define ACIS1   1
279#define ACIS0   0
280
281#define MONDR   _SFR_IO8 (0x31)
282
283#define SMCR    _SFR_IO8 (0x33)
284/* SMCR */
285#define SM2     3
286#define SM1     2
287#define SM0     1
288#define SE      0
289
290#define MCUSR   _SFR_IO8 (0x34)
291/* MCUSR */
292#define WDRF    3
293#define BORF    2
294#define EXTRF   1
295#define PORF    0
296
297#define MCUCR   _SFR_IO8 (0x35)
298/* MCUCR */
299#define PUD     4
300#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__)  || defined (__AVR_ATmega48A__) || defined(__AVR_ATmega48PA__)
301#define IVSEL   1
302#define IVCE    0
303#endif
304
305#define SPMCSR  _SFR_IO8 (0x37)
306/* SPMCSR */
307#define SPMIE     7
308#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) || (__AVR_ATmega88P__) || defined (__AVR_ATmega168P__) || (__AVR_ATmega88A__) || defined (__AVR_ATmega168A__) || (__AVR_ATmega88PA__) || defined (__AVR_ATmega168PA__)
309#  define RWWSB   6
310#  define RWWSRE  4
311#endif
312#if defined(__AVR_ATmega48A) || defined(__AVR_ATmega48PA) || defined(__AVR_ATmega88A) || defined(__AVR_ATmega88PA) || defined(__AVR_ATmega168A) || defined(__AVR_ATmega168PA)
313        #define SIGRD 5
314#endif
315#define BLBSET    3
316#define PGWRT     2
317#define PGERS     1
318#define SELFPRGEN 0
319#define SPMEN     0
320
321/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
322/* 0x3F SREG      [defined in <avr/io.h>] */
323
324#define WDTCSR  _SFR_MEM8 (0x60)
325/* WDTCSR */
326#define WDIF    7
327#define WDIE    6
328#define WDP3    5
329#define WDCE    4
330#define WDE     3
331#define WDP2    2
332#define WDP1    1
333#define WDP0    0
334
335#define CLKPR   _SFR_MEM8 (0x61)
336/* CLKPR */
337#define CLKPCE  7
338#define CLKPS3  3
339#define CLKPS2  2
340#define CLKPS1  1
341#define CLKPS0  0
342
343#define PRR     _SFR_MEM8 (0x64)
344/* PRR */
345#define PRTWI    7
346#define PRTIM2   6
347#define PRTIM0   5
348#define PRTIM1   3
349#define PRSPI    2
350#define PRUSART0 1
351#define PRADC    0
352
353#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI))
354#define __AVR_HAVE_PRR_PRADC
355#define __AVR_HAVE_PRR_PRUSART0
356#define __AVR_HAVE_PRR_PRSPI
357#define __AVR_HAVE_PRR_PRTIM1
358#define __AVR_HAVE_PRR_PRTIM0
359#define __AVR_HAVE_PRR_PRTIM2
360#define __AVR_HAVE_PRR_PRTWI
361
362#define OSCCAL  _SFR_MEM8 (0x66)
363
364#define PCICR   _SFR_MEM8 (0x68)
365/* PCICR */
366#define PCIE2   2
367#define PCIE1   1
368#define PCIE0   0
369
370#define EICRA   _SFR_MEM8 (0x69)
371/* EICRA */
372#define ISC11   3
373#define ISC10   2
374#define ISC01   1
375#define ISC00   0
376
377#define PCMSK0  _SFR_MEM8 (0x6B)
378/* PCMSK0 */
379#define PCINT7    7
380#define PCINT6    6
381#define PCINT5    5
382#define PCINT4    4
383#define PCINT3    3
384#define PCINT2    2
385#define PCINT1    1
386#define PCINT0    0
387
388#define PCMSK1  _SFR_MEM8 (0x6C)
389/* PCMSK1 */
390#define PCINT14   6
391#define PCINT13   5
392#define PCINT12   4
393#define PCINT11   3
394#define PCINT10   2
395#define PCINT9    1
396#define PCINT8    0
397
398#define PCMSK2  _SFR_MEM8 (0x6D)
399/* PCMSK2 */
400#define PCINT23   7
401#define PCINT22   6
402#define PCINT21   5
403#define PCINT20   4
404#define PCINT19   3
405#define PCINT18   2
406#define PCINT17   1
407#define PCINT16   0
408
409#define TIMSK0  _SFR_MEM8 (0x6E)
410/* TIMSK0 */
411#define OCIE0B  2
412#define OCIE0A  1
413#define TOIE0   0
414
415#define TIMSK1  _SFR_MEM8 (0x6F)
416/* TIMSK1 */
417#define ICIE1   5
418#define OCIE1B  2
419#define OCIE1A  1
420#define TOIE1   0
421
422#define TIMSK2  _SFR_MEM8 (0x70)
423/* TIMSK2 */
424#define OCIE2B  2
425#define OCIE2A  1
426#define TOIE2   0
427
428#ifndef __ASSEMBLER__
429#define ADC     _SFR_MEM16 (0x78)
430#endif
431#define ADCW    _SFR_MEM16 (0x78)
432#define ADCL    _SFR_MEM8 (0x78)
433#define ADCH    _SFR_MEM8 (0x79)
434
435#define ADCSRA  _SFR_MEM8 (0x7A)
436/* ADCSRA */
437#define ADEN    7
438#define ADSC    6
439#define ADATE   5
440#define ADIF    4
441#define ADIE    3
442#define ADPS2   2
443#define ADPS1   1
444#define ADPS0   0
445
446#define ADCSRB  _SFR_MEM8 (0x7B)
447/* ADCSRB */
448#define ACME    6
449#define ADTS2   2
450#define ADTS1   1
451#define ADTS0   0
452
453#define ADMUX   _SFR_MEM8 (0x7C)
454/* ADMUX */
455#define REFS1   7
456#define REFS0   6
457#define ADLAR   5
458#define MUX3    3
459#define MUX2    2
460#define MUX1    1
461#define MUX0    0
462
463#define DIDR0   _SFR_MEM8 (0x7E)
464/* DIDR0 */
465#define ADC5D   5
466#define ADC4D   4
467#define ADC3D   3
468#define ADC2D   2
469#define ADC1D   1
470#define ADC0D   0
471
472#define DIDR1   _SFR_MEM8 (0x7F)
473/* DIDR1 */
474#define AIN1D   1
475#define AIN0D   0
476
477#define TCCR1A  _SFR_MEM8 (0x80)
478/* TCCR1A */
479#define COM1A1  7
480#define COM1A0  6
481#define COM1B1  5
482#define COM1B0  4
483#define WGM11   1
484#define WGM10   0
485
486#define TCCR1B  _SFR_MEM8 (0x81)
487/* TCCR1B */
488#define ICNC1   7
489#define ICES1   6
490#define WGM13   4
491#define WGM12   3
492#define CS12    2
493#define CS11    1
494#define CS10    0
495
496#define TCCR1C  _SFR_MEM8 (0x82)
497/* TCCR1C */
498#define FOC1A   7
499#define FOC1B   6
500
501#define TCNT1   _SFR_MEM16 (0x84)
502#define TCNT1L  _SFR_MEM8 (0x84)
503#define TCNT1H  _SFR_MEM8 (0x85)
504
505#define ICR1    _SFR_MEM16 (0x86)
506#define ICR1L   _SFR_MEM8 (0x86)
507#define ICR1H   _SFR_MEM8 (0x87)
508
509#define OCR1A   _SFR_MEM16 (0x88)
510#define OCR1AL  _SFR_MEM8 (0x88)
511#define OCR1AH  _SFR_MEM8 (0x89)
512
513#define OCR1B   _SFR_MEM16 (0x8A)
514#define OCR1BL  _SFR_MEM8 (0x8A)
515#define OCR1BH  _SFR_MEM8 (0x8B)
516
517#define TCCR2A  _SFR_MEM8 (0xB0)
518/* TCCR2A */
519#define COM2A1  7
520#define COM2A0  6
521#define COM2B1  5
522#define COM2B0  4
523#define WGM21   1
524#define WGM20   0
525
526#define TCCR2B  _SFR_MEM8 (0xB1)
527/* TCCR2B */
528#define FOC2A   7
529#define FOC2B   6
530#define WGM22   3
531#define CS22    2
532#define CS21    1
533#define CS20    0
534
535#define TCNT2   _SFR_MEM8 (0xB2)
536#define OCR2A   _SFR_MEM8 (0xB3)
537#define OCR2B   _SFR_MEM8 (0xB4)
538
539#define ASSR    _SFR_MEM8 (0xB6)
540/* ASSR */
541#define EXCLK    6
542#define AS2      5
543#define TCN2UB   4
544#define OCR2AUB  3
545#define OCR2BUB  2
546#define TCR2AUB  1
547#define TCR2BUB  0
548
549#define TWBR    _SFR_MEM8 (0xB8)
550
551#define TWSR    _SFR_MEM8 (0xB9)
552/* TWSR */
553#define TWS7    7
554#define TWS6    6
555#define TWS5    5
556#define TWS4    4
557#define TWS3    3
558#define TWPS1   1
559#define TWPS0   0
560
561#define TWAR    _SFR_MEM8 (0xBA)
562/* TWAR */
563#define TWA6    7
564#define TWA5    6
565#define TWA4    5
566#define TWA3    4
567#define TWA2    3
568#define TWA1    2
569#define TWA0    1
570#define TWGCE   0
571
572#define TWDR    _SFR_MEM8 (0xBB)
573
574#define TWCR    _SFR_MEM8 (0xBC)
575/* TWCR */
576#define TWINT   7
577#define TWEA    6
578#define TWSTA   5
579#define TWSTO   4
580#define TWWC    3
581#define TWEN    2
582#define TWIE    0
583
584#define TWAMR   _SFR_MEM8 (0xBD)
585/* TWAMR */
586#define TWAM6   7
587#define TWAM5   6
588#define TWAM4   5
589#define TWAM3   4
590#define TWAM2   3
591#define TWAM1   2
592#define TWAM0   1
593
594#define UCSR0A  _SFR_MEM8 (0xC0)
595/* UCSR0A */
596#define RXC0    7
597#define TXC0    6
598#define UDRE0   5
599#define FE0     4
600#define DOR0    3
601#define UPE0    2
602#define U2X0    1
603#define MPCM0   0
604
605#define UCSR0B  _SFR_MEM8 (0xC1)
606/* UCSR0B */
607#define RXCIE0  7
608#define TXCIE0  6
609#define UDRIE0  5
610#define RXEN0   4
611#define TXEN0   3
612#define UCSZ02  2
613#define RXB80   1
614#define TXB80   0
615
616#define UCSR0C  _SFR_MEM8 (0xC2)
617/* UCSR0C */
618#define UMSEL01  7
619#define UMSEL00  6
620#define UPM01    5
621#define UPM00    4
622#define USBS0    3
623#define UCSZ01   2
624#define UDORD0   2
625#define UCSZ00   1
626#define UCPHA0   1
627#define UCPOL0   0
628
629#define UBRR0   _SFR_MEM16 (0xC4)
630#define UBRR0L  _SFR_MEM8 (0xC4)
631#define UBRR0H  _SFR_MEM8 (0xC5)
632#define UDR0    _SFR_MEM8 (0xC6)
633
634/* Interrupt vectors */
635
636/* External Interrupt Request 0 */
637#define INT0_vect_num           1
638#define INT0_vect                       _VECTOR(1)
639#define SIG_INTERRUPT0                  _VECTOR(1)
640
641/* External Interrupt Request 1 */
642#define INT1_vect_num           2
643#define INT1_vect                       _VECTOR(2)
644#define SIG_INTERRUPT1                  _VECTOR(2)
645
646/* Pin Change Interrupt Request 0 */
647#define PCINT0_vect_num         3
648#define PCINT0_vect                     _VECTOR(3)
649#define SIG_PIN_CHANGE0                 _VECTOR(3)
650
651/* Pin Change Interrupt Request 0 */
652#define PCINT1_vect_num         4
653#define PCINT1_vect                     _VECTOR(4)
654#define SIG_PIN_CHANGE1                 _VECTOR(4)
655
656/* Pin Change Interrupt Request 1 */
657#define PCINT2_vect_num         5
658#define PCINT2_vect                     _VECTOR(5)
659#define SIG_PIN_CHANGE2                 _VECTOR(5)
660
661/* Watchdog Time-out Interrupt */
662#define WDT_vect_num            6
663#define WDT_vect                        _VECTOR(6)
664#define SIG_WATCHDOG_TIMEOUT            _VECTOR(6)
665
666/* Timer/Counter2 Compare Match A */
667#define TIMER2_COMPA_vect_num   7
668#define TIMER2_COMPA_vect               _VECTOR(7)
669#define SIG_OUTPUT_COMPARE2A            _VECTOR(7)
670
671/* Timer/Counter2 Compare Match A */
672#define TIMER2_COMPB_vect_num   8
673#define TIMER2_COMPB_vect               _VECTOR(8)
674#define SIG_OUTPUT_COMPARE2B            _VECTOR(8)
675
676/* Timer/Counter2 Overflow */
677#define TIMER2_OVF_vect_num             9
678#define TIMER2_OVF_vect                 _VECTOR(9)
679#define SIG_OVERFLOW2                   _VECTOR(9)
680
681/* Timer/Counter1 Capture Event */
682#define TIMER1_CAPT_vect_num    10
683#define TIMER1_CAPT_vect                _VECTOR(10)
684#define SIG_INPUT_CAPTURE1              _VECTOR(10)
685
686/* Timer/Counter1 Compare Match A */
687#define TIMER1_COMPA_vect_num   11
688#define TIMER1_COMPA_vect               _VECTOR(11)
689#define SIG_OUTPUT_COMPARE1A            _VECTOR(11)
690
691/* Timer/Counter1 Compare Match B */
692#define TIMER1_COMPB_vect_num   12
693#define TIMER1_COMPB_vect               _VECTOR(12)
694#define SIG_OUTPUT_COMPARE1B            _VECTOR(12)
695
696/* Timer/Counter1 Overflow */
697#define TIMER1_OVF_vect_num             13
698#define TIMER1_OVF_vect                 _VECTOR(13)
699#define SIG_OVERFLOW1                   _VECTOR(13)
700
701/* TimerCounter0 Compare Match A */
702#define TIMER0_COMPA_vect_num   14
703#define TIMER0_COMPA_vect               _VECTOR(14)
704#define SIG_OUTPUT_COMPARE0A            _VECTOR(14)
705
706/* TimerCounter0 Compare Match B */
707#define TIMER0_COMPB_vect_num   15
708#define TIMER0_COMPB_vect               _VECTOR(15)
709#define SIG_OUTPUT_COMPARE0B            _VECTOR(15)
710
711/* Timer/Couner0 Overflow */
712#define TIMER0_OVF_vect_num             16
713#define TIMER0_OVF_vect                 _VECTOR(16)
714#define SIG_OVERFLOW0                   _VECTOR(16)
715
716/* SPI Serial Transfer Complete */
717#define SPI_STC_vect_num                17
718#define SPI_STC_vect                    _VECTOR(17)
719#define SIG_SPI                         _VECTOR(17)
720
721/* USART Rx Complete */
722#define USART_RX_vect_num               18
723#define USART_RX_vect                   _VECTOR(18)
724#define SIG_USART_RECV                  _VECTOR(18)
725
726/* USART, Data Register Empty */
727#define USART_UDRE_vect_num             19
728#define USART_UDRE_vect                 _VECTOR(19)
729#define SIG_USART_DATA                  _VECTOR(19)
730
731/* USART Tx Complete */
732#define USART_TX_vect_num               20
733#define USART_TX_vect                   _VECTOR(20)
734#define SIG_USART_TRANS                 _VECTOR(20)
735
736/* ADC Conversion Complete */
737#define ADC_vect_num            21
738#define ADC_vect                        _VECTOR(21)
739#define SIG_ADC                         _VECTOR(21)
740
741/* EEPROM Ready */
742#define EE_READY_vect_num               22
743#define EE_READY_vect                   _VECTOR(22)
744#define SIG_EEPROM_READY                _VECTOR(22)
745
746/* Analog Comparator */
747#define ANALOG_COMP_vect_num    23
748#define ANALOG_COMP_vect                _VECTOR(23)
749#define SIG_COMPARATOR                  _VECTOR(23)
750
751/* Two-wire Serial Interface */
752#define TWI_vect_num            24
753#define TWI_vect                        _VECTOR(24)
754#define SIG_TWI                         _VECTOR(24)
755#define SIG_2WIRE_SERIAL                _VECTOR(24)
756
757/* Store Program Memory Read */
758#define SPM_READY_vect_num              25
759#define SPM_READY_vect                  _VECTOR(25)
760#define SIG_SPM_READY                   _VECTOR(25)
761
762/* The mega48 and mega88 vector tables are single instruction entries (16 bits
763   per entry for an RJMP) while the mega168 table has double instruction
764   entries (32 bits per entry for a JMP). */
765
766#if defined (__AVR_ATmega168__) || defined (__AVR_ATmega168A__)
767#  define _VECTORS_SIZE 104
768#else
769#  define _VECTORS_SIZE 52
770#endif
771
772
773/* Deprecated items */
774#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
775
776#pragma GCC system_header
777
778#pragma GCC poison SIG_INTERRUPT0
779#pragma GCC poison SIG_INTERRUPT1
780#pragma GCC poison SIG_PIN_CHANGE0
781#pragma GCC poison SIG_PIN_CHANGE1
782#pragma GCC poison SIG_PIN_CHANGE2
783#pragma GCC poison SIG_WATCHDOG_TIMEOUT
784#pragma GCC poison SIG_OUTPUT_COMPARE2A
785#pragma GCC poison SIG_OUTPUT_COMPARE2B
786#pragma GCC poison SIG_OVERFLOW2
787#pragma GCC poison SIG_INPUT_CAPTURE1
788#pragma GCC poison SIG_OUTPUT_COMPARE1A
789#pragma GCC poison SIG_OUTPUT_COMPARE1B
790#pragma GCC poison SIG_OVERFLOW1
791#pragma GCC poison SIG_OUTPUT_COMPARE0A
792#pragma GCC poison SIG_OUTPUT_COMPARE0B
793#pragma GCC poison SIG_OVERFLOW0
794#pragma GCC poison SIG_SPI
795#pragma GCC poison SIG_USART_RECV
796#pragma GCC poison SIG_USART_DATA
797#pragma GCC poison SIG_USART_TRANS
798#pragma GCC poison SIG_ADC
799#pragma GCC poison SIG_EEPROM_READY
800#pragma GCC poison SIG_COMPARATOR
801#pragma GCC poison SIG_TWI
802#pragma GCC poison SIG_2WIRE_SERIAL
803#pragma GCC poison SIG_SPM_READY
804
805#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
806
807
808#endif /* _AVR_IOM8_H_ */
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