source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iomxxhva.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

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1/* Copyright (c) 2007, Anatoly Sokolov
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iomxxhva.h 2225 2011-03-02 16:27:26Z arcanum $ */
32
33/* iomxxhva.h - definitions for ATmega8HVA and ATmega16HVA.  */
34
35#ifndef _AVR_IOMXXHVA_H_
36#define _AVR_IOMXXHVA_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly.  */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iomxxhva.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* Registers and associated bit numbers */
51
52#define PINA    _SFR_IO8(0X00)
53#define PINA1   1
54#define PINA0   0
55
56#define DDRA    _SFR_IO8(0x01)
57#define DDA1    1
58#define DDA0    0
59
60#define PORTA   _SFR_IO8(0x02)
61#define PA1     1
62#define PA0     0
63
64#define PINB    _SFR_IO8(0X03)
65#define PINB3   3
66#define PINB2   2
67#define PINB1   1
68#define PINB0   0
69
70#define DDRB    _SFR_IO8(0x04)
71#define DDB3    3
72#define DDB2    2
73#define DDB1    1
74#define DDB0    0
75
76#define PORTB   _SFR_IO8(0x05)
77#define PB3     3
78#define PB2     2
79#define PB1     1
80#define PB0     0
81
82#define PINC    _SFR_IO8(0x06)
83#define PINC0   0
84
85/* Reserved [0x7] */
86
87#define PORTC   _SFR_IO8(0x08)
88#define PC0     0
89
90/* Reserved [0x9..0x14] */
91
92#define TIFR0   _SFR_IO8(0x15)
93#define ICF0    3
94#define OCF0B   2
95#define OCF0A   1
96#define TOV0    0
97
98#define TIFR1   _SFR_IO8(0x16)
99#define ICF1    3
100#define OCF1B   2
101#define OCF1A   1
102#define TOV1    0
103
104#define OSICSR  _SFR_IO8(0x17)
105#define OSISEL0 4
106#define OSIST   1
107#define OSIEN   0
108
109/* Reserved [0x18..0x1B] */
110
111#define EIFR    _SFR_IO8(0x1C)
112#define INTF2   2
113#define INTF1   1
114#define INTF0   0
115
116#define EIMSK   _SFR_IO8(0x1D)
117#define INT2    2
118#define INT1    1
119#define INT0    0
120
121#define GPIOR0  _SFR_IO8(0x1E)
122
123#define EECR    _SFR_IO8(0x1F)
124#define EEPM1   5
125#define EEPM0   4
126#define EERIE   3
127#define EEMPE   2
128#define EEPE    1
129#define EERE    0
130
131#define EEDR    _SFR_IO8(0x20)
132
133#define EEAR    _SFR_IO8(0x21)
134#define EEARL   _SFR_IO8(0x21)
135
136/* 6-char sequence denoting where to find the EEPROM registers in memory space.
137   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
138   subroutines.
139   First two letters:  EECR address.
140   Second two letters: EEDR address.
141   Last two letters:   EEAR address.  */
142#define __EEPROM_REG_LOCATIONS__ 1F2021
143
144/* Reserved [0x22] */
145
146#define GTCCR   _SFR_IO8(0x23)
147#define TSM     7
148#define PSRSYNC 0
149
150#define TCCR0A  _SFR_IO8(0x24)
151#define TCW0    7
152#define ICEN0   6
153#define ICNC0   5
154#define ICES0   4
155#define ICS0    3
156#define WGM00   0
157
158#define TCCR0B  _SFR_IO8(0x25)
159#define CS02    2
160#define CS01    1
161#define CS00    0
162
163#define TCNT0   _SFR_IO16(0X26)
164#define TCNT0L  _SFR_IO8(0X26)
165#define TCNT0H  _SFR_IO8(0X27)
166
167#define OCR0A   _SFR_IO8(0x28)
168
169#define OCR0B   _SFR_IO8(0X29)
170
171#define GPIOR1  _SFR_IO8(0x2A)
172
173#define GPIOR2  _SFR_IO8(0x2B)
174
175#define SPCR    _SFR_IO8(0x2C)
176#define SPIE    7
177#define SPE     6
178#define DORD    5
179#define MSTR    4
180#define CPOL    3
181#define CPHA    2
182#define SPR1    1
183#define SPR0    0
184
185#define SPSR    _SFR_IO8(0x2D)
186#define SPIF    7
187#define WCOL    6
188#define SPI2X   0
189
190#define SPDR    _SFR_IO8(0x2E)
191
192/* Reserved [0x2F..0x30] */
193
194#define DWDR    _SFR_IO8(0x31)
195#define IDRD    7
196
197/* Reserved [0x32] */
198
199#define SMCR    _SFR_IO8(0x33)
200#define SM2     3
201#define SM1     2
202#define SM0     1
203#define SE      0
204
205#define MCUSR   _SFR_IO8(0x34)
206#define OCDRF   4
207#define WDRF    3
208#define BORF    2
209#define EXTRF   1
210#define PORF    0
211
212#define MCUCR   _SFR_IO8(0x35)
213#define CKOE    5
214#define PUD     4
215
216/* Reserved [0x36] */
217
218#define SPMCSR  _SFR_IO8(0x37)
219#define SIGRD   5
220#define CTPB    4
221#define RFLB    3
222#define PGWRT   2
223#define PGERS   1
224#define SPMEN   0
225
226/* Reserved [0x38..0x3C] */
227
228/* SP [0x3D..0x3E] */
229/* SREG [0x3F] */
230
231#define WDTCSR  _SFR_MEM8(0x60)
232#define WDIF    7
233#define WDIE    6
234#define WDP3    5
235#define WDCE    4
236#define WDE     3
237#define WDP2    2
238#define WDP1    1
239#define WDP0    0
240
241#define CLKPR   _SFR_MEM8(0x61)
242#define CLKPCE  7
243#define CLKPS1  1
244#define CLKPS0  0
245
246/* Reserved [0x62..0x63] */
247
248#define PRR0    _SFR_MEM8(0x64)
249#define PRVRM   5
250#define PRSPI   3
251#define PRTIM1  2
252#define PRTIM0  1
253#define PRVADC  0
254
255#define __AVR_HAVE_PRR0 ((1<<PRVADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRVRM))
256#define __AVR_HAVE_PRR0_PRVADC
257#define __AVR_HAVE_PRR0_PRTIM0
258#define __AVR_HAVE_PRR0_PRTIM1
259#define __AVR_HAVE_PRR0_PRSPI
260#define __AVR_HAVE_PRR0_PRVRM
261
262/* Reserved [0x65] */
263
264#define FOSCCAL _SFR_MEM8(0x66)
265
266/* Reserved [0x67..0x68] */
267
268#define EICRA   _SFR_MEM8(0x69)
269#define ISC21   5
270#define ISC20   4
271#define ISC11   3
272#define ISC10   2
273#define ISC01   1
274#define ISC00   0
275
276/* Reserved [0x6A..0x6D] */
277
278#define TIMSK0  _SFR_MEM8(0x6E)
279#define ICIE0   3
280#define OCIE0B  2
281#define OCIE0A  1
282#define TOIE0   0
283
284#define TIMSK1  _SFR_MEM8(0x6F)
285#define ICIE1   3
286#define OCIE1B  2
287#define OCIE1A  1
288#define TOIE1   0
289
290/* Reserved [0x70..0x77] */
291
292#define VADC    _SFR_MEM16(0x78)
293#define VADCL   _SFR_MEM8(0x78)
294#define VADCH   _SFR_MEM8(0x79)
295
296#define VADCSR  _SFR_MEM8(0x7A)
297#define VADEN   3
298#define VADSC   2
299#define VADCCIF 1
300#define VADCCIE 0
301
302/* Reserved [0x7B] */
303
304#define VADMUX  _SFR_MEM8(0x7C)
305#define VADMUX3 3
306#define VADMUX2 2
307#define VADMUX1 1
308#define VADMUX0 0
309
310/* Reserved [0x7D] */
311
312#define DIDR0   _SFR_MEM8(0x7E)
313#define PA1DID  1
314#define PA0DID  0
315
316/* Reserved [0x7F] */
317
318#define TCCR1A  _SFR_MEM8(0x80)
319#define TCW1    7
320#define ICEN1   6
321#define ICNC1   5
322#define ICES1   4
323#define ICS1    3
324#define WGM10   0
325
326#define TCCR1B  _SFR_MEM8(0x81)
327#define CS12    2
328#define CS11    1
329#define CS10    0
330
331/* Reserved [0x82..0x83] */
332
333#define TCNT1   _SFR_MEM16(0x84)
334#define TCNT1L  _SFR_MEM8(0x84)
335#define TCNT1H  _SFR_MEM8(0x85)
336
337/* Reserved [0x86..0x87] */
338
339#define OCR1A   _SFR_MEM8(0x88)
340
341#define OCR1B   _SFR_MEM8(0x89)
342
343/* Reserved [0x8A..0xC7] */
344
345#define ROCR    _SFR_MEM8(0xC8)
346#define ROCS    7
347#define ROCWIF  1
348#define ROCWIE  0
349
350/* Reserved [0xC9..0xCF] */
351
352#define BGCCR   _SFR_MEM8(0xD0)
353#define BGD     7
354#define BGCC5   5
355#define BGCC4   4
356#define BGCC3   3
357#define BGCC2   2
358#define BGCC1   1
359#define BGCC0   0
360
361#define BGCRR   _SFR_MEM8(0xD1)
362#define BGCR7   7
363#define BGCR6   6
364#define BGCR5   5
365#define BGCR4   4
366#define BGCR3   3
367#define BGCR2   2
368#define BGCR1   1
369#define BGCR0   0
370
371/* Reserved [0xD2..0xDF] */
372
373/* CC-ADC Accumulate Current */
374/* TODO: Add _SFR_MEM32 */
375/* #define CADAC   _SFR_MEM32(0xE0) */
376#define CADAC0  _SFR_MEM8(0xE0)
377#define CADAC1  _SFR_MEM8(0xE1)
378#define CADAC2  _SFR_MEM8(0xE2)
379#define CADAC3  _SFR_MEM8(0xE3)
380
381#define CADCSRA _SFR_MEM8(0xE4)
382#define CADEN   7
383#define CADPOL  6
384#define CADUB   5
385#define CADAS1  4
386#define CADAS0  3
387#define CADSI1  2
388#define CADSI0  1
389#define CADSE   0
390
391#define CADCSRB _SFR_MEM8(0xE5)
392#define CADACIE 6
393#define CADRCIE 5
394#define CADICIE 4
395#define CADACIF 2
396#define CADRCIF 1
397#define CADICIF 0
398
399#define CADRC   _SFR_MEM8(0xE6)
400
401/* Reserved [0xE7] */
402
403#define CADIC   _SFR_MEM16(0xE8)
404#define CADICL  _SFR_MEM8(0xE8)
405#define CADICH  _SFR_MEM8(0xE9)
406
407/* Reserved [0xEA..0xEF] */
408
409#define FCSR    _SFR_MEM8(0xF0)
410#define DUVRD   3
411#define CPS     2
412#define DFE     1
413#define CFE     0
414
415/* Reserved [0xF1] */
416
417#define BPIMSK  _SFR_MEM8(0xF2)
418#define SCIE    4
419#define DOCIE   3
420#define COCIE   2
421#define DHCIE   1
422#define CHCIE   0
423
424#define BPIFR   _SFR_MEM8(0xF3)
425#define SCIF    4
426#define DOCIF   3
427#define COCIF   2
428#define DHCIF   1
429#define CHCIF   0
430
431/* Reserved [0xF4] */
432
433#define BPSCD   _SFR_MEM8(0xF5)
434
435#define BPDOCD  _SFR_MEM8(0xF6)
436
437#define BPCOCD  _SFR_MEM8(0xF7)
438
439#define BPDHCD  _SFR_MEM8(0xF8)
440
441#define BPCHCD  _SFR_MEM8(0xF9)
442
443#define BPSCTR  _SFR_MEM8(0xFA)
444
445#define BPOCTR  _SFR_MEM8(0xFB)
446
447#define BPHCTR  _SFR_MEM8(0xFC)
448
449#define BPCR    _SFR_MEM8(0xFD)
450#define SCD     4
451#define DOCD    3
452#define COCD    2
453#define DHCD    1
454#define CHCD    0
455
456#define BPPLR   _SFR_MEM8(0xFE)
457#define BPPLE   1
458#define BPPL    0
459
460/* Reserved [0xFF] */
461
462/* Interrupt vectors */
463/* Battery Protection Interrupt */
464#define BPINT_vect_num          1
465#define BPINT_vect                      _VECTOR(1)
466
467/* Voltage Regulator Monitor Interrupt */
468#define VREGMON_vect_num                2
469#define VREGMON_vect                    _VECTOR(2)
470
471/* External Interrupt Request 0 */
472#define INT0_vect_num           3
473#define INT0_vect                       _VECTOR(3)
474
475/* External Interrupt Request 1 */
476#define INT1_vect_num           4
477#define INT1_vect                       _VECTOR(4)
478
479/* External Interrupt Request 2 */
480#define INT2_vect_num           5
481#define INT2_vect                       _VECTOR(5)
482
483/* Watchdog Timeout Interrupt */
484#define WDT_vect_num            6
485#define WDT_vect                        _VECTOR(6)
486
487/* Timer/Counter 1 Input Capture */
488#define TIMER1_IC_vect_num              7
489#define TIMER1_IC_vect                  _VECTOR(7)
490
491/* Timer/Counter 1 Compare A Match */
492#define TIMER1_COMPA_vect_num   8
493#define TIMER1_COMPA_vect               _VECTOR(8)
494
495/* Timer/Counter 1 Compare B Match */
496#define TIMER1_COMPB_vect_num   9
497#define TIMER1_COMPB_vect               _VECTOR(9)
498
499/* Timer/Counter 1 Overflow */
500#define TIMER1_OVF_vect_num             10
501#define TIMER1_OVF_vect                 _VECTOR(10)
502
503/* Timer/Counter 0 Input Capture */
504#define TIMER0_IC_vect_num              11
505#define TIMER0_IC_vect                  _VECTOR(11)
506
507/* Timer/Counter0 Compare A Match */
508#define TIMER0_COMPA_vect_num   12
509#define TIMER0_COMPA_vect               _VECTOR(12)
510
511/* Timer/Counter0 Compare B Match */
512#define TIMER0_COMPB_vect_num   13
513#define TIMER0_COMPB_vect               _VECTOR(13)
514
515/* Timer/Counter0 Overflow */
516#define TIMER0_OVF_vect_num             14
517#define TIMER0_OVF_vect                 _VECTOR(14)
518
519/* SPI Serial Transfer Complete */
520#define SPI_STC_vect_num                15
521#define SPI_STC_vect                    _VECTOR(15)
522
523/* Voltage ADC Conversion Complete */
524#define VADC_vect_num           16
525#define VADC_vect                       _VECTOR(16)
526
527/* Coulomb Counter ADC Conversion Complete */
528#define CCADC_CONV_vect_num             17
529#define CCADC_CONV_vect                 _VECTOR(17)
530
531/* Coloumb Counter ADC Regular Current */
532#define CCADC_REG_CUR_vect_num  18
533#define CCADC_REG_CUR_vect              _VECTOR(18)
534
535/* Coloumb Counter ADC Accumulator */
536#define CCADC_ACC_vect_num              19
537#define CCADC_ACC_vect                  _VECTOR(19)
538
539/* EEPROM Ready */
540#define EE_READY_vect_num               20
541#define EE_READY_vect                   _VECTOR(20)
542
543#if defined (__AVR_ATmega16HVA__)
544#  define _VECTORS_SIZE 84
545#else
546#  define _VECTORS_SIZE 42
547#endif
548
549
550#endif  /* _AVR_IOMXXHVA_H_ */
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