source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iotn15.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 3 years ago

Adding new version

File size: 8.0 KB
Line 
1/* Copyright (c) 2002,2005 Marek Michalkiewicz
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iotn15.h 2236 2011-03-17 21:53:39Z arcanum $ */
32
33/* avr/iotn15.h - definitions for ATtiny15 */
34
35#ifndef _AVR_IOTN15_H_
36#define _AVR_IOTN15_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iotn15.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50#ifndef __ASSEMBLER__
51#  warning "MCU not supported by the C compiler"
52#endif
53
54/* I/O registers */
55
56/* 0x00..0x03 reserved */
57
58#ifndef __ASSEMBLER__
59#define ADC     _SFR_IO16 (0x04)
60#endif
61#define ADCW    _SFR_IO16(0x04)
62#define ADCL    _SFR_IO8(0x04)
63#define ADCH    _SFR_IO8(0x05)
64#define ADCSR   _SFR_IO8(0x06)
65#define ADMUX   _SFR_IO8(0x07)
66
67/* Analog Comparator Control and Status Register */
68#define ACSR    _SFR_IO8(0x08)
69
70/* 0x09..0x15 reserved */
71
72/* Input Pins, Port B */
73#define PINB    _SFR_IO8(0x16)
74
75/* Data Direction Register, Port B */
76#define DDRB    _SFR_IO8(0x17)
77
78/* Data Register, Port B */
79#define PORTB   _SFR_IO8(0x18)
80
81/* 0x19..0x1B reserved */
82
83/* EEPROM Control Register */
84#define EECR    _SFR_IO8(0x1C)
85
86/* EEPROM Data Register */
87#define EEDR    _SFR_IO8(0x1D)
88
89/* EEPROM Address Register */
90#define EEAR    _SFR_IO8(0x1E)
91#define EEARL   _SFR_IO8(0x1E)
92
93/* 0x1F..0x20 reserved */
94
95/* Watchdog Timer Control Register */
96#define WDTCR   _SFR_IO8(0x21)
97
98/* 0x22..0x2B reserved */
99#define SFIOR   _SFR_IO8(0x2C)
100
101#define OCR1B   _SFR_IO8(0x2D)
102#define OCR1A   _SFR_IO8(0x2E)
103#define TCNT1   _SFR_IO8(0x2F)
104#define TCCR1   _SFR_IO8(0x30)
105
106/* Oscillator Calibration Register */
107#define OSCCAL  _SFR_IO8(0x31)
108
109/* Timer/Counter0 (8-bit) */
110#define TCNT0   _SFR_IO8(0x32)
111
112/* Timer/Counter0 Control Register */
113#define TCCR0   _SFR_IO8(0x33)
114
115/* MCU general Status Register */
116#define MCUSR   _SFR_IO8(0x34)
117
118/* MCU general Control Register */
119#define MCUCR   _SFR_IO8(0x35)
120
121/* 0x36..0x37 reserved */
122
123/* Timer/Counter Interrupt Flag Register */
124#define TIFR    _SFR_IO8(0x38)
125
126/* Timer/Counter Interrupt MaSK Register */
127#define TIMSK   _SFR_IO8(0x39)
128
129/* General Interrupt Flag Register */
130#define GIFR    _SFR_IO8(0x3A)
131
132/* General Interrupt MaSK register */
133#define GIMSK   _SFR_IO8(0x3B)
134
135/* 0x3C..0x3E reserved */
136
137/* 0x3F SREG */
138
139/* Interrupt vectors */
140
141/* External Interrupt 0 */
142#define INT0_vect_num                   1
143#define INT0_vect                       _VECTOR(1)
144#define SIG_INTERRUPT0                  _VECTOR(1)
145
146/* External Interrupt Request 0 */
147#define IO_PINS_vect_num                2
148#define IO_PINS_vect                    _VECTOR(2)
149#define SIG_PIN                         _VECTOR(2)
150#define SIG_PIN_CHANGE                  _VECTOR(2)
151
152/* Timer/Counter1 Compare Match */
153#define TIMER1_COMP_vect_num    3
154#define TIMER1_COMP_vect            _VECTOR(3)
155#define SIG_OUTPUT_COMPARE1A    _VECTOR(3)
156
157/* Timer/Counter1 Overflow */
158#define TIMER1_OVF_vect_num             4
159#define TIMER1_OVF_vect                 _VECTOR(4)
160#define SIG_OVERFLOW1                   _VECTOR(4)
161
162/* Timer/Counter0 Overflow */
163#define TIMER0_OVF_vect_num             5
164#define TIMER0_OVF_vect                 _VECTOR(5)
165#define SIG_OVERFLOW0                   _VECTOR(5)
166
167/* EEPROM Ready */
168#define EE_RDY_vect_num                 6
169#define EE_RDY_vect                         _VECTOR(6)
170#define SIG_EEPROM_READY                _VECTOR(6)
171
172/* Analog Comparator */
173#define ANA_COMP_vect_num               7
174#define ANA_COMP_vect                   _VECTOR(7)
175#define SIG_COMPARATOR                  _VECTOR(7)
176
177/* ADC Conversion Ready */
178#define ADC_vect_num                    8
179#define ADC_vect                        _VECTOR(8)
180#define SIG_ADC                         _VECTOR(8)
181
182#define _VECTORS_SIZE 18
183
184/* Bit numbers */
185
186/* GIMSK */
187#define INT0    6
188#define PCIE    5
189
190/* GIFR */
191#define INTF0   6
192#define PCIF    5
193
194/* TIMSK */
195#define OCIE1   6
196#define TOIE1   2
197#define TOIE0   1
198
199/* TIFR */
200#define OCF1    6
201#define TOV1    2
202#define TOV0    1
203
204/* MCUCR */
205#define PUD     6
206#define SE      5
207#define SM1     4
208#define SM0     3
209#define ISC01   1
210#define ISC00   0
211
212/* MCUSR */
213#define WDRF    3
214#define BORF    2
215#define EXTRF   1
216#define PORF    0
217
218/* TCCR0 */
219#define CS02    2
220#define CS01    1
221#define CS00    0
222
223/* TCCR1 */
224#define CTC1    7
225#define PWM1    6
226#define COM1A1  5
227#define COM1A0  4
228#define CS13    3
229#define CS12    2
230#define CS11    1
231#define CS10    0
232
233/* SFIOR */
234#define FOC1A   2
235#define PSR1    1
236#define PSR0    0
237
238/* WDTCR */
239#define WDTOE   4
240#define WDE     3
241#define WDP2    2
242#define WDP1    1
243#define WDP0    0
244
245/*
246   PB5 = RESET# / ADC0
247   PB4 = ADC3
248   PB3 = ADC2
249   PB2 = SCK / ADC1 / T0 / INT0
250   PB1 = MISO / AIN1 / OCP
251   PB0 = MOSI / AIN0 / AREF
252 */
253
254/* PORTB */
255#define PB4     4
256#define PB3     3
257#define PB2     2
258#define PB1     1
259#define PB0     0
260
261/* DDRB */
262#define DDB4    4
263#define DDB3    3
264#define DDB2    2
265#define DDB1    1
266#define DDB0    0
267
268/* PINB */
269#define PINB5   5
270#define PINB4   4
271#define PINB3   3
272#define PINB2   2
273#define PINB1   1
274#define PINB0   0
275
276/* ACSR */
277#define ACD     7
278#define GREF    6
279#define ACO     5
280#define ACI     4
281#define ACIE    3
282#define ACIS1   1
283#define ACIS0   0
284
285/* ADMUX */
286#define REFS1   7
287#define REFS0   6
288#define ADLAR   5
289#define MUX2    2
290#define MUX1    1
291#define MUX0    0
292
293/* ADCSR */
294#define ADEN    7
295#define ADSC    6
296#define ADFR    5
297#define ADIF    4
298#define ADIE    3
299#define ADPS2   2
300#define ADPS1   1
301#define ADPS0   0
302
303/* EEPROM Control Register */
304#define EERIE   3
305#define EEMWE   2
306#define EEWE    1
307#define EERE    0
308
309#define RAMSTART    0x60
310/* Last memory addresses */
311#define RAMEND          0x1F
312#define XRAMEND         0x0
313#define E2END           0x3F
314#define E2PAGESIZE  2
315#define FLASHEND        0x3FF
316
317
318/* Fuses */
319
320#define FUSE_MEMORY_SIZE 1
321
322/* Fuse Byte */
323#define FUSE_CKSEL0      (unsigned char)~_BV(0)
324#define FUSE_CKSEL1      (unsigned char)~_BV(1)
325#define FUSE_RSTDISBL    (unsigned char)~_BV(4)
326#define FUSE_SPIEN       (unsigned char)~_BV(5)
327#define FUSE_BODEN       (unsigned char)~_BV(6)
328#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
329#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_SPIEN)
330
331
332/* Lock Bits */
333#define __LOCK_BITS_EXIST
334
335
336/* Signature */
337#define SIGNATURE_0 0x1E
338#define SIGNATURE_1 0x90
339#define SIGNATURE_2 0x06
340
341
342/* Deprecated items */
343#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
344
345#pragma GCC system_header
346
347#pragma GCC poison SIG_INTERRUPT0
348#pragma GCC poison SIG_PIN
349#pragma GCC poison SIG_PIN_CHANGE
350#pragma GCC poison SIG_OUTPUT_COMPARE1A
351#pragma GCC poison SIG_OVERFLOW1
352#pragma GCC poison SIG_OVERFLOW0
353#pragma GCC poison SIG_EEPROM_READY
354#pragma GCC poison SIG_COMPARATOR
355#pragma GCC poison SIG_ADC
356
357#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
358
359#define SLEEP_MODE_IDLE (0x00<<3)
360#define SLEEP_MODE_ADC (0x01<<3)
361#define SLEEP_MODE_PWR_DOWN (0x02<<3)
362
363#endif /* _AVR_IOTN15_H_ */
Note: See TracBrowser for help on using the repository browser.