source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iotn24a.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 3 years ago

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1/* Copyright (c) 2009 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iotn24a.h 2414 2014-03-21 16:04:00Z pitchumani $ */
32
33/* avr/iotn24a.h - definitions for ATtiny24A */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iotn24a.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_ATtiny24A_H_
49#define _AVR_ATtiny24A_H_ 1
50
51
52/* Registers and associated bit numbers. */
53
54#define PRR _SFR_IO8(0x00)
55#define PRADC 0
56#define PRUSI 1
57#define PRTIM0 2
58#define PRTIM1 3
59
60#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1))
61#define __AVR_HAVE_PRR_PRADC
62#define __AVR_HAVE_PRR_PRUSI
63#define __AVR_HAVE_PRR_PRTIM0
64#define __AVR_HAVE_PRR_PRTIM1
65
66#define DIDR0 _SFR_IO8(0x01)
67#define ADC0D 0
68#define ADC1D 1
69#define ADC2D 2
70#define ADC3D 3
71#define ADC4D 4
72#define ADC5D 5
73#define ADC6D 6
74#define ADC7D 7
75
76#define ADCSRB _SFR_IO8(0x03)
77#define ADTS0 0
78#define ADTS1 1
79#define ADTS2 2
80#define ADLAR 4
81#define ACME 6
82#define BIN 7
83
84#ifndef __ASSEMBLER__
85#define ADC _SFR_IO16(0x04)
86#endif
87#define ADCW _SFR_IO16(0x04)
88
89#define ADCL _SFR_IO8(0x04)
90#define ADCL0 0
91#define ADCL1 1
92#define ADCL2 2
93#define ADCL3 3
94#define ADCL4 4
95#define ADCL5 5
96#define ADCL6 6
97#define ADCL7 7
98
99#define ADCH _SFR_IO8(0x05)
100#define ADCH0 0
101#define ADCH1 1
102#define ADCH2 2
103#define ADCH3 3
104#define ADCH4 4
105#define ADCH5 5
106#define ADCH6 6
107#define ADCH7 7
108
109#define ADCSRA _SFR_IO8(0x06)
110#define ADPS0 0
111#define ADPS1 1
112#define ADPS2 2
113#define ADIE 3
114#define ADIF 4
115#define ADATE 5
116#define ADSC 6
117#define ADEN 7
118
119#define ADMUX _SFR_IO8(0x07)
120#define MUX0 0
121#define MUX1 1
122#define MUX2 2
123#define MUX3 3
124#define MUX4 4
125#define MUX5 5
126#define REFS0 6
127#define REFS1 7
128
129#define ACSR _SFR_IO8(0x08)
130#define ACIS0 0
131#define ACIS1 1
132#define ACIC 2
133#define ACIE 3
134#define ACI 4
135#define ACO 5
136#define ACBG 6
137#define ACD 7
138
139#define TIFR1 _SFR_IO8(0x0B)
140#define TOV1 0
141#define OCF1A 1
142#define OCF1B 2
143#define ICF1 5
144
145#define TIMSK1 _SFR_IO8(0x0C)
146#define TOIE1 0
147#define OCIE1A 1
148#define OCIE1B 2
149#define ICIE1 5
150
151#define USICR _SFR_IO8(0x0D)
152#define USITC 0
153#define USICLK 1
154#define USICS0 2
155#define USICS1 3
156#define USIWM0 4
157#define USIWM1 5
158#define USIOIE 6
159#define USISIE 7
160
161#define USISR _SFR_IO8(0x0E)
162#define USICNT0 0
163#define USICNT1 1
164#define USICNT2 2
165#define USICNT3 3
166#define USIDC 4
167#define USIPF 5
168#define USIOIF 6
169#define USISIF 7
170
171#define USIDR _SFR_IO8(0x0F)
172#define USIDR0 0
173#define USIDR1 1
174#define USIDR2 2
175#define USIDR3 3
176#define USIDR4 4
177#define USIDR5 5
178#define USIDR6 6
179#define USIDR7 7
180
181#define USIBR _SFR_IO8(0x10)
182#define USIBR0 0
183#define USIBR1 1
184#define USIBR2 2
185#define USIBR3 3
186#define USIBR4 4
187#define USIBR5 5
188#define USIBR6 6
189#define USIBR7 7
190
191#define PCMSK0 _SFR_IO8(0x12)
192#define PCINT0 0
193#define PCINT1 1
194#define PCINT2 2
195#define PCINT3 3
196#define PCINT4 4
197#define PCINT5 5
198#define PCINT6 6
199#define PCINT7 7
200
201#define GPIOR0 _SFR_IO8(0x13)
202#define GPIOR00 0
203#define GPIOR01 1
204#define GPIOR02 2
205#define GPIOR03 3
206#define GPIOR04 4
207#define GPIOR05 5
208#define GPIOR06 6
209#define GPIOR07 7
210
211#define GPIOR1 _SFR_IO8(0x14)
212#define GPIOR10 0
213#define GPIOR11 1
214#define GPIOR12 2
215#define GPIOR13 3
216#define GPIOR14 4
217#define GPIOR15 5
218#define GPIOR16 6
219#define GPIOR17 7
220
221#define GPIOR2 _SFR_IO8(0x15)
222#define GPIOR20 0
223#define GPIOR21 1
224#define GPIOR22 2
225#define GPIOR23 3
226#define GPIOR24 4
227#define GPIOR25 5
228#define GPIOR26 6
229#define GPIOR27 7
230
231#define PINB _SFR_IO8(0x16)
232#define PINB0 0
233#define PINB1 1
234#define PINB2 2
235#define PINB3 3
236
237#define DDRB _SFR_IO8(0x17)
238#define DDB0 0
239#define DDB1 1
240#define DDB2 2
241#define DDB3 3
242
243#define PORTB _SFR_IO8(0x18)
244#define PORTB0 0
245#define PORTB1 1
246#define PORTB2 2
247#define PORTB3 3
248
249#define PINA _SFR_IO8(0x19)
250#define PINA0 0
251#define PINA1 1
252#define PINA2 2
253#define PINA3 3
254#define PINA4 4
255#define PINA5 5
256#define PINA6 6
257#define PINA7 7
258
259#define DDRA _SFR_IO8(0x1A)
260#define DDA0 0
261#define DDA1 1
262#define DDA2 2
263#define DDA3 3
264#define DDA4 4
265#define DDA5 5
266#define DDA6 6
267#define DDA7 7
268
269#define PORTA _SFR_IO8(0x1B)
270#define PORTA0 0
271#define PORTA1 1
272#define PORTA2 2
273#define PORTA3 3
274#define PORTA4 4
275#define PORTA5 5
276#define PORTA6 6
277#define PORTA7 7
278
279#define EECR _SFR_IO8(0x1C)
280#define EERE 0
281#define EEPE 1
282#define EEMPE 2
283#define EERIE 3
284#define EEPM0 4
285#define EEPM1 5
286
287#define EEDR _SFR_IO8(0x1D)
288#define EEDR0 0
289#define EEDR1 1
290#define EEDR2 2
291#define EEDR3 3
292#define EEDR4 4
293#define EEDR5 5
294#define EEDR6 6
295#define EEDR7 7
296
297#define EEAR _SFR_IO16(0x1E)
298
299#define EEARL _SFR_IO8(0x1E)
300#define EEAR0 0
301#define EEAR1 1
302#define EEAR2 2
303#define EEAR3 3
304#define EEAR4 4
305#define EEAR5 5
306#define EEAR6 6
307#define EEAR7 7
308
309#define EEARH _SFR_IO8(0x1F)
310#define EEAR8 0
311
312#define PCMSK1 _SFR_IO8(0x20)
313#define PCINT8 0
314#define PCINT9 1
315#define PCINT10 2
316#define PCINT11 3
317
318#define WDTCSR _SFR_IO8(0x21)
319#define WDP0 0
320#define WDP1 1
321#define WDP2 2
322#define WDE 3
323#define WDCE 4
324#define WDP3 5
325#define WDIE 6
326#define WDIF 7
327
328#define TCCR1C _SFR_IO8(0x22)
329#define FOC1B 6
330#define FOC1A 7
331
332#define GTCCR _SFR_IO8(0x23)
333#define PSR10 0
334#define TSM 7
335
336#define ICR1 _SFR_IO16(0x24)
337
338#define ICR1L _SFR_IO8(0x24)
339#define ICR1L0 0
340#define ICR1L1 1
341#define ICR1L2 2
342#define ICR1L3 3
343#define ICR1L4 4
344#define ICR1L5 5
345#define ICR1L6 6
346#define ICR1L7 7
347
348#define ICR1H _SFR_IO8(0x25)
349#define ICR1H0 0
350#define ICR1H1 1
351#define ICR1H2 2
352#define ICR1H3 3
353#define ICR1H4 4
354#define ICR1H5 5
355#define ICR1H6 6
356#define ICR1H7 7
357
358#define CLKPR _SFR_IO8(0x26)
359#define CLKPS0 0
360#define CLKPS1 1
361#define CLKPS2 2
362#define CLKPS3 3
363#define CLKPCE 7
364
365#define DWDR _SFR_IO8(0x27)
366
367#define OCR1B _SFR_IO16(0x28)
368
369#define OCR1BL _SFR_IO8(0x28)
370#define OCR1BL0 0
371#define OCR1BL1 1
372#define OCR1BL2 2
373#define OCR1BL3 3
374#define OCR1BL4 4
375#define OCR1BL5 5
376#define OCR1BL6 6
377#define OCR1BL7 7
378
379#define OCR1BH _SFR_IO8(0x29)
380#define OCR1BH0 0
381#define OCR1BH1 1
382#define OCR1BH2 2
383#define OCR1BH3 3
384#define OCR1BH4 4
385#define OCR1BH5 5
386#define OCR1BH6 6
387#define OCR1BH7 7
388
389#define OCR1A _SFR_IO16(0x2A)
390
391#define OCR1AL _SFR_IO8(0x2A)
392#define OCR1AL0 0
393#define OCR1AL1 1
394#define OCR1AL2 2
395#define OCR1AL3 3
396#define OCR1AL4 4
397#define OCR1AL5 5
398#define OCR1AL6 6
399#define OCR1AL7 7
400
401#define OCR1AH _SFR_IO8(0x2B)
402#define OCR1AH0 0
403#define OCR1AH1 1
404#define OCR1AH2 2
405#define OCR1AH3 3
406#define OCR1AH4 4
407#define OCR1AH5 5
408#define OCR1AH6 6
409#define OCR1AH7 7
410
411#define TCNT1 _SFR_IO16(0x2C)
412
413#define TCNT1L _SFR_IO8(0x2C)
414#define TCNT1L0 0
415#define TCNT1L1 1
416#define TCNT1L2 2
417#define TCNT1L3 3
418#define TCNT1L4 4
419#define TCNT1L5 5
420#define TCNT1L6 6
421#define TCNT1L7 7
422
423#define TCNT1H _SFR_IO8(0x2D)
424#define TCNT1H0 0
425#define TCNT1H1 1
426#define TCNT1H2 2
427#define TCNT1H3 3
428#define TCNT1H4 4
429#define TCNT1H5 5
430#define TCNT1H6 6
431#define TCNT1H7 7
432
433#define TCCR1B _SFR_IO8(0x2E)
434#define CS10 0
435#define CS11 1
436#define CS12 2
437#define WGM12 3
438#define WGM13 4
439#define ICES1 6
440#define ICNC1 7
441
442#define TCCR1A _SFR_IO8(0x2F)
443#define WGM10 0
444#define WGM11 1
445#define COM1B0 4
446#define COM1B1 5
447#define COM1A0 6
448#define COM1A1 7
449
450#define TCCR0A _SFR_IO8(0x30)
451#define WGM00 0
452#define WGM01 1
453#define COM0B0 4
454#define COM0B1 5
455#define COM0A0 6
456#define COM0A1 7
457
458#define OSCCAL _SFR_IO8(0x31)
459#define CAL0 0
460#define CAL1 1
461#define CAL2 2
462#define CAL3 3
463#define CAL4 4
464#define CAL5 5
465#define CAL6 6
466#define CAL7 7
467
468#define TCNT0 _SFR_IO8(0x32)
469#define TCNT0_0 0
470#define TCNT0_1 1
471#define TCNT0_2 2
472#define TCNT0_3 3
473#define TCNT0_4 4
474#define TCNT0_5 5
475#define TCNT0_6 6
476#define TCNT0_7 7
477
478#define TCCR0B _SFR_IO8(0x33)
479#define CS00 0
480#define CS01 1
481#define CS02 2
482#define WGM02 3
483#define FOC0B 6
484#define FOC0A 7
485
486#define MCUSR _SFR_IO8(0x34)
487#define PORF 0
488#define EXTRF 1
489#define BORF 2
490#define WDRF 3
491
492#define MCUCR _SFR_IO8(0x35)
493#define ISC00 0
494#define ISC01 1
495#define BODSE 2
496#define SM0 3
497#define SM1 4
498#define SE 5
499#define PUD 6
500#define BODS 7
501
502#define OCR0A _SFR_IO8(0x36)
503#define OCR0A_0 0
504#define OCR0A_1 1
505#define OCR0A_2 2
506#define OCR0A_3 3
507#define OCR0A_4 4
508#define OCR0A_5 5
509#define OCR0A_6 6
510#define OCR0A_7 7
511
512#define SPMCSR _SFR_IO8(0x37)
513#define SPMEN 0
514#define PGERS 1
515#define PGWRT 2
516#define RFLB 3
517#define CTPB 4
518
519#define TIFR0 _SFR_IO8(0x38)
520#define TOV0 0
521#define OCF0A 1
522#define OCF0B 2
523
524#define TIMSK0 _SFR_IO8(0x39)
525#define TOIE0 0
526#define OCIE0A 1
527#define OCIE0B 2
528
529#define GIFR _SFR_IO8(0x3A)
530#define PCIF0 4
531#define PCIF1 5
532#define INTF0 6
533
534#define GIMSK _SFR_IO8(0x3B)
535#define PCIE0 4
536#define PCIE1 5
537#define INT0 6
538
539#define OCR0B _SFR_IO8(0x3C)
540#define OCR0_0 0
541#define OCR0_1 1
542#define OCR0_2 2
543#define OCR0_3 3
544#define OCR0_4 4
545#define OCR0_5 5
546#define OCR0_6 6
547#define OCR0_7 7
548
549
550/* Interrupt vectors */
551/* Vector 0 is the reset vector */
552#define EXT_INT0_vect_num  1
553#define EXT_INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
554#define PCINT0_vect_num  2
555#define PCINT0_vect      _VECTOR(2)  /* Pin Change Interrupt Request 0 */
556#define PCINT1_vect_num  3
557#define PCINT1_vect      _VECTOR(3)  /* Pin Change Interrupt Request 1 */
558#define WDT_vect_num  4
559#define WDT_vect      _VECTOR(4)  /* Watchdog Time-out */
560#define WATCHDOG_vect_num  4
561#define WATCHDOG_vect      _VECTOR(4)  /* alias */
562#define TIM1_CAPT_vect_num  5
563#define TIM1_CAPT_vect      _VECTOR(5)  /* Timer/Counter1 Capture Event */
564#define TIM1_COMPA_vect_num  6
565#define TIM1_COMPA_vect      _VECTOR(6)  /* Timer/Counter1 Compare Match A */
566#define TIM1_COMPB_vect_num  7
567#define TIM1_COMPB_vect      _VECTOR(7)  /* Timer/Counter1 Compare Match B */
568#define TIM1_OVF_vect_num  8
569#define TIM1_OVF_vect      _VECTOR(8)  /* Timer/Counter1 Overflow */
570#define TIM0_COMPA_vect_num  9
571#define TIM0_COMPA_vect      _VECTOR(9)  /* Timer/Counter0 Compare Match A */
572#define TIM0_COMPB_vect_num  10
573#define TIM0_COMPB_vect      _VECTOR(10)  /* Timer/Counter0 Compare Match B */
574#define TIM0_OVF_vect_num  11
575#define TIM0_OVF_vect      _VECTOR(11)  /* Timer/Counter0 Overflow */
576#define ANA_COMP_vect_num  12
577#define ANA_COMP_vect      _VECTOR(12)  /* Analog Comparator */
578#define ADC_vect_num  13
579#define ADC_vect      _VECTOR(13)  /* ADC Conversion Complete */
580#define EE_RDY_vect_num  14
581#define EE_RDY_vect      _VECTOR(14)  /* EEPROM Ready */
582#define USI_STR_vect_num  15
583#define USI_STR_vect      _VECTOR(15)  /* USI START */
584#define USI_OVF_vect_num  16
585#define USI_OVF_vect      _VECTOR(16)  /* USI Overflow */
586
587#define _VECTOR_SIZE 2 /* Size of individual vector. */
588#define _VECTORS_SIZE (17 * _VECTOR_SIZE)
589
590
591/* Constants */
592#define SPM_PAGESIZE (32)
593#define RAMSTART     (0x60)
594#define RAMSIZE      (128)
595#define RAMEND       (RAMSTART + RAMSIZE - 1)
596#define XRAMSTART    (NA)
597#define XRAMSIZE     (0)
598#define XRAMEND      (RAMEND)
599#define E2END        (0x7F)
600#define E2PAGESIZE   (4)
601#define FLASHEND     (0x7FF)
602
603
604/* Fuses */
605#define FUSE_MEMORY_SIZE 3
606
607/* Low Fuse Byte */
608#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock source */
609#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock source */
610#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock source */
611#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock source */
612#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
613#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
614#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock Output Enable */
615#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
616#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
617
618/* High Fuse Byte */
619#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
620#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
621#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
622#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through the Chip Erase */
623#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog Timer always on */
624#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial Program and Data Downloading */
625#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
626#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset disable */
627#define HFUSE_DEFAULT (FUSE_SPIEN)
628
629/* Extended Fuse Byte */
630#define FUSE_SELFPRGEN  (unsigned char)~_BV(0)  /* Self-Programming Enable */
631#define EFUSE_DEFAULT (0xFF)
632
633
634/* Lock Bits */
635#define __LOCK_BITS_EXIST
636
637
638/* Signature */
639#define SIGNATURE_0 0x1E
640#define SIGNATURE_1 0x91
641#define SIGNATURE_2 0x0B
642
643
644/* Device Pin Definitions */
645#define ADC4_DDR   DDRA
646#define ADC4_PORT  PORTA
647#define ADC4_PIN   PINA
648#define ADC4_BIT   4
649
650#define USCK_DDR   DDRA
651#define USCK_PORT  PORTA
652#define USCK_PIN   PINA
653#define USCK_BIT   4
654
655#define SCL_DDR   DDRA
656#define SCL_PORT  PORTA
657#define SCL_PIN   PINA
658#define SCL_BIT   4
659
660#define T1_DDR   DDRA
661#define T1_PORT  PORTA
662#define T1_PIN   PINA
663#define T1_BIT   4
664
665#define PCINT4_DDR   DDRA
666#define PCINT4_PORT  PORTA
667#define PCINT4_PIN   PINA
668#define PCINT4_BIT   4
669
670#define ADC3_DDR   DDRA
671#define ADC3_PORT  PORTA
672#define ADC3_PIN   PINA
673#define ADC3_BIT   3
674
675#define T0_DDR   DDRA
676#define T0_PORT  PORTA
677#define T0_PIN   PINA
678#define T0_BIT   3
679
680#define PCINT3_DDR   DDRA
681#define PCINT3_PORT  PORTA
682#define PCINT3_PIN   PINA
683#define PCINT3_BIT   3
684
685#define ADC2_DDR   DDRA
686#define ADC2_PORT  PORTA
687#define ADC2_PIN   PINA
688#define ADC2_BIT   2
689
690#define AIN1_DDR   DDRA
691#define AIN1_PORT  PORTA
692#define AIN1_PIN   PINA
693#define AIN1_BIT   2
694
695#define PCINT2_DDR   DDRA
696#define PCINT2_PORT  PORTA
697#define PCINT2_PIN   PINA
698#define PCINT2_BIT   2
699
700#define ADC1_DDR   DDRA
701#define ADC1_PORT  PORTA
702#define ADC1_PIN   PINA
703#define ADC1_BIT   1
704
705#define AIN0_DDR   DDRA
706#define AIN0_PORT  PORTA
707#define AIN0_PIN   PINA
708#define AIN0_BIT   1
709
710#define PCINT1_DDR   DDRA
711#define PCINT1_PORT  PORTA
712#define PCINT1_PIN   PINA
713#define PCINT1_BIT   1
714
715#define ADC0_DDR   DDRA
716#define ADC0_PORT  PORTA
717#define ADC0_PIN   PINA
718#define ADC0_BIT   0
719
720#define PCINT0_DDR   DDRA
721#define PCINT0_PORT  PORTA
722#define PCINT0_PIN   PINA
723#define PCINT0_BIT   0
724
725#define PCINT8_DDR   DDRB
726#define PCINT8_PORT  PORTB
727#define PCINT8_PIN   PINB
728#define PCINT8_BIT   0
729
730#define PCINT9_DDR   DDRB
731#define PCINT9_PORT  PORTB
732#define PCINT9_PIN   PINB
733#define PCINT9_BIT   1
734
735#define PCINT11_DDR   DDRB
736#define PCINT11_PORT  PORTB
737#define PCINT11_PIN   PINB
738#define PCINT11_BIT   3
739
740#define dW_DDR   DDRB
741#define dW_PORT  PORTB
742#define dW_PIN   PINB
743#define dW_BIT   3
744
745#define PCINT10_DDR   DDRB
746#define PCINT10_PORT  PORTB
747#define PCINT10_PIN   PINB
748#define PCINT10_BIT   2
749
750#define INT0_DDR   DDRB
751#define INT0_PORT  PORTB
752#define INT0_PIN   PINB
753#define INT0_BIT   2
754
755#define OC0A_DDR   DDRB
756#define OC0A_PORT  PORTB
757#define OC0A_PIN   PINB
758#define OC0A_BIT   2
759
760#define CKOUT_DDR   DDRB
761#define CKOUT_PORT  PORTB
762#define CKOUT_PIN   PINB
763#define CKOUT_BIT   2
764
765#define PCINT7_DDR   DDRA
766#define PCINT7_PORT  PORTA
767#define PCINT7_PIN   PINA
768#define PCINT7_BIT   7
769
770#define ICP1_DDR   DDRA
771#define ICP1_PORT  PORTA
772#define ICP1_PIN   PINA
773#define ICP1_BIT   7
774
775#define OC0B_DDR   DDRA
776#define OC0B_PORT  PORTA
777#define OC0B_PIN   PINA
778#define OC0B_BIT   7
779
780#define ADC7_DDR   DDRA
781#define ADC7_PORT  PORTA
782#define ADC7_PIN   PINA
783#define ADC7_BIT   7
784
785#define PCINT6_DDR   DDRA
786#define PCINT6_PORT  PORTA
787#define PCINT6_PIN   PINA
788#define PCINT6_BIT   6
789
790#define OC1A_DDR   DDRA
791#define OC1A_PORT  PORTA
792#define OC1A_PIN   PINA
793#define OC1A_BIT   6
794
795#define DI_DDR   DDRA
796#define DI_PORT  PORTA
797#define DI_PIN   PINA
798#define DI_BIT   6
799
800#define SDA_DDR   DDRA
801#define SDA_PORT  PORTA
802#define SDA_PIN   PINA
803#define SDA_BIT   6
804
805#define MOSI_DDR   DDRA
806#define MOSI_PORT  PORTA
807#define MOSI_PIN   PINA
808#define MOSI_BIT   6
809
810#define ADC6_DDR   DDRA
811#define ADC6_PORT  PORTA
812#define ADC6_PIN   PINA
813#define ADC6_BIT   6
814
815#define ADC5_DDR   DDRA
816#define ADC5_PORT  PORTA
817#define ADC5_PIN   PINA
818#define ADC5_BIT   5
819
820#define DO_DDR   DDRA
821#define DO_PORT  PORTA
822#define DO_PIN   PINA
823#define DO_BIT   5
824
825#define MISO_DDR   DDRA
826#define MISO_PORT  PORTA
827#define MISO_PIN   PINA
828#define MISO_BIT   5
829
830#define OC1B_DDR   DDRA
831#define OC1B_PORT  PORTA
832#define OC1B_PIN   PINA
833#define OC1B_BIT   5
834
835#define PCINT5_DDR   DDRA
836#define PCINT5_PORT  PORTA
837#define PCINT5_PIN   PINA
838#define PCINT5_BIT   5
839
840#define SLEEP_MODE_IDLE (0x00<<3)
841#define SLEEP_MODE_ADC (0x01<<3)
842#define SLEEP_MODE_PWR_DOWN (0x02<<3)
843#define SLEEP_MODE_STANDBY (0x03<<3)
844
845#endif /* _AVR_ATtiny24A_H_ */
846
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