source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iotn26.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

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1/* Copyright (c) 2004,2005 Eric B. Weddington
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iotn26.h 2236 2011-03-17 21:53:39Z arcanum $ */
32
33/* avr/iotn26.h - definitions for ATtiny26 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iotn26.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47#ifndef _AVR_IOTN26_H_
48#define _AVR_IOTN26_H_ 1
49
50/* Registers and associated bit numbers */
51
52/* Reserved [0x00..0x03] */
53
54#define ADCW    _SFR_IO16(0x04)
55#ifndef __ASSEMBLER__
56#define ADC     _SFR_IO16(0x04)
57#endif
58
59#define ADCL    _SFR_IO8(0x04)
60#define ADCH    _SFR_IO8(0x05)
61
62#define ADCSR   _SFR_IO8(0x06)
63#define ADPS0   0
64#define ADPS1   1
65#define ADPS2   2
66#define ADIE    3
67#define ADIF    4
68#define ADFR    5
69#define ADSC    6
70#define ADEN    7
71
72#define ADMUX   _SFR_IO8(0x07)
73#define MUX0    0
74#define MUX1    1
75#define MUX2    2
76#define MUX3    3
77#define MUX4    4
78#define ADLAR   5
79#define REFS0   6
80#define REFS1   7
81
82#define ACSR    _SFR_IO8(0x08)
83#define ACIS0   0
84#define ACIS1   1
85#define ACME    2
86#define ACIE    3
87#define ACI     4
88#define ACO     5
89#define ACBG    6
90#define ACD     7
91
92/* Reserved [0x09..0x0C] */
93
94#define USICR   _SFR_IO8(0x0D)
95#define USITC   0
96#define USICLK  1
97#define USICS0  2
98#define USICS1  3
99#define USIWM0  4
100#define USIWM1  5
101#define USIOIE  6
102#define USISIE  7
103
104#define USISR   _SFR_IO8(0x0E)
105#define USICNT0 0
106#define USICNT1 1
107#define USICNT2 2
108#define USICNT3 3
109#define USIDC   4
110#define USIPF   5
111#define USIOIF  6
112#define USISIF  7
113
114#define USIDR   _SFR_IO8(0x0F)
115
116/* Reserved [0x10..0x15] */
117
118
119#define PINB    _SFR_IO8(0x16)
120#define PINB0   0
121#define PINB1   1
122#define PINB2   2
123#define PINB3   3
124#define PINB4   4
125#define PINB5   5
126#define PINB6   6
127#define PINB7   7
128
129#define DDRB    _SFR_IO8(0x17)
130#define DDB0    0
131#define DDB1    1
132#define DDB2    2
133#define DDB3    3
134#define DDB4    4
135#define DDB5    5
136#define DDB6    6
137#define DDB7    7
138
139#define PORTB   _SFR_IO8(0x18)
140#define PB0     0
141#define PB1     1
142#define PB2     2
143#define PB3     3
144#define PB4     4
145#define PB5     5
146#define PB6     6
147#define PB7     7
148
149#define PINA    _SFR_IO8(0x19)
150#define PINA0   0
151#define PINA1   1
152#define PINA2   2
153#define PINA3   3
154#define PINA4   4
155#define PINA5   5
156#define PINA6   6
157#define PINA7   7
158
159#define DDRA    _SFR_IO8(0x1A)
160#define DDA0    0
161#define DDA1    1
162#define DDA2    2
163#define DDA3    3
164#define DDA4    4
165#define DDA5    5
166#define DDA6    6
167#define DDA7    7
168
169#define PORTA   _SFR_IO8(0x1B)
170#define PA0     0
171#define PA1     1
172#define PA2     2
173#define PA3     3
174#define PA4     4
175#define PA5     5
176#define PA6     6
177#define PA7     7
178
179/* EEPROM Control Register */
180#define EECR    _SFR_IO8(0x1C)
181#define EERE    0
182#define EEWE    1
183#define EEMWE   2
184#define EERIE   3
185
186/* EEPROM Data Register */
187#define EEDR    _SFR_IO8(0x1D)
188
189/* EEPROM Address Register */
190#define EEAR    _SFR_IO8(0x1E)
191#define EEARL   _SFR_IO8(0x1E)
192
193/* Reserved [0x1F..0x20] */
194
195#define WDTCR   _SFR_IO8(0x21)
196#define WDP0    0
197#define WDP1    1
198#define WDP2    2
199#define WDE     3
200#define WDCE    4
201
202/* Reserved [0x22..0x28] */
203
204#define PLLCSR  _SFR_IO8(0x29)
205#define PLOCK   0
206#define PLLE    1
207#define PCKE    2
208
209/* Reserved [0x2A] */
210
211#define OCR1C   _SFR_IO8(0x2B)
212
213#define OCR1B   _SFR_IO8(0x2C)
214
215#define OCR1A   _SFR_IO8(0x2D)
216
217#define TCNT1   _SFR_IO8(0x2E)
218
219#define TCCR1B  _SFR_IO8(0x2F)
220#define CS10    0
221#define CS11    1
222#define CS12    2
223#define CS13    3
224#define PSR1    6
225#define CTC1    7
226
227#define TCCR1A  _SFR_IO8(0x30)
228#define PWM1B   0
229#define PWM1A   1
230#define FOC1B   2
231#define FOC1A   3
232#define COM1B0  4
233#define COM1B1  5
234#define COM1A0  6
235#define COM1A1  7
236
237#define OSCCAL  _SFR_IO8(0x31)
238
239#define TCNT0   _SFR_IO8(0x32)
240
241#define TCCR0   _SFR_IO8(0x33)
242#define CS00    0
243#define CS01    1
244#define CS02    2
245#define PSR0    3
246
247#define MCUSR   _SFR_IO8(0x34)
248#define PORF    0
249#define EXTRF   1
250#define BORF    2
251#define WDRF    3
252
253#define MCUCR   _SFR_IO8(0x35)
254#define ISC00   0
255#define ISC01   1
256#define SM0     3
257#define SM1     4
258#define SE      5
259#define PUD     6
260
261/* Reserved [0x36..0x37] */
262
263#define TIFR    _SFR_IO8(0x38)
264#define TOV0    1
265#define TOV1    2
266#define OCF1B   5
267#define OCF1A   6
268
269#define TIMSK   _SFR_IO8(0x39)
270#define TOIE0   1
271#define TOIE1   2
272#define OCIE1B  5
273#define OCIE1A  6
274
275#define GIFR    _SFR_IO8(0x3A)
276#define PCIF    5
277#define INTF0   6
278
279#define GIMSK   _SFR_IO8(0x3B)
280#define PCIE0   4
281#define PCIE1   5
282#define INT0    6
283
284/* Reserved [0x3C] */
285
286/* SP [0x3D] */
287
288/* Reserved [0x3E] */
289
290/* SREG [0x3F] */
291
292
293/* Interrupt vectors */
294/* Interrupt vector 0 is the reset vector. */
295/* External Interrupt 0 */
296#define INT0_vect_num                   1
297#define INT0_vect                       _VECTOR(1)
298#define SIG_INTERRUPT0                  _VECTOR(1)
299
300/* External Interrupt Request 0 */
301#define IO_PINS_vect_num        2
302#define IO_PINS_vect                    _VECTOR(2)
303#define SIG_PIN_CHANGE                  _VECTOR(2)
304
305/* Timer/Counter1 Compare Match 1A */
306#define TIMER1_CMPA_vect_num    3
307#define TIMER1_CMPA_vect                _VECTOR(3)
308#define SIG_OUTPUT_COMPARE1A    _VECTOR(3)
309
310/* Timer/Counter1 Compare Match 1B */
311#define TIMER1_CMPB_vect_num    4
312#define TIMER1_CMPB_vect                _VECTOR(4)
313#define SIG_OUTPUT_COMPARE1B    _VECTOR(4)
314
315/* Timer/Counter1 Overflow */
316#define TIMER1_OVF1_vect_num    5
317#define TIMER1_OVF1_vect                _VECTOR(5)
318#define SIG_OVERFLOW1                   _VECTOR(5)
319
320/* Timer/Counter0 Overflow */
321#define TIMER0_OVF0_vect_num    6
322#define TIMER0_OVF0_vect                _VECTOR(6)
323#define SIG_OVERFLOW0                   _VECTOR(6)
324
325/* USI Start */
326#define USI_STRT_vect_num               7
327#define USI_STRT_vect                   _VECTOR(7)
328#define SIG_USI_START                   _VECTOR(7)
329
330/* USI Overflow */
331#define USI_OVF_vect_num                8
332#define USI_OVF_vect                    _VECTOR(8)
333#define SIG_USI_OVERFLOW                _VECTOR(8)
334
335/* EEPROM Ready */
336#define EE_RDY_vect_num                 9
337#define EE_RDY_vect                     _VECTOR(9)
338#define SIG_EEPROM_READY                _VECTOR(9)
339
340/* Analog Comparator */
341#define ANA_COMP_vect_num       10
342#define ANA_COMP_vect                   _VECTOR(10)
343#define SIG_ANA_COMP                    _VECTOR(10)
344#define SIG_COMPARATOR                  _VECTOR(10)
345
346/* ADC Conversion Complete */
347#define ADC_vect_num                    11
348#define ADC_vect                        _VECTOR(11)
349#define SIG_ADC                         _VECTOR(11)
350
351#define _VECTORS_SIZE 24
352
353
354/* Constants */
355#define RAMSTART    0x60
356#define RAMEND      0xDF
357#define XRAMEND     RAMEND
358#define E2END       0x7F
359#define E2PAGESIZE  4
360#define FLASHEND    0x07FF
361
362
363/* Fuses */
364
365#define FUSE_MEMORY_SIZE 2
366
367/* Low Fuse Byte */
368#define FUSE_CKSEL0      (unsigned char)~_BV(0)
369#define FUSE_CKSEL1      (unsigned char)~_BV(1)
370#define FUSE_CKSEL2      (unsigned char)~_BV(2)
371#define FUSE_CKSEL3      (unsigned char)~_BV(3)
372#define FUSE_SUT0        (unsigned char)~_BV(4)
373#define FUSE_SUT1        (unsigned char)~_BV(5)
374#define FUSE_CKOPT       (unsigned char)~_BV(6)
375#define FUSE_PLLCK       (unsigned char)~_BV(7)
376#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0)
377
378/* High Fuse Byte */
379#define FUSE_BODEN       (unsigned char)~_BV(0)
380#define FUSE_BODLEVEL    (unsigned char)~_BV(1)
381#define FUSE_EESAVE      (unsigned char)~_BV(2)
382#define FUSE_SPIEN       (unsigned char)~_BV(3)
383#define FUSE_RSTDISBL    (unsigned char)~_BV(4)
384#define HFUSE_DEFAULT (FUSE_SPIEN)
385
386
387/* Lock Bits */
388#define __LOCK_BITS_EXIST
389
390
391/* Signature */
392#define SIGNATURE_0 0x1E
393#define SIGNATURE_1 0x91
394#define SIGNATURE_2 0x09
395
396
397/* Deprecated items */
398#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__)
399
400#pragma GCC system_header
401
402#pragma GCC poison SIG_INTERRUPT0
403#pragma GCC poison SIG_PIN_CHANGE
404#pragma GCC poison SIG_OUTPUT_COMPARE1A
405#pragma GCC poison SIG_OUTPUT_COMPARE1B
406#pragma GCC poison SIG_OVERFLOW1
407#pragma GCC poison SIG_OVERFLOW0
408#pragma GCC poison SIG_USI_START
409#pragma GCC poison SIG_USI_OVERFLOW
410#pragma GCC poison SIG_EEPROM_READY
411#pragma GCC poison SIG_ANA_COMP
412#pragma GCC poison SIG_COMPARATOR
413#pragma GCC poison SIG_ADC
414
415#endif  /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */
416
417#define SLEEP_MODE_IDLE (0x00<<3)
418#define SLEEP_MODE_ADC (0x01<<3)
419#define SLEEP_MODE_PWR_DOWN (0x02<<3)
420#define SLEEP_MODE_STANDBY (0x03<<3)
421
422#endif  /* _AVR_IOTN26_H_ */
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