source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iotn4.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

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1/* Copyright (c) 2009 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iotn4.h 2063 2009-11-18 22:06:28Z arcanum $ */
32
33/* avr/iotn4.h - definitions for ATtiny4 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iotn4.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_ATtiny4_H_
49#define _AVR_ATtiny4_H_ 1
50
51
52/* Registers and associated bit numbers. */
53
54#define PINB _SFR_IO8(0x00)
55#define PINB0 0
56#define PINB1 1
57#define PINB2 2
58#define PINB3 3
59
60#define DDRB _SFR_IO8(0x01)
61#define DDB0 0
62#define DDB1 1
63#define DDB2 2
64#define DDB3 3
65
66#define PORTB _SFR_IO8(0x02)
67#define PORTB0 0
68#define PORTB1 1
69#define PORTB2 2
70#define PORTB3 3
71
72#define PUEB _SFR_IO8(0x03)
73#define PUEB0 0
74#define PUEB1 1
75#define PUEB2 2
76#define PUEB3 3
77
78#define PORTCR _SFR_IO8(0x0C)
79#define BBMB 1
80
81#define PCMSK _SFR_IO8(0x10)
82#define PCINT0 0
83#define PCINT1 1
84#define PCINT2 2
85#define PCINT3 3
86
87#define PCIFR _SFR_IO8(0x11)
88#define PCIF0 0
89
90#define PCICR _SFR_IO8(0x12)
91#define PCIE0 0
92
93#define EIMSK _SFR_IO8(0x13)
94#define INT0 0
95
96#define EIFR _SFR_IO8(0x14)
97#define INTF0 0
98
99#define EICRA _SFR_IO8(0x15)
100#define ISC00 0
101#define ISC01 1
102
103#define DIDR0 _SFR_IO8(0x17)
104#define AIN0D 0
105#define AIN1D 1
106
107#define ACSR _SFR_IO8(0x1F)
108#define ACIS0 0
109#define ACIS1 1
110#define ACIC 2
111#define ACIE 3
112#define ACI 4
113#define ACO 5
114#define ACD 7
115
116#define ICR0 _SFR_IO16(0x22)
117
118#define ICR0L _SFR_IO8(0x22)
119#define ICR0_0 0
120#define ICR0_1 1
121#define ICR0_2 2
122#define ICR0_3 3
123#define ICR0_4 4
124#define ICR0_5 5
125#define ICR0_6 6
126#define ICR0_7 7
127
128#define ICR0H _SFR_IO8(0x23)
129#define ICR0_8 0
130#define ICR0_9 1
131#define ICR0_10 2
132#define ICR0_11 3
133#define ICR0_12 4
134#define ICR0_13 5
135#define ICR0_14 6
136#define ICR0_15 7
137
138#define OCR0B _SFR_IO16(0x24)
139
140#define OCR0BL _SFR_IO8(0x24)
141#define OCR0B0 0
142#define OCR0B1 1
143#define OCR0B2 2
144#define OCR0B3 3
145#define OCR0B4 4
146#define OCR0B5 5
147#define OCR0B6 6
148#define OCR0B7 7
149
150#define OCR0BH _SFR_IO8(0x25)
151#define OCR0B8 0
152#define OCR0B9 1
153#define OCR0B10 2
154#define OCR0B11 3
155#define OCR0B12 4
156#define OCR0B13 5
157#define OCR0B14 6
158#define OCR0B15 7
159
160#define OCR0A _SFR_IO16(0x26)
161
162#define OCR0AL _SFR_IO8(0x26)
163#define OCR0A0 0
164#define OCR0A1 1
165#define OCR0A2 2
166#define OCR0A3 3
167#define OCR0A4 4
168#define OCR0A5 5
169#define OCR0A6 6
170#define OCR0A7 7
171
172#define OCR0AH _SFR_IO8(0x27)
173#define OCR0A8 0
174#define OCR0A9 1
175#define OCR0A10 2
176#define OCR0A11 3
177#define OCR0A12 4
178#define OCR0A13 5
179#define OCR0A14 6
180#define OCR0A15 7
181
182#define TCNT0 _SFR_IO16(0x28)
183
184#define TCNT0L _SFR_IO8(0x28)
185#define TCNT0_0 0
186#define TCNT0_1 1
187#define TCNT0_2 2
188#define TCNT0_3 3
189#define TCNT0_4 4
190#define TCNT0_5 5
191#define TCNT0_6 6
192#define TCNT0_7 7
193
194#define TCNT0H _SFR_IO8(0x29)
195#define TCNT0_8 0
196#define TCNT0_9 1
197#define TCNT0_10 2
198#define TCNT0_11 3
199#define TCNT0_12 4
200#define TCNT0_13 5
201#define TCNT0_14 6
202#define TCNT0_15 7
203
204#define TIFR0 _SFR_IO8(0x2A)
205#define TOV0 0
206#define OCF0A 1
207#define OCF0B 2
208#define ICF0 5
209
210#define TIMSK0 _SFR_IO8(0x2B)
211#define TOIE0 0
212#define OCIE0A 1
213#define OCIE0B 2
214#define ICIE0 5
215
216#define TCCR0C _SFR_IO8(0x2C)
217#define FOC0B 6
218#define FOC0A 7
219
220#define TCCR0B _SFR_IO8(0x2D)
221#define CS00 0
222#define CS01 1
223#define CS02 2
224#define WGM02 3
225#define WGM03 4
226#define ICES0 6
227#define ICNC0 7
228
229#define TCCR0A _SFR_IO8(0x2E)
230#define WGM00 0
231#define WGM01 1
232#define COM0B0 4
233#define COM0B1 5
234#define COM0A0 6
235#define COM0A1 7
236
237#define GTCCR _SFR_IO8(0x2F)
238#define PSR 0
239#define TSM 7
240
241#define WDTCSR _SFR_IO8(0x31)
242#define WDP0 0
243#define WDP1 1
244#define WDP2 2
245#define WDE 3
246#define WDP3 5
247#define WDIE 6
248#define WDIF 7
249
250#define NVMCSR _SFR_IO8(0x32)
251#define NVMBSY 7
252
253#define NVMCMD _SFR_IO8(0x33)
254#define NVMCMD0 0
255#define NVMCMD1 1
256#define NVMCMD2 2
257#define NVMCMD3 3
258#define NVMCMD4 4
259#define NVMCMD5 5
260
261#define VLMCSR _SFR_IO8(0x34)
262#define VLM0 0
263#define VLM1 1
264#define VLM2 2
265#define VLMIE 6
266#define VLMF 7
267
268#define PRR _SFR_IO8(0x35)
269#define PRTIM0 0
270#define PRADC 1
271
272#define __AVR_HAVE_PRR  ((1<<PRTIM0)|(1<<PRADC))
273#define __AVR_HAVE_PRR_PRTIM0
274#define __AVR_HAVE_PRR_PRADC
275
276#define CLKPSR _SFR_IO8(0x36)
277#define CLKPS0 0
278#define CLKPS1 1
279#define CLKPS2 2
280#define CLKPS3 3
281
282#define CLKMSR _SFR_IO8(0x37)
283#define CLKMS0 0
284#define CLKMS1 1
285
286#define OSCCAL _SFR_IO8(0x39)
287#define CAL0 0
288#define CAL1 1
289#define CAL2 2
290#define CAL3 3
291#define CAL4 4
292#define CAL5 5
293#define CAL6 6
294#define CAL7 7
295
296#define SMCR _SFR_IO8(0x3A)
297#define SE 0
298#define SM0 1
299#define SM1 2
300#define SM2 3
301
302#define RSTFLR _SFR_IO8(0x3B)
303#define PORF 0
304#define EXTRF 1
305#define WDRF 3
306
307#define CCP _SFR_IO8(0x3C)
308#define CCP0 0
309#define CCP1 1
310#define CCP2 2
311#define CCP3 3
312#define CCP4 4
313#define CCP5 5
314#define CCP6 6
315#define CCP7 7
316
317
318/* Interrupt vectors */
319/* Vector 0 is the reset vector */
320#define INT0_vect_num  1
321#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
322#define PCINT0_vect_num  2
323#define PCINT0_vect      _VECTOR(2)  /* Pin Change Interrupt Request 0 */
324#define TIM0_CAPT_vect_num  3
325#define TIM0_CAPT_vect      _VECTOR(3)  /* Timer/Counter0 Input Capture */
326#define TIM0_OVF_vect_num  4
327#define TIM0_OVF_vect      _VECTOR(4)  /* Timer/Counter0 Overflow */
328#define TIM0_COMPA_vect_num  5
329#define TIM0_COMPA_vect      _VECTOR(5)  /* Timer/Counter Compare Match A */
330#define TIM0_COMPB_vect_num  6
331#define TIM0_COMPB_vect      _VECTOR(6)  /* Timer/Counter Compare Match B */
332#define ANA_COMP_vect_num  7
333#define ANA_COMP_vect      _VECTOR(7)  /* Analog Comparator */
334#define WDT_vect_num  8
335#define WDT_vect      _VECTOR(8)  /* Watchdog Time-out */
336#define VLM_vect_num  9
337#define VLM_vect      _VECTOR(9)  /* Vcc Voltage Level Monitor */
338
339#define _VECTOR_SIZE 2 /* Size of individual vector. */
340#define _VECTORS_SIZE (10 * _VECTOR_SIZE)
341
342
343/* Constants */
344#define SPM_PAGESIZE (32)
345#define RAMSTART     (0x40)
346#define RAMSIZE      (32)
347#define RAMEND       (RAMSTART + RAMSIZE - 1)
348#define XRAMSTART    (NA)
349#define XRAMSIZE     (0)
350#define XRAMEND      (RAMEND)
351#define E2END        (0x0)
352#define E2PAGESIZE   (0)
353#define FLASHEND     (0x1FF)
354
355
356/* Fuses */
357#define FUSE_MEMORY_SIZE 0
358
359
360/* Lock Bits */
361#define __LOCK_BITS_EXIST
362
363
364/* Signature */
365#define SIGNATURE_0 0x1E
366#define SIGNATURE_1 0x90
367#define SIGNATURE_2 0x0A
368
369
370/* Device Pin Definitions */
371#define SPDATA_DDR   DDRCINT
372#define SPDATA_PORT  PORTCINT
373#define SPDATA_PIN   PINCINT
374#define SPDATA_BIT   INT0
375
376#define OC0A_DDR   DDRCINT
377#define OC0A_PORT  PORTCINT
378#define OC0A_PIN   PINCINT
379#define OC0A_BIT   INT0
380
381#define ADC0_DDR   DDRCINT
382#define ADC0_PORT  PORTCINT
383#define ADC0_PIN   PINCINT
384#define ADC0_BIT   INT0
385
386#define AIN0_DDR   DDRCINT
387#define AIN0_PORT  PORTCINT
388#define AIN0_PIN   PINCINT
389#define AIN0_BIT   INT0
390
391#define PB0_DDR   DDRCINT
392#define PB0_PORT  PORTCINT
393#define PB0_PIN   PINCINT
394#define PB0_BIT   INT0
395
396#define SPCLK_DDR   DDRCINT
397#define SPCLK_PORT  PORTCINT
398#define SPCLK_PIN   PINCINT
399#define SPCLK_BIT   INT1
400
401#define CLKI_DDR   DDRCINT
402#define CLKI_PORT  PORTCINT
403#define CLKI_PIN   PINCINT
404#define CLKI_BIT   INT1
405
406#define ICP0_DDR   DDRCINT
407#define ICP0_PORT  PORTCINT
408#define ICP0_PIN   PINCINT
409#define ICP0_BIT   INT1
410
411#define OC0B_DDR   DDRCINT
412#define OC0B_PORT  PORTCINT
413#define OC0B_PIN   PINCINT
414#define OC0B_BIT   INT1
415
416#define ADC1_DDR   DDRCINT
417#define ADC1_PORT  PORTCINT
418#define ADC1_PIN   PINCINT
419#define ADC1_BIT   INT1
420
421#define AIN1_DDR   DDRCINT
422#define AIN1_PORT  PORTCINT
423#define AIN1_PIN   PINCINT
424#define AIN1_BIT   INT1
425
426#define PB1_DDR   DDRCINT
427#define PB1_PORT  PORTCINT
428#define PB1_PIN   PINCINT
429#define PB1_BIT   INT1
430
431#define CLKO_DDR   DDRT
432#define CLKO_PORT  PORTT
433#define CLKO_PIN   PINT
434#define CLKO_BIT   T0
435
436#define PCINT2_DDR   DDRT
437#define PCINT2_PORT  PORTT
438#define PCINT2_PIN   PINT
439#define PCINT2_BIT   T0
440
441#define INT0_DDR   DDRT
442#define INT0_PORT  PORTT
443#define INT0_PIN   PINT
444#define INT0_BIT   T0
445
446#define ADC2_DDR   DDRT
447#define ADC2_PORT  PORTT
448#define ADC2_PIN   PINT
449#define ADC2_BIT   T0
450
451#define PB2_DDR   DDRT
452#define PB2_PORT  PORTT
453#define PB2_PIN   PINT
454#define PB2_BIT   T0
455
456#define PCINT3_DDR   DDRRESET
457#define PCINT3_PORT  PORTRESET
458#define PCINT3_PIN   PINRESET
459#define PCINT3_BIT   RESET
460
461#define ADC3_DDR   DDRRESET
462#define ADC3_PORT  PORTRESET
463#define ADC3_PIN   PINRESET
464#define ADC3_BIT   RESET
465
466#define PB3_DDR   DDRRESET
467#define PB3_PORT  PORTRESET
468#define PB3_PIN   PINRESET
469#define PB3_BIT   RESET
470
471#define SLEEP_MODE_IDLE (0x00<<1)
472#define SLEEP_MODE_ADC (0x01<<1)
473#define SLEEP_MODE_PWR_DOWN (0x02<<1)
474#define SLEEP_MODE_STANDBY (0x04<<1)
475
476#endif /* _AVR_ATtiny4_H_ */
477
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