source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iotn828.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

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1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATTINY828_H_INCLUDED
36#define _AVR_ATTINY828_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "iotn828.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define PINA    _SFR_IO8(0x00)
52#define PINA7   7
53#define PINA6   6
54#define PINA5   5
55#define PINA4   4
56#define PINA3   3
57#define PINA2   2
58#define PINA1   1
59#define PINA0   0
60
61#define DDRA    _SFR_IO8(0x01)
62#define DDRA7   7
63// Inserted "DDA7" from "DDRA7" due to compatibility
64#define DDA7    7
65#define DDRA6   6
66// Inserted "DDA6" from "DDRA6" due to compatibility
67#define DDA6    6
68#define DDRA5   5
69// Inserted "DDA5" from "DDRA5" due to compatibility
70#define DDA5    5
71#define DDRA4   4
72// Inserted "DDA4" from "DDRA4" due to compatibility
73#define DDA4    4
74#define DDRA3   3
75// Inserted "DDA3" from "DDRA3" due to compatibility
76#define DDA3    3
77#define DDRA2   2
78// Inserted "DDA2" from "DDRA2" due to compatibility
79#define DDA2    2
80#define DDRA1   1
81// Inserted "DDA1" from "DDRA1" due to compatibility
82#define DDA1    1
83#define DDRA0   0
84// Inserted "DDA0" from "DDRA0" due to compatibility
85#define DDA0    0
86
87#define PORTA   _SFR_IO8(0x02)
88#define PORTA7  7
89#define PORTA6  6
90#define PORTA5  5
91#define PORTA4  4
92#define PORTA3  3
93#define PORTA2  2
94#define PORTA1  1
95#define PORTA0  0
96
97#define PUEA    _SFR_IO8(0x03)
98
99#define PINB    _SFR_IO8(0x04)
100#define PINB7   7
101#define PINB6   6
102#define PINB5   5
103#define PINB4   4
104#define PINB3   3
105#define PINB2   2
106#define PINB1   1
107#define PINB0   0
108
109#define DDRB    _SFR_IO8(0x05)
110#define DDRB7   7
111// Inserted "DDB7" from "DDRB7" due to compatibility
112#define DDB7    7
113#define DDRB6   6
114// Inserted "DDB6" from "DDRB6" due to compatibility
115#define DDB6    6
116#define DDRB5   5
117// Inserted "DDB5" from "DDRB5" due to compatibility
118#define DDB5    5
119#define DDRB4   4
120// Inserted "DDB4" from "DDRB4" due to compatibility
121#define DDB4    4
122#define DDRB3   3
123// Inserted "DDB3" from "DDRB3" due to compatibility
124#define DDB3    3
125#define DDRB2   2
126// Inserted "DDB2" from "DDRB2" due to compatibility
127#define DDB2    2
128#define DDRB1   1
129// Inserted "DDB1" from "DDRB1" due to compatibility
130#define DDB1    1
131#define DDRB0   0
132// Inserted "DDB0" from "DDRB0" due to compatibility
133#define DDB0    0
134
135#define PORTB   _SFR_IO8(0x06)
136#define PORTB7  7
137#define PORTB6  6
138#define PORTB5  5
139#define PORTB4  4
140#define PORTB3  3
141#define PORTB2  2
142#define PORTB1  1
143#define PORTB0  0
144
145#define PUEB    _SFR_IO8(0x07)
146
147#define PINC    _SFR_IO8(0x08)
148#define PINC7   7
149#define PINC6   6
150#define PINC5   5
151#define PINC4   4
152#define PINC3   3
153#define PINC2   2
154#define PINC1   1
155#define PINC0   0
156
157#define DDRC    _SFR_IO8(0x09)
158#define DDRC7   7
159// Inserted "DDC7" from "DDRC7" due to compatibility
160#define DDC7    7
161#define DDRC6   6
162// Inserted "DDC6" from "DDRC6" due to compatibility
163#define DDC6    6
164#define DDRC5   5
165// Inserted "DDC5" from "DDRC5" due to compatibility
166#define DDC5    5
167#define DDRC4   4
168// Inserted "DDC4" from "DDRC4" due to compatibility
169#define DDC4    4
170#define DDRC3   3
171// Inserted "DDC3" from "DDRC3" due to compatibility
172#define DDC3    3
173#define DDRC2   2
174// Inserted "DDC2" from "DDRC2" due to compatibility
175#define DDC2    2
176#define DDRC1   1
177// Inserted "DDC1" from "DDRC1" due to compatibility
178#define DDC1    1
179#define DDRC0   0
180// Inserted "DDC0" from "DDRC0" due to compatibility
181#define DDC0    0
182
183#define PORTC   _SFR_IO8(0x0A)
184#define PORTC7  7
185#define PORTC6  6
186#define PORTC5  5
187#define PORTC4  4
188#define PORTC3  3
189#define PORTC2  2
190#define PORTC1  1
191#define PORTC0  0
192
193#define PUEC    _SFR_IO8(0x0B)
194
195#define PIND    _SFR_IO8(0x0C)
196#define PIND3   3
197#define PIND2   2
198#define PIND1   1
199#define PIND0   0
200
201#define DDRD    _SFR_IO8(0x0D)
202#define DDRD3   3
203// Inserted "DDD3" from "DDRD3" due to compatibility
204#define DDD3    3
205#define DDRD2   2
206// Inserted "DDD2" from "DDRD2" due to compatibility
207#define DDD2    2
208#define DDRD1   1
209// Inserted "DDD1" from "DDRD1" due to compatibility
210#define DDD1    1
211#define DDRD0   0
212// Inserted "DDD0" from "DDRD0" due to compatibility
213#define DDD0    0
214
215#define PORTD   _SFR_IO8(0x0E)
216#define PORTD3  3
217#define PORTD2  2
218#define PORTD1  1
219#define PORTD0  0
220
221#define PUED    _SFR_IO8(0x0F)
222
223/* Reserved [0x10..0x13] */
224
225#define PHDE    _SFR_IO8(0x14)
226#define PHDEC   2
227
228#define TIFR0   _SFR_IO8(0x15)
229#define TOV0    0
230#define OCF0A   1
231#define OCF0B   2
232
233#define TIFR1   _SFR_IO8(0x16)
234#define TOV1    0
235#define OCF1A   1
236#define OCF1B   2
237#define ICF1    5
238
239/* Reserved [0x17..0x1A] */
240
241#define PCIFR   _SFR_IO8(0x1B)
242#define PCIF0   0
243#define PCIF1   1
244#define PCIF2   2
245#define PCIF3   3
246
247#define EIFR    _SFR_IO8(0x1C)
248#define INTF0   0
249#define INTF1   1
250
251#define EIMSK   _SFR_IO8(0x1D)
252#define INT0    0
253#define INT1    1
254
255#define GPIOR0  _SFR_IO8(0x1E)
256
257#define EECR    _SFR_IO8(0x1F)
258#define EERE    0
259#define EEPE    1
260#define EEMPE   2
261#define EERIE   3
262#define EEPM0   4
263#define EEPM1   5
264
265#define EEDR    _SFR_IO8(0x20)
266
267#define EEAR    _SFR_IO8(0x21)
268
269/* Reserved [0x22] */
270
271#define GTCCR   _SFR_IO8(0x23)
272#define PSRSYNC 0
273#define TSM     7
274
275#define TCCR0A  _SFR_IO8(0x24)
276#define WGM00   0
277#define WGM01   1
278#define COM0B0  4
279#define COM0B1  5
280#define COM0A0  6
281#define COM0A1  7
282
283#define TCCR0B  _SFR_IO8(0x25)
284#define CS00    0
285#define CS01    1
286#define CS02    2
287#define WGM02   3
288#define FOC0B   6
289#define FOC0A   7
290
291#define TCNT0   _SFR_IO8(0x26)
292
293#define OCR0A   _SFR_IO8(0x27)
294
295#define OCR0B   _SFR_IO8(0x28)
296
297/* Reserved [0x29] */
298
299#define GPIOR1  _SFR_IO8(0x2A)
300
301#define GPIOR2  _SFR_IO8(0x2B)
302
303#define SPCR    _SFR_IO8(0x2C)
304#define SPR0    0
305#define SPR1    1
306#define CPHA    2
307#define CPOL    3
308#define MSTR    4
309#define DORD    5
310#define SPE     6
311#define SPIE    7
312
313#define SPSR    _SFR_IO8(0x2D)
314#define SPI2X   0
315#define WCOL    6
316#define SPIF    7
317
318#define SPDR    _SFR_IO8(0x2E)
319
320#define ACSRB   _SFR_IO8(0x2F)
321#define ACPMUX0 0
322#define ACPMUX1 1
323#define ACNMUX0 2
324#define ACNMUX1 3
325#define HLEV    6
326#define HSEL    7
327
328#define ACSRA   _SFR_IO8(0x30)
329#define ACIS0   0
330#define ACIS1   1
331#define ACIC    2
332#define ACIE    3
333#define ACI     4
334#define ACO     5
335#define ACPMUX2 6
336#define ACD     7
337
338/* Reserved [0x31..0x32] */
339
340#define SMCR    _SFR_IO8(0x33)
341#define SE      0
342#define SM0     1
343#define SM1     2
344
345#define MCUSR   _SFR_IO8(0x34)
346#define PORF    0
347#define EXTRF   1
348#define BORF    2
349#define WDRF    3
350
351#define MCUCR   _SFR_IO8(0x35)
352#define IVSEL   1
353
354#define CCP     _SFR_IO8(0x36)
355
356#define SPMCSR  _SFR_IO8(0x37)
357#define SPMEN   0
358#define PGERS   1
359#define PGWRT   2
360#define RWFLB   3
361#define RWWSRE  4
362#define RSIG    5
363#define RWWSB   6
364#define SPMIE   7
365
366/* Reserved [0x38..0x3C] */
367
368/* SP [0x3D..0x3E] */
369
370/* SREG [0x3F] */
371
372#define WDTCSR  _SFR_MEM8(0x60)
373#define WDE     3
374#define WDP0    0
375#define WDP1    1
376#define WDP2    2
377#define WDP3    5
378#define WDIE    6
379#define WDIF    7
380
381#define CLKPR   _SFR_MEM8(0x61)
382#define CLKPS0  0
383#define CLKPS1  1
384#define CLKPS2  2
385#define CLKPS3  3
386
387/* Reserved [0x62..0x63] */
388
389#define PRR     _SFR_MEM8(0x64)
390#define PRADC   0
391#define PRUSART0 1
392#define PRSPI   2
393#define PRTIM1  3
394#define PRTIM0  5
395#define PRTWI   7
396
397#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTWI))
398#define __AVR_HAVE_PRR_PRADC
399#define __AVR_HAVE_PRR_PRUSART0
400#define __AVR_HAVE_PRR_PRSPI
401#define __AVR_HAVE_PRR_PRTIM1
402#define __AVR_HAVE_PRR_PRTIM0
403#define __AVR_HAVE_PRR_PRTWI
404
405/* Reserved [0x65] */
406
407#define OSCCAL0 _SFR_MEM8(0x66)
408
409#define OSCCAL1 _SFR_MEM8(0x67)
410
411#define PCICR   _SFR_MEM8(0x68)
412#define PCIE0   0
413#define PCIE1   1
414#define PCIE2   2
415#define PCIE3   3
416
417#define EICRA   _SFR_MEM8(0x69)
418#define ISC00   0
419#define ISC01   1
420#define ISC10   2
421#define ISC11   3
422
423/* Reserved [0x6A] */
424
425#define PCMSK0  _SFR_MEM8(0x6B)
426#define PCINT0  0
427#define PCINT1  1
428#define PCINT2  2
429#define PCINT3  3
430#define PCINT4  4
431#define PCINT5  5
432#define PCINT6  6
433#define PCINT7  7
434
435#define PCMSK1  _SFR_MEM8(0x6C)
436#define PCINT8  0
437#define PCINT9  1
438#define PCINT10 2
439#define PCINT11 3
440#define PCINT12 4
441#define PCINT13 5
442#define PCINT14 6
443#define PCINT15 7
444
445#define PCMSK2  _SFR_MEM8(0x6D)
446#define PCINT16 0
447#define PCINT17 1
448#define PCINT18 2
449#define PCINT19 3
450#define PCINT20 4
451#define PCINT21 5
452#define PCINT22 6
453#define PCINT23 7
454
455#define TIMSK0  _SFR_MEM8(0x6E)
456#define TOIE0   0
457#define OCIE0A  1
458#define OCIE0B  2
459
460#define TIMSK1  _SFR_MEM8(0x6F)
461#define TOIE1   0
462#define OCIE1A  1
463#define OCIE1B  2
464#define ICIE1   5
465
466/* Reserved [0x70..0x72] */
467
468#define PCMSK3  _SFR_MEM8(0x73)
469#define PCINT24 0
470#define PCINT25 1
471#define PCINT26 2
472#define PCINT27 3
473
474/* Reserved [0x74..0x77] */
475
476/* Combine ADCL and ADCH */
477#ifndef __ASSEMBLER__
478#define ADC     _SFR_MEM16(0x78)
479#endif
480#define ADCW    _SFR_MEM16(0x78)
481
482#define ADCL    _SFR_MEM8(0x78)
483#define ADCH    _SFR_MEM8(0x79)
484
485#define ADCSRA  _SFR_MEM8(0x7A)
486#define ADPS0   0
487#define ADPS1   1
488#define ADPS2   2
489#define ADIE    3
490#define ADIF    4
491#define ADATE   5
492#define ADSC    6
493#define ADEN    7
494
495#define ADCSRB  _SFR_MEM8(0x7B)
496#define ADTS0   0
497#define ADTS1   1
498#define ADTS2   2
499#define ADLAR   3
500
501#define ADMUXA  _SFR_MEM8(0x7C)
502#define MUX0    0
503#define MUX1    1
504#define MUX2    2
505#define MUX3    3
506#define MUX4    4
507
508#define ADMUXB  _SFR_MEM8(0x7D)
509#define MUX5    0
510#define REFS    5
511
512#define DIDR0   _SFR_MEM8(0x7E)
513#define ADC0D   0
514#define ADC1D   1
515#define ADC2D   2
516#define ADC3D   3
517#define ADC4D   4
518#define ADC5D   5
519#define ADC6D   6
520#define ADC7D   7
521
522#define DIDR1   _SFR_MEM8(0x7F)
523#define ADC8D   0
524#define ADC9D   1
525#define ADC10D  2
526#define ADC11D  3
527#define ADC12D  4
528#define ADC13D  5
529#define ADC14D  6
530#define ADC15D  7
531
532#define TCCR1A  _SFR_MEM8(0x80)
533#define WGM10   0
534#define WGM11   1
535#define COM1B0  4
536#define COM1B1  5
537#define COM1A0  6
538#define COM1A1  7
539
540#define TCCR1B  _SFR_MEM8(0x81)
541#define CS10    0
542#define CS11    1
543#define CS12    2
544#define WGM12   3
545#define WGM13   4
546#define ICES1   6
547#define ICNC1   7
548
549#define TCCR1C  _SFR_MEM8(0x82)
550#define FOC1B   6
551#define FOC1A   7
552
553/* Reserved [0x83] */
554
555/* Combine TCNT1L and TCNT1H */
556#define TCNT1   _SFR_MEM16(0x84)
557
558#define TCNT1L  _SFR_MEM8(0x84)
559#define TCNT1H  _SFR_MEM8(0x85)
560
561/* Combine ICR1L and ICR1H */
562#define ICR1    _SFR_MEM16(0x86)
563
564#define ICR1L   _SFR_MEM8(0x86)
565#define ICR1H   _SFR_MEM8(0x87)
566
567/* Combine OCR1AL and OCR1AH */
568#define OCR1A   _SFR_MEM16(0x88)
569
570#define OCR1AL  _SFR_MEM8(0x88)
571#define OCR1AH  _SFR_MEM8(0x89)
572
573/* Combine OCR1BL and OCR1BH */
574#define OCR1B   _SFR_MEM16(0x8A)
575
576#define OCR1BL  _SFR_MEM8(0x8A)
577#define OCR1BH  _SFR_MEM8(0x8B)
578
579/* Reserved [0x8C..0xB7] */
580
581#define TWSCRA  _SFR_MEM8(0xB8)
582#define TWSME   0
583#define TWPME   1
584#define TWSIE   2
585#define TWEN    3
586#define TWASIE  4
587#define TWDIE   5
588#define TWSHE   7
589
590#define TWSCRB  _SFR_MEM8(0xB9)
591#define TWCMD0  0
592#define TWCMD1  1
593#define TWAA    2
594#define TWHNM   3
595
596#define TWSSRA  _SFR_MEM8(0xBA)
597#define TWAS    0
598#define TWDIR   1
599#define TWBE    2
600#define TWC     3
601#define TWRA    4
602#define TWCH    5
603#define TWASIF  6
604#define TWDIF   7
605
606#define TWSAM   _SFR_MEM8(0xBB)
607#define TWAE    0
608#define TWSAM1  1
609#define TWSAM2  2
610#define TWSAM3  3
611#define TWSAM4  4
612#define TWSAM5  5
613#define TWSAM6  6
614#define TWSAM7  7
615
616#define TWSA    _SFR_MEM8(0xBC)
617
618#define TWSD    _SFR_MEM8(0xBD)
619#define TWSD0   0
620#define TWSD1   1
621#define TWSD2   2
622#define TWSD3   3
623#define TWSD4   4
624#define TWSD5   5
625#define TWSD6   6
626#define TWSD7   7
627
628/* Reserved [0xBE..0xBF] */
629
630#define UCSRA   _SFR_MEM8(0xC0)
631#define MPCM    0
632#define U2X     1
633#define UPE     2
634#define DOR     3
635#define FE      4
636#define UDRE    5
637#define TXC     6
638#define RXC     7
639
640#define UCSRB   _SFR_MEM8(0xC1)
641#define TXB8    0
642#define RXB8    1
643#define UCSZ2   2
644#define TXEN    3
645#define RXEN    4
646#define UDRIE   5
647#define TXCIE   6
648#define RXCIE   7
649
650#define UCSRC   _SFR_MEM8(0xC2)
651#define UCPOL   0
652#define UCSZ0   1
653#define UCSZ1   2
654#define USBS    3
655#define UPM0    4
656#define UPM1    5
657#define UMSEL0  6
658#define UMSEL1  7
659
660#define UCSRD   _SFR_MEM8(0xC3)
661#define SFDE    5
662#define RXS     6
663#define RXSIE   7
664
665/* Combine UBRRL and UBRRH */
666#define UBRR    _SFR_MEM16(0xC4)
667
668#define UBRRL   _SFR_MEM8(0xC4)
669#define UBRRH   _SFR_MEM8(0xC5)
670
671#define UDR     _SFR_MEM8(0xC6)
672
673/* Reserved [0xC7..0xDD] */
674
675#define DIDR2   _SFR_MEM8(0xDE)
676#define ADC16D  0
677#define ADC17D  1
678#define ADC18D  2
679#define ADC19D  3
680#define ADC20D  4
681#define ADC21D  5
682#define ADC22D  6
683#define ADC23D  7
684
685#define DIDR3   _SFR_MEM8(0xDF)
686#define ADC24D  0
687#define ADC25D  1
688#define ADC26D  2
689#define ADC27D  3
690
691/* Reserved [0xE0..0xE1] */
692
693#define TOCPMCOE _SFR_MEM8(0xE2)
694#define TOCC0OE 0
695#define TOCC1OE 1
696#define TOCC2OE 2
697#define TOCC3OE 3
698#define TOCC4OE 4
699#define TOCC5OE 5
700#define TOCC6OE 6
701#define TOCC7OE 7
702
703/* Reserved [0xE3..0xE7] */
704
705#define TOCPMSA0 _SFR_MEM8(0xE8)
706#define TOCC0S0 0
707#define TOCC0S1 1
708#define TOCC1S0 2
709#define TOCC1S1 3
710#define TOCC2S0 4
711#define TOCC2S1 5
712#define TOCC3S0 6
713#define TOCC3S1 7
714
715#define TOCPMSA1 _SFR_MEM8(0xE9)
716#define TOCC4S0 0
717#define TOCC4S1 1
718#define TOCC5S0 2
719#define TOCC5S1 3
720#define TOCC6S0 4
721#define TOCC6S1 5
722#define TOCC7S0 6
723#define TOCC7S1 7
724
725/* Reserved [0xEA..0xEF] */
726
727#define OSCTCAL0A _SFR_MEM8(0xF0)
728
729#define OSCTCAL0B _SFR_MEM8(0xF1)
730
731
732
733/* Values and associated defines */
734
735
736#define SLEEP_MODE_IDLE (0x00<<1)
737#define SLEEP_MODE_ADC (0x01<<1)
738#define SLEEP_MODE_PWR_DOWN (0x02<<1)
739
740/* Interrupt vectors */
741/* Vector 0 is the reset vector */
742/* External Interrupt Request 0 */
743#define INT0_vect            _VECTOR(1)
744#define INT0_vect_num        1
745
746/* External Interrupt Request 1 */
747#define INT1_vect            _VECTOR(2)
748#define INT1_vect_num        2
749
750/* Pin Change Interrupt Request 0 */
751#define PCINT0_vect            _VECTOR(3)
752#define PCINT0_vect_num        3
753
754/* Pin Change Interrupt Request 1 */
755#define PCINT1_vect            _VECTOR(4)
756#define PCINT1_vect_num        4
757
758/* Pin Change Interrupt Request 2 */
759#define PCINT2_vect            _VECTOR(5)
760#define PCINT2_vect_num        5
761
762/* Pin Change Interrupt Request 3 */
763#define PCINT3_vect            _VECTOR(6)
764#define PCINT3_vect_num        6
765
766/* Watchdog Time-out Interrupt */
767#define WDT_vect            _VECTOR(7)
768#define WDT_vect_num        7
769
770/* Timer/Counter1 Capture Event */
771#define TIMER1_CAPT_vect            _VECTOR(8)
772#define TIMER1_CAPT_vect_num        8
773
774/* Timer/Counter1 Compare Match A */
775#define TIMER1_COMPA_vect            _VECTOR(9)
776#define TIMER1_COMPA_vect_num        9
777
778/* Timer/Counter1 Compare Match B */
779#define TIMER1_COMPB_vect            _VECTOR(10)
780#define TIMER1_COMPB_vect_num        10
781
782/* Timer/Counter1 Overflow */
783#define TIMER1_OVF_vect            _VECTOR(11)
784#define TIMER1_OVF_vect_num        11
785
786/* Timer/Counter0 Compare Match A */
787#define TIMER0_COMPA_vect            _VECTOR(12)
788#define TIMER0_COMPA_vect_num        12
789
790/* Timer/Counter0 Compare Match B */
791#define TIMER0_COMPB_vect            _VECTOR(13)
792#define TIMER0_COMPB_vect_num        13
793
794/* Timer/Counter0 Overflow */
795#define TIMER0_OVF_vect            _VECTOR(14)
796#define TIMER0_OVF_vect_num        14
797
798/* SPI Serial Transfer Complete */
799#define SPI_STC_vect            _VECTOR(15)
800#define SPI_STC_vect_num        15
801
802/* USART, Start */
803#define USART_START_vect            _VECTOR(16)
804#define USART_START_vect_num        16
805
806/* USART Rx Complete */
807#define USART_RX_vect            _VECTOR(17)
808#define USART_RX_vect_num        17
809
810/* USART, Data Register Empty */
811#define USART_UDRE_vect            _VECTOR(18)
812#define USART_UDRE_vect_num        18
813
814/* USART Tx Complete */
815#define USART_TX_vect            _VECTOR(19)
816#define USART_TX_vect_num        19
817
818/* ADC Conversion Complete */
819#define ADC_vect            _VECTOR(20)
820#define ADC_vect_num        20
821
822/* EEPROM Ready */
823#define EE_READY_vect            _VECTOR(21)
824#define EE_READY_vect_num        21
825
826/* Analog Comparator */
827#define ANALOG_COMP_vect            _VECTOR(22)
828#define ANALOG_COMP_vect_num        22
829
830/* Two-wire Serial Interface */
831#define TWI_SLAVE_vect            _VECTOR(23)
832#define TWI_SLAVE_vect_num        23
833
834/* Store Program Memory Read */
835#define SPM_Ready_vect            _VECTOR(24)
836#define SPM_Ready_vect_num        24
837
838/* Touch Sensing */
839#define QTRIP_vect            _VECTOR(25)
840#define QTRIP_vect_num        25
841
842#define _VECTORS_SIZE 52
843
844
845/* Constants */
846
847#define SPM_PAGESIZE 64
848#define FLASHSTART   0x0000
849#define FLASHEND     0x1FFF
850#define RAMSTART     0x0100
851#define RAMSIZE      512
852#define RAMEND       0x02FF
853#define E2START     0
854#define E2SIZE      256
855#define E2PAGESIZE  4
856#define E2END       0x00FF
857#define XRAMEND      RAMEND
858
859
860/* Fuses */
861
862#define FUSE_MEMORY_SIZE 3
863
864/* Low Fuse Byte */
865#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
866#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
867#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(4)
868#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(5)
869#define FUSE_CKOUT       (unsigned char)~_BV(6)
870#define FUSE_CKDIV8      (unsigned char)~_BV(7)
871#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_CKDIV8)
872
873
874/* High Fuse Byte */
875#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
876#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
877#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
878#define FUSE_EESAVE      (unsigned char)~_BV(3)
879#define FUSE_WDTON       (unsigned char)~_BV(4)
880#define FUSE_SPIEN       (unsigned char)~_BV(5)
881#define FUSE_DWEN        (unsigned char)~_BV(6)
882#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
883#define HFUSE_DEFAULT    (FUSE_SPIEN)
884
885
886/* Extended Fuse Byte */
887#define FUSE_BOOTRST     (unsigned char)~_BV(0)
888#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
889#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
890#define FUSE_BODACT0     (unsigned char)~_BV(4)
891#define FUSE_BODACT1     (unsigned char)~_BV(5)
892#define FUSE_BODPD0      (unsigned char)~_BV(6)
893#define FUSE_BODPD1      (unsigned char)~_BV(7)
894#define EFUSE_DEFAULT    (0xFF)
895
896
897
898/* Lock Bits */
899#define __LOCK_BITS_EXIST
900#define __BOOT_LOCK_BITS_0_EXIST
901#define __BOOT_LOCK_BITS_1_EXIST
902
903
904/* Signature */
905#define SIGNATURE_0 0x1E
906#define SIGNATURE_1 0x93
907#define SIGNATURE_2 0x14
908
909
910#endif /* #ifdef _AVR_ATTINY828_H_INCLUDED */
911
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