source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iotn841.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

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1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_ATTINY841_H_INCLUDED
36#define _AVR_ATTINY841_H_INCLUDED
37
38
39#ifndef _AVR_IO_H_
40#  error "Include <avr/io.h> instead of this file."
41#endif
42
43#ifndef _AVR_IOXXX_H_
44#  define _AVR_IOXXX_H_ "iotn841.h"
45#else
46#  error "Attempt to include more than one <avr/ioXXX.h> file."
47#endif
48
49/* Registers and associated bit numbers */
50
51#define ADCSRB  _SFR_IO8(0x04)
52#define ADTS0   0
53#define ADTS1   1
54#define ADTS2   2
55#define ADLAR   3
56
57#define ADCSRA  _SFR_IO8(0x05)
58#define ADPS0   0
59#define ADPS1   1
60#define ADPS2   2
61#define ADIE    3
62#define ADIF    4
63#define ADATE   5
64#define ADSC    6
65#define ADEN    7
66
67/* Combine ADCL and ADCH */
68#ifndef __ASSEMBLER__
69#define ADC     _SFR_IO16(0x06)
70#endif
71#define ADCW    _SFR_IO16(0x06)
72
73#define ADCL    _SFR_IO8(0x06)
74#define ADCH    _SFR_IO8(0x07)
75
76#define ADMUXB  _SFR_IO8(0x08)
77#define GSEL0   0
78#define GSEL1   1
79#define REFS0   5
80#define REFS1   6
81#define REFS2   7
82
83#define ADMUXA  _SFR_IO8(0x09)
84#define MUX0    0
85#define MUX1    1
86#define MUX2    2
87#define MUX3    3
88#define MUX4    4
89#define MUX5    5
90
91#define ACSR0A  _SFR_IO8(0x0A)
92#define ACIS00  0
93#define ACIS01  1
94#define ACIC0   2
95#define ACIE0   3
96#define ACI0    4
97#define ACO0    5
98#define ACPMUX2 6
99#define ACD0    7
100
101#define ACSR0B  _SFR_IO8(0x0B)
102#define ACPMUX0 0
103#define ACPMUX1 1
104#define ACNMUX0 2
105#define ACNMUX1 3
106#define ACOE0   4
107#define HLEV0   6
108#define HSEL0   7
109
110#define ACSR1A  _SFR_IO8(0x0C)
111#define ACIS10  0
112#define ACIS11  1
113#define ACIC1   2
114#define ACIE1   3
115#define ACI1    4
116#define ACO1    5
117#define ACBG1   6
118#define ACD1    7
119
120#define ACSR1B  _SFR_IO8(0x0D)
121#define ACME1   2
122#define ACOE1   4
123#define HLEV1   6
124#define HSEL1   7
125
126#define TIFR1   _SFR_IO8(0x0E)
127#define TOV1    0
128#define OCF1A   1
129#define OCF1B   2
130#define ICF1    5
131
132#define TIMSK1  _SFR_IO8(0x0F)
133#define TOIE1   0
134#define OCIE1A  1
135#define OCIE1B  2
136#define ICIE1   5
137
138#define TIFR2   _SFR_IO8(0x10)
139#define TOV2    0
140#define OCF2A   1
141#define OCF2B   2
142#define ICF2    5
143
144#define TIMSK2  _SFR_IO8(0x11)
145#define TOIE2   0
146#define OCIE2A  1
147#define OCIE2B  2
148#define ICIE2   5
149
150#define PCMSK0  _SFR_IO8(0x12)
151#define PCINT0  0
152#define PCINT1  1
153#define PCINT2  2
154#define PCINT3  3
155#define PCINT4  4
156#define PCINT5  5
157#define PCINT6  6
158#define PCINT7  7
159
160#define GPIOR0  _SFR_IO8(0x13)
161
162#define GPIOR1  _SFR_IO8(0x14)
163
164#define GPIOR2  _SFR_IO8(0x15)
165
166#define PINB    _SFR_IO8(0x16)
167#define PINB3   3
168#define PINB2   2
169#define PINB1   1
170#define PINB0   0
171
172#define DDRB    _SFR_IO8(0x17)
173#define DDRB3   3
174// Inserted "DDB3" from "DDRB3" due to compatibility
175#define DDB3    3
176#define DDRB2   2
177// Inserted "DDB2" from "DDRB2" due to compatibility
178#define DDB2    2
179#define DDRB1   1
180// Inserted "DDB1" from "DDRB1" due to compatibility
181#define DDB1    1
182#define DDRB0   0
183// Inserted "DDB0" from "DDRB0" due to compatibility
184#define DDB0    0
185
186#define PORTB   _SFR_IO8(0x18)
187#define PORTB3  3
188#define PORTB2  2
189#define PORTB1  1
190#define PORTB0  0
191
192#define PINA    _SFR_IO8(0x19)
193#define PINA7   7
194#define PINA6   6
195#define PINA5   5
196#define PINA4   4
197#define PINA3   3
198#define PINA2   2
199#define PINA1   1
200#define PINA0   0
201
202#define DDRA    _SFR_IO8(0x1A)
203#define DDRA7   7
204// Inserted "DDA7" from "DDRA7" due to compatibility
205#define DDA7    7
206#define DDRA6   6
207// Inserted "DDA6" from "DDRA6" due to compatibility
208#define DDA6    6
209#define DDRA5   5
210// Inserted "DDA5" from "DDRA5" due to compatibility
211#define DDA5    5
212#define DDRA4   4
213// Inserted "DDA4" from "DDRA4" due to compatibility
214#define DDA4    4
215#define DDRA3   3
216// Inserted "DDA3" from "DDRA3" due to compatibility
217#define DDA3    3
218#define DDRA2   2
219// Inserted "DDA2" from "DDRA2" due to compatibility
220#define DDA2    2
221#define DDRA1   1
222// Inserted "DDA1" from "DDRA1" due to compatibility
223#define DDA1    1
224#define DDRA0   0
225// Inserted "DDA0" from "DDRA0" due to compatibility
226#define DDA0    0
227
228#define PORTA   _SFR_IO8(0x1B)
229#define PORTA7  7
230#define PORTA6  6
231#define PORTA5  5
232#define PORTA4  4
233#define PORTA3  3
234#define PORTA2  2
235#define PORTA1  1
236#define PORTA0  0
237
238#define EECR    _SFR_IO8(0x1C)
239#define EERE    0
240#define EEPE    1
241#define EEMPE   2
242#define EERIE   3
243#define EEPM0   4
244#define EEPM1   5
245
246#define EEDR    _SFR_IO8(0x1D)
247
248/* Combine EEARL and EEARH */
249#define EEAR    _SFR_IO16(0x1E)
250
251#define EEARL   _SFR_IO8(0x1E)
252#define EEARH   _SFR_IO8(0x1F)
253
254#define PCMSK1  _SFR_IO8(0x20)
255#define PCINT8  0
256#define PCINT9  1
257#define PCINT10 2
258#define PCINT11 3
259
260#define WDTCSR  _SFR_IO8(0x21)
261#define WDE     3
262#define WDP0    0
263#define WDP1    1
264#define WDP2    2
265#define WDP3    5
266#define WDIE    6
267#define WDIF    7
268
269#define TCCR1C  _SFR_IO8(0x22)
270#define FOC1B   6
271#define FOC1A   7
272
273#define GTCCR   _SFR_IO8(0x23)
274#define PSR     0
275#define TSM     7
276
277/* Combine ICR1L and ICR1H */
278#define ICR1    _SFR_IO16(0x24)
279
280#define ICR1L   _SFR_IO8(0x24)
281#define ICR1H   _SFR_IO8(0x25)
282
283/* Reserved [0x26..0x27] */
284
285/* Combine OCR1BL and OCR1BH */
286#define OCR1B   _SFR_IO16(0x28)
287
288#define OCR1BL  _SFR_IO8(0x28)
289#define OCR1BH  _SFR_IO8(0x29)
290
291/* Combine OCR1AL and OCR1AH */
292#define OCR1A   _SFR_IO16(0x2A)
293
294#define OCR1AL  _SFR_IO8(0x2A)
295#define OCR1AH  _SFR_IO8(0x2B)
296
297/* Combine TCNT1L and TCNT1H */
298#define TCNT1   _SFR_IO16(0x2C)
299
300#define TCNT1L  _SFR_IO8(0x2C)
301#define TCNT1H  _SFR_IO8(0x2D)
302
303#define TCCR1B  _SFR_IO8(0x2E)
304#define CS10    0
305#define CS11    1
306#define CS12    2
307#define WGM12   3
308#define WGM13   4
309#define ICES1   6
310#define ICNC1   7
311
312#define TCCR1A  _SFR_IO8(0x2F)
313#define WGM10   0
314#define WGM11   1
315#define COM1B0  4
316#define COM1B1  5
317#define COM1A0  6
318#define COM1A1  7
319
320#define TCCR0A  _SFR_IO8(0x30)
321#define WGM00   0
322#define WGM01   1
323#define COM0B0  4
324#define COM0B1  5
325#define COM0A0  6
326#define COM0A1  7
327
328/* Reserved [0x31] */
329
330#define TCNT0   _SFR_IO8(0x32)
331
332#define TCCR0B  _SFR_IO8(0x33)
333#define CS00    0
334#define CS01    1
335#define CS02    2
336#define WGM02   3
337#define FOC0B   6
338#define FOC0A   7
339
340#define MCUSR   _SFR_IO8(0x34)
341#define PORF    0
342#define EXTRF   1
343#define BORF    2
344#define WDRF    3
345
346#define MCUCR   _SFR_IO8(0x35)
347#define ISC00   0
348#define ISC01   1
349#define SM0     3
350#define SM1     4
351#define SE      5
352
353#define OCR0A   _SFR_IO8(0x36)
354
355#define SPMCSR  _SFR_IO8(0x37)
356#define SPMEN   0
357#define PGERS   1
358#define PGWRT   2
359#define RFLB    3
360#define CTPB    4
361#define RSIG    5
362
363#define TIFR0   _SFR_IO8(0x38)
364#define TOV0    0
365#define OCF0A   1
366#define OCF0B   2
367
368#define TIMSK0  _SFR_IO8(0x39)
369#define TOIE0   0
370#define OCIE0A  1
371#define OCIE0B  2
372
373#define GIFR    _SFR_IO8(0x3A)
374#define PCIF0   4
375#define PCIF1   5
376#define INTF0   6
377
378#define GIMSK   _SFR_IO8(0x3B)
379#define PCIE0   4
380#define PCIE1   5
381#define INT0    6
382
383#define OCR0B   _SFR_IO8(0x3C)
384
385/* SP [0x3D..0x3E] */
386
387/* SREG [0x3F] */
388
389#define DIDR0   _SFR_MEM8(0x60)
390#define ADC0D   0
391#define ADC1D   1
392#define ADC2D   2
393#define ADC3D   3
394#define ADC4D   4
395#define ADC5D   5
396#define ADC6D   6
397#define ADC7D   7
398
399#define DIDR1   _SFR_MEM8(0x61)
400#define ADC11D  0
401#define ADC10D  1
402#define ADC8D   2
403#define ADC9D   3
404
405#define PUEB    _SFR_MEM8(0x62)
406
407#define PUEA    _SFR_MEM8(0x63)
408
409#define PORTCR  _SFR_MEM8(0x64)
410#define BBMB    1
411#define BBMA    0
412
413#define REMAP   _SFR_MEM8(0x65)
414#define U0MAP   0
415#define SPIMAP  1
416
417#define TOCPMCOE _SFR_MEM8(0x66)
418#define TOCC0OE 0
419#define TOCC1OE 1
420#define TOCC2OE 2
421#define TOCC3OE 3
422#define TOCC4OE 4
423#define TOCC5OE 5
424#define TOCC6OE 6
425#define TOCC7OE 7
426
427#define TOCPMSA0 _SFR_MEM8(0x67)
428#define TOCC0S0 0
429#define TOCC0S1 1
430#define TOCC1S0 2
431#define TOCC1S1 3
432#define TOCC2S0 4
433#define TOCC2S1 5
434#define TOCC3S0 6
435#define TOCC3S1 7
436
437#define TOCPMSA1 _SFR_MEM8(0x68)
438#define TOCC4S0 0
439#define TOCC4S1 1
440#define TOCC5S0 2
441#define TOCC5S1 3
442#define TOCC6S0 4
443#define TOCC6S1 5
444#define TOCC7S0 6
445#define TOCC7S1 7
446
447/* Reserved [0x69] */
448
449#define PHDE    _SFR_MEM8(0x6A)
450#define PHDEA0  0
451#define PHDEA1  1
452
453/* Reserved [0x6B..0x6F] */
454
455#define PRR     _SFR_MEM8(0x70)
456#define PRADC   0
457#define PRTIM0  1
458#define PRTIM1  2
459#define PRTIM2  3
460#define PRSPI   4
461#define PRUSART0 5
462#define PRUSART1 6
463#define PRTWI   7
464
465#define __AVR_HAVE_PRR  ((1<<PRADC)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTWI))
466#define __AVR_HAVE_PRR_PRADC
467#define __AVR_HAVE_PRR_PRTIM0
468#define __AVR_HAVE_PRR_PRTIM1
469#define __AVR_HAVE_PRR_PRTIM2
470#define __AVR_HAVE_PRR_PRSPI
471#define __AVR_HAVE_PRR_PRUSART0
472#define __AVR_HAVE_PRR_PRUSART1
473#define __AVR_HAVE_PRR_PRTWI
474
475#define CCP     _SFR_MEM8(0x71)
476
477#define CLKCR   _SFR_MEM8(0x72)
478#define CKSEL0  0
479#define CKSEL1  1
480#define CKSEL2  2
481#define CKSEL3  3
482#define SUT     4
483#define CKOUTC  5
484#define CSTR    6
485#define OSCRDY  7
486
487#define CLKPR   _SFR_MEM8(0x73)
488#define CLKPS0  0
489#define CLKPS1  1
490#define CLKPS2  2
491#define CLKPS3  3
492
493#define OSCCAL0 _SFR_MEM8(0x74)
494
495#define OSCTCAL0A _SFR_MEM8(0x75)
496
497#define OSCTCAL0B _SFR_MEM8(0x76)
498
499#define OSCCAL1 _SFR_MEM8(0x77)
500
501/* Reserved [0x78..0x7F] */
502
503#define UDR0    _SFR_MEM8(0x80)
504
505/* Combine UBRR0L and UBRR0H */
506#define UBRR0   _SFR_MEM16(0x81)
507
508#define UBRR0L  _SFR_MEM8(0x81)
509#define UBRR0H  _SFR_MEM8(0x82)
510
511#define UCSR0D  _SFR_MEM8(0x83)
512#define SFDE0   5
513#define RXS0    6
514#define RXSIE0  7
515
516#define UCSR0C  _SFR_MEM8(0x84)
517#define UCPOL0  0
518#define UCSZ00  1
519#define UCSZ01  2
520#define USBS0   3
521#define UPM00   4
522#define UPM01   5
523#define UMSEL00 6
524#define UMSEL01 7
525
526#define UCSR0B  _SFR_MEM8(0x85)
527#define TXB80   0
528#define RXB80   1
529#define UCSZ02  2
530#define TXEN0   3
531#define RXEN0   4
532#define UDRIE0  5
533#define TXCIE0  6
534#define RXCIE0  7
535
536#define UCSR0A  _SFR_MEM8(0x86)
537#define MPCM0   0
538#define U2X0    1
539#define UPE0    2
540#define DOR0    3
541#define FE0     4
542#define UDRE0   5
543#define TXC0    6
544#define RXC0    7
545
546/* Reserved [0x87..0x8F] */
547
548#define UDR1    _SFR_MEM8(0x90)
549
550/* Combine UBRR1L and UBRR1H */
551#define UBRR1   _SFR_MEM16(0x91)
552
553#define UBRR1L  _SFR_MEM8(0x91)
554#define UBRR1H  _SFR_MEM8(0x92)
555
556#define UCSR1D  _SFR_MEM8(0x93)
557#define SFDE1   5
558#define RXS1    6
559#define RXSIE1  7
560
561#define UCSR1C  _SFR_MEM8(0x94)
562#define UCPOL1  0
563#define UCSZ10  1
564#define UCSZ11  2
565#define USBS1   3
566#define UPM10   4
567#define UPM11   5
568#define UMSEL10 6
569#define UMSEL11 7
570
571#define UCSR1B  _SFR_MEM8(0x95)
572#define TXB81   0
573#define RXB81   1
574#define UCSZ12  2
575#define TXEN1   3
576#define RXEN1   4
577#define UDRIE1  5
578#define TXCIE1  6
579#define RXCIE1  7
580
581#define UCSR1A  _SFR_MEM8(0x96)
582#define MPCM1   0
583#define U2X1    1
584#define UPE1    2
585#define DOR1    3
586#define FE1     4
587#define UDRE1   5
588#define TXC1    6
589#define RXC1    7
590
591/* Reserved [0x97..0x9F] */
592
593#define TWSD    _SFR_MEM8(0xA0)
594#define TWSD0   0
595#define TWSD1   1
596#define TWSD2   2
597#define TWSD3   3
598#define TWSD4   4
599#define TWSD5   5
600#define TWSD6   6
601#define TWSD7   7
602
603#define TWSAM   _SFR_MEM8(0xA1)
604#define TWAE    0
605#define TWSAM1  1
606#define TWSAM2  2
607#define TWSAM3  3
608#define TWSAM4  4
609#define TWSAM5  5
610#define TWSAM6  6
611#define TWSAM7  7
612
613#define TWSA    _SFR_MEM8(0xA2)
614
615#define TWSSRA  _SFR_MEM8(0xA3)
616#define TWAS    0
617#define TWDIR   1
618#define TWBE    2
619#define TWC     3
620#define TWRA    4
621#define TWCH    5
622#define TWASIF  6
623#define TWDIF   7
624
625#define TWSCRB  _SFR_MEM8(0xA4)
626#define TWCMD0  0
627#define TWCMD1  1
628#define TWAA    2
629#define TWHNM   3
630
631#define TWSCRA  _SFR_MEM8(0xA5)
632#define TWSME   0
633#define TWPME   1
634#define TWSIE   2
635#define TWEN    3
636#define TWASIE  4
637#define TWDIE   5
638#define TWSHE   7
639
640/* Reserved [0xA6..0xAF] */
641
642#define SPDR    _SFR_MEM8(0xB0)
643
644#define SPSR    _SFR_MEM8(0xB1)
645#define SPI2X   0
646#define WCOL    6
647#define SPIF    7
648
649#define SPCR    _SFR_MEM8(0xB2)
650#define SPR0    0
651#define SPR1    1
652#define CPHA    2
653#define CPOL    3
654#define MSTR    4
655#define DORD    5
656#define SPE     6
657#define SPIE    7
658
659/* Reserved [0xB3..0xBF] */
660
661/* Combine ICR2L and ICR2H */
662#define ICR2    _SFR_MEM16(0xC0)
663
664#define ICR2L   _SFR_MEM8(0xC0)
665#define ICR2H   _SFR_MEM8(0xC1)
666
667/* Combine OCR2BL and OCR2BH */
668#define OCR2B   _SFR_MEM16(0xC2)
669
670#define OCR2BL  _SFR_MEM8(0xC2)
671#define OCR2BH  _SFR_MEM8(0xC3)
672
673/* Combine OCR2AL and OCR2AH */
674#define OCR2A   _SFR_MEM16(0xC4)
675
676#define OCR2AL  _SFR_MEM8(0xC4)
677#define OCR2AH  _SFR_MEM8(0xC5)
678
679/* Combine TCNT2L and TCNT2H */
680#define TCNT2   _SFR_MEM16(0xC6)
681
682#define TCNT2L  _SFR_MEM8(0xC6)
683#define TCNT2H  _SFR_MEM8(0xC7)
684
685#define TCCR2C  _SFR_MEM8(0xC8)
686#define FOC2B   6
687#define FOC2A   7
688
689#define TCCR2B  _SFR_MEM8(0xC9)
690#define CS20    0
691#define CS21    1
692#define CS22    2
693#define WGM22   3
694#define WGM23   4
695#define ICES2   6
696#define ICNC2   7
697
698#define TCCR2A  _SFR_MEM8(0xCA)
699#define WGM20   0
700#define WGM21   1
701#define COM2B0  4
702#define COM2B1  5
703#define COM2A0  6
704#define COM2A1  7
705
706
707
708/* Values and associated defines */
709
710
711#define SLEEP_MODE_IDLE (0x00<<3)
712#define SLEEP_MODE_ADC (0x01<<3)
713#define SLEEP_MODE_PWR_DOWN (0x02<<3)
714#define SLEEP_MODE_STANDBY (0x03<<3)
715
716/* Interrupt vectors */
717/* Vector 0 is the reset vector */
718/* External Interrupt Request 0 */
719#define INT0_vect            _VECTOR(1)
720#define INT0_vect_num        1
721
722/* Pin Change Interrupt Request 0 */
723#define PCINT0_vect            _VECTOR(2)
724#define PCINT0_vect_num        2
725
726/* Pin Change Interrupt Request 1 */
727#define PCINT1_vect            _VECTOR(3)
728#define PCINT1_vect_num        3
729
730/* Watchdog Time-out Interrupt */
731#define WDT_vect            _VECTOR(4)
732#define WDT_vect_num        4
733
734/* Timer/Counter1 Capture Event */
735#define TIMER1_CAPT_vect            _VECTOR(5)
736#define TIMER1_CAPT_vect_num        5
737
738/* Timer/Counter1 Compare Match A */
739#define TIMER1_COMPA_vect            _VECTOR(6)
740#define TIMER1_COMPA_vect_num        6
741
742/* Timer/Counter1 Compare Match B */
743#define TIMER1_COMPB_vect            _VECTOR(7)
744#define TIMER1_COMPB_vect_num        7
745
746/* Timer/Counter1 Overflow */
747#define TIMER1_OVF_vect            _VECTOR(8)
748#define TIMER1_OVF_vect_num        8
749
750/* TimerCounter0 Compare Match A */
751#define TIMER0_COMPA_vect            _VECTOR(9)
752#define TIMER0_COMPA_vect_num        9
753
754/* TimerCounter0 Compare Match B */
755#define TIMER0_COMPB_vect            _VECTOR(10)
756#define TIMER0_COMPB_vect_num        10
757
758/* Timer/Couner0 Overflow */
759#define TIMER0_OVF_vect            _VECTOR(11)
760#define TIMER0_OVF_vect_num        11
761
762/* Analog Comparator 0 */
763#define ANA_COMP0_vect            _VECTOR(12)
764#define ANA_COMP0_vect_num        12
765
766/* ADC Conversion Complete */
767#define ADC_vect            _VECTOR(13)
768#define ADC_vect_num        13
769
770/* EEPROM Ready */
771#define EE_RDY_vect            _VECTOR(14)
772#define EE_RDY_vect_num        14
773
774/* Analog Comparator 1 */
775#define ANA_COMP1_vect            _VECTOR(15)
776#define ANA_COMP1_vect_num        15
777
778/* Timer/Counter2 Capture Event */
779#define TIMER2_CAPT_vect            _VECTOR(16)
780#define TIMER2_CAPT_vect_num        16
781
782/* Timer/Counter2 Compare Match A */
783#define TIMER2_COMPA_vect            _VECTOR(17)
784#define TIMER2_COMPA_vect_num        17
785
786/* Timer/Counter2 Compare Match B */
787#define TIMER2_COMPB_vect            _VECTOR(18)
788#define TIMER2_COMPB_vect_num        18
789
790/* Timer/Counter2 Overflow */
791#define TIMER2_OVF_vect            _VECTOR(19)
792#define TIMER2_OVF_vect_num        19
793
794/* Serial Peripheral Interface */
795#define SPI_vect            _VECTOR(20)
796#define SPI_vect_num        20
797
798/* USART0, Start */
799#define USART0_START_vect            _VECTOR(21)
800#define USART0_START_vect_num        21
801
802/* USART0, Rx Complete */
803#define USART0_RX_vect            _VECTOR(22)
804#define USART0_RX_vect_num        22
805
806/* USART0 Data Register Empty */
807#define USART0_UDRE_vect            _VECTOR(23)
808#define USART0_UDRE_vect_num        23
809
810/* USART0, Tx Complete */
811#define USART0_TX_vect            _VECTOR(24)
812#define USART0_TX_vect_num        24
813
814/* USART1, Start */
815#define USART1_START_vect            _VECTOR(25)
816#define USART1_START_vect_num        25
817
818/* USART1, Rx Complete */
819#define USART1_RX_vect            _VECTOR(26)
820#define USART1_RX_vect_num        26
821
822/* USART1 Data Register Empty */
823#define USART1_UDRE_vect            _VECTOR(27)
824#define USART1_UDRE_vect_num        27
825
826/* USART1, Tx Complete */
827#define USART1_TX_vect            _VECTOR(28)
828#define USART1_TX_vect_num        28
829
830/* Two-wire Serial Interface */
831#define TWI_SLAVE_vect            _VECTOR(29)
832#define TWI_SLAVE_vect_num        29
833
834#define _VECTORS_SIZE 60
835
836
837/* Constants */
838
839#define SPM_PAGESIZE 16
840#define FLASHSTART   0x0000
841#define FLASHEND     0x1FFF
842#define RAMSTART     0x0100
843#define RAMSIZE      512
844#define RAMEND       0x02FF
845#define E2START     0
846#define E2SIZE      512
847#define E2PAGESIZE  4
848#define E2END       0x01FF
849#define XRAMEND      RAMEND
850
851
852/* Fuses */
853
854#define FUSE_MEMORY_SIZE 3
855
856/* Low Fuse Byte */
857#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
858#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
859#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
860#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
861#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
862#define FUSE_CKOUT       (unsigned char)~_BV(6)
863#define FUSE_CKDIV8      (unsigned char)~_BV(7)
864#define LFUSE_DEFAULT    (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8)
865
866
867/* High Fuse Byte */
868#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
869#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
870#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
871#define FUSE_EESAVE      (unsigned char)~_BV(3)
872#define FUSE_WDTON       (unsigned char)~_BV(4)
873#define FUSE_SPIEN       (unsigned char)~_BV(5)
874#define FUSE_DWEN        (unsigned char)~_BV(6)
875#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
876#define HFUSE_DEFAULT    (FUSE_SPIEN)
877
878
879/* Extended Fuse Byte */
880#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
881#define FUSE_BODACT0     (unsigned char)~_BV(1)
882#define FUSE_BODACT1     (unsigned char)~_BV(2)
883#define FUSE_BODPD0      (unsigned char)~_BV(3)
884#define FUSE_BODPD1      (unsigned char)~_BV(4)
885#define FUSE_ULPOSCSEL0  (unsigned char)~_BV(5)
886#define FUSE_ULPOSCSEL1  (unsigned char)~_BV(6)
887#define FUSE_ULPOSCSEL2  (unsigned char)~_BV(7)
888#define EFUSE_DEFAULT    (0xFF)
889
890
891
892/* Lock Bits */
893#define __LOCK_BITS_EXIST
894
895
896/* Signature */
897#define SIGNATURE_0 0x1E
898#define SIGNATURE_1 0x93
899#define SIGNATURE_2 0x15
900
901
902#endif /* #ifdef _AVR_ATTINY841_H_INCLUDED */
903
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