source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iox128d4.h @ 46

Last change on this file since 46 was 46, checked in by jrpelegrina, 4 years ago

First release to Xenial

File size: 244.5 KB
Line 
1/*****************************************************************************
2 *
3 * Copyright (C) 2014 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_IO_H_
36#  error "Include <avr/io.h> instead of this file."
37#endif
38
39#ifndef _AVR_IOXXX_H_
40#  define _AVR_IOXXX_H_ "iox128d4.h"
41#else
42#  error "Attempt to include more than one <avr/ioXXX.h> file."
43#endif
44
45#ifndef _AVR_ATXMEGA128D4_H_INCLUDED
46#define _AVR_ATXMEGA128D4_H_INCLUDED
47
48/* Ungrouped common registers */
49#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
50#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
51#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
52#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
53
54/* Deprecated */
55#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
56#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
57#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
58#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
59
60#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
61#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
62#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
63#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
64#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
65#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
66#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
67#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
68#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
69
70/* C Language Only */
71#if !defined (__ASSEMBLER__)
72
73#include <stdint.h>
74
75typedef volatile uint8_t register8_t;
76typedef volatile uint16_t register16_t;
77typedef volatile uint32_t register32_t;
78
79
80#ifdef _WORDREGISTER
81#undef _WORDREGISTER
82#endif
83#define _WORDREGISTER(regname)   \
84    __extension__ union \
85    { \
86        register16_t regname; \
87        struct \
88        { \
89            register8_t regname ## L; \
90            register8_t regname ## H; \
91        }; \
92    }
93
94#ifdef _DWORDREGISTER
95#undef _DWORDREGISTER
96#endif
97#define _DWORDREGISTER(regname)  \
98    __extension__ union \
99    { \
100        register32_t regname; \
101        struct \
102        { \
103            register8_t regname ## 0; \
104            register8_t regname ## 1; \
105            register8_t regname ## 2; \
106            register8_t regname ## 3; \
107        }; \
108    }
109
110
111/*
112==========================================================================
113IO Module Structures
114==========================================================================
115*/
116
117
118/*
119--------------------------------------------------------------------------
120VPORT - Virtual Ports
121--------------------------------------------------------------------------
122*/
123
124/* Virtual Port */
125typedef struct VPORT_struct
126{
127    register8_t DIR;  /* I/O Port Data Direction */
128    register8_t OUT;  /* I/O Port Output */
129    register8_t IN;  /* I/O Port Input */
130    register8_t INTFLAGS;  /* Interrupt Flag Register */
131} VPORT_t;
132
133
134/*
135--------------------------------------------------------------------------
136XOCD - On-Chip Debug System
137--------------------------------------------------------------------------
138*/
139
140/* On-Chip Debug System */
141typedef struct OCD_struct
142{
143    register8_t OCDR0;  /* OCD Register 0 */
144    register8_t OCDR1;  /* OCD Register 1 */
145} OCD_t;
146
147
148/*
149--------------------------------------------------------------------------
150CPU - CPU
151--------------------------------------------------------------------------
152*/
153
154/* CCP signatures */
155typedef enum CCP_enum
156{
157    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
158    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
159} CCP_t;
160
161
162/*
163--------------------------------------------------------------------------
164CLK - Clock System
165--------------------------------------------------------------------------
166*/
167
168/* Clock System */
169typedef struct CLK_struct
170{
171    register8_t CTRL;  /* Control Register */
172    register8_t PSCTRL;  /* Prescaler Control Register */
173    register8_t LOCK;  /* Lock register */
174    register8_t RTCCTRL;  /* RTC Control Register */
175    register8_t reserved_0x04;
176} CLK_t;
177
178
179/* Power Reduction */
180typedef struct PR_struct
181{
182    register8_t PRGEN;  /* General Power Reduction */
183    register8_t PRPA;  /* Power Reduction Port A */
184    register8_t reserved_0x02;
185    register8_t PRPC;  /* Power Reduction Port C */
186    register8_t PRPD;  /* Power Reduction Port D */
187    register8_t PRPE;  /* Power Reduction Port E */
188    register8_t PRPF;  /* Power Reduction Port F */
189} PR_t;
190
191/* System Clock Selection */
192typedef enum CLK_SCLKSEL_enum
193{
194    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2 MHz RC Oscillator */
195    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32 MHz RC Oscillator */
196    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32.768 kHz RC Oscillator */
197    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
198    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
199} CLK_SCLKSEL_t;
200
201/* Prescaler A Division Factor */
202typedef enum CLK_PSADIV_enum
203{
204    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
205    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
206    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
207    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
208    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
209    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
210    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
211    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
212    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
213    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
214} CLK_PSADIV_t;
215
216/* Prescaler B and C Division Factor */
217typedef enum CLK_PSBCDIV_enum
218{
219    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
220    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
221    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
222    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
223} CLK_PSBCDIV_t;
224
225/* RTC Clock Source */
226typedef enum CLK_RTCSRC_enum
227{
228    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1 kHz from internal 32kHz ULP */
229    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
230    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1.024 kHz from 32.768 kHz internal oscillator */
231    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
232    CLK_RTCSRC_RCOSC32_gc = (0x06<<1),  /* 32.768 kHz from 32.768 kHz internal oscillator */
233    CLK_RTCSRC_EXTCLK_gc = (0x07<<1),  /* External Clock from TOSC1 */
234} CLK_RTCSRC_t;
235
236
237/*
238--------------------------------------------------------------------------
239SLEEP - Sleep Controller
240--------------------------------------------------------------------------
241*/
242
243/* Sleep Controller */
244typedef struct SLEEP_struct
245{
246    register8_t CTRL;  /* Control Register */
247} SLEEP_t;
248
249/* Sleep Mode */
250typedef enum SLEEP_SMODE_enum
251{
252    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
253    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
254    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
255    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
256    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
257} SLEEP_SMODE_t;
258
259
260/*
261--------------------------------------------------------------------------
262OSC - Oscillator
263--------------------------------------------------------------------------
264*/
265
266/* Oscillator */
267typedef struct OSC_struct
268{
269    register8_t CTRL;  /* Control Register */
270    register8_t STATUS;  /* Status Register */
271    register8_t XOSCCTRL;  /* External Oscillator Control Register */
272    register8_t XOSCFAIL;  /* Oscillator Failure Detection Register */
273    register8_t RC32KCAL;  /* 32.768 kHz Internal Oscillator Calibration Register */
274    register8_t PLLCTRL;  /* PLL Control Register */
275    register8_t DFLLCTRL;  /* DFLL Control Register */
276} OSC_t;
277
278/* Oscillator Frequency Range */
279typedef enum OSC_FRQRANGE_enum
280{
281    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
282    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
283    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
284    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
285} OSC_FRQRANGE_t;
286
287/* External Oscillator Selection and Startup Time */
288typedef enum OSC_XOSCSEL_enum
289{
290    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
291    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32.768 kHz TOSC - 32K CLK */
292    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16 MHz XTAL - 256 CLK */
293    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16 MHz XTAL - 1K CLK */
294    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16 MHz XTAL - 16K CLK */
295} OSC_XOSCSEL_t;
296
297/* PLL Clock Source */
298typedef enum OSC_PLLSRC_enum
299{
300    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2 MHz RC Oscillator */
301    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32 MHz RC Oscillator */
302    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
303} OSC_PLLSRC_t;
304
305/* 2 MHz DFLL Calibration Reference */
306typedef enum OSC_RC2MCREF_enum
307{
308    OSC_RC2MCREF_RC32K_gc = (0x00<<0),  /* Internal 32.768 kHz RC Oscillator */
309    OSC_RC2MCREF_XOSC32K_gc = (0x01<<0),  /* External 32.768 kHz Crystal Oscillator */
310} OSC_RC2MCREF_t;
311
312/* 32 MHz DFLL Calibration Reference */
313typedef enum OSC_RC32MCREF_enum
314{
315    OSC_RC32MCREF_RC32K_gc = (0x00<<1),  /* Internal 32.768 kHz RC Oscillator */
316    OSC_RC32MCREF_XOSC32K_gc = (0x01<<1),  /* External 32.768 kHz Crystal Oscillator */
317} OSC_RC32MCREF_t;
318
319
320/*
321--------------------------------------------------------------------------
322DFLL - DFLL
323--------------------------------------------------------------------------
324*/
325
326/* DFLL */
327typedef struct DFLL_struct
328{
329    register8_t CTRL;  /* Control Register */
330    register8_t reserved_0x01;
331    register8_t CALA;  /* Calibration Register A */
332    register8_t CALB;  /* Calibration Register B */
333    register8_t COMP0;  /* Oscillator Compare Register 0 */
334    register8_t COMP1;  /* Oscillator Compare Register 1 */
335    register8_t COMP2;  /* Oscillator Compare Register 2 */
336    register8_t reserved_0x07;
337} DFLL_t;
338
339
340/*
341--------------------------------------------------------------------------
342RST - Reset
343--------------------------------------------------------------------------
344*/
345
346/* Reset */
347typedef struct RST_struct
348{
349    register8_t STATUS;  /* Status Register */
350    register8_t CTRL;  /* Control Register */
351} RST_t;
352
353
354/*
355--------------------------------------------------------------------------
356WDT - Watch-Dog Timer
357--------------------------------------------------------------------------
358*/
359
360/* Watch-Dog Timer */
361typedef struct WDT_struct
362{
363    register8_t CTRL;  /* Control */
364    register8_t WINCTRL;  /* Windowed Mode Control */
365    register8_t STATUS;  /* Status */
366} WDT_t;
367
368/* Period setting */
369typedef enum WDT_PER_enum
370{
371    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
372    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
373    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
374    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
375    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.128s @ 3.3V) */
376    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.256s @ 3.3V) */
377    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.512s @ 3.3V) */
378    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
379    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
380    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
381    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
382} WDT_PER_t;
383
384/* Closed window period */
385typedef enum WDT_WPER_enum
386{
387    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
388    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
389    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
390    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
391    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.128s @ 3.3V) */
392    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.256s @ 3.3V) */
393    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.512s @ 3.3V) */
394    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
395    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
396    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
397    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
398} WDT_WPER_t;
399
400
401/*
402--------------------------------------------------------------------------
403MCU - MCU Control
404--------------------------------------------------------------------------
405*/
406
407/* MCU Control */
408typedef struct MCU_struct
409{
410    register8_t DEVID0;  /* Device ID byte 0 */
411    register8_t DEVID1;  /* Device ID byte 1 */
412    register8_t DEVID2;  /* Device ID byte 2 */
413    register8_t REVID;  /* Revision ID */
414    register8_t reserved_0x04;
415    register8_t reserved_0x05;
416    register8_t reserved_0x06;
417    register8_t ANAINIT;  /* Analog Startup Delay */
418    register8_t EVSYSLOCK;  /* Event System Lock */
419    register8_t AWEXLOCK;  /* AWEX Lock */
420    register8_t reserved_0x0A;
421    register8_t reserved_0x0B;
422} MCU_t;
423
424
425/*
426--------------------------------------------------------------------------
427PMIC - Programmable Multi-level Interrupt Controller
428--------------------------------------------------------------------------
429*/
430
431/* Programmable Multi-level Interrupt Controller */
432typedef struct PMIC_struct
433{
434    register8_t STATUS;  /* Status Register */
435    register8_t INTPRI;  /* Interrupt Priority */
436    register8_t CTRL;  /* Control Register */
437    register8_t reserved_0x03;
438    register8_t reserved_0x04;
439    register8_t reserved_0x05;
440    register8_t reserved_0x06;
441    register8_t reserved_0x07;
442    register8_t reserved_0x08;
443    register8_t reserved_0x09;
444    register8_t reserved_0x0A;
445    register8_t reserved_0x0B;
446    register8_t reserved_0x0C;
447    register8_t reserved_0x0D;
448    register8_t reserved_0x0E;
449    register8_t reserved_0x0F;
450} PMIC_t;
451
452
453/*
454--------------------------------------------------------------------------
455PORTCFG - Port Configuration
456--------------------------------------------------------------------------
457*/
458
459/* I/O port Configuration */
460typedef struct PORTCFG_struct
461{
462    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
463    register8_t reserved_0x01;
464    register8_t VPCTRLA;  /* Virtual Port Control Register A */
465    register8_t VPCTRLB;  /* Virtual Port Control Register B */
466    register8_t CLKEVOUT;  /* Clock and Event Out Register */
467    register8_t reserved_0x05;
468    register8_t EVOUTSEL;  /* Event Output Select */
469} PORTCFG_t;
470
471/* Virtual Port Mapping */
472typedef enum PORTCFG_VP02MAP_enum
473{
474    PORTCFG_VP02MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
475    PORTCFG_VP02MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
476    PORTCFG_VP02MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
477    PORTCFG_VP02MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
478    PORTCFG_VP02MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
479    PORTCFG_VP02MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
480    PORTCFG_VP02MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
481    PORTCFG_VP02MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
482    PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
483    PORTCFG_VP02MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
484    PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
485    PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
486    PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
487    PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
488    PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
489    PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
490} PORTCFG_VP02MAP_t;
491
492/* Virtual Port Mapping */
493typedef enum PORTCFG_VP13MAP_enum
494{
495    PORTCFG_VP13MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
496    PORTCFG_VP13MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
497    PORTCFG_VP13MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
498    PORTCFG_VP13MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
499    PORTCFG_VP13MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
500    PORTCFG_VP13MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
501    PORTCFG_VP13MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
502    PORTCFG_VP13MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
503    PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
504    PORTCFG_VP13MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
505    PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
506    PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
507    PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
508    PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
509    PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
510    PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
511} PORTCFG_VP13MAP_t;
512
513/* System Clock Output Port */
514typedef enum PORTCFG_CLKOUT_enum
515{
516    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* System Clock Output Disabled */
517    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* System Clock Output on Port C pin 7 */
518    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* System Clock Output on Port D pin 7 */
519    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* System Clock Output on Port E pin 7 */
520} PORTCFG_CLKOUT_t;
521
522/* Peripheral Clock Output Select */
523typedef enum PORTCFG_CLKOUTSEL_enum
524{
525    PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2),  /* 1x Peripheral Clock Output to pin */
526    PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2),  /* 2x Peripheral Clock Output to pin */
527    PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2),  /* 4x Peripheral Clock Output to pin */
528} PORTCFG_CLKOUTSEL_t;
529
530/* Event Output Port */
531typedef enum PORTCFG_EVOUT_enum
532{
533    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
534    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
535    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
536    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
537} PORTCFG_EVOUT_t;
538
539/* Event Output Select */
540typedef enum PORTCFG_EVOUTSEL_enum
541{
542    PORTCFG_EVOUTSEL_0_gc = (0x00<<0),  /* Event Channel 0 output to pin */
543    PORTCFG_EVOUTSEL_1_gc = (0x01<<0),  /* Event Channel 1 output to pin */
544    PORTCFG_EVOUTSEL_2_gc = (0x02<<0),  /* Event Channel 2 output to pin */
545    PORTCFG_EVOUTSEL_3_gc = (0x03<<0),  /* Event Channel 3 output to pin */
546} PORTCFG_EVOUTSEL_t;
547
548
549/*
550--------------------------------------------------------------------------
551CRC - Cyclic Redundancy Checker
552--------------------------------------------------------------------------
553*/
554
555/* Cyclic Redundancy Checker */
556typedef struct CRC_struct
557{
558    register8_t CTRL;  /* Control Register */
559    register8_t STATUS;  /* Status Register */
560    register8_t reserved_0x02;
561    register8_t DATAIN;  /* Data Input */
562    register8_t CHECKSUM0;  /* Checksum byte 0 */
563    register8_t CHECKSUM1;  /* Checksum byte 1 */
564    register8_t CHECKSUM2;  /* Checksum byte 2 */
565    register8_t CHECKSUM3;  /* Checksum byte 3 */
566} CRC_t;
567
568/* Reset */
569typedef enum CRC_RESET_enum
570{
571    CRC_RESET_NO_gc = (0x00<<6),  /* No Reset */
572    CRC_RESET_RESET0_gc = (0x02<<6),  /* Reset CRC with CHECKSUM to all zeros */
573    CRC_RESET_RESET1_gc = (0x03<<6),  /* Reset CRC with CHECKSUM to all ones */
574} CRC_RESET_t;
575
576/* Input Source */
577typedef enum CRC_SOURCE_enum
578{
579    CRC_SOURCE_DISABLE_gc = (0x00<<0),  /* Disabled */
580    CRC_SOURCE_IO_gc = (0x01<<0),  /* I/O Interface */
581    CRC_SOURCE_FLASH_gc = (0x02<<0),  /* Flash */
582} CRC_SOURCE_t;
583
584
585/*
586--------------------------------------------------------------------------
587EVSYS - Event System
588--------------------------------------------------------------------------
589*/
590
591/* Event System */
592typedef struct EVSYS_struct
593{
594    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
595    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
596    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
597    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
598    register8_t reserved_0x04;
599    register8_t reserved_0x05;
600    register8_t reserved_0x06;
601    register8_t reserved_0x07;
602    register8_t CH0CTRL;  /* Channel 0 Control Register */
603    register8_t CH1CTRL;  /* Channel 1 Control Register */
604    register8_t CH2CTRL;  /* Channel 2 Control Register */
605    register8_t CH3CTRL;  /* Channel 3 Control Register */
606    register8_t reserved_0x0C;
607    register8_t reserved_0x0D;
608    register8_t reserved_0x0E;
609    register8_t reserved_0x0F;
610    register8_t STROBE;  /* Event Strobe */
611    register8_t DATA;  /* Event Data */
612} EVSYS_t;
613
614/* Quadrature Decoder Index Recognition Mode */
615typedef enum EVSYS_QDIRM_enum
616{
617    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
618    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
619    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
620    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
621} EVSYS_QDIRM_t;
622
623/* Digital filter coefficient */
624typedef enum EVSYS_DIGFILT_enum
625{
626    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
627    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
628    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
629    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
630    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
631    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
632    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
633    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
634} EVSYS_DIGFILT_t;
635
636/* Event Channel multiplexer input selection */
637typedef enum EVSYS_CHMUX_enum
638{
639    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
640    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
641    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
642    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
643    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
644    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
645    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
646    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
647    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
648    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
649    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
650    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
651    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
652    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
653    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
654    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
655    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
656    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
657    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
658    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
659    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
660    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
661    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
662    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
663    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
664    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
665    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
666    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
667    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
668    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
669    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
670    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
671    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
672    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
673    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
674    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
675    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
676    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
677    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
678    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
679    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
680    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
681    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
682    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
683    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
684    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
685    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
686    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
687    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
688    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
689    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
690    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
691    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
692    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
693    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
694    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
695    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
696    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
697    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
698    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
699    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
700    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
701    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
702    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
703    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
704    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
705    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
706    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
707    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
708    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
709    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
710    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
711    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
712    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
713    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
714    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
715    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
716    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
717    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
718    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
719    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
720    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
721    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
722    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
723    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
724    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
725    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
726    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
727    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
728    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
729    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
730    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
731    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
732    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
733    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
734    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
735    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
736    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
737    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
738} EVSYS_CHMUX_t;
739
740
741/*
742--------------------------------------------------------------------------
743NVM - Non Volatile Memory Controller
744--------------------------------------------------------------------------
745*/
746
747/* Non-volatile Memory Controller */
748typedef struct NVM_struct
749{
750    register8_t ADDR0;  /* Address Register 0 */
751    register8_t ADDR1;  /* Address Register 1 */
752    register8_t ADDR2;  /* Address Register 2 */
753    register8_t reserved_0x03;
754    register8_t DATA0;  /* Data Register 0 */
755    register8_t DATA1;  /* Data Register 1 */
756    register8_t DATA2;  /* Data Register 2 */
757    register8_t reserved_0x07;
758    register8_t reserved_0x08;
759    register8_t reserved_0x09;
760    register8_t CMD;  /* Command */
761    register8_t CTRLA;  /* Control Register A */
762    register8_t CTRLB;  /* Control Register B */
763    register8_t INTCTRL;  /* Interrupt Control */
764    register8_t reserved_0x0E;
765    register8_t STATUS;  /* Status */
766    register8_t LOCKBITS;  /* Lock Bits */
767} NVM_t;
768
769/* NVM Command */
770typedef enum NVM_CMD_enum
771{
772    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
773    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
774    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
775    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
776    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
777    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
778    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
779    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
780    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
781    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
782    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
783    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
784    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
785    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
786    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
787    NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0),  /* Erase Flash Page */
788    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
789    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
790    NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0),  /* Write Flash Page */
791    NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0),  /* Erase-and-write Flash Page */
792    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
793    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
794    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
795    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
796    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
797    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
798    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Application section CRC */
799    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /*  Boot Section CRC */
800    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Flash Range CRC */
801    NVM_CMD_CHIP_ERASE_gc = (0x40<<0),  /* Erase Chip */
802    NVM_CMD_READ_NVM_gc = (0x43<<0),  /* Read NVM */
803    NVM_CMD_WRITE_FUSE_gc = (0x4C<<0),  /* Write Fuse byte */
804    NVM_CMD_ERASE_BOOT_gc = (0x68<<0),  /* Erase Boot Section */
805    NVM_CMD_FLASH_CRC_gc = (0x78<<0),  /* Flash CRC */
806} NVM_CMD_t;
807
808/* SPM ready interrupt level */
809typedef enum NVM_SPMLVL_enum
810{
811    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
812    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
813    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
814    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
815} NVM_SPMLVL_t;
816
817/* EEPROM ready interrupt level */
818typedef enum NVM_EELVL_enum
819{
820    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
821    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
822    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
823    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
824} NVM_EELVL_t;
825
826/* Boot lock bits - boot setcion */
827typedef enum NVM_BLBB_enum
828{
829    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
830    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
831    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
832    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
833} NVM_BLBB_t;
834
835/* Boot lock bits - application section */
836typedef enum NVM_BLBA_enum
837{
838    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
839    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
840    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
841    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
842} NVM_BLBA_t;
843
844/* Boot lock bits - application table section */
845typedef enum NVM_BLBAT_enum
846{
847    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
848    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
849    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
850    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
851} NVM_BLBAT_t;
852
853/* Lock bits */
854typedef enum NVM_LB_enum
855{
856    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
857    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
858    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
859} NVM_LB_t;
860
861
862/*
863--------------------------------------------------------------------------
864ADC - Analog/Digital Converter
865--------------------------------------------------------------------------
866*/
867
868/* ADC Channel */
869typedef struct ADC_CH_struct
870{
871    register8_t CTRL;  /* Control Register */
872    register8_t MUXCTRL;  /* MUX Control */
873    register8_t INTCTRL;  /* Channel Interrupt Control Register */
874    register8_t INTFLAGS;  /* Interrupt Flags */
875    _WORDREGISTER(RES);  /* Channel Result */
876    register8_t SCAN;  /* Input Channel Scan */
877    register8_t reserved_0x07;
878} ADC_CH_t;
879
880
881/* Analog-to-Digital Converter */
882typedef struct ADC_struct
883{
884    register8_t CTRLA;  /* Control Register A */
885    register8_t CTRLB;  /* Control Register B */
886    register8_t REFCTRL;  /* Reference Control */
887    register8_t EVCTRL;  /* Event Control */
888    register8_t PRESCALER;  /* Clock Prescaler */
889    register8_t reserved_0x05;
890    register8_t INTFLAGS;  /* Interrupt Flags */
891    register8_t TEMP;  /* Temporary Register */
892    register8_t reserved_0x08;
893    register8_t reserved_0x09;
894    register8_t reserved_0x0A;
895    register8_t reserved_0x0B;
896    _WORDREGISTER(CAL);  /* Calibration Value */
897    register8_t reserved_0x0E;
898    register8_t reserved_0x0F;
899    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
900    register8_t reserved_0x12;
901    register8_t reserved_0x13;
902    register8_t reserved_0x14;
903    register8_t reserved_0x15;
904    register8_t reserved_0x16;
905    register8_t reserved_0x17;
906    _WORDREGISTER(CMP);  /* Compare Value */
907    register8_t reserved_0x1A;
908    register8_t reserved_0x1B;
909    register8_t reserved_0x1C;
910    register8_t reserved_0x1D;
911    register8_t reserved_0x1E;
912    register8_t reserved_0x1F;
913    ADC_CH_t CH0;  /* ADC Channel 0 */
914} ADC_t;
915
916/* Current Limitation */
917typedef enum ADC_CURRLIMIT_enum
918{
919    ADC_CURRLIMIT_NO_gc = (0x00<<5),  /* No current limit,     300ksps max sampling rate */
920    ADC_CURRLIMIT_LOW_gc = (0x01<<5),  /* Low current limit,    250ksps max sampling rate */
921    ADC_CURRLIMIT_MED_gc = (0x02<<5),  /* Medium current limit, 150ksps max sampling rate */
922    ADC_CURRLIMIT_HIGH_gc = (0x03<<5),  /* High current limit,   50ksps max sampling rate */
923} ADC_CURRLIMIT_t;
924
925/* Positive input multiplexer selection */
926typedef enum ADC_CH_MUXPOS_enum
927{
928    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
929    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
930    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
931    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
932    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
933    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
934    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
935    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
936    ADC_CH_MUXPOS_PIN8_gc = (0x08<<3),  /* Input pin 8 */
937    ADC_CH_MUXPOS_PIN9_gc = (0x09<<3),  /* Input pin 9 */
938    ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3),  /* Input pin 10 */
939    ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3),  /* Input pin 11 */
940} ADC_CH_MUXPOS_t;
941
942/* Internal input multiplexer selections */
943typedef enum ADC_CH_MUXINT_enum
944{
945    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
946    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
947    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
948} ADC_CH_MUXINT_t;
949
950/* Negative input multiplexer selection */
951typedef enum ADC_CH_MUXNEG_enum
952{
953    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
954    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
955    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
956    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
957    ADC_CH_MUXNEG_PIN4_gc = (0x00<<0),  /* Input pin 4 */
958    ADC_CH_MUXNEG_PIN5_gc = (0x01<<0),  /* Input pin 5 */
959    ADC_CH_MUXNEG_PIN6_gc = (0x02<<0),  /* Input pin 6 */
960    ADC_CH_MUXNEG_PIN7_gc = (0x03<<0),  /* Input pin 7 */
961} ADC_CH_MUXNEG_t;
962
963/* Input mode */
964typedef enum ADC_CH_INPUTMODE_enum
965{
966    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
967    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
968    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
969    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
970} ADC_CH_INPUTMODE_t;
971
972/* Gain factor */
973typedef enum ADC_CH_GAIN_enum
974{
975    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
976    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
977    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
978    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
979    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
980    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
981    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
982    ADC_CH_GAIN_DIV2_gc = (0x07<<2),  /* x/2 gain */
983} ADC_CH_GAIN_t;
984
985/* Conversion result resolution */
986typedef enum ADC_RESOLUTION_enum
987{
988    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
989    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
990    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
991} ADC_RESOLUTION_t;
992
993/* Voltage reference selection */
994typedef enum ADC_REFSEL_enum
995{
996    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
997    ADC_REFSEL_INTVCC_gc = (0x01<<4),  /* Internal VCC / 1.6 */
998    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
999    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
1000    ADC_REFSEL_INTVCC2_gc = (0x04<<4),  /* Internal VCC / 2 */
1001} ADC_REFSEL_t;
1002
1003/* Event channel input selection */
1004typedef enum ADC_EVSEL_enum
1005{
1006    ADC_EVSEL_0_gc = (0x00<<3),  /* Event Channel 0 */
1007    ADC_EVSEL_1_gc = (0x01<<3),  /* Event Channel 1 */
1008    ADC_EVSEL_2_gc = (0x02<<3),  /* Event Channel 2 */
1009    ADC_EVSEL_3_gc = (0x03<<3),  /* Event Channel 3 */
1010} ADC_EVSEL_t;
1011
1012/* Event action selection */
1013typedef enum ADC_EVACT_enum
1014{
1015    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
1016    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
1017    ADC_EVACT_SYNCSWEEP_gc = (0x06<<0),  /* The ADC is flushed and restarted for accurate timing */
1018} ADC_EVACT_t;
1019
1020/* Interupt mode */
1021typedef enum ADC_CH_INTMODE_enum
1022{
1023    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
1024    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
1025    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
1026} ADC_CH_INTMODE_t;
1027
1028/* Interrupt level */
1029typedef enum ADC_CH_INTLVL_enum
1030{
1031    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
1032    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
1033    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
1034    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
1035} ADC_CH_INTLVL_t;
1036
1037/* Clock prescaler */
1038typedef enum ADC_PRESCALER_enum
1039{
1040    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
1041    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
1042    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
1043    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
1044    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
1045    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
1046    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
1047    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
1048} ADC_PRESCALER_t;
1049
1050
1051/*
1052--------------------------------------------------------------------------
1053AC - Analog Comparator
1054--------------------------------------------------------------------------
1055*/
1056
1057/* Analog Comparator */
1058typedef struct AC_struct
1059{
1060    register8_t AC0CTRL;  /* Analog Comparator 0 Control */
1061    register8_t AC1CTRL;  /* Analog Comparator 1 Control */
1062    register8_t AC0MUXCTRL;  /* Analog Comparator 0 MUX Control */
1063    register8_t AC1MUXCTRL;  /* Analog Comparator 1 MUX Control */
1064    register8_t CTRLA;  /* Control Register A */
1065    register8_t CTRLB;  /* Control Register B */
1066    register8_t WINCTRL;  /* Window Mode Control */
1067    register8_t STATUS;  /* Status */
1068} AC_t;
1069
1070/* Interrupt mode */
1071typedef enum AC_INTMODE_enum
1072{
1073    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
1074    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
1075    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
1076} AC_INTMODE_t;
1077
1078/* Interrupt level */
1079typedef enum AC_INTLVL_enum
1080{
1081    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
1082    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
1083    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
1084    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
1085} AC_INTLVL_t;
1086
1087/* Hysteresis mode selection */
1088typedef enum AC_HYSMODE_enum
1089{
1090    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
1091    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
1092    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
1093} AC_HYSMODE_t;
1094
1095/* Positive input multiplexer selection */
1096typedef enum AC_MUXPOS_enum
1097{
1098    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
1099    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
1100    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
1101    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
1102    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
1103    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
1104    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
1105} AC_MUXPOS_t;
1106
1107/* Negative input multiplexer selection */
1108typedef enum AC_MUXNEG_enum
1109{
1110    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
1111    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
1112    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
1113    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
1114    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
1115    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
1116    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
1117} AC_MUXNEG_t;
1118
1119/* Windows interrupt mode */
1120typedef enum AC_WINTMODE_enum
1121{
1122    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
1123    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
1124    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
1125    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
1126} AC_WINTMODE_t;
1127
1128/* Window interrupt level */
1129typedef enum AC_WINTLVL_enum
1130{
1131    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
1132    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
1133    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
1134    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
1135} AC_WINTLVL_t;
1136
1137/* Window mode state */
1138typedef enum AC_WSTATE_enum
1139{
1140    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
1141    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
1142    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
1143} AC_WSTATE_t;
1144
1145
1146/*
1147--------------------------------------------------------------------------
1148RTC - Real-Time Counter
1149--------------------------------------------------------------------------
1150*/
1151
1152/* Real-Time Counter */
1153typedef struct RTC_struct
1154{
1155    register8_t CTRL;  /* Control Register */
1156    register8_t STATUS;  /* Status Register */
1157    register8_t INTCTRL;  /* Interrupt Control Register */
1158    register8_t INTFLAGS;  /* Interrupt Flags */
1159    register8_t TEMP;  /* Temporary register */
1160    register8_t reserved_0x05;
1161    register8_t reserved_0x06;
1162    register8_t reserved_0x07;
1163    _WORDREGISTER(CNT);  /* Count Register */
1164    _WORDREGISTER(PER);  /* Period Register */
1165    _WORDREGISTER(COMP);  /* Compare Register */
1166} RTC_t;
1167
1168/* Prescaler Factor */
1169typedef enum RTC_PRESCALER_enum
1170{
1171    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
1172    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
1173    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
1174    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
1175    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
1176    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
1177    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
1178    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
1179} RTC_PRESCALER_t;
1180
1181/* Compare Interrupt level */
1182typedef enum RTC_COMPINTLVL_enum
1183{
1184    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1185    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1186    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1187    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
1188} RTC_COMPINTLVL_t;
1189
1190/* Overflow Interrupt level */
1191typedef enum RTC_OVFINTLVL_enum
1192{
1193    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1194    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1195    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1196    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
1197} RTC_OVFINTLVL_t;
1198
1199
1200/*
1201--------------------------------------------------------------------------
1202TWI - Two-Wire Interface
1203--------------------------------------------------------------------------
1204*/
1205
1206/*  */
1207typedef struct TWI_MASTER_struct
1208{
1209    register8_t CTRLA;  /* Control Register A */
1210    register8_t CTRLB;  /* Control Register B */
1211    register8_t CTRLC;  /* Control Register C */
1212    register8_t STATUS;  /* Status Register */
1213    register8_t BAUD;  /* Baurd Rate Control Register */
1214    register8_t ADDR;  /* Address Register */
1215    register8_t DATA;  /* Data Register */
1216} TWI_MASTER_t;
1217
1218
1219/*  */
1220typedef struct TWI_SLAVE_struct
1221{
1222    register8_t CTRLA;  /* Control Register A */
1223    register8_t CTRLB;  /* Control Register B */
1224    register8_t STATUS;  /* Status Register */
1225    register8_t ADDR;  /* Address Register */
1226    register8_t DATA;  /* Data Register */
1227    register8_t ADDRMASK;  /* Address Mask Register */
1228} TWI_SLAVE_t;
1229
1230
1231/* Two-Wire Interface */
1232typedef struct TWI_struct
1233{
1234    register8_t CTRL;  /* TWI Common Control Register */
1235    TWI_MASTER_t MASTER;  /* TWI master module */
1236    TWI_SLAVE_t SLAVE;  /* TWI slave module */
1237} TWI_t;
1238
1239/* SDA Hold Time */
1240typedef enum TWI_SDAHOLD_enum
1241{
1242    TWI_SDAHOLD_OFF_gc = (0x00<<1),  /* SDA Hold Time off */
1243    TWI_SDAHOLD_50NS_gc = (0x01<<1),  /* SDA Hold Time 50 ns */
1244    TWI_SDAHOLD_300NS_gc = (0x02<<1),  /* SDA Hold Time 300 ns */
1245    TWI_SDAHOLD_400NS_gc = (0x03<<1),  /* SDA Hold Time 400 ns */
1246} TWI_SDAHOLD_t;
1247
1248/* Master Interrupt Level */
1249typedef enum TWI_MASTER_INTLVL_enum
1250{
1251    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1252    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
1253    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1254    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
1255} TWI_MASTER_INTLVL_t;
1256
1257/* Inactive Timeout */
1258typedef enum TWI_MASTER_TIMEOUT_enum
1259{
1260    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
1261    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
1262    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
1263    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
1264} TWI_MASTER_TIMEOUT_t;
1265
1266/* Master Command */
1267typedef enum TWI_MASTER_CMD_enum
1268{
1269    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
1270    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
1271    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
1272    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
1273} TWI_MASTER_CMD_t;
1274
1275/* Master Bus State */
1276typedef enum TWI_MASTER_BUSSTATE_enum
1277{
1278    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
1279    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
1280    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
1281    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
1282} TWI_MASTER_BUSSTATE_t;
1283
1284/* Slave Interrupt Level */
1285typedef enum TWI_SLAVE_INTLVL_enum
1286{
1287    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1288    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
1289    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1290    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
1291} TWI_SLAVE_INTLVL_t;
1292
1293/* Slave Command */
1294typedef enum TWI_SLAVE_CMD_enum
1295{
1296    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
1297    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
1298    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
1299} TWI_SLAVE_CMD_t;
1300
1301
1302/*
1303--------------------------------------------------------------------------
1304PORT - I/O Port Configuration
1305--------------------------------------------------------------------------
1306*/
1307
1308/* I/O Ports */
1309typedef struct PORT_struct
1310{
1311    register8_t DIR;  /* I/O Port Data Direction */
1312    register8_t DIRSET;  /* I/O Port Data Direction Set */
1313    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
1314    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
1315    register8_t OUT;  /* I/O Port Output */
1316    register8_t OUTSET;  /* I/O Port Output Set */
1317    register8_t OUTCLR;  /* I/O Port Output Clear */
1318    register8_t OUTTGL;  /* I/O Port Output Toggle */
1319    register8_t IN;  /* I/O port Input */
1320    register8_t INTCTRL;  /* Interrupt Control Register */
1321    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
1322    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
1323    register8_t INTFLAGS;  /* Interrupt Flag Register */
1324    register8_t reserved_0x0D;
1325    register8_t REMAP;  /* I/O Port Pin Remap Register */
1326    register8_t reserved_0x0F;
1327    register8_t PIN0CTRL;  /* Pin 0 Control Register */
1328    register8_t PIN1CTRL;  /* Pin 1 Control Register */
1329    register8_t PIN2CTRL;  /* Pin 2 Control Register */
1330    register8_t PIN3CTRL;  /* Pin 3 Control Register */
1331    register8_t PIN4CTRL;  /* Pin 4 Control Register */
1332    register8_t PIN5CTRL;  /* Pin 5 Control Register */
1333    register8_t PIN6CTRL;  /* Pin 6 Control Register */
1334    register8_t PIN7CTRL;  /* Pin 7 Control Register */
1335} PORT_t;
1336
1337/* Port Interrupt 0 Level */
1338typedef enum PORT_INT0LVL_enum
1339{
1340    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1341    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
1342    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
1343    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
1344} PORT_INT0LVL_t;
1345
1346/* Port Interrupt 1 Level */
1347typedef enum PORT_INT1LVL_enum
1348{
1349    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1350    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
1351    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
1352    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
1353} PORT_INT1LVL_t;
1354
1355/* Output/Pull Configuration */
1356typedef enum PORT_OPC_enum
1357{
1358    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
1359    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
1360    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
1361    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
1362    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
1363    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
1364    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
1365    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
1366} PORT_OPC_t;
1367
1368/* Input/Sense Configuration */
1369typedef enum PORT_ISC_enum
1370{
1371    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
1372    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
1373    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
1374    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
1375    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
1376} PORT_ISC_t;
1377
1378
1379/*
1380--------------------------------------------------------------------------
1381TC - 16-bit Timer/Counter With PWM
1382--------------------------------------------------------------------------
1383*/
1384
1385/* 16-bit Timer/Counter 0 */
1386typedef struct TC0_struct
1387{
1388    register8_t CTRLA;  /* Control  Register A */
1389    register8_t CTRLB;  /* Control Register B */
1390    register8_t CTRLC;  /* Control register C */
1391    register8_t CTRLD;  /* Control Register D */
1392    register8_t CTRLE;  /* Control Register E */
1393    register8_t reserved_0x05;
1394    register8_t INTCTRLA;  /* Interrupt Control Register A */
1395    register8_t INTCTRLB;  /* Interrupt Control Register B */
1396    register8_t CTRLFCLR;  /* Control Register F Clear */
1397    register8_t CTRLFSET;  /* Control Register F Set */
1398    register8_t CTRLGCLR;  /* Control Register G Clear */
1399    register8_t CTRLGSET;  /* Control Register G Set */
1400    register8_t INTFLAGS;  /* Interrupt Flag Register */
1401    register8_t reserved_0x0D;
1402    register8_t reserved_0x0E;
1403    register8_t TEMP;  /* Temporary Register For 16-bit Access */
1404    register8_t reserved_0x10;
1405    register8_t reserved_0x11;
1406    register8_t reserved_0x12;
1407    register8_t reserved_0x13;
1408    register8_t reserved_0x14;
1409    register8_t reserved_0x15;
1410    register8_t reserved_0x16;
1411    register8_t reserved_0x17;
1412    register8_t reserved_0x18;
1413    register8_t reserved_0x19;
1414    register8_t reserved_0x1A;
1415    register8_t reserved_0x1B;
1416    register8_t reserved_0x1C;
1417    register8_t reserved_0x1D;
1418    register8_t reserved_0x1E;
1419    register8_t reserved_0x1F;
1420    _WORDREGISTER(CNT);  /* Count */
1421    register8_t reserved_0x22;
1422    register8_t reserved_0x23;
1423    register8_t reserved_0x24;
1424    register8_t reserved_0x25;
1425    _WORDREGISTER(PER);  /* Period */
1426    _WORDREGISTER(CCA);  /* Compare or Capture A */
1427    _WORDREGISTER(CCB);  /* Compare or Capture B */
1428    _WORDREGISTER(CCC);  /* Compare or Capture C */
1429    _WORDREGISTER(CCD);  /* Compare or Capture D */
1430    register8_t reserved_0x30;
1431    register8_t reserved_0x31;
1432    register8_t reserved_0x32;
1433    register8_t reserved_0x33;
1434    register8_t reserved_0x34;
1435    register8_t reserved_0x35;
1436    _WORDREGISTER(PERBUF);  /* Period Buffer */
1437    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
1438    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
1439    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
1440    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
1441} TC0_t;
1442
1443
1444/* 16-bit Timer/Counter 1 */
1445typedef struct TC1_struct
1446{
1447    register8_t CTRLA;  /* Control  Register A */
1448    register8_t CTRLB;  /* Control Register B */
1449    register8_t CTRLC;  /* Control register C */
1450    register8_t CTRLD;  /* Control Register D */
1451    register8_t CTRLE;  /* Control Register E */
1452    register8_t reserved_0x05;
1453    register8_t INTCTRLA;  /* Interrupt Control Register A */
1454    register8_t INTCTRLB;  /* Interrupt Control Register B */
1455    register8_t CTRLFCLR;  /* Control Register F Clear */
1456    register8_t CTRLFSET;  /* Control Register F Set */
1457    register8_t CTRLGCLR;  /* Control Register G Clear */
1458    register8_t CTRLGSET;  /* Control Register G Set */
1459    register8_t INTFLAGS;  /* Interrupt Flag Register */
1460    register8_t reserved_0x0D;
1461    register8_t reserved_0x0E;
1462    register8_t TEMP;  /* Temporary Register For 16-bit Access */
1463    register8_t reserved_0x10;
1464    register8_t reserved_0x11;
1465    register8_t reserved_0x12;
1466    register8_t reserved_0x13;
1467    register8_t reserved_0x14;
1468    register8_t reserved_0x15;
1469    register8_t reserved_0x16;
1470    register8_t reserved_0x17;
1471    register8_t reserved_0x18;
1472    register8_t reserved_0x19;
1473    register8_t reserved_0x1A;
1474    register8_t reserved_0x1B;
1475    register8_t reserved_0x1C;
1476    register8_t reserved_0x1D;
1477    register8_t reserved_0x1E;
1478    register8_t reserved_0x1F;
1479    _WORDREGISTER(CNT);  /* Count */
1480    register8_t reserved_0x22;
1481    register8_t reserved_0x23;
1482    register8_t reserved_0x24;
1483    register8_t reserved_0x25;
1484    _WORDREGISTER(PER);  /* Period */
1485    _WORDREGISTER(CCA);  /* Compare or Capture A */
1486    _WORDREGISTER(CCB);  /* Compare or Capture B */
1487    register8_t reserved_0x2C;
1488    register8_t reserved_0x2D;
1489    register8_t reserved_0x2E;
1490    register8_t reserved_0x2F;
1491    register8_t reserved_0x30;
1492    register8_t reserved_0x31;
1493    register8_t reserved_0x32;
1494    register8_t reserved_0x33;
1495    register8_t reserved_0x34;
1496    register8_t reserved_0x35;
1497    _WORDREGISTER(PERBUF);  /* Period Buffer */
1498    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
1499    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
1500} TC1_t;
1501
1502/* Clock Selection */
1503typedef enum TC_CLKSEL_enum
1504{
1505    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
1506    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
1507    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
1508    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
1509    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
1510    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
1511    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
1512    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
1513    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
1514    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
1515    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
1516    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
1517} TC_CLKSEL_t;
1518
1519/* Waveform Generation Mode */
1520typedef enum TC_WGMODE_enum
1521{
1522    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
1523    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
1524    TC_WGMODE_SINGLESLOPE_gc = (0x03<<0),  /* Single Slope */
1525    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
1526    TC_WGMODE_DSTOP_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
1527    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
1528    TC_WGMODE_DSBOTH_gc = (0x06<<0),  /* Dual Slope, Update on both TOP and BOTTOM */
1529    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on both TOP and BOTTOM */
1530    TC_WGMODE_DSBOTTOM_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
1531    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
1532} TC_WGMODE_t;
1533
1534/* Byte Mode */
1535typedef enum TC_BYTEM_enum
1536{
1537    TC_BYTEM_NORMAL_gc = (0x00<<0),  /* 16-bit mode */
1538    TC_BYTEM_BYTEMODE_gc = (0x01<<0),  /* Timer/Counter operating in byte mode only */
1539    TC_BYTEM_SPLITMODE_gc = (0x02<<0),  /* Timer/Counter split into two 8-bit Counters (TC2) */
1540} TC_BYTEM_t;
1541
1542/* Event Action */
1543typedef enum TC_EVACT_enum
1544{
1545    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
1546    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
1547    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
1548    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
1549    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
1550    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
1551    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
1552} TC_EVACT_t;
1553
1554/* Event Selection */
1555typedef enum TC_EVSEL_enum
1556{
1557    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
1558    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
1559    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
1560    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
1561    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
1562} TC_EVSEL_t;
1563
1564/* Error Interrupt Level */
1565typedef enum TC_ERRINTLVL_enum
1566{
1567    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1568    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1569    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1570    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
1571} TC_ERRINTLVL_t;
1572
1573/* Overflow Interrupt Level */
1574typedef enum TC_OVFINTLVL_enum
1575{
1576    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1577    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1578    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1579    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
1580} TC_OVFINTLVL_t;
1581
1582/* Compare or Capture D Interrupt Level */
1583typedef enum TC_CCDINTLVL_enum
1584{
1585    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1586    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
1587    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1588    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
1589} TC_CCDINTLVL_t;
1590
1591/* Compare or Capture C Interrupt Level */
1592typedef enum TC_CCCINTLVL_enum
1593{
1594    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
1595    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
1596    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
1597    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
1598} TC_CCCINTLVL_t;
1599
1600/* Compare or Capture B Interrupt Level */
1601typedef enum TC_CCBINTLVL_enum
1602{
1603    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1604    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1605    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1606    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
1607} TC_CCBINTLVL_t;
1608
1609/* Compare or Capture A Interrupt Level */
1610typedef enum TC_CCAINTLVL_enum
1611{
1612    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1613    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1614    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1615    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
1616} TC_CCAINTLVL_t;
1617
1618/* Timer/Counter Command */
1619typedef enum TC_CMD_enum
1620{
1621    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
1622    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
1623    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
1624    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
1625} TC_CMD_t;
1626
1627
1628/*
1629--------------------------------------------------------------------------
1630TC2 - 16-bit Timer/Counter type 2
1631--------------------------------------------------------------------------
1632*/
1633
1634/* 16-bit Timer/Counter type 2 */
1635typedef struct TC2_struct
1636{
1637    register8_t CTRLA;  /* Control Register A */
1638    register8_t CTRLB;  /* Control Register B */
1639    register8_t CTRLC;  /* Control register C */
1640    register8_t reserved_0x03;
1641    register8_t CTRLE;  /* Control Register E */
1642    register8_t reserved_0x05;
1643    register8_t INTCTRLA;  /* Interrupt Control Register A */
1644    register8_t INTCTRLB;  /* Interrupt Control Register B */
1645    register8_t reserved_0x08;
1646    register8_t CTRLF;  /* Control Register F */
1647    register8_t reserved_0x0A;
1648    register8_t reserved_0x0B;
1649    register8_t INTFLAGS;  /* Interrupt Flag Register */
1650    register8_t reserved_0x0D;
1651    register8_t reserved_0x0E;
1652    register8_t reserved_0x0F;
1653    register8_t reserved_0x10;
1654    register8_t reserved_0x11;
1655    register8_t reserved_0x12;
1656    register8_t reserved_0x13;
1657    register8_t reserved_0x14;
1658    register8_t reserved_0x15;
1659    register8_t reserved_0x16;
1660    register8_t reserved_0x17;
1661    register8_t reserved_0x18;
1662    register8_t reserved_0x19;
1663    register8_t reserved_0x1A;
1664    register8_t reserved_0x1B;
1665    register8_t reserved_0x1C;
1666    register8_t reserved_0x1D;
1667    register8_t reserved_0x1E;
1668    register8_t reserved_0x1F;
1669    register8_t LCNT;  /* Low Byte Count */
1670    register8_t HCNT;  /* High Byte Count */
1671    register8_t reserved_0x22;
1672    register8_t reserved_0x23;
1673    register8_t reserved_0x24;
1674    register8_t reserved_0x25;
1675    register8_t LPER;  /* Low Byte Period */
1676    register8_t HPER;  /* High Byte Period */
1677    register8_t LCMPA;  /* Low Byte Compare A */
1678    register8_t HCMPA;  /* High Byte Compare A */
1679    register8_t LCMPB;  /* Low Byte Compare B */
1680    register8_t HCMPB;  /* High Byte Compare B */
1681    register8_t LCMPC;  /* Low Byte Compare C */
1682    register8_t HCMPC;  /* High Byte Compare C */
1683    register8_t LCMPD;  /* Low Byte Compare D */
1684    register8_t HCMPD;  /* High Byte Compare D */
1685} TC2_t;
1686
1687/* Clock Selection */
1688typedef enum TC2_CLKSEL_enum
1689{
1690    TC2_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
1691    TC2_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
1692    TC2_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
1693    TC2_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
1694    TC2_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
1695    TC2_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
1696    TC2_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
1697    TC2_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
1698    TC2_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
1699    TC2_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
1700    TC2_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
1701    TC2_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
1702} TC2_CLKSEL_t;
1703
1704/* Byte Mode */
1705typedef enum TC2_BYTEM_enum
1706{
1707    TC2_BYTEM_NORMAL_gc = (0x00<<0),  /* 16-bit mode */
1708    TC2_BYTEM_BYTEMODE_gc = (0x01<<0),  /* Timer/Counter operating in byte mode only (TC2) */
1709    TC2_BYTEM_SPLITMODE_gc = (0x02<<0),  /* Timer/Counter split into two 8-bit Counters */
1710} TC2_BYTEM_t;
1711
1712/* High Byte Underflow Interrupt Level */
1713typedef enum TC2_HUNFINTLVL_enum
1714{
1715    TC2_HUNFINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1716    TC2_HUNFINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1717    TC2_HUNFINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1718    TC2_HUNFINTLVL_HI_gc = (0x03<<2),  /* High Level */
1719} TC2_HUNFINTLVL_t;
1720
1721/* Low Byte Underflow Interrupt Level */
1722typedef enum TC2_LUNFINTLVL_enum
1723{
1724    TC2_LUNFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1725    TC2_LUNFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1726    TC2_LUNFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1727    TC2_LUNFINTLVL_HI_gc = (0x03<<0),  /* High Level */
1728} TC2_LUNFINTLVL_t;
1729
1730/* Low Byte Compare D Interrupt Level */
1731typedef enum TC2_LCMPDINTLVL_enum
1732{
1733    TC2_LCMPDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1734    TC2_LCMPDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
1735    TC2_LCMPDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1736    TC2_LCMPDINTLVL_HI_gc = (0x03<<6),  /* High Level */
1737} TC2_LCMPDINTLVL_t;
1738
1739/* Low Byte Compare C Interrupt Level */
1740typedef enum TC2_LCMPCINTLVL_enum
1741{
1742    TC2_LCMPCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
1743    TC2_LCMPCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
1744    TC2_LCMPCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
1745    TC2_LCMPCINTLVL_HI_gc = (0x03<<4),  /* High Level */
1746} TC2_LCMPCINTLVL_t;
1747
1748/* Low Byte Compare B Interrupt Level */
1749typedef enum TC2_LCMPBINTLVL_enum
1750{
1751    TC2_LCMPBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1752    TC2_LCMPBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1753    TC2_LCMPBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1754    TC2_LCMPBINTLVL_HI_gc = (0x03<<2),  /* High Level */
1755} TC2_LCMPBINTLVL_t;
1756
1757/* Low Byte Compare A Interrupt Level */
1758typedef enum TC2_LCMPAINTLVL_enum
1759{
1760    TC2_LCMPAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1761    TC2_LCMPAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1762    TC2_LCMPAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1763    TC2_LCMPAINTLVL_HI_gc = (0x03<<0),  /* High Level */
1764} TC2_LCMPAINTLVL_t;
1765
1766/* Timer/Counter Command */
1767typedef enum TC2_CMD_enum
1768{
1769    TC2_CMD_NONE_gc = (0x00<<2),  /* No Command */
1770    TC2_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
1771    TC2_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
1772} TC2_CMD_t;
1773
1774/* Timer/Counter Command */
1775typedef enum TC2_CMDEN_enum
1776{
1777    TC2_CMDEN_LOW_gc = (0x01<<0),  /* Low Byte Timer/Counter */
1778    TC2_CMDEN_HIGH_gc = (0x02<<0),  /* High Byte Timer/Counter */
1779    TC2_CMDEN_BOTH_gc = (0x03<<0),  /* Both Low Byte and High Byte Timer/Counters */
1780} TC2_CMDEN_t;
1781
1782
1783/*
1784--------------------------------------------------------------------------
1785AWEX - Timer/Counter Advanced Waveform Extension
1786--------------------------------------------------------------------------
1787*/
1788
1789/* Advanced Waveform Extension */
1790typedef struct AWEX_struct
1791{
1792    register8_t CTRL;  /* Control Register */
1793    register8_t reserved_0x01;
1794    register8_t FDEMASK;  /* Fault Detection Event Mask */
1795    register8_t FDCTRL;  /* Fault Detection Control Register */
1796    register8_t STATUS;  /* Status Register */
1797    register8_t STATUSSET;  /* Status Set Register */
1798    register8_t DTBOTH;  /* Dead Time Both Sides */
1799    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
1800    register8_t DTLS;  /* Dead Time Low Side */
1801    register8_t DTHS;  /* Dead Time High Side */
1802    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
1803    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
1804    register8_t OUTOVEN;  /* Output Override Enable */
1805} AWEX_t;
1806
1807/* Fault Detect Action */
1808typedef enum AWEX_FDACT_enum
1809{
1810    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
1811    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
1812    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
1813} AWEX_FDACT_t;
1814
1815
1816/*
1817--------------------------------------------------------------------------
1818HIRES - Timer/Counter High-Resolution Extension
1819--------------------------------------------------------------------------
1820*/
1821
1822/* High-Resolution Extension */
1823typedef struct HIRES_struct
1824{
1825    register8_t CTRLA;  /* Control Register */
1826} HIRES_t;
1827
1828/* High Resolution Enable */
1829typedef enum HIRES_HREN_enum
1830{
1831    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
1832    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
1833    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
1834    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
1835} HIRES_HREN_t;
1836
1837
1838/*
1839--------------------------------------------------------------------------
1840USART - Universal Asynchronous Receiver-Transmitter
1841--------------------------------------------------------------------------
1842*/
1843
1844/* Universal Synchronous/Asynchronous Receiver/Transmitter */
1845typedef struct USART_struct
1846{
1847    register8_t DATA;  /* Data Register */
1848    register8_t STATUS;  /* Status Register */
1849    register8_t reserved_0x02;
1850    register8_t CTRLA;  /* Control Register A */
1851    register8_t CTRLB;  /* Control Register B */
1852    register8_t CTRLC;  /* Control Register C */
1853    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
1854    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
1855} USART_t;
1856
1857/* Receive Complete Interrupt level */
1858typedef enum USART_RXCINTLVL_enum
1859{
1860    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
1861    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
1862    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
1863    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
1864} USART_RXCINTLVL_t;
1865
1866/* Transmit Complete Interrupt level */
1867typedef enum USART_TXCINTLVL_enum
1868{
1869    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1870    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1871    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1872    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
1873} USART_TXCINTLVL_t;
1874
1875/* Data Register Empty Interrupt level */
1876typedef enum USART_DREINTLVL_enum
1877{
1878    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1879    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1880    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1881    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
1882} USART_DREINTLVL_t;
1883
1884/* Character Size */
1885typedef enum USART_CHSIZE_enum
1886{
1887    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
1888    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
1889    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
1890    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
1891    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
1892} USART_CHSIZE_t;
1893
1894/* Communication Mode */
1895typedef enum USART_CMODE_enum
1896{
1897    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
1898    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
1899    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
1900    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
1901} USART_CMODE_t;
1902
1903/* Parity Mode */
1904typedef enum USART_PMODE_enum
1905{
1906    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
1907    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
1908    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
1909} USART_PMODE_t;
1910
1911
1912/*
1913--------------------------------------------------------------------------
1914SPI - Serial Peripheral Interface
1915--------------------------------------------------------------------------
1916*/
1917
1918/* Serial Peripheral Interface */
1919typedef struct SPI_struct
1920{
1921    register8_t CTRL;  /* Control Register */
1922    register8_t INTCTRL;  /* Interrupt Control Register */
1923    register8_t STATUS;  /* Status Register */
1924    register8_t DATA;  /* Data Register */
1925} SPI_t;
1926
1927/* SPI Mode */
1928typedef enum SPI_MODE_enum
1929{
1930    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
1931    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
1932    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
1933    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
1934} SPI_MODE_t;
1935
1936/* Prescaler setting */
1937typedef enum SPI_PRESCALER_enum
1938{
1939    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
1940    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
1941    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
1942    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
1943} SPI_PRESCALER_t;
1944
1945/* Interrupt level */
1946typedef enum SPI_INTLVL_enum
1947{
1948    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1949    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
1950    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1951    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
1952} SPI_INTLVL_t;
1953
1954
1955/*
1956--------------------------------------------------------------------------
1957IRCOM - IR Communication Module
1958--------------------------------------------------------------------------
1959*/
1960
1961/* IR Communication Module */
1962typedef struct IRCOM_struct
1963{
1964    register8_t CTRL;  /* Control Register */
1965    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
1966    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
1967} IRCOM_t;
1968
1969/* Event channel selection */
1970typedef enum IRDA_EVSEL_enum
1971{
1972    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
1973    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
1974    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
1975    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
1976    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
1977} IRDA_EVSEL_t;
1978
1979
1980/*
1981--------------------------------------------------------------------------
1982FUSE - Fuses and Lockbits
1983--------------------------------------------------------------------------
1984*/
1985
1986/* Fuses */
1987typedef struct NVM_FUSES_struct
1988{
1989    register8_t reserved_0x00;
1990    register8_t FUSEBYTE1;  /* Watchdog Configuration */
1991    register8_t FUSEBYTE2;  /* Reset Configuration */
1992    register8_t reserved_0x03;
1993    register8_t FUSEBYTE4;  /* Start-up Configuration */
1994    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
1995} NVM_FUSES_t;
1996
1997/* Boot Loader Section Reset Vector */
1998typedef enum BOOTRST_enum
1999{
2000    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
2001    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
2002} BOOTRST_t;
2003
2004/* Timer Oscillator pin location */
2005typedef enum TOSCSEL_enum
2006{
2007    TOSCSEL_ALTERNATE_gc = (0x00<<5),  /* TOSC1 / TOSC2 on separate pins */
2008    TOSCSEL_XTAL_gc = (0x01<<5),  /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
2009} TOSCSEL_t;
2010
2011/* BOD operation */
2012typedef enum BOD_enum
2013{
2014    BOD_SAMPLED_gc = (0x01<<0),  /* BOD enabled in sampled mode */
2015    BOD_CONTINUOUS_gc = (0x02<<0),  /* BOD enabled continuously */
2016    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
2017} BOD_t;
2018
2019/* BOD operation */
2020typedef enum BODACT_enum
2021{
2022    BODACT_SAMPLED_gc = (0x01<<4),  /* BOD enabled in sampled mode */
2023    BODACT_CONTINUOUS_gc = (0x02<<4),  /* BOD enabled continuously */
2024    BODACT_DISABLED_gc = (0x03<<4),  /* BOD Disabled */
2025} BODACT_t;
2026
2027/* Watchdog (Window) Timeout Period */
2028typedef enum WD_enum
2029{
2030    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
2031    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
2032    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
2033    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
2034    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
2035    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
2036    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
2037    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
2038    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
2039    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
2040    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
2041} WD_t;
2042
2043/* Watchdog (Window) Timeout Period */
2044typedef enum WDP_enum
2045{
2046    WDP_8CLK_gc = (0x00<<0),  /* 8 cycles (8ms @ 3.3V) */
2047    WDP_16CLK_gc = (0x01<<0),  /* 16 cycles (16ms @ 3.3V) */
2048    WDP_32CLK_gc = (0x02<<0),  /* 32 cycles (32ms @ 3.3V) */
2049    WDP_64CLK_gc = (0x03<<0),  /* 64 cycles (64ms @ 3.3V) */
2050    WDP_128CLK_gc = (0x04<<0),  /* 128 cycles (0.125s @ 3.3V) */
2051    WDP_256CLK_gc = (0x05<<0),  /* 256 cycles (0.25s @ 3.3V) */
2052    WDP_512CLK_gc = (0x06<<0),  /* 512 cycles (0.5s @ 3.3V) */
2053    WDP_1KCLK_gc = (0x07<<0),  /* 1K cycles (1s @ 3.3V) */
2054    WDP_2KCLK_gc = (0x08<<0),  /* 2K cycles (2s @ 3.3V) */
2055    WDP_4KCLK_gc = (0x09<<0),  /* 4K cycles (4s @ 3.3V) */
2056    WDP_8KCLK_gc = (0x0A<<0),  /* 8K cycles (8s @ 3.3V) */
2057} WDP_t;
2058
2059/* Start-up Time */
2060typedef enum SUT_enum
2061{
2062    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
2063    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
2064    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
2065} SUT_t;
2066
2067/* Brownout Detection Voltage Level */
2068typedef enum BODLVL_enum
2069{
2070    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
2071    BODLVL_1V8_gc = (0x06<<0),  /* 1.8 V */
2072    BODLVL_2V0_gc = (0x05<<0),  /* 2.0 V */
2073    BODLVL_2V2_gc = (0x04<<0),  /* 2.2 V */
2074    BODLVL_2V4_gc = (0x03<<0),  /* 2.4 V */
2075    BODLVL_2V6_gc = (0x02<<0),  /* 2.6 V */
2076    BODLVL_2V8_gc = (0x01<<0),  /* 2.8 V */
2077    BODLVL_3V0_gc = (0x00<<0),  /* 3.0 V */
2078} BODLVL_t;
2079
2080
2081/*
2082--------------------------------------------------------------------------
2083LOCKBIT - Fuses and Lockbits
2084--------------------------------------------------------------------------
2085*/
2086
2087/* Lock Bits */
2088typedef struct NVM_LOCKBITS_struct
2089{
2090    register8_t LOCKBITS;  /* Lock Bits */
2091} NVM_LOCKBITS_t;
2092
2093/* Boot lock bits - boot setcion */
2094typedef enum FUSE_BLBB_enum
2095{
2096    FUSE_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
2097    FUSE_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
2098    FUSE_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
2099    FUSE_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
2100} FUSE_BLBB_t;
2101
2102/* Boot lock bits - application section */
2103typedef enum FUSE_BLBA_enum
2104{
2105    FUSE_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
2106    FUSE_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
2107    FUSE_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
2108    FUSE_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
2109} FUSE_BLBA_t;
2110
2111/* Boot lock bits - application table section */
2112typedef enum FUSE_BLBAT_enum
2113{
2114    FUSE_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
2115    FUSE_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
2116    FUSE_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
2117    FUSE_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
2118} FUSE_BLBAT_t;
2119
2120/* Lock bits */
2121typedef enum FUSE_LB_enum
2122{
2123    FUSE_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
2124    FUSE_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
2125    FUSE_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
2126} FUSE_LB_t;
2127
2128
2129/*
2130--------------------------------------------------------------------------
2131SIGROW - Signature Row
2132--------------------------------------------------------------------------
2133*/
2134
2135/* Production Signatures */
2136typedef struct NVM_PROD_SIGNATURES_struct
2137{
2138    register8_t RCOSC2M;  /* RCOSC 2 MHz Calibration Value B */
2139    register8_t RCOSC2MA;  /* RCOSC 2 MHz Calibration Value A */
2140    register8_t RCOSC32K;  /* RCOSC 32.768 kHz Calibration Value */
2141    register8_t RCOSC32M;  /* RCOSC 32 MHz Calibration Value B */
2142    register8_t RCOSC32MA;  /* RCOSC 32 MHz Calibration Value A */
2143    register8_t reserved_0x05;
2144    register8_t reserved_0x06;
2145    register8_t reserved_0x07;
2146    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
2147    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
2148    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
2149    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
2150    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
2151    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
2152    register8_t reserved_0x0E;
2153    register8_t reserved_0x0F;
2154    register8_t WAFNUM;  /* Wafer Number */
2155    register8_t reserved_0x11;
2156    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
2157    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
2158    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
2159    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
2160    register8_t reserved_0x16;
2161    register8_t reserved_0x17;
2162    register8_t reserved_0x18;
2163    register8_t reserved_0x19;
2164    register8_t reserved_0x1A;
2165    register8_t reserved_0x1B;
2166    register8_t reserved_0x1C;
2167    register8_t reserved_0x1D;
2168    register8_t reserved_0x1E;
2169    register8_t reserved_0x1F;
2170    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
2171    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
2172    register8_t reserved_0x22;
2173    register8_t reserved_0x23;
2174    register8_t reserved_0x24;
2175    register8_t reserved_0x25;
2176    register8_t reserved_0x26;
2177    register8_t reserved_0x27;
2178    register8_t reserved_0x28;
2179    register8_t reserved_0x29;
2180    register8_t reserved_0x2A;
2181    register8_t reserved_0x2B;
2182    register8_t reserved_0x2C;
2183    register8_t reserved_0x2D;
2184    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
2185    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 1 */
2186    register8_t reserved_0x30;
2187    register8_t reserved_0x31;
2188    register8_t reserved_0x32;
2189    register8_t reserved_0x33;
2190    register8_t reserved_0x34;
2191    register8_t reserved_0x35;
2192    register8_t reserved_0x36;
2193    register8_t reserved_0x37;
2194    register8_t reserved_0x38;
2195    register8_t reserved_0x39;
2196    register8_t reserved_0x3A;
2197    register8_t reserved_0x3B;
2198    register8_t reserved_0x3C;
2199    register8_t reserved_0x3D;
2200    register8_t reserved_0x3E;
2201    register8_t reserved_0x3F;
2202} NVM_PROD_SIGNATURES_t;
2203
2204/*
2205==========================================================================
2206IO Module Instances. Mapped to memory.
2207==========================================================================
2208*/
2209
2210#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port */
2211#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port */
2212#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port */
2213#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port */
2214#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
2215#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
2216#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
2217#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator */
2218#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL */
2219#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL */
2220#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
2221#define RST    (*(RST_t *) 0x0078)  /* Reset */
2222#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
2223#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
2224#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Multi-level Interrupt Controller */
2225#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* I/O port Configuration */
2226#define CRC    (*(CRC_t *) 0x00D0)  /* Cyclic Redundancy Checker */
2227#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
2228#define NVM    (*(NVM_t *) 0x01C0)  /* Non-volatile Memory Controller */
2229#define ADCA    (*(ADC_t *) 0x0200)  /* Analog-to-Digital Converter */
2230#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator */
2231#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
2232#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface */
2233#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface */
2234#define PORTA    (*(PORT_t *) 0x0600)  /* I/O Ports */
2235#define PORTB    (*(PORT_t *) 0x0620)  /* I/O Ports */
2236#define PORTC    (*(PORT_t *) 0x0640)  /* I/O Ports */
2237#define PORTD    (*(PORT_t *) 0x0660)  /* I/O Ports */
2238#define PORTE    (*(PORT_t *) 0x0680)  /* I/O Ports */
2239#define PORTR    (*(PORT_t *) 0x07E0)  /* I/O Ports */
2240#define TCC0    (*(TC0_t *) 0x0800)  /* 16-bit Timer/Counter 0 */
2241#define TCC2    (*(TC2_t *) 0x0800)  /* 16-bit Timer/Counter type 2 */
2242#define TCC1    (*(TC1_t *) 0x0840)  /* 16-bit Timer/Counter 1 */
2243#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension */
2244#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension */
2245#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
2246#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface */
2247#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
2248#define TCD0    (*(TC0_t *) 0x0900)  /* 16-bit Timer/Counter 0 */
2249#define TCD2    (*(TC2_t *) 0x0900)  /* 16-bit Timer/Counter type 2 */
2250#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
2251#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface */
2252#define TCE0    (*(TC0_t *) 0x0A00)  /* 16-bit Timer/Counter 0 */
2253
2254
2255#endif /* !defined (__ASSEMBLER__) */
2256
2257
2258/* ========== Flattened fully qualified IO register names ========== */
2259
2260/* GPIO - General Purpose IO Registers */
2261#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
2262#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
2263#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
2264#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
2265
2266/* Deprecated */
2267#define GPIO_GPIO0  _SFR_MEM8(0x0000)
2268#define GPIO_GPIO1  _SFR_MEM8(0x0001)
2269#define GPIO_GPIO2  _SFR_MEM8(0x0002)
2270#define GPIO_GPIO3  _SFR_MEM8(0x0003)
2271
2272/* NVM_FUSES - Fuses */
2273#define FUSE_FUSEBYTE1  _SFR_MEM8(0x0001)
2274#define FUSE_FUSEBYTE2  _SFR_MEM8(0x0002)
2275#define FUSE_FUSEBYTE4  _SFR_MEM8(0x0004)
2276#define FUSE_FUSEBYTE5  _SFR_MEM8(0x0005)
2277
2278/* NVM_LOCKBITS - Lock Bits */
2279#define LOCKBIT_LOCKBITS  _SFR_MEM8(0x0000)
2280
2281/* NVM_PROD_SIGNATURES - Production Signatures */
2282#define PRODSIGNATURES_RCOSC2M  _SFR_MEM8(0x0000)
2283#define PRODSIGNATURES_RCOSC2MA  _SFR_MEM8(0x0001)
2284#define PRODSIGNATURES_RCOSC32K  _SFR_MEM8(0x0002)
2285#define PRODSIGNATURES_RCOSC32M  _SFR_MEM8(0x0003)
2286#define PRODSIGNATURES_RCOSC32MA  _SFR_MEM8(0x0004)
2287#define PRODSIGNATURES_LOTNUM0  _SFR_MEM8(0x0008)
2288#define PRODSIGNATURES_LOTNUM1  _SFR_MEM8(0x0009)
2289#define PRODSIGNATURES_LOTNUM2  _SFR_MEM8(0x000A)
2290#define PRODSIGNATURES_LOTNUM3  _SFR_MEM8(0x000B)
2291#define PRODSIGNATURES_LOTNUM4  _SFR_MEM8(0x000C)
2292#define PRODSIGNATURES_LOTNUM5  _SFR_MEM8(0x000D)
2293#define PRODSIGNATURES_WAFNUM  _SFR_MEM8(0x0010)
2294#define PRODSIGNATURES_COORDX0  _SFR_MEM8(0x0012)
2295#define PRODSIGNATURES_COORDX1  _SFR_MEM8(0x0013)
2296#define PRODSIGNATURES_COORDY0  _SFR_MEM8(0x0014)
2297#define PRODSIGNATURES_COORDY1  _SFR_MEM8(0x0015)
2298#define PRODSIGNATURES_ADCACAL0  _SFR_MEM8(0x0020)
2299#define PRODSIGNATURES_ADCACAL1  _SFR_MEM8(0x0021)
2300#define PRODSIGNATURES_TEMPSENSE0  _SFR_MEM8(0x002E)
2301#define PRODSIGNATURES_TEMPSENSE1  _SFR_MEM8(0x002F)
2302
2303/* VPORT - Virtual Port */
2304#define VPORT0_DIR  _SFR_MEM8(0x0010)
2305#define VPORT0_OUT  _SFR_MEM8(0x0011)
2306#define VPORT0_IN  _SFR_MEM8(0x0012)
2307#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
2308
2309/* VPORT - Virtual Port */
2310#define VPORT1_DIR  _SFR_MEM8(0x0014)
2311#define VPORT1_OUT  _SFR_MEM8(0x0015)
2312#define VPORT1_IN  _SFR_MEM8(0x0016)
2313#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
2314
2315/* VPORT - Virtual Port */
2316#define VPORT2_DIR  _SFR_MEM8(0x0018)
2317#define VPORT2_OUT  _SFR_MEM8(0x0019)
2318#define VPORT2_IN  _SFR_MEM8(0x001A)
2319#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
2320
2321/* VPORT - Virtual Port */
2322#define VPORT3_DIR  _SFR_MEM8(0x001C)
2323#define VPORT3_OUT  _SFR_MEM8(0x001D)
2324#define VPORT3_IN  _SFR_MEM8(0x001E)
2325#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
2326
2327/* OCD - On-Chip Debug System */
2328#define OCD_OCDR0  _SFR_MEM8(0x002E)
2329#define OCD_OCDR1  _SFR_MEM8(0x002F)
2330
2331/* CPU - CPU registers */
2332#define CPU_CCP  _SFR_MEM8(0x0034)
2333#define CPU_RAMPD  _SFR_MEM8(0x0038)
2334#define CPU_RAMPX  _SFR_MEM8(0x0039)
2335#define CPU_RAMPY  _SFR_MEM8(0x003A)
2336#define CPU_RAMPZ  _SFR_MEM8(0x003B)
2337#define CPU_EIND  _SFR_MEM8(0x003C)
2338#define CPU_SPL  _SFR_MEM8(0x003D)
2339#define CPU_SPH  _SFR_MEM8(0x003E)
2340#define CPU_SREG  _SFR_MEM8(0x003F)
2341
2342/* CLK - Clock System */
2343#define CLK_CTRL  _SFR_MEM8(0x0040)
2344#define CLK_PSCTRL  _SFR_MEM8(0x0041)
2345#define CLK_LOCK  _SFR_MEM8(0x0042)
2346#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
2347
2348/* SLEEP - Sleep Controller */
2349#define SLEEP_CTRL  _SFR_MEM8(0x0048)
2350
2351/* OSC - Oscillator */
2352#define OSC_CTRL  _SFR_MEM8(0x0050)
2353#define OSC_STATUS  _SFR_MEM8(0x0051)
2354#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
2355#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
2356#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
2357#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
2358#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
2359
2360/* DFLL - DFLL */
2361#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
2362#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
2363#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
2364#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
2365#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
2366#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
2367
2368/* DFLL - DFLL */
2369#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
2370#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
2371#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
2372#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
2373#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
2374#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
2375
2376/* PR - Power Reduction */
2377#define PR_PRGEN  _SFR_MEM8(0x0070)
2378#define PR_PRPA  _SFR_MEM8(0x0071)
2379#define PR_PRPC  _SFR_MEM8(0x0073)
2380#define PR_PRPD  _SFR_MEM8(0x0074)
2381#define PR_PRPE  _SFR_MEM8(0x0075)
2382#define PR_PRPF  _SFR_MEM8(0x0076)
2383
2384/* RST - Reset */
2385#define RST_STATUS  _SFR_MEM8(0x0078)
2386#define RST_CTRL  _SFR_MEM8(0x0079)
2387
2388/* WDT - Watch-Dog Timer */
2389#define WDT_CTRL  _SFR_MEM8(0x0080)
2390#define WDT_WINCTRL  _SFR_MEM8(0x0081)
2391#define WDT_STATUS  _SFR_MEM8(0x0082)
2392
2393/* MCU - MCU Control */
2394#define MCU_DEVID0  _SFR_MEM8(0x0090)
2395#define MCU_DEVID1  _SFR_MEM8(0x0091)
2396#define MCU_DEVID2  _SFR_MEM8(0x0092)
2397#define MCU_REVID  _SFR_MEM8(0x0093)
2398#define MCU_ANAINIT  _SFR_MEM8(0x0097)
2399#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
2400#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
2401
2402/* PMIC - Programmable Multi-level Interrupt Controller */
2403#define PMIC_STATUS  _SFR_MEM8(0x00A0)
2404#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
2405#define PMIC_CTRL  _SFR_MEM8(0x00A2)
2406
2407/* PORTCFG - I/O port Configuration */
2408#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
2409#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
2410#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
2411#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
2412#define PORTCFG_EVOUTSEL  _SFR_MEM8(0x00B6)
2413
2414/* CRC - Cyclic Redundancy Checker */
2415#define CRC_CTRL  _SFR_MEM8(0x00D0)
2416#define CRC_STATUS  _SFR_MEM8(0x00D1)
2417#define CRC_DATAIN  _SFR_MEM8(0x00D3)
2418#define CRC_CHECKSUM0  _SFR_MEM8(0x00D4)
2419#define CRC_CHECKSUM1  _SFR_MEM8(0x00D5)
2420#define CRC_CHECKSUM2  _SFR_MEM8(0x00D6)
2421#define CRC_CHECKSUM3  _SFR_MEM8(0x00D7)
2422
2423/* EVSYS - Event System */
2424#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
2425#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
2426#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
2427#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
2428#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
2429#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
2430#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
2431#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
2432#define EVSYS_STROBE  _SFR_MEM8(0x0190)
2433#define EVSYS_DATA  _SFR_MEM8(0x0191)
2434
2435/* NVM - Non-volatile Memory Controller */
2436#define NVM_ADDR0  _SFR_MEM8(0x01C0)
2437#define NVM_ADDR1  _SFR_MEM8(0x01C1)
2438#define NVM_ADDR2  _SFR_MEM8(0x01C2)
2439#define NVM_DATA0  _SFR_MEM8(0x01C4)
2440#define NVM_DATA1  _SFR_MEM8(0x01C5)
2441#define NVM_DATA2  _SFR_MEM8(0x01C6)
2442#define NVM_CMD  _SFR_MEM8(0x01CA)
2443#define NVM_CTRLA  _SFR_MEM8(0x01CB)
2444#define NVM_CTRLB  _SFR_MEM8(0x01CC)
2445#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
2446#define NVM_STATUS  _SFR_MEM8(0x01CF)
2447#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
2448
2449/* ADC - Analog-to-Digital Converter */
2450#define ADCA_CTRLA  _SFR_MEM8(0x0200)
2451#define ADCA_CTRLB  _SFR_MEM8(0x0201)
2452#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
2453#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
2454#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
2455#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
2456#define ADCA_TEMP  _SFR_MEM8(0x0207)
2457#define ADCA_CAL  _SFR_MEM16(0x020C)
2458#define ADCA_CH0RES  _SFR_MEM16(0x0210)
2459#define ADCA_CMP  _SFR_MEM16(0x0218)
2460#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
2461#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
2462#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
2463#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
2464#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
2465#define ADCA_CH0_SCAN  _SFR_MEM8(0x0226)
2466
2467/* AC - Analog Comparator */
2468#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
2469#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
2470#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
2471#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
2472#define ACA_CTRLA  _SFR_MEM8(0x0384)
2473#define ACA_CTRLB  _SFR_MEM8(0x0385)
2474#define ACA_WINCTRL  _SFR_MEM8(0x0386)
2475#define ACA_STATUS  _SFR_MEM8(0x0387)
2476
2477/* RTC - Real-Time Counter */
2478#define RTC_CTRL  _SFR_MEM8(0x0400)
2479#define RTC_STATUS  _SFR_MEM8(0x0401)
2480#define RTC_INTCTRL  _SFR_MEM8(0x0402)
2481#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
2482#define RTC_TEMP  _SFR_MEM8(0x0404)
2483#define RTC_CNT  _SFR_MEM16(0x0408)
2484#define RTC_PER  _SFR_MEM16(0x040A)
2485#define RTC_COMP  _SFR_MEM16(0x040C)
2486
2487/* TWI - Two-Wire Interface */
2488#define TWIC_CTRL  _SFR_MEM8(0x0480)
2489#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
2490#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
2491#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
2492#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
2493#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
2494#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
2495#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
2496#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
2497#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
2498#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
2499#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
2500#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
2501#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
2502
2503/* TWI - Two-Wire Interface */
2504#define TWIE_CTRL  _SFR_MEM8(0x04A0)
2505#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
2506#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
2507#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
2508#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
2509#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
2510#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
2511#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
2512#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
2513#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
2514#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
2515#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
2516#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
2517#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
2518
2519/* PORT - I/O Ports */
2520#define PORTA_DIR  _SFR_MEM8(0x0600)
2521#define PORTA_DIRSET  _SFR_MEM8(0x0601)
2522#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
2523#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
2524#define PORTA_OUT  _SFR_MEM8(0x0604)
2525#define PORTA_OUTSET  _SFR_MEM8(0x0605)
2526#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
2527#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
2528#define PORTA_IN  _SFR_MEM8(0x0608)
2529#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
2530#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
2531#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
2532#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
2533#define PORTA_REMAP  _SFR_MEM8(0x060E)
2534#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
2535#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
2536#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
2537#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
2538#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
2539#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
2540#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
2541#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
2542
2543/* PORT - I/O Ports */
2544#define PORTB_DIR  _SFR_MEM8(0x0620)
2545#define PORTB_DIRSET  _SFR_MEM8(0x0621)
2546#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
2547#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
2548#define PORTB_OUT  _SFR_MEM8(0x0624)
2549#define PORTB_OUTSET  _SFR_MEM8(0x0625)
2550#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
2551#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
2552#define PORTB_IN  _SFR_MEM8(0x0628)
2553#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
2554#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
2555#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
2556#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
2557#define PORTB_REMAP  _SFR_MEM8(0x062E)
2558#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
2559#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
2560#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
2561#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
2562#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
2563#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
2564#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
2565#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
2566
2567/* PORT - I/O Ports */
2568#define PORTC_DIR  _SFR_MEM8(0x0640)
2569#define PORTC_DIRSET  _SFR_MEM8(0x0641)
2570#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
2571#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
2572#define PORTC_OUT  _SFR_MEM8(0x0644)
2573#define PORTC_OUTSET  _SFR_MEM8(0x0645)
2574#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
2575#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
2576#define PORTC_IN  _SFR_MEM8(0x0648)
2577#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
2578#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
2579#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
2580#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
2581#define PORTC_REMAP  _SFR_MEM8(0x064E)
2582#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
2583#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
2584#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
2585#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
2586#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
2587#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
2588#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
2589#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
2590
2591/* PORT - I/O Ports */
2592#define PORTD_DIR  _SFR_MEM8(0x0660)
2593#define PORTD_DIRSET  _SFR_MEM8(0x0661)
2594#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
2595#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
2596#define PORTD_OUT  _SFR_MEM8(0x0664)
2597#define PORTD_OUTSET  _SFR_MEM8(0x0665)
2598#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
2599#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
2600#define PORTD_IN  _SFR_MEM8(0x0668)
2601#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
2602#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
2603#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
2604#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
2605#define PORTD_REMAP  _SFR_MEM8(0x066E)
2606#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
2607#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
2608#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
2609#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
2610#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
2611#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
2612#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
2613#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
2614
2615/* PORT - I/O Ports */
2616#define PORTE_DIR  _SFR_MEM8(0x0680)
2617#define PORTE_DIRSET  _SFR_MEM8(0x0681)
2618#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
2619#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
2620#define PORTE_OUT  _SFR_MEM8(0x0684)
2621#define PORTE_OUTSET  _SFR_MEM8(0x0685)
2622#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
2623#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
2624#define PORTE_IN  _SFR_MEM8(0x0688)
2625#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
2626#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
2627#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
2628#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
2629#define PORTE_REMAP  _SFR_MEM8(0x068E)
2630#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
2631#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
2632#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
2633#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
2634#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
2635#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
2636#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
2637#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
2638
2639/* PORT - I/O Ports */
2640#define PORTR_DIR  _SFR_MEM8(0x07E0)
2641#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
2642#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
2643#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
2644#define PORTR_OUT  _SFR_MEM8(0x07E4)
2645#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
2646#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
2647#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
2648#define PORTR_IN  _SFR_MEM8(0x07E8)
2649#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
2650#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
2651#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
2652#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
2653#define PORTR_REMAP  _SFR_MEM8(0x07EE)
2654#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
2655#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
2656#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
2657#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
2658#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
2659#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
2660#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
2661#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
2662
2663/* TC0 - 16-bit Timer/Counter 0 */
2664#define TCC0_CTRLA  _SFR_MEM8(0x0800)
2665#define TCC0_CTRLB  _SFR_MEM8(0x0801)
2666#define TCC0_CTRLC  _SFR_MEM8(0x0802)
2667#define TCC0_CTRLD  _SFR_MEM8(0x0803)
2668#define TCC0_CTRLE  _SFR_MEM8(0x0804)
2669#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
2670#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
2671#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
2672#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
2673#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
2674#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
2675#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
2676#define TCC0_TEMP  _SFR_MEM8(0x080F)
2677#define TCC0_CNT  _SFR_MEM16(0x0820)
2678#define TCC0_PER  _SFR_MEM16(0x0826)
2679#define TCC0_CCA  _SFR_MEM16(0x0828)
2680#define TCC0_CCB  _SFR_MEM16(0x082A)
2681#define TCC0_CCC  _SFR_MEM16(0x082C)
2682#define TCC0_CCD  _SFR_MEM16(0x082E)
2683#define TCC0_PERBUF  _SFR_MEM16(0x0836)
2684#define TCC0_CCABUF  _SFR_MEM16(0x0838)
2685#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
2686#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
2687#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
2688
2689/* TC2 - 16-bit Timer/Counter type 2 */
2690#define TCC2_CTRLA  _SFR_MEM8(0x0800)
2691#define TCC2_CTRLB  _SFR_MEM8(0x0801)
2692#define TCC2_CTRLC  _SFR_MEM8(0x0802)
2693#define TCC2_CTRLE  _SFR_MEM8(0x0804)
2694#define TCC2_INTCTRLA  _SFR_MEM8(0x0806)
2695#define TCC2_INTCTRLB  _SFR_MEM8(0x0807)
2696#define TCC2_CTRLF  _SFR_MEM8(0x0809)
2697#define TCC2_INTFLAGS  _SFR_MEM8(0x080C)
2698#define TCC2_LCNT  _SFR_MEM8(0x0820)
2699#define TCC2_HCNT  _SFR_MEM8(0x0821)
2700#define TCC2_LPER  _SFR_MEM8(0x0826)
2701#define TCC2_HPER  _SFR_MEM8(0x0827)
2702#define TCC2_LCMPA  _SFR_MEM8(0x0828)
2703#define TCC2_HCMPA  _SFR_MEM8(0x0829)
2704#define TCC2_LCMPB  _SFR_MEM8(0x082A)
2705#define TCC2_HCMPB  _SFR_MEM8(0x082B)
2706#define TCC2_LCMPC  _SFR_MEM8(0x082C)
2707#define TCC2_HCMPC  _SFR_MEM8(0x082D)
2708#define TCC2_LCMPD  _SFR_MEM8(0x082E)
2709#define TCC2_HCMPD  _SFR_MEM8(0x082F)
2710
2711/* TC1 - 16-bit Timer/Counter 1 */
2712#define TCC1_CTRLA  _SFR_MEM8(0x0840)
2713#define TCC1_CTRLB  _SFR_MEM8(0x0841)
2714#define TCC1_CTRLC  _SFR_MEM8(0x0842)
2715#define TCC1_CTRLD  _SFR_MEM8(0x0843)
2716#define TCC1_CTRLE  _SFR_MEM8(0x0844)
2717#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
2718#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
2719#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
2720#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
2721#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
2722#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
2723#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
2724#define TCC1_TEMP  _SFR_MEM8(0x084F)
2725#define TCC1_CNT  _SFR_MEM16(0x0860)
2726#define TCC1_PER  _SFR_MEM16(0x0866)
2727#define TCC1_CCA  _SFR_MEM16(0x0868)
2728#define TCC1_CCB  _SFR_MEM16(0x086A)
2729#define TCC1_PERBUF  _SFR_MEM16(0x0876)
2730#define TCC1_CCABUF  _SFR_MEM16(0x0878)
2731#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
2732
2733/* AWEX - Advanced Waveform Extension */
2734#define AWEXC_CTRL  _SFR_MEM8(0x0880)
2735#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
2736#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
2737#define AWEXC_STATUS  _SFR_MEM8(0x0884)
2738#define AWEXC_STATUSSET  _SFR_MEM8(0x0885)
2739#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
2740#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
2741#define AWEXC_DTLS  _SFR_MEM8(0x0888)
2742#define AWEXC_DTHS  _SFR_MEM8(0x0889)
2743#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
2744#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
2745#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
2746
2747/* HIRES - High-Resolution Extension */
2748#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
2749
2750/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
2751#define USARTC0_DATA  _SFR_MEM8(0x08A0)
2752#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
2753#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
2754#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
2755#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
2756#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
2757#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
2758
2759/* SPI - Serial Peripheral Interface */
2760#define SPIC_CTRL  _SFR_MEM8(0x08C0)
2761#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
2762#define SPIC_STATUS  _SFR_MEM8(0x08C2)
2763#define SPIC_DATA  _SFR_MEM8(0x08C3)
2764
2765/* IRCOM - IR Communication Module */
2766#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
2767#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
2768#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
2769
2770/* TC0 - 16-bit Timer/Counter 0 */
2771#define TCD0_CTRLA  _SFR_MEM8(0x0900)
2772#define TCD0_CTRLB  _SFR_MEM8(0x0901)
2773#define TCD0_CTRLC  _SFR_MEM8(0x0902)
2774#define TCD0_CTRLD  _SFR_MEM8(0x0903)
2775#define TCD0_CTRLE  _SFR_MEM8(0x0904)
2776#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
2777#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
2778#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
2779#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
2780#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
2781#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
2782#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
2783#define TCD0_TEMP  _SFR_MEM8(0x090F)
2784#define TCD0_CNT  _SFR_MEM16(0x0920)
2785#define TCD0_PER  _SFR_MEM16(0x0926)
2786#define TCD0_CCA  _SFR_MEM16(0x0928)
2787#define TCD0_CCB  _SFR_MEM16(0x092A)
2788#define TCD0_CCC  _SFR_MEM16(0x092C)
2789#define TCD0_CCD  _SFR_MEM16(0x092E)
2790#define TCD0_PERBUF  _SFR_MEM16(0x0936)
2791#define TCD0_CCABUF  _SFR_MEM16(0x0938)
2792#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
2793#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
2794#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
2795
2796/* TC2 - 16-bit Timer/Counter type 2 */
2797#define TCD2_CTRLA  _SFR_MEM8(0x0900)
2798#define TCD2_CTRLB  _SFR_MEM8(0x0901)
2799#define TCD2_CTRLC  _SFR_MEM8(0x0902)
2800#define TCD2_CTRLE  _SFR_MEM8(0x0904)
2801#define TCD2_INTCTRLA  _SFR_MEM8(0x0906)
2802#define TCD2_INTCTRLB  _SFR_MEM8(0x0907)
2803#define TCD2_CTRLF  _SFR_MEM8(0x0909)
2804#define TCD2_INTFLAGS  _SFR_MEM8(0x090C)
2805#define TCD2_LCNT  _SFR_MEM8(0x0920)
2806#define TCD2_HCNT  _SFR_MEM8(0x0921)
2807#define TCD2_LPER  _SFR_MEM8(0x0926)
2808#define TCD2_HPER  _SFR_MEM8(0x0927)
2809#define TCD2_LCMPA  _SFR_MEM8(0x0928)
2810#define TCD2_HCMPA  _SFR_MEM8(0x0929)
2811#define TCD2_LCMPB  _SFR_MEM8(0x092A)
2812#define TCD2_HCMPB  _SFR_MEM8(0x092B)
2813#define TCD2_LCMPC  _SFR_MEM8(0x092C)
2814#define TCD2_HCMPC  _SFR_MEM8(0x092D)
2815#define TCD2_LCMPD  _SFR_MEM8(0x092E)
2816#define TCD2_HCMPD  _SFR_MEM8(0x092F)
2817
2818/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
2819#define USARTD0_DATA  _SFR_MEM8(0x09A0)
2820#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
2821#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
2822#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
2823#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
2824#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
2825#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
2826
2827/* SPI - Serial Peripheral Interface */
2828#define SPID_CTRL  _SFR_MEM8(0x09C0)
2829#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
2830#define SPID_STATUS  _SFR_MEM8(0x09C2)
2831#define SPID_DATA  _SFR_MEM8(0x09C3)
2832
2833/* TC0 - 16-bit Timer/Counter 0 */
2834#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
2835#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
2836#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
2837#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
2838#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
2839#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
2840#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
2841#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
2842#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
2843#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
2844#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
2845#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
2846#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
2847#define TCE0_CNT  _SFR_MEM16(0x0A20)
2848#define TCE0_PER  _SFR_MEM16(0x0A26)
2849#define TCE0_CCA  _SFR_MEM16(0x0A28)
2850#define TCE0_CCB  _SFR_MEM16(0x0A2A)
2851#define TCE0_CCC  _SFR_MEM16(0x0A2C)
2852#define TCE0_CCD  _SFR_MEM16(0x0A2E)
2853#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
2854#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
2855#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
2856#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
2857#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
2858
2859
2860
2861/*================== Bitfield Definitions ================== */
2862
2863/* VPORT - Virtual Ports */
2864/* VPORT.INTFLAGS  bit masks and bit positions */
2865#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
2866#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
2867
2868#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
2869#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
2870
2871/* XOCD - On-Chip Debug System */
2872/* OCD.OCDR0  bit masks and bit positions */
2873#define OCD_OCDRD_gm  0xFF  /* OCDR Dirty group mask. */
2874#define OCD_OCDRD_gp  0  /* OCDR Dirty group position. */
2875#define OCD_OCDRD0_bm  (1<<0)  /* OCDR Dirty bit 0 mask. */
2876#define OCD_OCDRD0_bp  0  /* OCDR Dirty bit 0 position. */
2877#define OCD_OCDRD1_bm  (1<<1)  /* OCDR Dirty bit 1 mask. */
2878#define OCD_OCDRD1_bp  1  /* OCDR Dirty bit 1 position. */
2879#define OCD_OCDRD2_bm  (1<<2)  /* OCDR Dirty bit 2 mask. */
2880#define OCD_OCDRD2_bp  2  /* OCDR Dirty bit 2 position. */
2881#define OCD_OCDRD3_bm  (1<<3)  /* OCDR Dirty bit 3 mask. */
2882#define OCD_OCDRD3_bp  3  /* OCDR Dirty bit 3 position. */
2883#define OCD_OCDRD4_bm  (1<<4)  /* OCDR Dirty bit 4 mask. */
2884#define OCD_OCDRD4_bp  4  /* OCDR Dirty bit 4 position. */
2885#define OCD_OCDRD5_bm  (1<<5)  /* OCDR Dirty bit 5 mask. */
2886#define OCD_OCDRD5_bp  5  /* OCDR Dirty bit 5 position. */
2887#define OCD_OCDRD6_bm  (1<<6)  /* OCDR Dirty bit 6 mask. */
2888#define OCD_OCDRD6_bp  6  /* OCDR Dirty bit 6 position. */
2889#define OCD_OCDRD7_bm  (1<<7)  /* OCDR Dirty bit 7 mask. */
2890#define OCD_OCDRD7_bp  7  /* OCDR Dirty bit 7 position. */
2891
2892/* OCD.OCDR1  bit masks and bit positions */
2893/* OCD_OCDRD  Predefined. */
2894/* OCD_OCDRD  Predefined. */
2895
2896/* CPU - CPU */
2897/* CPU.CCP  bit masks and bit positions */
2898#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
2899#define CPU_CCP_gp  0  /* CCP signature group position. */
2900#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
2901#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
2902#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
2903#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
2904#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
2905#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
2906#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
2907#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
2908#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
2909#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
2910#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
2911#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
2912#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
2913#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
2914#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
2915#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
2916
2917/* CPU.SREG  bit masks and bit positions */
2918#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
2919#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
2920
2921#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
2922#define CPU_T_bp  6  /* Transfer Bit bit position. */
2923
2924#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
2925#define CPU_H_bp  5  /* Half Carry Flag bit position. */
2926
2927#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
2928#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
2929
2930#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
2931#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
2932
2933#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
2934#define CPU_N_bp  2  /* Negative Flag bit position. */
2935
2936#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
2937#define CPU_Z_bp  1  /* Zero Flag bit position. */
2938
2939#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
2940#define CPU_C_bp  0  /* Carry Flag bit position. */
2941
2942/* CLK - Clock System */
2943/* CLK.CTRL  bit masks and bit positions */
2944#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
2945#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
2946#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
2947#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
2948#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
2949#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
2950#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
2951#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
2952
2953/* CLK.PSCTRL  bit masks and bit positions */
2954#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
2955#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
2956#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
2957#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
2958#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
2959#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
2960#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
2961#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
2962#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
2963#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
2964#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
2965#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
2966
2967#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
2968#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
2969#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
2970#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
2971#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
2972#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
2973
2974/* CLK.LOCK  bit masks and bit positions */
2975#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
2976#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
2977
2978/* CLK.RTCCTRL  bit masks and bit positions */
2979#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
2980#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
2981#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
2982#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
2983#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
2984#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
2985#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
2986#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
2987
2988#define CLK_RTCEN_bm  0x01  /* Clock Source Enable bit mask. */
2989#define CLK_RTCEN_bp  0  /* Clock Source Enable bit position. */
2990
2991/* PR.PRGEN  bit masks and bit positions */
2992#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
2993#define PR_RTC_bp  2  /* Real-time Counter bit position. */
2994
2995#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
2996#define PR_EVSYS_bp  1  /* Event System bit position. */
2997
2998/* PR.PRPA  bit masks and bit positions */
2999#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
3000#define PR_ADC_bp  1  /* Port A ADC bit position. */
3001
3002#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
3003#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
3004
3005/* PR.PRPC  bit masks and bit positions */
3006#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
3007#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
3008
3009#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
3010#define PR_USART0_bp  4  /* Port C USART0 bit position. */
3011
3012#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
3013#define PR_SPI_bp  3  /* Port C SPI bit position. */
3014
3015#define PR_HIRES_bm  0x04  /* Port C HIRES bit mask. */
3016#define PR_HIRES_bp  2  /* Port C HIRES bit position. */
3017
3018#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
3019#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
3020
3021#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
3022#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
3023
3024/* PR.PRPD  bit masks and bit positions */
3025/* PR_USART0  Predefined. */
3026/* PR_USART0  Predefined. */
3027
3028/* PR_SPI  Predefined. */
3029/* PR_SPI  Predefined. */
3030
3031/* PR_TC0  Predefined. */
3032/* PR_TC0  Predefined. */
3033
3034/* PR.PRPE  bit masks and bit positions */
3035/* PR_TWI  Predefined. */
3036/* PR_TWI  Predefined. */
3037
3038/* PR_USART0  Predefined. */
3039/* PR_USART0  Predefined. */
3040
3041/* PR_TC0  Predefined. */
3042/* PR_TC0  Predefined. */
3043
3044/* PR.PRPF  bit masks and bit positions */
3045/* PR_USART0  Predefined. */
3046/* PR_USART0  Predefined. */
3047
3048/* PR_TC0  Predefined. */
3049/* PR_TC0  Predefined. */
3050
3051/* SLEEP - Sleep Controller */
3052/* SLEEP.CTRL  bit masks and bit positions */
3053#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
3054#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
3055#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
3056#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
3057#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
3058#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
3059#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
3060#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
3061
3062#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
3063#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
3064
3065/* OSC - Oscillator */
3066/* OSC.CTRL  bit masks and bit positions */
3067#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
3068#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
3069
3070#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
3071#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
3072
3073#define OSC_RC32KEN_bm  0x04  /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
3074#define OSC_RC32KEN_bp  2  /* Internal 32.768 kHz RC Oscillator Enable bit position. */
3075
3076#define OSC_RC32MEN_bm  0x02  /* Internal 32 MHz RC Oscillator Enable bit mask. */
3077#define OSC_RC32MEN_bp  1  /* Internal 32 MHz RC Oscillator Enable bit position. */
3078
3079#define OSC_RC2MEN_bm  0x01  /* Internal 2 MHz RC Oscillator Enable bit mask. */
3080#define OSC_RC2MEN_bp  0  /* Internal 2 MHz RC Oscillator Enable bit position. */
3081
3082/* OSC.STATUS  bit masks and bit positions */
3083#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
3084#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
3085
3086#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
3087#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
3088
3089#define OSC_RC32KRDY_bm  0x04  /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
3090#define OSC_RC32KRDY_bp  2  /* Internal 32.768 kHz RC Oscillator Ready bit position. */
3091
3092#define OSC_RC32MRDY_bm  0x02  /* Internal 32 MHz RC Oscillator Ready bit mask. */
3093#define OSC_RC32MRDY_bp  1  /* Internal 32 MHz RC Oscillator Ready bit position. */
3094
3095#define OSC_RC2MRDY_bm  0x01  /* Internal 2 MHz RC Oscillator Ready bit mask. */
3096#define OSC_RC2MRDY_bp  0  /* Internal 2 MHz RC Oscillator Ready bit position. */
3097
3098/* OSC.XOSCCTRL  bit masks and bit positions */
3099#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
3100#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
3101#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
3102#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
3103#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
3104#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
3105
3106#define OSC_X32KLPM_bm  0x20  /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
3107#define OSC_X32KLPM_bp  5  /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
3108
3109#define OSC_XOSCPWR_bm  0x10  /* 16 MHz Crystal Oscillator High Power mode bit mask. */
3110#define OSC_XOSCPWR_bp  4  /* 16 MHz Crystal Oscillator High Power mode bit position. */
3111
3112#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
3113#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
3114#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
3115#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
3116#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
3117#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
3118#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
3119#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
3120#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
3121#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
3122
3123/* OSC.XOSCFAIL  bit masks and bit positions */
3124#define OSC_PLLFDIF_bm  0x08  /* PLL Failure Detection Interrupt Flag bit mask. */
3125#define OSC_PLLFDIF_bp  3  /* PLL Failure Detection Interrupt Flag bit position. */
3126
3127#define OSC_PLLFDEN_bm  0x04  /* PLL Failure Detection Enable bit mask. */
3128#define OSC_PLLFDEN_bp  2  /* PLL Failure Detection Enable bit position. */
3129
3130#define OSC_XOSCFDIF_bm  0x02  /* XOSC Failure Detection Interrupt Flag bit mask. */
3131#define OSC_XOSCFDIF_bp  1  /* XOSC Failure Detection Interrupt Flag bit position. */
3132
3133#define OSC_XOSCFDEN_bm  0x01  /* XOSC Failure Detection Enable bit mask. */
3134#define OSC_XOSCFDEN_bp  0  /* XOSC Failure Detection Enable bit position. */
3135
3136/* OSC.PLLCTRL  bit masks and bit positions */
3137#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
3138#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
3139#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
3140#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
3141#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
3142#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
3143
3144#define OSC_PLLDIV_bm  0x20  /* Divide by 2 bit mask. */
3145#define OSC_PLLDIV_bp  5  /* Divide by 2 bit position. */
3146
3147#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
3148#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
3149#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
3150#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
3151#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
3152#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
3153#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
3154#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
3155#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
3156#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
3157#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
3158#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
3159
3160/* OSC.DFLLCTRL  bit masks and bit positions */
3161#define OSC_RC32MCREF_gm  0x06  /* 32 MHz DFLL Calibration Reference group mask. */
3162#define OSC_RC32MCREF_gp  1  /* 32 MHz DFLL Calibration Reference group position. */
3163#define OSC_RC32MCREF0_bm  (1<<1)  /* 32 MHz DFLL Calibration Reference bit 0 mask. */
3164#define OSC_RC32MCREF0_bp  1  /* 32 MHz DFLL Calibration Reference bit 0 position. */
3165#define OSC_RC32MCREF1_bm  (1<<2)  /* 32 MHz DFLL Calibration Reference bit 1 mask. */
3166#define OSC_RC32MCREF1_bp  2  /* 32 MHz DFLL Calibration Reference bit 1 position. */
3167
3168#define OSC_RC2MCREF_bm  0x01  /* 2 MHz DFLL Calibration Reference bit mask. */
3169#define OSC_RC2MCREF_bp  0  /* 2 MHz DFLL Calibration Reference bit position. */
3170
3171/* DFLL - DFLL */
3172/* DFLL.CTRL  bit masks and bit positions */
3173#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
3174#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
3175
3176/* DFLL.CALA  bit masks and bit positions */
3177#define DFLL_CALL_gm  0x7F  /* DFLL Calibration Value A group mask. */
3178#define DFLL_CALL_gp  0  /* DFLL Calibration Value A group position. */
3179#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration Value A bit 0 mask. */
3180#define DFLL_CALL0_bp  0  /* DFLL Calibration Value A bit 0 position. */
3181#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration Value A bit 1 mask. */
3182#define DFLL_CALL1_bp  1  /* DFLL Calibration Value A bit 1 position. */
3183#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration Value A bit 2 mask. */
3184#define DFLL_CALL2_bp  2  /* DFLL Calibration Value A bit 2 position. */
3185#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration Value A bit 3 mask. */
3186#define DFLL_CALL3_bp  3  /* DFLL Calibration Value A bit 3 position. */
3187#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration Value A bit 4 mask. */
3188#define DFLL_CALL4_bp  4  /* DFLL Calibration Value A bit 4 position. */
3189#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration Value A bit 5 mask. */
3190#define DFLL_CALL5_bp  5  /* DFLL Calibration Value A bit 5 position. */
3191#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration Value A bit 6 mask. */
3192#define DFLL_CALL6_bp  6  /* DFLL Calibration Value A bit 6 position. */
3193
3194/* DFLL.CALB  bit masks and bit positions */
3195#define DFLL_CALH_gm  0x3F  /* DFLL Calibration Value B group mask. */
3196#define DFLL_CALH_gp  0  /* DFLL Calibration Value B group position. */
3197#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration Value B bit 0 mask. */
3198#define DFLL_CALH0_bp  0  /* DFLL Calibration Value B bit 0 position. */
3199#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration Value B bit 1 mask. */
3200#define DFLL_CALH1_bp  1  /* DFLL Calibration Value B bit 1 position. */
3201#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration Value B bit 2 mask. */
3202#define DFLL_CALH2_bp  2  /* DFLL Calibration Value B bit 2 position. */
3203#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration Value B bit 3 mask. */
3204#define DFLL_CALH3_bp  3  /* DFLL Calibration Value B bit 3 position. */
3205#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration Value B bit 4 mask. */
3206#define DFLL_CALH4_bp  4  /* DFLL Calibration Value B bit 4 position. */
3207#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration Value B bit 5 mask. */
3208#define DFLL_CALH5_bp  5  /* DFLL Calibration Value B bit 5 position. */
3209
3210/* RST - Reset */
3211/* RST.STATUS  bit masks and bit positions */
3212#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
3213#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
3214
3215#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
3216#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
3217
3218#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
3219#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
3220
3221#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
3222#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
3223
3224#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
3225#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
3226
3227#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
3228#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
3229
3230#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
3231#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
3232
3233/* RST.CTRL  bit masks and bit positions */
3234#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
3235#define RST_SWRST_bp  0  /* Software Reset bit position. */
3236
3237/* WDT - Watch-Dog Timer */
3238/* WDT.CTRL  bit masks and bit positions */
3239#define WDT_PER_gm  0x3C  /* Period group mask. */
3240#define WDT_PER_gp  2  /* Period group position. */
3241#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
3242#define WDT_PER0_bp  2  /* Period bit 0 position. */
3243#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
3244#define WDT_PER1_bp  3  /* Period bit 1 position. */
3245#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
3246#define WDT_PER2_bp  4  /* Period bit 2 position. */
3247#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
3248#define WDT_PER3_bp  5  /* Period bit 3 position. */
3249
3250#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
3251#define WDT_ENABLE_bp  1  /* Enable bit position. */
3252
3253#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
3254#define WDT_CEN_bp  0  /* Change Enable bit position. */
3255
3256/* WDT.WINCTRL  bit masks and bit positions */
3257#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
3258#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
3259#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
3260#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
3261#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
3262#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
3263#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
3264#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
3265#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
3266#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
3267
3268#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
3269#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
3270
3271#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
3272#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
3273
3274/* WDT.STATUS  bit masks and bit positions */
3275#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
3276#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
3277
3278/* MCU - MCU Control */
3279/* MCU.ANAINIT  bit masks and bit positions */
3280#define MCU_STARTUPDLYA_gm  0x03  /* Analog startup delay Port A group mask. */
3281#define MCU_STARTUPDLYA_gp  0  /* Analog startup delay Port A group position. */
3282#define MCU_STARTUPDLYA0_bm  (1<<0)  /* Analog startup delay Port A bit 0 mask. */
3283#define MCU_STARTUPDLYA0_bp  0  /* Analog startup delay Port A bit 0 position. */
3284#define MCU_STARTUPDLYA1_bm  (1<<1)  /* Analog startup delay Port A bit 1 mask. */
3285#define MCU_STARTUPDLYA1_bp  1  /* Analog startup delay Port A bit 1 position. */
3286
3287/* MCU.EVSYSLOCK  bit masks and bit positions */
3288#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
3289#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
3290
3291/* MCU.AWEXLOCK  bit masks and bit positions */
3292#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
3293#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
3294
3295/* PMIC - Programmable Multi-level Interrupt Controller */
3296/* PMIC.STATUS  bit masks and bit positions */
3297#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
3298#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
3299
3300#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
3301#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
3302
3303#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
3304#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
3305
3306#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
3307#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
3308
3309/* PMIC.INTPRI  bit masks and bit positions */
3310#define PMIC_INTPRI_gm  0xFF  /* Interrupt Priority group mask. */
3311#define PMIC_INTPRI_gp  0  /* Interrupt Priority group position. */
3312#define PMIC_INTPRI0_bm  (1<<0)  /* Interrupt Priority bit 0 mask. */
3313#define PMIC_INTPRI0_bp  0  /* Interrupt Priority bit 0 position. */
3314#define PMIC_INTPRI1_bm  (1<<1)  /* Interrupt Priority bit 1 mask. */
3315#define PMIC_INTPRI1_bp  1  /* Interrupt Priority bit 1 position. */
3316#define PMIC_INTPRI2_bm  (1<<2)  /* Interrupt Priority bit 2 mask. */
3317#define PMIC_INTPRI2_bp  2  /* Interrupt Priority bit 2 position. */
3318#define PMIC_INTPRI3_bm  (1<<3)  /* Interrupt Priority bit 3 mask. */
3319#define PMIC_INTPRI3_bp  3  /* Interrupt Priority bit 3 position. */
3320#define PMIC_INTPRI4_bm  (1<<4)  /* Interrupt Priority bit 4 mask. */
3321#define PMIC_INTPRI4_bp  4  /* Interrupt Priority bit 4 position. */
3322#define PMIC_INTPRI5_bm  (1<<5)  /* Interrupt Priority bit 5 mask. */
3323#define PMIC_INTPRI5_bp  5  /* Interrupt Priority bit 5 position. */
3324#define PMIC_INTPRI6_bm  (1<<6)  /* Interrupt Priority bit 6 mask. */
3325#define PMIC_INTPRI6_bp  6  /* Interrupt Priority bit 6 position. */
3326#define PMIC_INTPRI7_bm  (1<<7)  /* Interrupt Priority bit 7 mask. */
3327#define PMIC_INTPRI7_bp  7  /* Interrupt Priority bit 7 position. */
3328
3329/* PMIC.CTRL  bit masks and bit positions */
3330#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
3331#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
3332
3333#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
3334#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
3335
3336#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
3337#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
3338
3339#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
3340#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
3341
3342#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
3343#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
3344
3345/* PORTCFG - Port Configuration */
3346/* PORTCFG.VPCTRLA  bit masks and bit positions */
3347#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
3348#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
3349#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
3350#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
3351#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
3352#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
3353#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
3354#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
3355#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
3356#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
3357
3358#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
3359#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
3360#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
3361#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
3362#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
3363#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
3364#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
3365#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
3366#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
3367#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
3368
3369/* PORTCFG.VPCTRLB  bit masks and bit positions */
3370#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
3371#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
3372#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
3373#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
3374#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
3375#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
3376#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
3377#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
3378#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
3379#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
3380
3381#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
3382#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
3383#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
3384#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
3385#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
3386#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
3387#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
3388#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
3389#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
3390#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
3391
3392/* PORTCFG.CLKEVOUT  bit masks and bit positions */
3393#define PORTCFG_CLKOUT_gm  0x03  /* Peripheral Clock Output Port group mask. */
3394#define PORTCFG_CLKOUT_gp  0  /* Peripheral Clock Output Port group position. */
3395#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Peripheral Clock Output Port bit 0 mask. */
3396#define PORTCFG_CLKOUT0_bp  0  /* Peripheral Clock Output Port bit 0 position. */
3397#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Peripheral Clock Output Port bit 1 mask. */
3398#define PORTCFG_CLKOUT1_bp  1  /* Peripheral Clock Output Port bit 1 position. */
3399
3400#define PORTCFG_CLKOUTSEL_gm  0x0C  /* Peripheral Clock Output Select group mask. */
3401#define PORTCFG_CLKOUTSEL_gp  2  /* Peripheral Clock Output Select group position. */
3402#define PORTCFG_CLKOUTSEL0_bm  (1<<2)  /* Peripheral Clock Output Select bit 0 mask. */
3403#define PORTCFG_CLKOUTSEL0_bp  2  /* Peripheral Clock Output Select bit 0 position. */
3404#define PORTCFG_CLKOUTSEL1_bm  (1<<3)  /* Peripheral Clock Output Select bit 1 mask. */
3405#define PORTCFG_CLKOUTSEL1_bp  3  /* Peripheral Clock Output Select bit 1 position. */
3406
3407#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
3408#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
3409#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
3410#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
3411#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
3412#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
3413
3414#define PORTCFG_RTCOUT_bm  0x40  /* RTC Clock Output bit mask. */
3415#define PORTCFG_RTCOUT_bp  6  /* RTC Clock Output bit position. */
3416
3417#define PORTCFG_CLKEVPIN_bm  0x80  /* Peripheral Clock and Event Output pin Select bit mask. */
3418#define PORTCFG_CLKEVPIN_bp  7  /* Peripheral Clock and Event Output pin Select bit position. */
3419
3420/* PORTCFG.EVOUTSEL  bit masks and bit positions */
3421#define PORTCFG_EVOUTSEL_gm  0x07  /* Event Output Select group mask. */
3422#define PORTCFG_EVOUTSEL_gp  0  /* Event Output Select group position. */
3423#define PORTCFG_EVOUTSEL0_bm  (1<<0)  /* Event Output Select bit 0 mask. */
3424#define PORTCFG_EVOUTSEL0_bp  0  /* Event Output Select bit 0 position. */
3425#define PORTCFG_EVOUTSEL1_bm  (1<<1)  /* Event Output Select bit 1 mask. */
3426#define PORTCFG_EVOUTSEL1_bp  1  /* Event Output Select bit 1 position. */
3427#define PORTCFG_EVOUTSEL2_bm  (1<<2)  /* Event Output Select bit 2 mask. */
3428#define PORTCFG_EVOUTSEL2_bp  2  /* Event Output Select bit 2 position. */
3429
3430/* CRC - Cyclic Redundancy Checker */
3431/* CRC.CTRL  bit masks and bit positions */
3432#define CRC_RESET_gm  0xC0  /* Reset group mask. */
3433#define CRC_RESET_gp  6  /* Reset group position. */
3434#define CRC_RESET0_bm  (1<<6)  /* Reset bit 0 mask. */
3435#define CRC_RESET0_bp  6  /* Reset bit 0 position. */
3436#define CRC_RESET1_bm  (1<<7)  /* Reset bit 1 mask. */
3437#define CRC_RESET1_bp  7  /* Reset bit 1 position. */
3438
3439#define CRC_CRC32_bm  0x20  /* CRC Mode bit mask. */
3440#define CRC_CRC32_bp  5  /* CRC Mode bit position. */
3441
3442#define CRC_SOURCE_gm  0x0F  /* Input Source group mask. */
3443#define CRC_SOURCE_gp  0  /* Input Source group position. */
3444#define CRC_SOURCE0_bm  (1<<0)  /* Input Source bit 0 mask. */
3445#define CRC_SOURCE0_bp  0  /* Input Source bit 0 position. */
3446#define CRC_SOURCE1_bm  (1<<1)  /* Input Source bit 1 mask. */
3447#define CRC_SOURCE1_bp  1  /* Input Source bit 1 position. */
3448#define CRC_SOURCE2_bm  (1<<2)  /* Input Source bit 2 mask. */
3449#define CRC_SOURCE2_bp  2  /* Input Source bit 2 position. */
3450#define CRC_SOURCE3_bm  (1<<3)  /* Input Source bit 3 mask. */
3451#define CRC_SOURCE3_bp  3  /* Input Source bit 3 position. */
3452
3453/* CRC.STATUS  bit masks and bit positions */
3454#define CRC_ZERO_bm  0x02  /* Zero detection bit mask. */
3455#define CRC_ZERO_bp  1  /* Zero detection bit position. */
3456
3457#define CRC_BUSY_bm  0x01  /* Busy bit mask. */
3458#define CRC_BUSY_bp  0  /* Busy bit position. */
3459
3460/* EVSYS - Event System */
3461/* EVSYS.CH0MUX  bit masks and bit positions */
3462#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
3463#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
3464#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
3465#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
3466#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
3467#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
3468#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
3469#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
3470#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
3471#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
3472#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
3473#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
3474#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
3475#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
3476#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
3477#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
3478#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
3479#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
3480
3481/* EVSYS.CH1MUX  bit masks and bit positions */
3482/* EVSYS_CHMUX  Predefined. */
3483/* EVSYS_CHMUX  Predefined. */
3484
3485/* EVSYS.CH2MUX  bit masks and bit positions */
3486/* EVSYS_CHMUX  Predefined. */
3487/* EVSYS_CHMUX  Predefined. */
3488
3489/* EVSYS.CH3MUX  bit masks and bit positions */
3490/* EVSYS_CHMUX  Predefined. */
3491/* EVSYS_CHMUX  Predefined. */
3492
3493/* EVSYS.CH0CTRL  bit masks and bit positions */
3494#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
3495#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
3496#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
3497#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
3498#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
3499#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
3500
3501#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
3502#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
3503
3504#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
3505#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
3506
3507#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
3508#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
3509#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
3510#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
3511#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
3512#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
3513#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
3514#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
3515
3516/* EVSYS.CH1CTRL  bit masks and bit positions */
3517/* EVSYS_DIGFILT  Predefined. */
3518/* EVSYS_DIGFILT  Predefined. */
3519
3520/* EVSYS.CH2CTRL  bit masks and bit positions */
3521/* EVSYS_DIGFILT  Predefined. */
3522/* EVSYS_DIGFILT  Predefined. */
3523
3524/* EVSYS.CH3CTRL  bit masks and bit positions */
3525/* EVSYS_DIGFILT  Predefined. */
3526/* EVSYS_DIGFILT  Predefined. */
3527
3528/* NVM - Non Volatile Memory Controller */
3529/* NVM.CMD  bit masks and bit positions */
3530#define NVM_CMD_gm  0x7F  /* Command group mask. */
3531#define NVM_CMD_gp  0  /* Command group position. */
3532#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
3533#define NVM_CMD0_bp  0  /* Command bit 0 position. */
3534#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
3535#define NVM_CMD1_bp  1  /* Command bit 1 position. */
3536#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
3537#define NVM_CMD2_bp  2  /* Command bit 2 position. */
3538#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
3539#define NVM_CMD3_bp  3  /* Command bit 3 position. */
3540#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
3541#define NVM_CMD4_bp  4  /* Command bit 4 position. */
3542#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
3543#define NVM_CMD5_bp  5  /* Command bit 5 position. */
3544#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
3545#define NVM_CMD6_bp  6  /* Command bit 6 position. */
3546
3547/* NVM.CTRLA  bit masks and bit positions */
3548#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
3549#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
3550
3551/* NVM.CTRLB  bit masks and bit positions */
3552#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
3553#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
3554
3555#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
3556#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
3557
3558#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
3559#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
3560
3561#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
3562#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
3563
3564/* NVM.INTCTRL  bit masks and bit positions */
3565#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
3566#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
3567#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
3568#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
3569#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
3570#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
3571
3572#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
3573#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
3574#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
3575#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
3576#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
3577#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
3578
3579/* NVM.STATUS  bit masks and bit positions */
3580#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
3581#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
3582
3583#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
3584#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
3585
3586#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
3587#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
3588
3589#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
3590#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
3591
3592/* NVM.LOCKBITS  bit masks and bit positions */
3593#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
3594#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
3595#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
3596#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
3597#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
3598#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
3599
3600#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
3601#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
3602#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
3603#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
3604#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
3605#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
3606
3607#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
3608#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
3609#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
3610#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
3611#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
3612#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
3613
3614#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
3615#define NVM_LB_gp  0  /* Lock Bits group position. */
3616#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
3617#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
3618#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
3619#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
3620
3621/* ADC - Analog/Digital Converter */
3622/* ADC_CH.CTRL  bit masks and bit positions */
3623#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
3624#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
3625
3626#define ADC_CH_GAIN_gm  0x1C  /* Gain Factor group mask. */
3627#define ADC_CH_GAIN_gp  2  /* Gain Factor group position. */
3628#define ADC_CH_GAIN0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
3629#define ADC_CH_GAIN0_bp  2  /* Gain Factor bit 0 position. */
3630#define ADC_CH_GAIN1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
3631#define ADC_CH_GAIN1_bp  3  /* Gain Factor bit 1 position. */
3632#define ADC_CH_GAIN2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
3633#define ADC_CH_GAIN2_bp  4  /* Gain Factor bit 2 position. */
3634
3635#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
3636#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
3637#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
3638#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
3639#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
3640#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
3641
3642/* ADC_CH.MUXCTRL  bit masks and bit positions */
3643#define ADC_CH_MUXPOS_gm  0x78  /* MUX selection on Positive ADC input group mask. */
3644#define ADC_CH_MUXPOS_gp  3  /* MUX selection on Positive ADC input group position. */
3645#define ADC_CH_MUXPOS0_bm  (1<<3)  /* MUX selection on Positive ADC input bit 0 mask. */
3646#define ADC_CH_MUXPOS0_bp  3  /* MUX selection on Positive ADC input bit 0 position. */
3647#define ADC_CH_MUXPOS1_bm  (1<<4)  /* MUX selection on Positive ADC input bit 1 mask. */
3648#define ADC_CH_MUXPOS1_bp  4  /* MUX selection on Positive ADC input bit 1 position. */
3649#define ADC_CH_MUXPOS2_bm  (1<<5)  /* MUX selection on Positive ADC input bit 2 mask. */
3650#define ADC_CH_MUXPOS2_bp  5  /* MUX selection on Positive ADC input bit 2 position. */
3651#define ADC_CH_MUXPOS3_bm  (1<<6)  /* MUX selection on Positive ADC input bit 3 mask. */
3652#define ADC_CH_MUXPOS3_bp  6  /* MUX selection on Positive ADC input bit 3 position. */
3653
3654#define ADC_CH_MUXINT_gm  0x78  /* MUX selection on Internal ADC input group mask. */
3655#define ADC_CH_MUXINT_gp  3  /* MUX selection on Internal ADC input group position. */
3656#define ADC_CH_MUXINT0_bm  (1<<3)  /* MUX selection on Internal ADC input bit 0 mask. */
3657#define ADC_CH_MUXINT0_bp  3  /* MUX selection on Internal ADC input bit 0 position. */
3658#define ADC_CH_MUXINT1_bm  (1<<4)  /* MUX selection on Internal ADC input bit 1 mask. */
3659#define ADC_CH_MUXINT1_bp  4  /* MUX selection on Internal ADC input bit 1 position. */
3660#define ADC_CH_MUXINT2_bm  (1<<5)  /* MUX selection on Internal ADC input bit 2 mask. */
3661#define ADC_CH_MUXINT2_bp  5  /* MUX selection on Internal ADC input bit 2 position. */
3662#define ADC_CH_MUXINT3_bm  (1<<6)  /* MUX selection on Internal ADC input bit 3 mask. */
3663#define ADC_CH_MUXINT3_bp  6  /* MUX selection on Internal ADC input bit 3 position. */
3664
3665#define ADC_CH_MUXNEG_gm  0x03  /* MUX selection on Negative ADC input group mask. */
3666#define ADC_CH_MUXNEG_gp  0  /* MUX selection on Negative ADC input group position. */
3667#define ADC_CH_MUXNEG0_bm  (1<<0)  /* MUX selection on Negative ADC input bit 0 mask. */
3668#define ADC_CH_MUXNEG0_bp  0  /* MUX selection on Negative ADC input bit 0 position. */
3669#define ADC_CH_MUXNEG1_bm  (1<<1)  /* MUX selection on Negative ADC input bit 1 mask. */
3670#define ADC_CH_MUXNEG1_bp  1  /* MUX selection on Negative ADC input bit 1 position. */
3671
3672/* ADC_CH.INTCTRL  bit masks and bit positions */
3673#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
3674#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
3675#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
3676#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
3677#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
3678#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
3679
3680#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
3681#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
3682#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
3683#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
3684#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
3685#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
3686
3687/* ADC_CH.INTFLAGS  bit masks and bit positions */
3688#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
3689#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
3690
3691/* ADC_CH.SCAN  bit masks and bit positions */
3692#define ADC_CH_OFFSET_gm  0xF0  /* Positive MUX setting offset group mask. */
3693#define ADC_CH_OFFSET_gp  4  /* Positive MUX setting offset group position. */
3694#define ADC_CH_OFFSET0_bm  (1<<4)  /* Positive MUX setting offset bit 0 mask. */
3695#define ADC_CH_OFFSET0_bp  4  /* Positive MUX setting offset bit 0 position. */
3696#define ADC_CH_OFFSET1_bm  (1<<5)  /* Positive MUX setting offset bit 1 mask. */
3697#define ADC_CH_OFFSET1_bp  5  /* Positive MUX setting offset bit 1 position. */
3698#define ADC_CH_OFFSET2_bm  (1<<6)  /* Positive MUX setting offset bit 2 mask. */
3699#define ADC_CH_OFFSET2_bp  6  /* Positive MUX setting offset bit 2 position. */
3700#define ADC_CH_OFFSET3_bm  (1<<7)  /* Positive MUX setting offset bit 3 mask. */
3701#define ADC_CH_OFFSET3_bp  7  /* Positive MUX setting offset bit 3 position. */
3702
3703#define ADC_CH_SCANNUM_gm  0x0F  /* Number of Channels included in scan group mask. */
3704#define ADC_CH_SCANNUM_gp  0  /* Number of Channels included in scan group position. */
3705#define ADC_CH_SCANNUM0_bm  (1<<0)  /* Number of Channels included in scan bit 0 mask. */
3706#define ADC_CH_SCANNUM0_bp  0  /* Number of Channels included in scan bit 0 position. */
3707#define ADC_CH_SCANNUM1_bm  (1<<1)  /* Number of Channels included in scan bit 1 mask. */
3708#define ADC_CH_SCANNUM1_bp  1  /* Number of Channels included in scan bit 1 position. */
3709#define ADC_CH_SCANNUM2_bm  (1<<2)  /* Number of Channels included in scan bit 2 mask. */
3710#define ADC_CH_SCANNUM2_bp  2  /* Number of Channels included in scan bit 2 position. */
3711#define ADC_CH_SCANNUM3_bm  (1<<3)  /* Number of Channels included in scan bit 3 mask. */
3712#define ADC_CH_SCANNUM3_bp  3  /* Number of Channels included in scan bit 3 position. */
3713
3714/* ADC.CTRLA  bit masks and bit positions */
3715#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
3716#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
3717
3718#define ADC_FLUSH_bm  0x02  /* ADC Flush bit mask. */
3719#define ADC_FLUSH_bp  1  /* ADC Flush bit position. */
3720
3721#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
3722#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
3723
3724/* ADC.CTRLB  bit masks and bit positions */
3725#define ADC_CURRLIMIT_gm  0x60  /* Current Limitation group mask. */
3726#define ADC_CURRLIMIT_gp  5  /* Current Limitation group position. */
3727#define ADC_CURRLIMIT0_bm  (1<<5)  /* Current Limitation bit 0 mask. */
3728#define ADC_CURRLIMIT0_bp  5  /* Current Limitation bit 0 position. */
3729#define ADC_CURRLIMIT1_bm  (1<<6)  /* Current Limitation bit 1 mask. */
3730#define ADC_CURRLIMIT1_bp  6  /* Current Limitation bit 1 position. */
3731
3732#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
3733#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
3734
3735#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
3736#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
3737
3738#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
3739#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
3740#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
3741#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
3742#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
3743#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
3744
3745/* ADC.REFCTRL  bit masks and bit positions */
3746#define ADC_REFSEL_gm  0x70  /* Reference Selection group mask. */
3747#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
3748#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
3749#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
3750#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
3751#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
3752#define ADC_REFSEL2_bm  (1<<6)  /* Reference Selection bit 2 mask. */
3753#define ADC_REFSEL2_bp  6  /* Reference Selection bit 2 position. */
3754
3755#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
3756#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
3757
3758#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
3759#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
3760
3761/* ADC.EVCTRL  bit masks and bit positions */
3762#define ADC_EVSEL_gm  0x18  /* Event Input Select group mask. */
3763#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
3764#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
3765#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
3766#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
3767#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
3768
3769#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
3770#define ADC_EVACT_gp  0  /* Event Action Select group position. */
3771#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
3772#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
3773#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
3774#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
3775#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
3776#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
3777
3778/* ADC.PRESCALER  bit masks and bit positions */
3779#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
3780#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
3781#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
3782#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
3783#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
3784#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
3785#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
3786#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
3787
3788/* ADC.INTFLAGS  bit masks and bit positions */
3789#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
3790#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
3791
3792/* AC - Analog Comparator */
3793/* AC.AC0CTRL  bit masks and bit positions */
3794#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
3795#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
3796#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
3797#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
3798#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
3799#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
3800
3801#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
3802#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
3803#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
3804#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
3805#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
3806#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
3807
3808#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
3809#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
3810#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
3811#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
3812#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
3813#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
3814
3815#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
3816#define AC_ENABLE_bp  0  /* Enable bit position. */
3817
3818/* AC.AC1CTRL  bit masks and bit positions */
3819/* AC_INTMODE  Predefined. */
3820/* AC_INTMODE  Predefined. */
3821
3822/* AC_INTLVL  Predefined. */
3823/* AC_INTLVL  Predefined. */
3824
3825/* AC_HYSMODE  Predefined. */
3826/* AC_HYSMODE  Predefined. */
3827
3828/* AC_ENABLE  Predefined. */
3829/* AC_ENABLE  Predefined. */
3830
3831/* AC.AC0MUXCTRL  bit masks and bit positions */
3832#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
3833#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
3834#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
3835#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
3836#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
3837#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
3838#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
3839#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
3840
3841#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
3842#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
3843#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
3844#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
3845#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
3846#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
3847#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
3848#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
3849
3850/* AC.AC1MUXCTRL  bit masks and bit positions */
3851/* AC_MUXPOS  Predefined. */
3852/* AC_MUXPOS  Predefined. */
3853
3854/* AC_MUXNEG  Predefined. */
3855/* AC_MUXNEG  Predefined. */
3856
3857/* AC.CTRLA  bit masks and bit positions */
3858#define AC_AC1OUT_bm  0x02  /* Analog Comparator 1 Output Enable bit mask. */
3859#define AC_AC1OUT_bp  1  /* Analog Comparator 1 Output Enable bit position. */
3860
3861#define AC_AC0OUT_bm  0x01  /* Analog Comparator 0 Output Enable bit mask. */
3862#define AC_AC0OUT_bp  0  /* Analog Comparator 0 Output Enable bit position. */
3863
3864/* AC.CTRLB  bit masks and bit positions */
3865#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
3866#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
3867#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
3868#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
3869#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
3870#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
3871#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
3872#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
3873#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
3874#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
3875#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
3876#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
3877#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
3878#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
3879
3880/* AC.WINCTRL  bit masks and bit positions */
3881#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
3882#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
3883
3884#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
3885#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
3886#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
3887#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
3888#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
3889#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
3890
3891#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
3892#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
3893#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
3894#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
3895#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
3896#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
3897
3898/* AC.STATUS  bit masks and bit positions */
3899#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
3900#define AC_WSTATE_gp  6  /* Window Mode State group position. */
3901#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
3902#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
3903#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
3904#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
3905
3906#define AC_AC1STATE_bm  0x20  /* Analog Comparator 1 State bit mask. */
3907#define AC_AC1STATE_bp  5  /* Analog Comparator 1 State bit position. */
3908
3909#define AC_AC0STATE_bm  0x10  /* Analog Comparator 0 State bit mask. */
3910#define AC_AC0STATE_bp  4  /* Analog Comparator 0 State bit position. */
3911
3912#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
3913#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
3914
3915#define AC_AC1IF_bm  0x02  /* Analog Comparator 1 Interrupt Flag bit mask. */
3916#define AC_AC1IF_bp  1  /* Analog Comparator 1 Interrupt Flag bit position. */
3917
3918#define AC_AC0IF_bm  0x01  /* Analog Comparator 0 Interrupt Flag bit mask. */
3919#define AC_AC0IF_bp  0  /* Analog Comparator 0 Interrupt Flag bit position. */
3920
3921/* RTC - Real-Time Counter */
3922/* RTC.CTRL  bit masks and bit positions */
3923#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
3924#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
3925#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
3926#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
3927#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
3928#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
3929#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
3930#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
3931
3932/* RTC.STATUS  bit masks and bit positions */
3933#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
3934#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
3935
3936/* RTC.INTCTRL  bit masks and bit positions */
3937#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
3938#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
3939#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
3940#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
3941#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
3942#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
3943
3944#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
3945#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
3946#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
3947#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
3948#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
3949#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
3950
3951/* RTC.INTFLAGS  bit masks and bit positions */
3952#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
3953#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
3954
3955#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
3956#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
3957
3958/* TWI - Two-Wire Interface */
3959/* TWI_MASTER.CTRLA  bit masks and bit positions */
3960#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
3961#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
3962#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
3963#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
3964#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
3965#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
3966
3967#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
3968#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
3969
3970#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
3971#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
3972
3973#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
3974#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
3975
3976/* TWI_MASTER.CTRLB  bit masks and bit positions */
3977#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
3978#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
3979#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
3980#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
3981#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
3982#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
3983
3984#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
3985#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
3986
3987#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
3988#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
3989
3990/* TWI_MASTER.CTRLC  bit masks and bit positions */
3991#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
3992#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
3993
3994#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
3995#define TWI_MASTER_CMD_gp  0  /* Command group position. */
3996#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
3997#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
3998#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
3999#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
4000
4001/* TWI_MASTER.STATUS  bit masks and bit positions */
4002#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
4003#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
4004
4005#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
4006#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
4007
4008#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
4009#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
4010
4011#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
4012#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
4013
4014#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
4015#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
4016
4017#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
4018#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
4019
4020#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
4021#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
4022#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
4023#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
4024#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
4025#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
4026
4027/* TWI_SLAVE.CTRLA  bit masks and bit positions */
4028#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
4029#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
4030#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
4031#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
4032#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
4033#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
4034
4035#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
4036#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
4037
4038#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
4039#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
4040
4041#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
4042#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
4043
4044#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
4045#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
4046
4047#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
4048#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
4049
4050#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
4051#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
4052
4053/* TWI_SLAVE.CTRLB  bit masks and bit positions */
4054#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
4055#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
4056
4057#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
4058#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
4059#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
4060#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
4061#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
4062#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
4063
4064/* TWI_SLAVE.STATUS  bit masks and bit positions */
4065#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
4066#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
4067
4068#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
4069#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
4070
4071#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
4072#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
4073
4074#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
4075#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
4076
4077#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
4078#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
4079
4080#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
4081#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
4082
4083#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
4084#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
4085
4086#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
4087#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
4088
4089/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
4090#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
4091#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
4092#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
4093#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
4094#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
4095#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
4096#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
4097#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
4098#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
4099#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
4100#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
4101#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
4102#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
4103#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
4104#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
4105#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
4106
4107#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
4108#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
4109
4110/* TWI.CTRL  bit masks and bit positions */
4111#define TWI_SDAHOLD_gm  0x06  /* SDA Hold Time Enable group mask. */
4112#define TWI_SDAHOLD_gp  1  /* SDA Hold Time Enable group position. */
4113#define TWI_SDAHOLD0_bm  (1<<1)  /* SDA Hold Time Enable bit 0 mask. */
4114#define TWI_SDAHOLD0_bp  1  /* SDA Hold Time Enable bit 0 position. */
4115#define TWI_SDAHOLD1_bm  (1<<2)  /* SDA Hold Time Enable bit 1 mask. */
4116#define TWI_SDAHOLD1_bp  2  /* SDA Hold Time Enable bit 1 position. */
4117
4118#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
4119#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
4120
4121/* PORT - I/O Port Configuration */
4122/* PORT.INTCTRL  bit masks and bit positions */
4123#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
4124#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
4125#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
4126#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
4127#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
4128#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
4129
4130#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
4131#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
4132#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
4133#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
4134#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
4135#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
4136
4137/* PORT.INTFLAGS  bit masks and bit positions */
4138#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
4139#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
4140
4141#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
4142#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
4143
4144/* PORT.REMAP  bit masks and bit positions */
4145#define PORT_SPI_bm  0x20  /* SPI bit mask. */
4146#define PORT_SPI_bp  5  /* SPI bit position. */
4147
4148#define PORT_USART0_bm  0x10  /* USART0 bit mask. */
4149#define PORT_USART0_bp  4  /* USART0 bit position. */
4150
4151#define PORT_TC0D_bm  0x08  /* Timer/Counter 0 Output Compare D bit mask. */
4152#define PORT_TC0D_bp  3  /* Timer/Counter 0 Output Compare D bit position. */
4153
4154#define PORT_TC0C_bm  0x04  /* Timer/Counter 0 Output Compare C bit mask. */
4155#define PORT_TC0C_bp  2  /* Timer/Counter 0 Output Compare C bit position. */
4156
4157#define PORT_TC0B_bm  0x02  /* Timer/Counter 0 Output Compare B bit mask. */
4158#define PORT_TC0B_bp  1  /* Timer/Counter 0 Output Compare B bit position. */
4159
4160#define PORT_TC0A_bm  0x01  /* Timer/Counter 0 Output Compare A bit mask. */
4161#define PORT_TC0A_bp  0  /* Timer/Counter 0 Output Compare A bit position. */
4162
4163/* PORT.PIN0CTRL  bit masks and bit positions */
4164#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
4165#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
4166
4167#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
4168#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
4169
4170#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
4171#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
4172#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
4173#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
4174#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
4175#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
4176#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
4177#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
4178
4179#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
4180#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
4181#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
4182#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
4183#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
4184#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
4185#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
4186#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
4187
4188/* PORT.PIN1CTRL  bit masks and bit positions */
4189/* PORT_SRLEN  Predefined. */
4190/* PORT_SRLEN  Predefined. */
4191
4192/* PORT_INVEN  Predefined. */
4193/* PORT_INVEN  Predefined. */
4194
4195/* PORT_OPC  Predefined. */
4196/* PORT_OPC  Predefined. */
4197
4198/* PORT_ISC  Predefined. */
4199/* PORT_ISC  Predefined. */
4200
4201/* PORT.PIN2CTRL  bit masks and bit positions */
4202/* PORT_SRLEN  Predefined. */
4203/* PORT_SRLEN  Predefined. */
4204
4205/* PORT_INVEN  Predefined. */
4206/* PORT_INVEN  Predefined. */
4207
4208/* PORT_OPC  Predefined. */
4209/* PORT_OPC  Predefined. */
4210
4211/* PORT_ISC  Predefined. */
4212/* PORT_ISC  Predefined. */
4213
4214/* PORT.PIN3CTRL  bit masks and bit positions */
4215/* PORT_SRLEN  Predefined. */
4216/* PORT_SRLEN  Predefined. */
4217
4218/* PORT_INVEN  Predefined. */
4219/* PORT_INVEN  Predefined. */
4220
4221/* PORT_OPC  Predefined. */
4222/* PORT_OPC  Predefined. */
4223
4224/* PORT_ISC  Predefined. */
4225/* PORT_ISC  Predefined. */
4226
4227/* PORT.PIN4CTRL  bit masks and bit positions */
4228/* PORT_SRLEN  Predefined. */
4229/* PORT_SRLEN  Predefined. */
4230
4231/* PORT_INVEN  Predefined. */
4232/* PORT_INVEN  Predefined. */
4233
4234/* PORT_OPC  Predefined. */
4235/* PORT_OPC  Predefined. */
4236
4237/* PORT_ISC  Predefined. */
4238/* PORT_ISC  Predefined. */
4239
4240/* PORT.PIN5CTRL  bit masks and bit positions */
4241/* PORT_SRLEN  Predefined. */
4242/* PORT_SRLEN  Predefined. */
4243
4244/* PORT_INVEN  Predefined. */
4245/* PORT_INVEN  Predefined. */
4246
4247/* PORT_OPC  Predefined. */
4248/* PORT_OPC  Predefined. */
4249
4250/* PORT_ISC  Predefined. */
4251/* PORT_ISC  Predefined. */
4252
4253/* PORT.PIN6CTRL  bit masks and bit positions */
4254/* PORT_SRLEN  Predefined. */
4255/* PORT_SRLEN  Predefined. */
4256
4257/* PORT_INVEN  Predefined. */
4258/* PORT_INVEN  Predefined. */
4259
4260/* PORT_OPC  Predefined. */
4261/* PORT_OPC  Predefined. */
4262
4263/* PORT_ISC  Predefined. */
4264/* PORT_ISC  Predefined. */
4265
4266/* PORT.PIN7CTRL  bit masks and bit positions */
4267/* PORT_SRLEN  Predefined. */
4268/* PORT_SRLEN  Predefined. */
4269
4270/* PORT_INVEN  Predefined. */
4271/* PORT_INVEN  Predefined. */
4272
4273/* PORT_OPC  Predefined. */
4274/* PORT_OPC  Predefined. */
4275
4276/* PORT_ISC  Predefined. */
4277/* PORT_ISC  Predefined. */
4278
4279/* TC - 16-bit Timer/Counter With PWM */
4280/* TC0.CTRLA  bit masks and bit positions */
4281#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4282#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
4283#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4284#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4285#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4286#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4287#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4288#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4289#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4290#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4291
4292/* TC0.CTRLB  bit masks and bit positions */
4293#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
4294#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
4295
4296#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
4297#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
4298
4299#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
4300#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
4301
4302#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
4303#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
4304
4305#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
4306#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
4307#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
4308#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
4309#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
4310#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
4311#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
4312#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
4313
4314/* TC0.CTRLC  bit masks and bit positions */
4315#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
4316#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
4317
4318#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
4319#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
4320
4321#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
4322#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
4323
4324#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
4325#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
4326
4327/* TC0.CTRLD  bit masks and bit positions */
4328#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
4329#define TC0_EVACT_gp  5  /* Event Action group position. */
4330#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
4331#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
4332#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
4333#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
4334#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
4335#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
4336
4337#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
4338#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
4339
4340#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
4341#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
4342#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
4343#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
4344#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
4345#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
4346#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
4347#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
4348#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
4349#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
4350
4351/* TC0.CTRLE  bit masks and bit positions */
4352#define TC0_BYTEM_gm  0x03  /* Byte Mode group mask. */
4353#define TC0_BYTEM_gp  0  /* Byte Mode group position. */
4354#define TC0_BYTEM0_bm  (1<<0)  /* Byte Mode bit 0 mask. */
4355#define TC0_BYTEM0_bp  0  /* Byte Mode bit 0 position. */
4356#define TC0_BYTEM1_bm  (1<<1)  /* Byte Mode bit 1 mask. */
4357#define TC0_BYTEM1_bp  1  /* Byte Mode bit 1 position. */
4358
4359/* TC0.INTCTRLA  bit masks and bit positions */
4360#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
4361#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
4362#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
4363#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
4364#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
4365#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
4366
4367#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
4368#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
4369#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
4370#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
4371#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
4372#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
4373
4374/* TC0.INTCTRLB  bit masks and bit positions */
4375#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
4376#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
4377#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
4378#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
4379#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
4380#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
4381
4382#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
4383#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
4384#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
4385#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
4386#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
4387#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
4388
4389#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
4390#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
4391#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
4392#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
4393#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
4394#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
4395
4396#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
4397#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
4398#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
4399#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
4400#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
4401#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
4402
4403/* TC0.CTRLFCLR  bit masks and bit positions */
4404#define TC0_CMD_gm  0x0C  /* Command group mask. */
4405#define TC0_CMD_gp  2  /* Command group position. */
4406#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
4407#define TC0_CMD0_bp  2  /* Command bit 0 position. */
4408#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
4409#define TC0_CMD1_bp  3  /* Command bit 1 position. */
4410
4411#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
4412#define TC0_LUPD_bp  1  /* Lock Update bit position. */
4413
4414#define TC0_DIR_bm  0x01  /* Direction bit mask. */
4415#define TC0_DIR_bp  0  /* Direction bit position. */
4416
4417/* TC0.CTRLFSET  bit masks and bit positions */
4418/* TC0_CMD  Predefined. */
4419/* TC0_CMD  Predefined. */
4420
4421/* TC0_LUPD  Predefined. */
4422/* TC0_LUPD  Predefined. */
4423
4424/* TC0_DIR  Predefined. */
4425/* TC0_DIR  Predefined. */
4426
4427/* TC0.CTRLGCLR  bit masks and bit positions */
4428#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
4429#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
4430
4431#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
4432#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
4433
4434#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
4435#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
4436
4437#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
4438#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
4439
4440#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
4441#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
4442
4443/* TC0.CTRLGSET  bit masks and bit positions */
4444/* TC0_CCDBV  Predefined. */
4445/* TC0_CCDBV  Predefined. */
4446
4447/* TC0_CCCBV  Predefined. */
4448/* TC0_CCCBV  Predefined. */
4449
4450/* TC0_CCBBV  Predefined. */
4451/* TC0_CCBBV  Predefined. */
4452
4453/* TC0_CCABV  Predefined. */
4454/* TC0_CCABV  Predefined. */
4455
4456/* TC0_PERBV  Predefined. */
4457/* TC0_PERBV  Predefined. */
4458
4459/* TC0.INTFLAGS  bit masks and bit positions */
4460#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
4461#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
4462
4463#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
4464#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
4465
4466#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
4467#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
4468
4469#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
4470#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
4471
4472#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
4473#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
4474
4475#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
4476#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
4477
4478/* TC1.CTRLA  bit masks and bit positions */
4479#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4480#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
4481#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4482#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4483#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4484#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4485#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4486#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4487#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4488#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4489
4490/* TC1.CTRLB  bit masks and bit positions */
4491#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
4492#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
4493
4494#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
4495#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
4496
4497#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
4498#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
4499#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
4500#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
4501#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
4502#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
4503#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
4504#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
4505
4506/* TC1.CTRLC  bit masks and bit positions */
4507#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
4508#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
4509
4510#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
4511#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
4512
4513/* TC1.CTRLD  bit masks and bit positions */
4514#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
4515#define TC1_EVACT_gp  5  /* Event Action group position. */
4516#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
4517#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
4518#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
4519#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
4520#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
4521#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
4522
4523#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
4524#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
4525
4526#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
4527#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
4528#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
4529#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
4530#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
4531#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
4532#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
4533#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
4534#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
4535#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
4536
4537/* TC1.CTRLE  bit masks and bit positions */
4538#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
4539#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
4540
4541/* TC1.INTCTRLA  bit masks and bit positions */
4542#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
4543#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
4544#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
4545#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
4546#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
4547#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
4548
4549#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
4550#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
4551#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
4552#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
4553#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
4554#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
4555
4556/* TC1.INTCTRLB  bit masks and bit positions */
4557#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
4558#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
4559#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
4560#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
4561#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
4562#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
4563
4564#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
4565#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
4566#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
4567#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
4568#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
4569#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
4570
4571/* TC1.CTRLFCLR  bit masks and bit positions */
4572#define TC1_CMD_gm  0x0C  /* Command group mask. */
4573#define TC1_CMD_gp  2  /* Command group position. */
4574#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
4575#define TC1_CMD0_bp  2  /* Command bit 0 position. */
4576#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
4577#define TC1_CMD1_bp  3  /* Command bit 1 position. */
4578
4579#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
4580#define TC1_LUPD_bp  1  /* Lock Update bit position. */
4581
4582#define TC1_DIR_bm  0x01  /* Direction bit mask. */
4583#define TC1_DIR_bp  0  /* Direction bit position. */
4584
4585/* TC1.CTRLFSET  bit masks and bit positions */
4586/* TC1_CMD  Predefined. */
4587/* TC1_CMD  Predefined. */
4588
4589/* TC1_LUPD  Predefined. */
4590/* TC1_LUPD  Predefined. */
4591
4592/* TC1_DIR  Predefined. */
4593/* TC1_DIR  Predefined. */
4594
4595/* TC1.CTRLGCLR  bit masks and bit positions */
4596#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
4597#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
4598
4599#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
4600#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
4601
4602#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
4603#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
4604
4605/* TC1.CTRLGSET  bit masks and bit positions */
4606/* TC1_CCBBV  Predefined. */
4607/* TC1_CCBBV  Predefined. */
4608
4609/* TC1_CCABV  Predefined. */
4610/* TC1_CCABV  Predefined. */
4611
4612/* TC1_PERBV  Predefined. */
4613/* TC1_PERBV  Predefined. */
4614
4615/* TC1.INTFLAGS  bit masks and bit positions */
4616#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
4617#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
4618
4619#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
4620#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
4621
4622#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
4623#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
4624
4625#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
4626#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
4627
4628/* TC2 - 16-bit Timer/Counter type 2 */
4629/* TC2.CTRLA  bit masks and bit positions */
4630#define TC2_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4631#define TC2_CLKSEL_gp  0  /* Clock Selection group position. */
4632#define TC2_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4633#define TC2_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4634#define TC2_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4635#define TC2_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4636#define TC2_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4637#define TC2_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4638#define TC2_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4639#define TC2_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4640
4641/* TC2.CTRLB  bit masks and bit positions */
4642#define TC2_HCMPDEN_bm  0x80  /* High Byte Compare D Enable bit mask. */
4643#define TC2_HCMPDEN_bp  7  /* High Byte Compare D Enable bit position. */
4644
4645#define TC2_HCMPCEN_bm  0x40  /* High Byte Compare C Enable bit mask. */
4646#define TC2_HCMPCEN_bp  6  /* High Byte Compare C Enable bit position. */
4647
4648#define TC2_HCMPBEN_bm  0x20  /* High Byte Compare B Enable bit mask. */
4649#define TC2_HCMPBEN_bp  5  /* High Byte Compare B Enable bit position. */
4650
4651#define TC2_HCMPAEN_bm  0x10  /* High Byte Compare A Enable bit mask. */
4652#define TC2_HCMPAEN_bp  4  /* High Byte Compare A Enable bit position. */
4653
4654#define TC2_LCMPDEN_bm  0x08  /* Low Byte Compare D Enable bit mask. */
4655#define TC2_LCMPDEN_bp  3  /* Low Byte Compare D Enable bit position. */
4656
4657#define TC2_LCMPCEN_bm  0x04  /* Low Byte Compare C Enable bit mask. */
4658#define TC2_LCMPCEN_bp  2  /* Low Byte Compare C Enable bit position. */
4659
4660#define TC2_LCMPBEN_bm  0x02  /* Low Byte Compare B Enable bit mask. */
4661#define TC2_LCMPBEN_bp  1  /* Low Byte Compare B Enable bit position. */
4662
4663#define TC2_LCMPAEN_bm  0x01  /* Low Byte Compare A Enable bit mask. */
4664#define TC2_LCMPAEN_bp  0  /* Low Byte Compare A Enable bit position. */
4665
4666/* TC2.CTRLC  bit masks and bit positions */
4667#define TC2_HCMPD_bm  0x80  /* High Byte Compare D Output Value bit mask. */
4668#define TC2_HCMPD_bp  7  /* High Byte Compare D Output Value bit position. */
4669
4670#define TC2_HCMPC_bm  0x40  /* High Byte Compare C Output Value bit mask. */
4671#define TC2_HCMPC_bp  6  /* High Byte Compare C Output Value bit position. */
4672
4673#define TC2_HCMPB_bm  0x20  /* High Byte Compare B Output Value bit mask. */
4674#define TC2_HCMPB_bp  5  /* High Byte Compare B Output Value bit position. */
4675
4676#define TC2_HCMPA_bm  0x10  /* High Byte Compare A Output Value bit mask. */
4677#define TC2_HCMPA_bp  4  /* High Byte Compare A Output Value bit position. */
4678
4679#define TC2_LCMPD_bm  0x08  /* Low Byte Compare D Output Value bit mask. */
4680#define TC2_LCMPD_bp  3  /* Low Byte Compare D Output Value bit position. */
4681
4682#define TC2_LCMPC_bm  0x04  /* Low Byte Compare C Output Value bit mask. */
4683#define TC2_LCMPC_bp  2  /* Low Byte Compare C Output Value bit position. */
4684
4685#define TC2_LCMPB_bm  0x02  /* Low Byte Compare B Output Value bit mask. */
4686#define TC2_LCMPB_bp  1  /* Low Byte Compare B Output Value bit position. */
4687
4688#define TC2_LCMPA_bm  0x01  /* Low Byte Compare A Output Value bit mask. */
4689#define TC2_LCMPA_bp  0  /* Low Byte Compare A Output Value bit position. */
4690
4691/* TC2.CTRLE  bit masks and bit positions */
4692#define TC2_BYTEM_gm  0x03  /* Byte Mode group mask. */
4693#define TC2_BYTEM_gp  0  /* Byte Mode group position. */
4694#define TC2_BYTEM0_bm  (1<<0)  /* Byte Mode bit 0 mask. */
4695#define TC2_BYTEM0_bp  0  /* Byte Mode bit 0 position. */
4696#define TC2_BYTEM1_bm  (1<<1)  /* Byte Mode bit 1 mask. */
4697#define TC2_BYTEM1_bp  1  /* Byte Mode bit 1 position. */
4698
4699/* TC2.INTCTRLA  bit masks and bit positions */
4700#define TC2_HUNFINTLVL_gm  0x0C  /* High Byte Underflow Interrupt Level group mask. */
4701#define TC2_HUNFINTLVL_gp  2  /* High Byte Underflow Interrupt Level group position. */
4702#define TC2_HUNFINTLVL0_bm  (1<<2)  /* High Byte Underflow Interrupt Level bit 0 mask. */
4703#define TC2_HUNFINTLVL0_bp  2  /* High Byte Underflow Interrupt Level bit 0 position. */
4704#define TC2_HUNFINTLVL1_bm  (1<<3)  /* High Byte Underflow Interrupt Level bit 1 mask. */
4705#define TC2_HUNFINTLVL1_bp  3  /* High Byte Underflow Interrupt Level bit 1 position. */
4706
4707#define TC2_LUNFINTLVL_gm  0x03  /* Low Byte Underflow interrupt level group mask. */
4708#define TC2_LUNFINTLVL_gp  0  /* Low Byte Underflow interrupt level group position. */
4709#define TC2_LUNFINTLVL0_bm  (1<<0)  /* Low Byte Underflow interrupt level bit 0 mask. */
4710#define TC2_LUNFINTLVL0_bp  0  /* Low Byte Underflow interrupt level bit 0 position. */
4711#define TC2_LUNFINTLVL1_bm  (1<<1)  /* Low Byte Underflow interrupt level bit 1 mask. */
4712#define TC2_LUNFINTLVL1_bp  1  /* Low Byte Underflow interrupt level bit 1 position. */
4713
4714/* TC2.INTCTRLB  bit masks and bit positions */
4715#define TC2_LCMPDINTLVL_gm  0xC0  /* Low Byte Compare D Interrupt Level group mask. */
4716#define TC2_LCMPDINTLVL_gp  6  /* Low Byte Compare D Interrupt Level group position. */
4717#define TC2_LCMPDINTLVL0_bm  (1<<6)  /* Low Byte Compare D Interrupt Level bit 0 mask. */
4718#define TC2_LCMPDINTLVL0_bp  6  /* Low Byte Compare D Interrupt Level bit 0 position. */
4719#define TC2_LCMPDINTLVL1_bm  (1<<7)  /* Low Byte Compare D Interrupt Level bit 1 mask. */
4720#define TC2_LCMPDINTLVL1_bp  7  /* Low Byte Compare D Interrupt Level bit 1 position. */
4721
4722#define TC2_LCMPCINTLVL_gm  0x30  /* Low Byte Compare C Interrupt Level group mask. */
4723#define TC2_LCMPCINTLVL_gp  4  /* Low Byte Compare C Interrupt Level group position. */
4724#define TC2_LCMPCINTLVL0_bm  (1<<4)  /* Low Byte Compare C Interrupt Level bit 0 mask. */
4725#define TC2_LCMPCINTLVL0_bp  4  /* Low Byte Compare C Interrupt Level bit 0 position. */
4726#define TC2_LCMPCINTLVL1_bm  (1<<5)  /* Low Byte Compare C Interrupt Level bit 1 mask. */
4727#define TC2_LCMPCINTLVL1_bp  5  /* Low Byte Compare C Interrupt Level bit 1 position. */
4728
4729#define TC2_LCMPBINTLVL_gm  0x0C  /* Low Byte Compare B Interrupt Level group mask. */
4730#define TC2_LCMPBINTLVL_gp  2  /* Low Byte Compare B Interrupt Level group position. */
4731#define TC2_LCMPBINTLVL0_bm  (1<<2)  /* Low Byte Compare B Interrupt Level bit 0 mask. */
4732#define TC2_LCMPBINTLVL0_bp  2  /* Low Byte Compare B Interrupt Level bit 0 position. */
4733#define TC2_LCMPBINTLVL1_bm  (1<<3)  /* Low Byte Compare B Interrupt Level bit 1 mask. */
4734#define TC2_LCMPBINTLVL1_bp  3  /* Low Byte Compare B Interrupt Level bit 1 position. */
4735
4736#define TC2_LCMPAINTLVL_gm  0x03  /* Low Byte Compare A Interrupt Level group mask. */
4737#define TC2_LCMPAINTLVL_gp  0  /* Low Byte Compare A Interrupt Level group position. */
4738#define TC2_LCMPAINTLVL0_bm  (1<<0)  /* Low Byte Compare A Interrupt Level bit 0 mask. */
4739#define TC2_LCMPAINTLVL0_bp  0  /* Low Byte Compare A Interrupt Level bit 0 position. */
4740#define TC2_LCMPAINTLVL1_bm  (1<<1)  /* Low Byte Compare A Interrupt Level bit 1 mask. */
4741#define TC2_LCMPAINTLVL1_bp  1  /* Low Byte Compare A Interrupt Level bit 1 position. */
4742
4743/* TC2.CTRLF  bit masks and bit positions */
4744#define TC2_CMD_gm  0x0C  /* Command group mask. */
4745#define TC2_CMD_gp  2  /* Command group position. */
4746#define TC2_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
4747#define TC2_CMD0_bp  2  /* Command bit 0 position. */
4748#define TC2_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
4749#define TC2_CMD1_bp  3  /* Command bit 1 position. */
4750
4751#define TC2_CMDEN_gm  0x03  /* Command Enable group mask. */
4752#define TC2_CMDEN_gp  0  /* Command Enable group position. */
4753#define TC2_CMDEN0_bm  (1<<0)  /* Command Enable bit 0 mask. */
4754#define TC2_CMDEN0_bp  0  /* Command Enable bit 0 position. */
4755#define TC2_CMDEN1_bm  (1<<1)  /* Command Enable bit 1 mask. */
4756#define TC2_CMDEN1_bp  1  /* Command Enable bit 1 position. */
4757
4758/* TC2.INTFLAGS  bit masks and bit positions */
4759#define TC2_LCMPDIF_bm  0x80  /* Low Byte Compare D Interrupt Flag bit mask. */
4760#define TC2_LCMPDIF_bp  7  /* Low Byte Compare D Interrupt Flag bit position. */
4761
4762#define TC2_LCMPCIF_bm  0x40  /* Low Byte Compare C Interrupt Flag bit mask. */
4763#define TC2_LCMPCIF_bp  6  /* Low Byte Compare C Interrupt Flag bit position. */
4764
4765#define TC2_LCMPBIF_bm  0x20  /* Low Byte Compare B Interrupt Flag bit mask. */
4766#define TC2_LCMPBIF_bp  5  /* Low Byte Compare B Interrupt Flag bit position. */
4767
4768#define TC2_LCMPAIF_bm  0x10  /* Low Byte Compare A Interrupt Flag bit mask. */
4769#define TC2_LCMPAIF_bp  4  /* Low Byte Compare A Interrupt Flag bit position. */
4770
4771#define TC2_HUNFIF_bm  0x02  /* High Byte Underflow Interrupt Flag bit mask. */
4772#define TC2_HUNFIF_bp  1  /* High Byte Underflow Interrupt Flag bit position. */
4773
4774#define TC2_LUNFIF_bm  0x01  /* Low Byte Underflow Interrupt Flag bit mask. */
4775#define TC2_LUNFIF_bp  0  /* Low Byte Underflow Interrupt Flag bit position. */
4776
4777/* AWEX - Timer/Counter Advanced Waveform Extension */
4778/* AWEX.CTRL  bit masks and bit positions */
4779#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
4780#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
4781
4782#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
4783#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
4784
4785#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
4786#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
4787
4788#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
4789#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
4790
4791#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
4792#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
4793
4794#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
4795#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
4796
4797/* AWEX.FDCTRL  bit masks and bit positions */
4798#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
4799#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
4800
4801#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
4802#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
4803
4804#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
4805#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
4806#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
4807#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
4808#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
4809#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
4810
4811/* AWEX.STATUS  bit masks and bit positions */
4812#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
4813#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
4814
4815#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
4816#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
4817
4818#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
4819#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
4820
4821/* AWEX.STATUSSET  bit masks and bit positions */
4822/* AWEX_FDF  Predefined. */
4823/* AWEX_FDF  Predefined. */
4824
4825/* AWEX_DTHSBUFV  Predefined. */
4826/* AWEX_DTHSBUFV  Predefined. */
4827
4828/* AWEX_DTLSBUFV  Predefined. */
4829/* AWEX_DTLSBUFV  Predefined. */
4830
4831/* HIRES - Timer/Counter High-Resolution Extension */
4832/* HIRES.CTRLA  bit masks and bit positions */
4833#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
4834#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
4835#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
4836#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
4837#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
4838#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
4839
4840/* USART - Universal Asynchronous Receiver-Transmitter */
4841/* USART.STATUS  bit masks and bit positions */
4842#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
4843#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
4844
4845#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
4846#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
4847
4848#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
4849#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
4850
4851#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
4852#define USART_FERR_bp  4  /* Frame Error bit position. */
4853
4854#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
4855#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
4856
4857#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
4858#define USART_PERR_bp  2  /* Parity Error bit position. */
4859
4860#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
4861#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
4862
4863/* USART.CTRLA  bit masks and bit positions */
4864#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
4865#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
4866#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
4867#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
4868#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
4869#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
4870
4871#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
4872#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
4873#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
4874#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
4875#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
4876#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
4877
4878#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
4879#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
4880#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
4881#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
4882#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
4883#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
4884
4885/* USART.CTRLB  bit masks and bit positions */
4886#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
4887#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
4888
4889#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
4890#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
4891
4892#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
4893#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
4894
4895#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
4896#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
4897
4898#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
4899#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
4900
4901/* USART.CTRLC  bit masks and bit positions */
4902#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
4903#define USART_CMODE_gp  6  /* Communication Mode group position. */
4904#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
4905#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
4906#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
4907#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
4908
4909#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
4910#define USART_PMODE_gp  4  /* Parity Mode group position. */
4911#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
4912#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
4913#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
4914#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
4915
4916#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
4917#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
4918
4919#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
4920#define USART_CHSIZE_gp  0  /* Character Size group position. */
4921#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
4922#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
4923#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
4924#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
4925#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
4926#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
4927
4928/* USART.BAUDCTRLA  bit masks and bit positions */
4929#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
4930#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
4931#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
4932#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
4933#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
4934#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
4935#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
4936#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
4937#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
4938#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
4939#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
4940#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
4941#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
4942#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
4943#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
4944#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
4945#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
4946#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
4947
4948/* USART.BAUDCTRLB  bit masks and bit positions */
4949#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
4950#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
4951#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
4952#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
4953#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
4954#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
4955#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
4956#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
4957#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
4958#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
4959
4960/* USART_BSEL  Predefined. */
4961/* USART_BSEL  Predefined. */
4962
4963/* SPI - Serial Peripheral Interface */
4964/* SPI.CTRL  bit masks and bit positions */
4965#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
4966#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
4967
4968#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
4969#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
4970
4971#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
4972#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
4973
4974#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
4975#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
4976
4977#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
4978#define SPI_MODE_gp  2  /* SPI Mode group position. */
4979#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
4980#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
4981#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
4982#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
4983
4984#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
4985#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
4986#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
4987#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
4988#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
4989#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
4990
4991/* SPI.INTCTRL  bit masks and bit positions */
4992#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
4993#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
4994#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
4995#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
4996#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
4997#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
4998
4999/* SPI.STATUS  bit masks and bit positions */
5000#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
5001#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
5002
5003#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
5004#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
5005
5006/* IRCOM - IR Communication Module */
5007/* IRCOM.CTRL  bit masks and bit positions */
5008#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
5009#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
5010#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
5011#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
5012#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
5013#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
5014#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
5015#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
5016#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
5017#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
5018
5019/* FUSE - Fuses and Lockbits */
5020/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
5021#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
5022#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
5023#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
5024#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
5025#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
5026#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
5027#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
5028#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
5029#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
5030#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
5031
5032#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
5033#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
5034#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
5035#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
5036#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
5037#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
5038#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
5039#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
5040#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
5041#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
5042
5043/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
5044#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
5045#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
5046
5047#define NVM_FUSES_TOSCSEL_bm  0x20  /* Timer Oscillator pin location bit mask. */
5048#define NVM_FUSES_TOSCSEL_bp  5  /* Timer Oscillator pin location bit position. */
5049
5050#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
5051#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
5052#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
5053#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
5054#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
5055#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
5056
5057/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
5058#define NVM_FUSES_RSTDISBL_bm  0x10  /* External Reset Disable bit mask. */
5059#define NVM_FUSES_RSTDISBL_bp  4  /* External Reset Disable bit position. */
5060
5061#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
5062#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
5063#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
5064#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
5065#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
5066#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
5067
5068#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
5069#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
5070
5071/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
5072#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
5073#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
5074#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
5075#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
5076#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
5077#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
5078
5079#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
5080#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
5081
5082#define NVM_FUSES_BODLVL_gm  0x07  /* Brownout Detection Voltage Level group mask. */
5083#define NVM_FUSES_BODLVL_gp  0  /* Brownout Detection Voltage Level group position. */
5084#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brownout Detection Voltage Level bit 0 mask. */
5085#define NVM_FUSES_BODLVL0_bp  0  /* Brownout Detection Voltage Level bit 0 position. */
5086#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brownout Detection Voltage Level bit 1 mask. */
5087#define NVM_FUSES_BODLVL1_bp  1  /* Brownout Detection Voltage Level bit 1 position. */
5088#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brownout Detection Voltage Level bit 2 mask. */
5089#define NVM_FUSES_BODLVL2_bp  2  /* Brownout Detection Voltage Level bit 2 position. */
5090
5091/* LOCKBIT - Fuses and Lockbits */
5092/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
5093#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
5094#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
5095#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
5096#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
5097#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
5098#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
5099
5100#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
5101#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
5102#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
5103#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
5104#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
5105#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
5106
5107#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
5108#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
5109#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
5110#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
5111#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
5112#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
5113
5114#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
5115#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
5116#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
5117#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
5118#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
5119#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
5120
5121
5122
5123// Generic Port Pins
5124
5125#define PIN0_bm 0x01
5126#define PIN0_bp 0
5127#define PIN1_bm 0x02
5128#define PIN1_bp 1
5129#define PIN2_bm 0x04
5130#define PIN2_bp 2
5131#define PIN3_bm 0x08
5132#define PIN3_bp 3
5133#define PIN4_bm 0x10
5134#define PIN4_bp 4
5135#define PIN5_bm 0x20
5136#define PIN5_bp 5
5137#define PIN6_bm 0x40
5138#define PIN6_bp 6
5139#define PIN7_bm 0x80
5140#define PIN7_bp 7
5141
5142/* ========== Interrupt Vector Definitions ========== */
5143/* Vector 0 is the reset vector */
5144
5145/* OSC interrupt vectors */
5146#define OSC_OSCF_vect_num  1
5147#define OSC_OSCF_vect      _VECTOR(1)  /* Oscillator Failure Interrupt (NMI) */
5148
5149/* PORTC interrupt vectors */
5150#define PORTC_INT0_vect_num  2
5151#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
5152#define PORTC_INT1_vect_num  3
5153#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
5154
5155/* PORTR interrupt vectors */
5156#define PORTR_INT0_vect_num  4
5157#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
5158#define PORTR_INT1_vect_num  5
5159#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
5160
5161/* RTC interrupt vectors */
5162#define RTC_OVF_vect_num  10
5163#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
5164#define RTC_COMP_vect_num  11
5165#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
5166
5167/* TWIC interrupt vectors */
5168#define TWIC_TWIS_vect_num  12
5169#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
5170#define TWIC_TWIM_vect_num  13
5171#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
5172
5173/* TCC0 interrupt vectors */
5174#define TCC0_OVF_vect_num  14
5175#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
5176
5177/* TCC2 interrupt vectors */
5178#define TCC2_LUNF_vect_num  14
5179#define TCC2_LUNF_vect      _VECTOR(14)  /* Low Byte Underflow Interrupt */
5180
5181/* TCC0 interrupt vectors */
5182#define TCC0_ERR_vect_num  15
5183#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
5184
5185/* TCC2 interrupt vectors */
5186#define TCC2_HUNF_vect_num  15
5187#define TCC2_HUNF_vect      _VECTOR(15)  /* High Byte Underflow Interrupt */
5188
5189/* TCC0 interrupt vectors */
5190#define TCC0_CCA_vect_num  16
5191#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
5192
5193/* TCC2 interrupt vectors */
5194#define TCC2_LCMPA_vect_num  16
5195#define TCC2_LCMPA_vect      _VECTOR(16)  /* Low Byte Compare A Interrupt */
5196
5197/* TCC0 interrupt vectors */
5198#define TCC0_CCB_vect_num  17
5199#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
5200
5201/* TCC2 interrupt vectors */
5202#define TCC2_LCMPB_vect_num  17
5203#define TCC2_LCMPB_vect      _VECTOR(17)  /* Low Byte Compare B Interrupt */
5204
5205/* TCC0 interrupt vectors */
5206#define TCC0_CCC_vect_num  18
5207#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
5208
5209/* TCC2 interrupt vectors */
5210#define TCC2_LCMPC_vect_num  18
5211#define TCC2_LCMPC_vect      _VECTOR(18)  /* Low Byte Compare C Interrupt */
5212
5213/* TCC0 interrupt vectors */
5214#define TCC0_CCD_vect_num  19
5215#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
5216
5217/* TCC2 interrupt vectors */
5218#define TCC2_LCMPD_vect_num  19
5219#define TCC2_LCMPD_vect      _VECTOR(19)  /* Low Byte Compare D Interrupt */
5220
5221/* TCC1 interrupt vectors */
5222#define TCC1_OVF_vect_num  20
5223#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
5224#define TCC1_ERR_vect_num  21
5225#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
5226#define TCC1_CCA_vect_num  22
5227#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
5228#define TCC1_CCB_vect_num  23
5229#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
5230
5231/* SPIC interrupt vectors */
5232#define SPIC_INT_vect_num  24
5233#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
5234
5235/* USARTC0 interrupt vectors */
5236#define USARTC0_RXC_vect_num  25
5237#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
5238#define USARTC0_DRE_vect_num  26
5239#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
5240#define USARTC0_TXC_vect_num  27
5241#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
5242
5243/* NVM interrupt vectors */
5244#define NVM_EE_vect_num  32
5245#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
5246#define NVM_SPM_vect_num  33
5247#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
5248
5249/* PORTB interrupt vectors */
5250#define PORTB_INT0_vect_num  34
5251#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
5252#define PORTB_INT1_vect_num  35
5253#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
5254
5255/* PORTE interrupt vectors */
5256#define PORTE_INT0_vect_num  43
5257#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
5258#define PORTE_INT1_vect_num  44
5259#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
5260
5261/* TWIE interrupt vectors */
5262#define TWIE_TWIS_vect_num  45
5263#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
5264#define TWIE_TWIM_vect_num  46
5265#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
5266
5267/* TCE0 interrupt vectors */
5268#define TCE0_OVF_vect_num  47
5269#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
5270#define TCE0_ERR_vect_num  48
5271#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
5272#define TCE0_CCA_vect_num  49
5273#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
5274#define TCE0_CCB_vect_num  50
5275#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
5276#define TCE0_CCC_vect_num  51
5277#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
5278#define TCE0_CCD_vect_num  52
5279#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
5280
5281/* USARTE0 interrupt vectors */
5282#define USARTE0_RXC_vect_num  58
5283#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
5284#define USARTE0_DRE_vect_num  59
5285#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
5286#define USARTE0_TXC_vect_num  60
5287#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
5288
5289/* PORTD interrupt vectors */
5290#define PORTD_INT0_vect_num  64
5291#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
5292#define PORTD_INT1_vect_num  65
5293#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
5294
5295/* PORTA interrupt vectors */
5296#define PORTA_INT0_vect_num  66
5297#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
5298#define PORTA_INT1_vect_num  67
5299#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
5300
5301/* ACA interrupt vectors */
5302#define ACA_AC0_vect_num  68
5303#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
5304#define ACA_AC1_vect_num  69
5305#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
5306#define ACA_ACW_vect_num  70
5307#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
5308
5309/* ADCA interrupt vectors */
5310#define ADCA_CH0_vect_num  71
5311#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
5312
5313/* TCD0 interrupt vectors */
5314#define TCD0_OVF_vect_num  77
5315#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
5316
5317/* TCD2 interrupt vectors */
5318#define TCD2_LUNF_vect_num  77
5319#define TCD2_LUNF_vect      _VECTOR(77)  /* Low Byte Underflow Interrupt */
5320
5321/* TCD0 interrupt vectors */
5322#define TCD0_ERR_vect_num  78
5323#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
5324
5325/* TCD2 interrupt vectors */
5326#define TCD2_HUNF_vect_num  78
5327#define TCD2_HUNF_vect      _VECTOR(78)  /* High Byte Underflow Interrupt */
5328
5329/* TCD0 interrupt vectors */
5330#define TCD0_CCA_vect_num  79
5331#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
5332
5333/* TCD2 interrupt vectors */
5334#define TCD2_LCMPA_vect_num  79
5335#define TCD2_LCMPA_vect      _VECTOR(79)  /* Low Byte Compare A Interrupt */
5336
5337/* TCD0 interrupt vectors */
5338#define TCD0_CCB_vect_num  80
5339#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
5340
5341/* TCD2 interrupt vectors */
5342#define TCD2_LCMPB_vect_num  80
5343#define TCD2_LCMPB_vect      _VECTOR(80)  /* Low Byte Compare B Interrupt */
5344
5345/* TCD0 interrupt vectors */
5346#define TCD0_CCC_vect_num  81
5347#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
5348
5349/* TCD2 interrupt vectors */
5350#define TCD2_LCMPC_vect_num  81
5351#define TCD2_LCMPC_vect      _VECTOR(81)  /* Low Byte Compare C Interrupt */
5352
5353/* TCD0 interrupt vectors */
5354#define TCD0_CCD_vect_num  82
5355#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
5356
5357/* TCD2 interrupt vectors */
5358#define TCD2_LCMPD_vect_num  82
5359#define TCD2_LCMPD_vect      _VECTOR(82)  /* Low Byte Compare D Interrupt */
5360
5361/* SPID interrupt vectors */
5362#define SPID_INT_vect_num  87
5363#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
5364
5365/* USARTD0 interrupt vectors */
5366#define USARTD0_RXC_vect_num  88
5367#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
5368#define USARTD0_DRE_vect_num  89
5369#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
5370#define USARTD0_TXC_vect_num  90
5371#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
5372
5373#define _VECTOR_SIZE 4 /* Size of individual vector. */
5374#define _VECTORS_SIZE (91 * _VECTOR_SIZE)
5375
5376
5377/* ========== Constants ========== */
5378
5379#define PROGMEM_START     (0x0000)
5380#define PROGMEM_SIZE      (139264)
5381#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
5382
5383#define APP_SECTION_START     (0x0000)
5384#define APP_SECTION_SIZE      (131072)
5385#define APP_SECTION_PAGE_SIZE (256)
5386#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
5387
5388#define APPTABLE_SECTION_START     (0x1E000)
5389#define APPTABLE_SECTION_SIZE      (8192)
5390#define APPTABLE_SECTION_PAGE_SIZE (256)
5391#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
5392
5393#define BOOT_SECTION_START     (0x20000)
5394#define BOOT_SECTION_SIZE      (8192)
5395#define BOOT_SECTION_PAGE_SIZE (256)
5396#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
5397
5398#define DATAMEM_START     (0x0000)
5399#define DATAMEM_SIZE      (16384)
5400#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
5401
5402#define IO_START     (0x0000)
5403#define IO_SIZE      (4096)
5404#define IO_PAGE_SIZE (0)
5405#define IO_END       (IO_START + IO_SIZE - 1)
5406
5407#define MAPPED_EEPROM_START     (0x1000)
5408#define MAPPED_EEPROM_SIZE      (2048)
5409#define MAPPED_EEPROM_PAGE_SIZE (0)
5410#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
5411
5412#define INTERNAL_SRAM_START     (0x2000)
5413#define INTERNAL_SRAM_SIZE      (8192)
5414#define INTERNAL_SRAM_PAGE_SIZE (0)
5415#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
5416
5417#define EEPROM_START     (0x0000)
5418#define EEPROM_SIZE      (2048)
5419#define EEPROM_PAGE_SIZE (32)
5420#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
5421
5422#define SIGNATURES_START     (0x0000)
5423#define SIGNATURES_SIZE      (3)
5424#define SIGNATURES_PAGE_SIZE (0)
5425#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
5426
5427#define FUSES_START     (0x0000)
5428#define FUSES_SIZE      (6)
5429#define FUSES_PAGE_SIZE (0)
5430#define FUSES_END       (FUSES_START + FUSES_SIZE - 1)
5431
5432#define LOCKBITS_START     (0x0000)
5433#define LOCKBITS_SIZE      (1)
5434#define LOCKBITS_PAGE_SIZE (0)
5435#define LOCKBITS_END       (LOCKBITS_START + LOCKBITS_SIZE - 1)
5436
5437#define USER_SIGNATURES_START     (0x0000)
5438#define USER_SIGNATURES_SIZE      (256)
5439#define USER_SIGNATURES_PAGE_SIZE (256)
5440#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
5441
5442#define PROD_SIGNATURES_START     (0x0000)
5443#define PROD_SIGNATURES_SIZE      (64)
5444#define PROD_SIGNATURES_PAGE_SIZE (256)
5445#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
5446
5447#define FLASHSTART   PROGMEM_START
5448#define FLASHEND     PROGMEM_END
5449#define SPM_PAGESIZE 256
5450#define RAMSTART     INTERNAL_SRAM_START
5451#define RAMSIZE      INTERNAL_SRAM_SIZE
5452#define RAMEND       INTERNAL_SRAM_END
5453#define E2END        EEPROM_END
5454#define E2PAGESIZE   EEPROM_PAGE_SIZE
5455
5456
5457/* ========== Fuses ========== */
5458#define FUSE_MEMORY_SIZE 6
5459
5460/* Fuse Byte 0 Reserved */
5461
5462/* Fuse Byte 1 */
5463#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
5464#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
5465#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
5466#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
5467#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
5468#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
5469#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
5470#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
5471#define FUSE1_DEFAULT  (0xFF)
5472
5473/* Fuse Byte 2 */
5474#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
5475#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
5476#define FUSE_TOSCSEL  (unsigned char)~_BV(5)  /* Timer Oscillator pin location */
5477#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
5478#define FUSE2_DEFAULT  (0xFF)
5479
5480/* Fuse Byte 3 Reserved */
5481
5482/* Fuse Byte 4 */
5483#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
5484#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
5485#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
5486#define FUSE_RSTDISBL  (unsigned char)~_BV(4)  /* External Reset Disable */
5487#define FUSE4_DEFAULT  (0xFF)
5488
5489/* Fuse Byte 5 */
5490#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brownout Detection Voltage Level Bit 0 */
5491#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brownout Detection Voltage Level Bit 1 */
5492#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brownout Detection Voltage Level Bit 2 */
5493#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
5494#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
5495#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
5496#define FUSE5_DEFAULT  (0xFF)
5497
5498/* ========== Lock Bits ========== */
5499#define __LOCK_BITS_EXIST
5500#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
5501#define __BOOT_LOCK_APPLICATION_BITS_EXIST
5502#define __BOOT_LOCK_BOOT_BITS_EXIST
5503
5504/* ========== Signature ========== */
5505#define SIGNATURE_0 0x1E
5506#define SIGNATURE_1 0x97
5507#define SIGNATURE_2 0x47
5508
5509
5510#endif /* #ifdef _AVR_ATXMEGA128D4_H_INCLUDED */
5511
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