source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iox16d4.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

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1/* Copyright (c) 2009-2010 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iox16d4.h 2200 2010-12-14 04:24:24Z arcanum $ */
32
33/* avr/iox16d4.h - definitions for ATxmega16D4 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iox16d4.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_ATxmega16D4_H_
49#define _AVR_ATxmega16D4_H_ 1
50
51
52/* Ungrouped common registers */
53#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
54#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
55#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
56#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
57#define GPIOR4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
58#define GPIOR5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
59#define GPIOR6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
60#define GPIOR7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
61#define GPIOR8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
62#define GPIOR9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
63#define GPIORA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
64#define GPIORB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
65#define GPIORC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
66#define GPIORD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
67#define GPIORE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
68#define GPIORF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
69
70/* Deprecated */
71#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
72#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
73#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
74#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
75#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
76#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
77#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
78#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
79#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
80#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
81#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
82#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
83#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
84#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
85#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
86#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
87
88#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
89#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
90#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
91#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
92#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
93#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
94#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
95#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
96#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
97
98
99/* C Language Only */
100#if !defined (__ASSEMBLER__)
101
102#include <stdint.h>
103
104typedef volatile uint8_t register8_t;
105typedef volatile uint16_t register16_t;
106typedef volatile uint32_t register32_t;
107
108
109#ifdef _WORDREGISTER
110#undef _WORDREGISTER
111#endif
112#define _WORDREGISTER(regname)   \
113    __extension__ union \
114    { \
115        register16_t regname; \
116        struct \
117        { \
118            register8_t regname ## L; \
119            register8_t regname ## H; \
120        }; \
121    }
122
123#ifdef _DWORDREGISTER
124#undef _DWORDREGISTER
125#endif
126#define _DWORDREGISTER(regname)  \
127   __extension__  union \
128    { \
129        register32_t regname; \
130        struct \
131        { \
132            register8_t regname ## 0; \
133            register8_t regname ## 1; \
134            register8_t regname ## 2; \
135            register8_t regname ## 3; \
136        }; \
137    }
138
139
140/*
141==========================================================================
142IO Module Structures
143==========================================================================
144*/
145
146
147/*
148--------------------------------------------------------------------------
149XOCD - On-Chip Debug System
150--------------------------------------------------------------------------
151*/
152
153/* On-Chip Debug System */
154typedef struct OCD_struct
155{
156    register8_t OCDR0;  /* OCD Register 0 */
157    register8_t OCDR1;  /* OCD Register 1 */
158} OCD_t;
159
160
161/* CCP signatures */
162typedef enum CCP_enum
163{
164    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
165    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
166} CCP_t;
167
168
169/*
170--------------------------------------------------------------------------
171CLK - Clock System
172--------------------------------------------------------------------------
173*/
174
175/* Clock System */
176typedef struct CLK_struct
177{
178    register8_t CTRL;  /* Control Register */
179    register8_t PSCTRL;  /* Prescaler Control Register */
180    register8_t LOCK;  /* Lock register */
181    register8_t RTCCTRL;  /* RTC Control Register */
182} CLK_t;
183
184/*
185--------------------------------------------------------------------------
186CLK - Clock System
187--------------------------------------------------------------------------
188*/
189
190/* Power Reduction */
191typedef struct PR_struct
192{
193    register8_t PRGEN;  /* General Power Reduction */
194    register8_t PRPA;  /* Power Reduction Port A */
195    register8_t PRPB;  /* Power Reduction Port B */
196    register8_t PRPC;  /* Power Reduction Port C */
197    register8_t PRPD;  /* Power Reduction Port D */
198    register8_t PRPE;  /* Power Reduction Port E */
199    register8_t PRPF;  /* Power Reduction Port F */
200} PR_t;
201
202/* System Clock Selection */
203typedef enum CLK_SCLKSEL_enum
204{
205    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
206    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
207    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
208    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
209    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
210} CLK_SCLKSEL_t;
211
212/* Prescaler A Division Factor */
213typedef enum CLK_PSADIV_enum
214{
215    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
216    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
217    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
218    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
219    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
220    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
221    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
222    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
223    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
224    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
225} CLK_PSADIV_t;
226
227/* Prescaler B and C Division Factor */
228typedef enum CLK_PSBCDIV_enum
229{
230    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
231    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
232    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
233    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
234} CLK_PSBCDIV_t;
235
236/* RTC Clock Source */
237typedef enum CLK_RTCSRC_enum
238{
239    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
240    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
241    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
242    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
243} CLK_RTCSRC_t;
244
245
246/*
247--------------------------------------------------------------------------
248SLEEP - Sleep Controller
249--------------------------------------------------------------------------
250*/
251
252/* Sleep Controller */
253typedef struct SLEEP_struct
254{
255    register8_t CTRL;  /* Control Register */
256} SLEEP_t;
257
258/* Sleep Mode */
259typedef enum SLEEP_SMODE_enum
260{
261    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
262    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
263    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
264    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
265    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
266} SLEEP_SMODE_t;
267
268#define SLEEP_MODE_IDLE (0x00<<1)
269#define SLEEP_MODE_PWR_DOWN (0x02<<1)
270#define SLEEP_MODE_PWR_SAVE (0x03<<1)
271#define SLEEP_MODE_STANDBY (0x06<<1)
272#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
273
274
275/*
276--------------------------------------------------------------------------
277OSC - Oscillator
278--------------------------------------------------------------------------
279*/
280
281/* Oscillator */
282typedef struct OSC_struct
283{
284    register8_t CTRL;  /* Control Register */
285    register8_t STATUS;  /* Status Register */
286    register8_t XOSCCTRL;  /* External Oscillator Control Register */
287    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
288    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
289    register8_t PLLCTRL;  /* PLL Control REgister */
290    register8_t DFLLCTRL;  /* DFLL Control Register */
291} OSC_t;
292
293/* Oscillator Frequency Range */
294typedef enum OSC_FRQRANGE_enum
295{
296    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
297    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
298    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
299    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
300} OSC_FRQRANGE_t;
301
302/* External Oscillator Selection and Startup Time */
303typedef enum OSC_XOSCSEL_enum
304{
305    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
306    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
307    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
308    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
309    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
310} OSC_XOSCSEL_t;
311
312/* PLL Clock Source */
313typedef enum OSC_PLLSRC_enum
314{
315    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
316    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
317    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
318} OSC_PLLSRC_t;
319
320
321/*
322--------------------------------------------------------------------------
323DFLL - DFLL
324--------------------------------------------------------------------------
325*/
326
327/* DFLL */
328typedef struct DFLL_struct
329{
330    register8_t CTRL;  /* Control Register */
331    register8_t reserved_0x01;
332    register8_t CALA;  /* Calibration Register A */
333    register8_t CALB;  /* Calibration Register B */
334    register8_t COMP0;  /* Oscillator Compare Register 0 */
335    register8_t COMP1;  /* Oscillator Compare Register 1 */
336    register8_t COMP2;  /* Oscillator Compare Register 2 */
337    register8_t reserved_0x07;
338} DFLL_t;
339
340
341/*
342--------------------------------------------------------------------------
343RST - Reset
344--------------------------------------------------------------------------
345*/
346
347/* Reset */
348typedef struct RST_struct
349{
350    register8_t STATUS;  /* Status Register */
351    register8_t CTRL;  /* Control Register */
352} RST_t;
353
354
355/*
356--------------------------------------------------------------------------
357WDT - Watch-Dog Timer
358--------------------------------------------------------------------------
359*/
360
361/* Watch-Dog Timer */
362typedef struct WDT_struct
363{
364    register8_t CTRL;  /* Control */
365    register8_t WINCTRL;  /* Windowed Mode Control */
366    register8_t STATUS;  /* Status */
367} WDT_t;
368
369/* Period setting */
370typedef enum WDT_PER_enum
371{
372    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
373    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
374    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
375    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
376    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
377    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
378    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
379    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
380    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
381    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
382    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
383} WDT_PER_t;
384
385/* Closed window period */
386typedef enum WDT_WPER_enum
387{
388    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
389    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
390    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
391    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
392    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
393    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
394    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
395    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
396    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
397    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
398    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
399} WDT_WPER_t;
400
401
402/*
403--------------------------------------------------------------------------
404MCU - MCU Control
405--------------------------------------------------------------------------
406*/
407
408/* MCU Control */
409typedef struct MCU_struct
410{
411    register8_t DEVID0;  /* Device ID byte 0 */
412    register8_t DEVID1;  /* Device ID byte 1 */
413    register8_t DEVID2;  /* Device ID byte 2 */
414    register8_t REVID;  /* Revision ID */
415    register8_t JTAGUID;  /* JTAG User ID */
416    register8_t reserved_0x05;
417    register8_t MCUCR;  /* MCU Control */
418    register8_t reserved_0x07;
419    register8_t EVSYSLOCK;  /* Event System Lock */
420    register8_t AWEXLOCK;  /* AWEX Lock */
421    register8_t reserved_0x0A;
422    register8_t reserved_0x0B;
423} MCU_t;
424
425
426/*
427--------------------------------------------------------------------------
428PMIC - Programmable Multi-level Interrupt Controller
429--------------------------------------------------------------------------
430*/
431
432/* Programmable Multi-level Interrupt Controller */
433typedef struct PMIC_struct
434{
435    register8_t STATUS;  /* Status Register */
436    register8_t INTPRI;  /* Interrupt Priority */
437    register8_t CTRL;  /* Control Register */
438} PMIC_t;
439
440
441/*
442--------------------------------------------------------------------------
443CRC - Cyclic Redundancy Checker
444--------------------------------------------------------------------------
445*/
446
447/* Cyclic Redundancy Checker */
448typedef struct CRC_struct
449{
450    register8_t CTRL;  /* Control Register */
451    register8_t STATUS;  /* Status Register */
452    register8_t reserved_0x02;
453    register8_t DATAIN;  /* Data Input */
454    register8_t CHECKSUM0;  /* Checksum byte 0 */
455    register8_t CHECKSUM1;  /* Checksum byte 1 */
456    register8_t CHECKSUM2;  /* Checksum byte 2 */
457    register8_t CHECKSUM3;  /* Checksum byte 3 */
458} CRC_t;
459
460/* Reset */
461typedef enum CRC_RESET_enum
462{
463    CRC_RESET_NO_gc = (0x00<<6),  /* No Reset */
464    CRC_RESET_RESET0_gc = (0x02<<6),  /* Reset CRC with CHECKSUM to all zeros */
465    CRC_RESET_RESET1_gc = (0x03<<6),  /* Reset CRC with CHECKSUM to all ones */
466} CRC_RESET_t;
467
468/* Input Source */
469typedef enum CRC_SOURCE_enum
470{
471    CRC_SOURCE_DISABLE_gc = (0x00<<0),  /* Disabled */
472    CRC_SOURCE_IO_gc = (0x01<<0),  /* I/O Interface */
473    CRC_SOURCE_FLASH_gc = (0x02<<0),  /* Flash */
474} CRC_SOURCE_t;
475
476
477/*
478--------------------------------------------------------------------------
479EVSYS - Event System
480--------------------------------------------------------------------------
481*/
482
483/* Event System */
484typedef struct EVSYS_struct
485{
486    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
487    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
488    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
489    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
490    register8_t reserved_0x04;
491    register8_t reserved_0x05;
492    register8_t reserved_0x06;
493    register8_t reserved_0x07;
494    register8_t CH0CTRL;  /* Channel 0 Control Register */
495    register8_t CH1CTRL;  /* Channel 1 Control Register */
496    register8_t CH2CTRL;  /* Channel 2 Control Register */
497    register8_t CH3CTRL;  /* Channel 3 Control Register */
498    register8_t reserved_0x0C;
499    register8_t reserved_0x0D;
500    register8_t reserved_0x0E;
501    register8_t reserved_0x0F;
502    register8_t STROBE;  /* Event Strobe */
503    register8_t DATA;  /* Event Data */
504} EVSYS_t;
505
506/* Quadrature Decoder Index Recognition Mode */
507typedef enum EVSYS_QDIRM_enum
508{
509    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
510    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
511    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
512    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
513} EVSYS_QDIRM_t;
514
515/* Digital filter coefficient */
516typedef enum EVSYS_DIGFILT_enum
517{
518    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
519    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
520    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
521    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
522    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
523    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
524    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
525    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
526} EVSYS_DIGFILT_t;
527
528/* Event Channel multiplexer input selection */
529typedef enum EVSYS_CHMUX_enum
530{
531    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
532    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
533    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
534    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
535    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
536    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
537    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
538    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
539    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
540    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
541    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
542    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
543    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
544    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
545    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
546    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
547    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
548    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
549    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
550    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
551    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
552    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
553    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
554    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
555    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
556    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
557    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
558    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
559    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
560    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
561    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
562    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
563    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
564    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
565    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
566    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
567    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
568    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
569    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
570    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
571    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
572    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
573    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
574    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
575    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
576    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
577    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
578    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
579    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
580    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
581    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
582    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
583    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
584    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
585    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
586    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
587    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
588    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
589    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
590    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
591    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
592    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
593    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
594    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
595    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
596    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
597    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
598    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
599    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
600    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
601    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
602    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
603    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
604    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
605    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
606    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
607    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
608    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
609    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
610    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
611    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
612    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
613    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
614    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
615    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
616    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
617    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
618    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
619    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
620    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
621    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
622    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
623    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
624    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
625    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
626    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
627    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
628    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
629    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
630    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
631    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
632    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
633    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
634    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
635    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
636    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
637    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
638    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
639    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
640    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
641    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
642} EVSYS_CHMUX_t;
643
644
645/*
646--------------------------------------------------------------------------
647NVM - Non Volatile Memory Controller
648--------------------------------------------------------------------------
649*/
650
651/* Non-volatile Memory Controller */
652typedef struct NVM_struct
653{
654    register8_t ADDR0;  /* Address Register 0 */
655    register8_t ADDR1;  /* Address Register 1 */
656    register8_t ADDR2;  /* Address Register 2 */
657    register8_t reserved_0x03;
658    register8_t DATA0;  /* Data Register 0 */
659    register8_t DATA1;  /* Data Register 1 */
660    register8_t DATA2;  /* Data Register 2 */
661    register8_t reserved_0x07;
662    register8_t reserved_0x08;
663    register8_t reserved_0x09;
664    register8_t CMD;  /* Command */
665    register8_t CTRLA;  /* Control Register A */
666    register8_t CTRLB;  /* Control Register B */
667    register8_t INTCTRL;  /* Interrupt Control */
668    register8_t reserved_0x0E;
669    register8_t STATUS;  /* Status */
670    register8_t LOCK_BITS;  /* Lock Bits */
671} NVM_t;
672
673/*
674--------------------------------------------------------------------------
675NVM - Non Volatile Memory Controller
676--------------------------------------------------------------------------
677*/
678
679/* Lock Bits */
680typedef struct NVM_LOCKBITS_struct
681{
682    register8_t LOCKBITS;  /* Lock Bits */
683} NVM_LOCKBITS_t;
684
685/*
686--------------------------------------------------------------------------
687NVM - Non Volatile Memory Controller
688--------------------------------------------------------------------------
689*/
690
691/* Fuses */
692typedef struct NVM_FUSES_struct
693{
694    register8_t FUSEBYTE0;  /* User ID */
695    register8_t FUSEBYTE1;  /* Watchdog Configuration */
696    register8_t FUSEBYTE2;  /* Reset Configuration */
697    register8_t reserved_0x03;
698    register8_t FUSEBYTE4;  /* Start-up Configuration */
699    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
700} NVM_FUSES_t;
701
702/*
703--------------------------------------------------------------------------
704NVM - Non Volatile Memory Controller
705--------------------------------------------------------------------------
706*/
707
708/* Production Signatures */
709typedef struct NVM_PROD_SIGNATURES_struct
710{
711    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
712    register8_t reserved_0x01;
713    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
714    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
715    register8_t reserved_0x04;
716    register8_t reserved_0x05;
717    register8_t reserved_0x06;
718    register8_t reserved_0x07;
719    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
720    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
721    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
722    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
723    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
724    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
725    register8_t reserved_0x0E;
726    register8_t reserved_0x0F;
727    register8_t WAFNUM;  /* Wafer Number */
728    register8_t reserved_0x11;
729    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
730    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
731    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
732    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
733    register8_t reserved_0x16;
734    register8_t reserved_0x17;
735    register8_t reserved_0x18;
736    register8_t reserved_0x19;
737    register8_t reserved_0x1A;
738    register8_t reserved_0x1B;
739    register8_t reserved_0x1C;
740    register8_t reserved_0x1D;
741    register8_t reserved_0x1E;
742    register8_t reserved_0x1F;
743    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
744    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
745    register8_t reserved_0x22;
746    register8_t reserved_0x23;
747    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
748    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
749    register8_t reserved_0x26;
750    register8_t reserved_0x27;
751    register8_t reserved_0x28;
752    register8_t reserved_0x29;
753    register8_t reserved_0x2A;
754    register8_t reserved_0x2B;
755    register8_t reserved_0x2C;
756    register8_t reserved_0x2D;
757    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
758    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
759    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
760    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
761    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
762    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
763    register8_t reserved_0x34;
764    register8_t reserved_0x35;
765    register8_t reserved_0x36;
766    register8_t reserved_0x37;
767    register8_t reserved_0x38;
768    register8_t reserved_0x39;
769    register8_t reserved_0x3A;
770    register8_t reserved_0x3B;
771    register8_t reserved_0x3C;
772    register8_t reserved_0x3D;
773    register8_t reserved_0x3E;
774} NVM_PROD_SIGNATURES_t;
775
776/* NVM Command */
777typedef enum NVM_CMD_enum
778{
779    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
780    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
781    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
782    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
783    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
784    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
785    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
786    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
787    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
788    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
789    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
790    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
791    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
792    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
793    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
794    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
795    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
796    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
797    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
798    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
799    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
800    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
801    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
802    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
803    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
804    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
805} NVM_CMD_t;
806
807/* SPM ready interrupt level */
808typedef enum NVM_SPMLVL_enum
809{
810    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
811    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
812    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
813    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
814} NVM_SPMLVL_t;
815
816/* EEPROM ready interrupt level */
817typedef enum NVM_EELVL_enum
818{
819    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
820    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
821    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
822    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
823} NVM_EELVL_t;
824
825/* Boot lock bits - boot setcion */
826typedef enum NVM_BLBB_enum
827{
828    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
829    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
830    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
831    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
832} NVM_BLBB_t;
833
834/* Boot lock bits - application section */
835typedef enum NVM_BLBA_enum
836{
837    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
838    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
839    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
840    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
841} NVM_BLBA_t;
842
843/* Boot lock bits - application table section */
844typedef enum NVM_BLBAT_enum
845{
846    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
847    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
848    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
849    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
850} NVM_BLBAT_t;
851
852/* Lock bits */
853typedef enum NVM_LB_enum
854{
855    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
856    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
857    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
858} NVM_LB_t;
859
860/* Boot Loader Section Reset Vector */
861typedef enum BOOTRST_enum
862{
863    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
864    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
865} BOOTRST_t;
866
867/* BOD operation */
868typedef enum BOD_enum
869{
870    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
871    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
872    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
873} BOD_t;
874
875/* Watchdog (Window) Timeout Period */
876typedef enum WD_enum
877{
878    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
879    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
880    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
881    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
882    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
883    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
884    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
885    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
886    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
887    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
888    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
889} WD_t;
890
891/* Start-up Time */
892typedef enum SUT_enum
893{
894    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
895    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
896    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
897} SUT_t;
898
899/* Brown Out Detection Voltage Level */
900typedef enum BODLVL_enum
901{
902    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
903    BODLVL_1V8_gc = (0x06<<0),  /* 1.8 V */
904    BODLVL_2V0_gc = (0x05<<0),  /* 2.0 V */
905    BODLVL_2V2_gc = (0x04<<0),  /* 2.2 V */
906    BODLVL_2V4_gc = (0x03<<0),  /* 2.4 V */
907    BODLVL_2V6_gc = (0x02<<0),  /* 2.6 V */
908    BODLVL_2V8_gc = (0x01<<0),  /* 2.8 V */
909    BODLVL_3V0_gc = (0x00<<0),  /* 3.0 V */
910} BODLVL_t;
911
912
913/*
914--------------------------------------------------------------------------
915AC - Analog Comparator
916--------------------------------------------------------------------------
917*/
918
919/* Analog Comparator */
920typedef struct AC_struct
921{
922    register8_t AC0CTRL;  /* Comparator 0 Control */
923    register8_t AC1CTRL;  /* Comparator 1 Control */
924    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
925    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
926    register8_t CTRLA;  /* Control Register A */
927    register8_t CTRLB;  /* Control Register B */
928    register8_t WINCTRL;  /* Window Mode Control */
929    register8_t STATUS;  /* Status */
930} AC_t;
931
932/* Interrupt mode */
933typedef enum AC_INTMODE_enum
934{
935    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
936    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
937    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
938} AC_INTMODE_t;
939
940/* Interrupt level */
941typedef enum AC_INTLVL_enum
942{
943    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
944    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
945    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
946    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
947} AC_INTLVL_t;
948
949/* Hysteresis mode selection */
950typedef enum AC_HYSMODE_enum
951{
952    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
953    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
954    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
955} AC_HYSMODE_t;
956
957/* Positive input multiplexer selection */
958typedef enum AC_MUXPOS_enum
959{
960    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
961    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
962    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
963    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
964    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
965    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
966    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
967    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
968} AC_MUXPOS_t;
969
970/* Negative input multiplexer selection */
971typedef enum AC_MUXNEG_enum
972{
973    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
974    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
975    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
976    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
977    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
978    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
979    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
980    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
981} AC_MUXNEG_t;
982
983/* Windows interrupt mode */
984typedef enum AC_WINTMODE_enum
985{
986    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
987    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
988    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
989    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
990} AC_WINTMODE_t;
991
992/* Window interrupt level */
993typedef enum AC_WINTLVL_enum
994{
995    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
996    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
997    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
998    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
999} AC_WINTLVL_t;
1000
1001/* Window mode state */
1002typedef enum AC_WSTATE_enum
1003{
1004    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
1005    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
1006    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
1007} AC_WSTATE_t;
1008
1009
1010/*
1011--------------------------------------------------------------------------
1012ADC - Analog/Digital Converter
1013--------------------------------------------------------------------------
1014*/
1015
1016/* ADC Channel */
1017typedef struct ADC_CH_struct
1018{
1019    register8_t CTRL;  /* Control Register */
1020    register8_t MUXCTRL;  /* MUX Control */
1021    register8_t INTCTRL;  /* Channel Interrupt Control */
1022    register8_t INTFLAGS;  /* Interrupt Flags */
1023    _WORDREGISTER(RES);  /* Channel Result */
1024    register8_t reserved_0x6;
1025    register8_t reserved_0x7;
1026} ADC_CH_t;
1027
1028/*
1029--------------------------------------------------------------------------
1030ADC - Analog/Digital Converter
1031--------------------------------------------------------------------------
1032*/
1033
1034/* Analog-to-Digital Converter */
1035typedef struct ADC_struct
1036{
1037    register8_t CTRLA;  /* Control Register A */
1038    register8_t CTRLB;  /* Control Register B */
1039    register8_t REFCTRL;  /* Reference Control */
1040    register8_t EVCTRL;  /* Event Control */
1041    register8_t PRESCALER;  /* Clock Prescaler */
1042    register8_t reserved_0x05;
1043    register8_t INTFLAGS;  /* Interrupt Flags */
1044    register8_t reserved_0x07;
1045    register8_t reserved_0x08;
1046    register8_t reserved_0x09;
1047    register8_t reserved_0x0A;
1048    register8_t reserved_0x0B;
1049    _WORDREGISTER(CAL);  /* Calibration Value */
1050    register8_t reserved_0x0E;
1051    register8_t reserved_0x0F;
1052    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
1053    register8_t reserved_0x12;
1054    register8_t reserved_0x13;
1055    register8_t reserved_0x14;
1056    register8_t reserved_0x15;
1057    register8_t reserved_0x16;
1058    register8_t reserved_0x17;
1059    _WORDREGISTER(CMP);  /* Compare Value */
1060    register8_t reserved_0x1A;
1061    register8_t reserved_0x1B;
1062    register8_t reserved_0x1C;
1063    register8_t reserved_0x1D;
1064    register8_t reserved_0x1E;
1065    register8_t reserved_0x1F;
1066    ADC_CH_t CH0;  /* ADC Channel 0 */
1067} ADC_t;
1068
1069/* Positive input multiplexer selection */
1070typedef enum ADC_CH_MUXPOS_enum
1071{
1072    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),   /* Input pin 0  */
1073    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),   /* Input pin 1  */
1074    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),   /* Input pin 2  */
1075    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),   /* Input pin 3  */
1076    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),   /* Input pin 4  */
1077    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),   /* Input pin 5  */
1078    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),   /* Input pin 6  */
1079    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),   /* Input pin 7  */
1080        ADC_CH_MUXPOS_PIN8_gc = (0x08<<3),   /* Input pin 8  */
1081        ADC_CH_MUXPOS_PIN9_gc = (0x09<<3),   /* Input pin 9  */
1082        ADC_CH_MUXPOS_PIN10_gc = (0x10<<3),  /* Input pin 10 */
1083        ADC_CH_MUXPOS_PIN11_gc = (0x11<<3),  /* Input pin 11 */
1084} ADC_CH_MUXPOS_t;
1085
1086/* Internal input multiplexer selections */
1087typedef enum ADC_CH_MUXINT_enum
1088{
1089    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
1090    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
1091    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
1092    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
1093} ADC_CH_MUXINT_t;
1094
1095/* Negative input multiplexer selection */
1096typedef enum ADC_CH_MUXNEG_enum
1097{
1098    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0, INPUTMODE[1:0] = 10 */
1099    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1, INPUTMODE[1:0] = 10 */
1100    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2, INPUTMODE[1:0] = 10 */
1101    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3, INPUTMODE[1:0] = 10 */
1102    ADC_CH_MUXNEG_PIN4_gc = (0x00<<0),  /* Input pin 4, INPUTMODE[1:0] = 11 */
1103    ADC_CH_MUXNEG_PIN5_gc = (0x01<<0),  /* Input pin 5, INPUTMODE[1:0] = 11 */
1104    ADC_CH_MUXNEG_PIN6_gc = (0x02<<0),  /* Input pin 6, INPUTMODE[1:0] = 11 */
1105    ADC_CH_MUXNEG_PIN7_gc = (0x03<<0),  /* Input pin 7, INPUTMODE[1:0] = 11 */
1106} ADC_CH_MUXNEG_t;
1107
1108/* Input mode */
1109typedef enum ADC_CH_INPUTMODE_enum
1110{
1111    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
1112    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
1113    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
1114    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
1115} ADC_CH_INPUTMODE_t;
1116
1117/* Gain factor */
1118typedef enum ADC_CH_GAIN_enum
1119{
1120    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
1121    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
1122    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
1123    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
1124    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
1125    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
1126    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
1127    ADC_CH_GAIN_DIV2_gc = (0x07<<2),  /* x/2 gain */           
1128} ADC_CH_GAIN_t;
1129
1130/* Conversion result resolution */
1131typedef enum ADC_RESOLUTION_enum
1132{
1133    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
1134    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
1135    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
1136} ADC_RESOLUTION_t;
1137
1138typedef enum ADC_CURRLIMIT_enum
1139{
1140    ADC_CURRLIMIT_NO_gc = (0x00<<5),  /* No limit */
1141    ADC_CURRLIMIT_LOW_gc = (0x01<<5),  /* Low current limit, max. sampling rate 1.5MSPS */
1142    ADC_CURRLIMIT_MED_gc = (0x02<<5),  /* Medium current limit, max. sampling rate 1MSPS */
1143    ADC_CURRLIMIT_HIGH_gc = (0x03<<5),  /* High current limit, max. sampling rate 0.5MSPS */
1144} ADC_CURRLIMIT_t;
1145
1146/* Voltage reference selection */
1147typedef enum ADC_REFSEL_enum
1148{
1149    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
1150    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC/1.6V */
1151    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
1152    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
1153} ADC_REFSEL_t;
1154
1155/* Channel sweep selection */
1156typedef enum ADC_SWEEP_enum
1157{
1158    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
1159} ADC_SWEEP_t;
1160
1161/* Event channel input selection */
1162typedef enum ADC_EVSEL_enum
1163{
1164    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
1165    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
1166    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
1167    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
1168    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
1169    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
1170    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
1171    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
1172} ADC_EVSEL_t;
1173
1174/* Event action selection */
1175typedef enum ADC_EVACT_enum
1176{
1177    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
1178    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
1179} ADC_EVACT_t;
1180
1181/* Interupt mode */
1182typedef enum ADC_CH_INTMODE_enum
1183{
1184    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
1185    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
1186    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
1187} ADC_CH_INTMODE_t;
1188
1189/* Interrupt level */
1190typedef enum ADC_CH_INTLVL_enum
1191{
1192    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
1193    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
1194    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
1195    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
1196} ADC_CH_INTLVL_t;
1197
1198/* Clock prescaler */
1199typedef enum ADC_PRESCALER_enum
1200{
1201    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
1202    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
1203    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
1204    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
1205    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
1206    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
1207    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
1208    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
1209} ADC_PRESCALER_t;
1210
1211
1212/*
1213--------------------------------------------------------------------------
1214RTC - Real-Time Clounter
1215--------------------------------------------------------------------------
1216*/
1217
1218/* Real-Time Counter */
1219typedef struct RTC_struct
1220{
1221    register8_t CTRL;  /* Control Register */
1222    register8_t STATUS;  /* Status Register */
1223    register8_t INTCTRL;  /* Interrupt Control Register */
1224    register8_t INTFLAGS;  /* Interrupt Flags */
1225    register8_t TEMP;  /* Temporary register */
1226    register8_t reserved_0x05;
1227    register8_t reserved_0x06;
1228    register8_t reserved_0x07;
1229    _WORDREGISTER(CNT);  /* Count Register */
1230    _WORDREGISTER(PER);  /* Period Register */
1231    _WORDREGISTER(COMP);  /* Compare Register */
1232} RTC_t;
1233
1234/* Prescaler Factor */
1235typedef enum RTC_PRESCALER_enum
1236{
1237    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
1238    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
1239    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
1240    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
1241    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
1242    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
1243    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
1244    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
1245} RTC_PRESCALER_t;
1246
1247/* Compare Interrupt level */
1248typedef enum RTC_COMPINTLVL_enum
1249{
1250    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1251    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1252    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1253    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
1254} RTC_COMPINTLVL_t;
1255
1256/* Overflow Interrupt level */
1257typedef enum RTC_OVFINTLVL_enum
1258{
1259    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1260    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1261    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1262    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
1263} RTC_OVFINTLVL_t;
1264
1265
1266/*
1267--------------------------------------------------------------------------
1268EBI - External Bus Interface
1269--------------------------------------------------------------------------
1270*/
1271
1272/* EBI Chip Select Module */
1273typedef struct EBI_CS_struct
1274{
1275    register8_t CTRLA;  /* Chip Select Control Register A */
1276    register8_t CTRLB;  /* Chip Select Control Register B */
1277    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
1278} EBI_CS_t;
1279
1280/*
1281--------------------------------------------------------------------------
1282EBI - External Bus Interface
1283--------------------------------------------------------------------------
1284*/
1285
1286/* External Bus Interface */
1287typedef struct EBI_struct
1288{
1289    register8_t CTRL;  /* Control */
1290    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
1291    register8_t reserved_0x02;
1292    register8_t reserved_0x03;
1293    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
1294    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
1295    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
1296    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
1297    register8_t reserved_0x0A;
1298    register8_t reserved_0x0B;
1299    register8_t reserved_0x0C;
1300    register8_t reserved_0x0D;
1301    register8_t reserved_0x0E;
1302    register8_t reserved_0x0F;
1303    EBI_CS_t CS0;  /* Chip Select 0 */
1304    EBI_CS_t CS1;  /* Chip Select 1 */
1305    EBI_CS_t CS2;  /* Chip Select 2 */
1306    EBI_CS_t CS3;  /* Chip Select 3 */
1307} EBI_t;
1308
1309/* Chip Select adress space */
1310typedef enum EBI_CS_ASIZE_enum
1311{
1312    EBI_CS_ASIZE_256B_gc = (0x00<<2),  /* 256 bytes */
1313    EBI_CS_ASIZE_512B_gc = (0x01<<2),  /* 512 bytes */
1314    EBI_CS_ASIZE_1KB_gc = (0x02<<2),  /* 1K bytes */
1315    EBI_CS_ASIZE_2KB_gc = (0x03<<2),  /* 2K bytes */
1316    EBI_CS_ASIZE_4KB_gc = (0x04<<2),  /* 4K bytes */
1317    EBI_CS_ASIZE_8KB_gc = (0x05<<2),  /* 8K bytes */
1318    EBI_CS_ASIZE_16KB_gc = (0x06<<2),  /* 16K bytes */
1319    EBI_CS_ASIZE_32KB_gc = (0x07<<2),  /* 32K bytes */
1320    EBI_CS_ASIZE_64KB_gc = (0x08<<2),  /* 64K bytes */
1321    EBI_CS_ASIZE_128KB_gc = (0x09<<2),  /* 128K bytes */
1322    EBI_CS_ASIZE_256KB_gc = (0x0A<<2),  /* 256K bytes */
1323    EBI_CS_ASIZE_512KB_gc = (0x0B<<2),  /* 512K bytes */
1324    EBI_CS_ASIZE_1MB_gc = (0x0C<<2),  /* 1M bytes */
1325    EBI_CS_ASIZE_2MB_gc = (0x0D<<2),  /* 2M bytes */
1326    EBI_CS_ASIZE_4MB_gc = (0x0E<<2),  /* 4M bytes */
1327    EBI_CS_ASIZE_8MB_gc = (0x0F<<2),  /* 8M bytes */
1328    EBI_CS_ASIZE_16M_gc = (0x10<<2),  /* 16M bytes */
1329} EBI_CS_ASIZE_t;
1330
1331/*  */
1332typedef enum EBI_CS_SRWS_enum
1333{
1334    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
1335    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
1336    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
1337    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
1338    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
1339    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
1340    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
1341    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
1342} EBI_CS_SRWS_t;
1343
1344/* Chip Select address mode */
1345typedef enum EBI_CS_MODE_enum
1346{
1347    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
1348    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
1349    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
1350    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
1351} EBI_CS_MODE_t;
1352
1353/* Chip Select SDRAM mode */
1354typedef enum EBI_CS_SDMODE_enum
1355{
1356    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
1357    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
1358} EBI_CS_SDMODE_t;
1359
1360/*  */
1361typedef enum EBI_SDDATAW_enum
1362{
1363    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
1364    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
1365} EBI_SDDATAW_t;
1366
1367/*  */
1368typedef enum EBI_LPCMODE_enum
1369{
1370    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
1371    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
1372} EBI_LPCMODE_t;
1373
1374/*  */
1375typedef enum EBI_SRMODE_enum
1376{
1377    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
1378    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
1379    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
1380    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
1381} EBI_SRMODE_t;
1382
1383/*  */
1384typedef enum EBI_IFMODE_enum
1385{
1386    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
1387    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
1388    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
1389    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
1390} EBI_IFMODE_t;
1391
1392/*  */
1393typedef enum EBI_SDCOL_enum
1394{
1395    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
1396    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
1397    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
1398    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
1399} EBI_SDCOL_t;
1400
1401/*  */
1402typedef enum EBI_MRDLY_enum
1403{
1404    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
1405    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
1406    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
1407    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
1408} EBI_MRDLY_t;
1409
1410/*  */
1411typedef enum EBI_ROWCYCDLY_enum
1412{
1413    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
1414    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
1415    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
1416    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
1417    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
1418    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
1419    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
1420    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
1421} EBI_ROWCYCDLY_t;
1422
1423/*  */
1424typedef enum EBI_RPDLY_enum
1425{
1426    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
1427    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
1428    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
1429    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
1430    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
1431    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
1432    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
1433    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
1434} EBI_RPDLY_t;
1435
1436/*  */
1437typedef enum EBI_WRDLY_enum
1438{
1439    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
1440    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
1441    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
1442    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
1443} EBI_WRDLY_t;
1444
1445/*  */
1446typedef enum EBI_ESRDLY_enum
1447{
1448    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
1449    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
1450    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
1451    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
1452    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
1453    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
1454    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
1455    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
1456} EBI_ESRDLY_t;
1457
1458/*  */
1459typedef enum EBI_ROWCOLDLY_enum
1460{
1461    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
1462    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
1463    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
1464    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
1465    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
1466    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
1467    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
1468    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
1469} EBI_ROWCOLDLY_t;
1470
1471
1472/*
1473--------------------------------------------------------------------------
1474TWI - Two-Wire Interface
1475--------------------------------------------------------------------------
1476*/
1477
1478/*  */
1479typedef struct TWI_MASTER_struct
1480{
1481    register8_t CTRLA;  /* Control Register A */
1482    register8_t CTRLB;  /* Control Register B */
1483    register8_t CTRLC;  /* Control Register C */
1484    register8_t STATUS;  /* Status Register */
1485    register8_t BAUD;  /* Baurd Rate Control Register */
1486    register8_t ADDR;  /* Address Register */
1487    register8_t DATA;  /* Data Register */
1488} TWI_MASTER_t;
1489
1490/*
1491--------------------------------------------------------------------------
1492TWI - Two-Wire Interface
1493--------------------------------------------------------------------------
1494*/
1495
1496/*  */
1497typedef struct TWI_SLAVE_struct
1498{
1499    register8_t CTRLA;  /* Control Register A */
1500    register8_t CTRLB;  /* Control Register B */
1501    register8_t STATUS;  /* Status Register */
1502    register8_t ADDR;  /* Address Register */
1503    register8_t DATA;  /* Data Register */
1504    register8_t ADDRMASK;  /* Address Mask Register */
1505} TWI_SLAVE_t;
1506
1507/*
1508--------------------------------------------------------------------------
1509TWI - Two-Wire Interface
1510--------------------------------------------------------------------------
1511*/
1512
1513/* Two-Wire Interface */
1514typedef struct TWI_struct
1515{
1516    register8_t CTRL;  /* TWI Common Control Register */
1517    TWI_MASTER_t MASTER;  /* TWI master module */
1518    TWI_SLAVE_t SLAVE;  /* TWI slave module */
1519} TWI_t;
1520
1521/* Master Interrupt Level */
1522typedef enum TWI_MASTER_INTLVL_enum
1523{
1524    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1525    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
1526    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1527    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
1528} TWI_MASTER_INTLVL_t;
1529
1530/* Inactive Timeout */
1531typedef enum TWI_MASTER_TIMEOUT_enum
1532{
1533    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
1534    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
1535    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
1536    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
1537} TWI_MASTER_TIMEOUT_t;
1538
1539/* Master Command */
1540typedef enum TWI_MASTER_CMD_enum
1541{
1542    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
1543    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
1544    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
1545    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
1546} TWI_MASTER_CMD_t;
1547
1548/* Master Bus State */
1549typedef enum TWI_MASTER_BUSSTATE_enum
1550{
1551    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
1552    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
1553    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
1554    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
1555} TWI_MASTER_BUSSTATE_t;
1556
1557/* Slave Interrupt Level */
1558typedef enum TWI_SLAVE_INTLVL_enum
1559{
1560    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1561    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
1562    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1563    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
1564} TWI_SLAVE_INTLVL_t;
1565
1566/* Slave Command */
1567typedef enum TWI_SLAVE_CMD_enum
1568{
1569    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
1570    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
1571    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
1572} TWI_SLAVE_CMD_t;
1573
1574
1575/*
1576--------------------------------------------------------------------------
1577PORT - Port Configuration
1578--------------------------------------------------------------------------
1579*/
1580
1581/* I/O port Configuration */
1582typedef struct PORTCFG_struct
1583{
1584    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
1585    register8_t reserved_0x01;
1586    register8_t VPCTRLA;  /* Virtual Port Control Register A */
1587    register8_t VPCTRLB;  /* Virtual Port Control Register B */
1588    register8_t CLKEVOUT;  /* Clock and Event Out Register */
1589} PORTCFG_t;
1590
1591/*
1592--------------------------------------------------------------------------
1593PORT - Port Configuration
1594--------------------------------------------------------------------------
1595*/
1596
1597/* Virtual Port */
1598typedef struct VPORT_struct
1599{
1600    register8_t DIR;  /* I/O Port Data Direction */
1601    register8_t OUT;  /* I/O Port Output */
1602    register8_t IN;  /* I/O Port Input */
1603    register8_t INTFLAGS;  /* Interrupt Flag Register */
1604} VPORT_t;
1605
1606/*
1607--------------------------------------------------------------------------
1608PORT - Port Configuration
1609--------------------------------------------------------------------------
1610*/
1611
1612/* I/O Ports */
1613typedef struct PORT_struct
1614{
1615    register8_t DIR;  /* I/O Port Data Direction */
1616    register8_t DIRSET;  /* I/O Port Data Direction Set */
1617    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
1618    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
1619    register8_t OUT;  /* I/O Port Output */
1620    register8_t OUTSET;  /* I/O Port Output Set */
1621    register8_t OUTCLR;  /* I/O Port Output Clear */
1622    register8_t OUTTGL;  /* I/O Port Output Toggle */
1623    register8_t IN;  /* I/O port Input */
1624    register8_t INTCTRL;  /* Interrupt Control Register */
1625    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
1626    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
1627    register8_t INTFLAGS;  /* Interrupt Flag Register */
1628    register8_t reserved_0x0D;
1629    register8_t reserved_0x0E;
1630    register8_t reserved_0x0F;
1631    register8_t PIN0CTRL;  /* Pin 0 Control Register */
1632    register8_t PIN1CTRL;  /* Pin 1 Control Register */
1633    register8_t PIN2CTRL;  /* Pin 2 Control Register */
1634    register8_t PIN3CTRL;  /* Pin 3 Control Register */
1635    register8_t PIN4CTRL;  /* Pin 4 Control Register */
1636    register8_t PIN5CTRL;  /* Pin 5 Control Register */
1637    register8_t PIN6CTRL;  /* Pin 6 Control Register */
1638    register8_t PIN7CTRL;  /* Pin 7 Control Register */
1639} PORT_t;
1640
1641/* Virtual Port 0 Mapping */
1642typedef enum PORTCFG_VP0MAP_enum
1643{
1644    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
1645    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
1646    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
1647    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
1648    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
1649    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
1650    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
1651    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
1652    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
1653    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
1654    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
1655    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
1656    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
1657    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
1658    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
1659    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
1660} PORTCFG_VP0MAP_t;
1661
1662/* Virtual Port 1 Mapping */
1663typedef enum PORTCFG_VP1MAP_enum
1664{
1665    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
1666    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
1667    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
1668    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
1669    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
1670    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
1671    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
1672    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
1673    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
1674    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
1675    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
1676    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
1677    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
1678    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
1679    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
1680    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
1681} PORTCFG_VP1MAP_t;
1682
1683/* Virtual Port 2 Mapping */
1684typedef enum PORTCFG_VP2MAP_enum
1685{
1686    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
1687    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
1688    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
1689    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
1690    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
1691    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
1692    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
1693    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
1694    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
1695    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
1696    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
1697    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
1698    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
1699    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
1700    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
1701    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
1702} PORTCFG_VP2MAP_t;
1703
1704/* Virtual Port 3 Mapping */
1705typedef enum PORTCFG_VP3MAP_enum
1706{
1707    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
1708    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
1709    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
1710    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
1711    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
1712    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
1713    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
1714    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
1715    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
1716    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
1717    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
1718    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
1719    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
1720    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
1721    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
1722    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
1723} PORTCFG_VP3MAP_t;
1724
1725/* Clock Output Port */
1726typedef enum PORTCFG_CLKOUT_enum
1727{
1728    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
1729    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
1730    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
1731    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
1732} PORTCFG_CLKOUT_t;
1733
1734/* Event Output Port */
1735typedef enum PORTCFG_EVOUT_enum
1736{
1737    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
1738    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
1739    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
1740    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
1741} PORTCFG_EVOUT_t;
1742
1743/* Port Interrupt 0 Level */
1744typedef enum PORT_INT0LVL_enum
1745{
1746    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1747    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
1748    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
1749    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
1750} PORT_INT0LVL_t;
1751
1752/* Port Interrupt 1 Level */
1753typedef enum PORT_INT1LVL_enum
1754{
1755    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1756    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
1757    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
1758    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
1759} PORT_INT1LVL_t;
1760
1761/* Output/Pull Configuration */
1762typedef enum PORT_OPC_enum
1763{
1764    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
1765    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
1766    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
1767    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
1768    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
1769    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
1770    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
1771    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
1772} PORT_OPC_t;
1773
1774/* Input/Sense Configuration */
1775typedef enum PORT_ISC_enum
1776{
1777    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
1778    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
1779    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
1780    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
1781    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
1782} PORT_ISC_t;
1783
1784
1785/*
1786--------------------------------------------------------------------------
1787TC - 16-bit Timer/Counter With PWM
1788--------------------------------------------------------------------------
1789*/
1790
1791/* 16-bit Timer/Counter 0 */
1792typedef struct TC0_struct
1793{
1794    register8_t CTRLA;  /* Control  Register A */
1795    register8_t CTRLB;  /* Control Register B */
1796    register8_t CTRLC;  /* Control register C */
1797    register8_t CTRLD;  /* Control Register D */
1798    register8_t CTRLE;  /* Control Register E */
1799    register8_t reserved_0x05;
1800    register8_t INTCTRLA;  /* Interrupt Control Register A */
1801    register8_t INTCTRLB;  /* Interrupt Control Register B */
1802    register8_t CTRLFCLR;  /* Control Register F Clear */
1803    register8_t CTRLFSET;  /* Control Register F Set */
1804    register8_t CTRLGCLR;  /* Control Register G Clear */
1805    register8_t CTRLGSET;  /* Control Register G Set */
1806    register8_t INTFLAGS;  /* Interrupt Flag Register */
1807    register8_t reserved_0x0D;
1808    register8_t reserved_0x0E;
1809    register8_t TEMP;  /* Temporary Register For 16-bit Access */
1810    register8_t reserved_0x10;
1811    register8_t reserved_0x11;
1812    register8_t reserved_0x12;
1813    register8_t reserved_0x13;
1814    register8_t reserved_0x14;
1815    register8_t reserved_0x15;
1816    register8_t reserved_0x16;
1817    register8_t reserved_0x17;
1818    register8_t reserved_0x18;
1819    register8_t reserved_0x19;
1820    register8_t reserved_0x1A;
1821    register8_t reserved_0x1B;
1822    register8_t reserved_0x1C;
1823    register8_t reserved_0x1D;
1824    register8_t reserved_0x1E;
1825    register8_t reserved_0x1F;
1826    _WORDREGISTER(CNT);  /* Count */
1827    register8_t reserved_0x22;
1828    register8_t reserved_0x23;
1829    register8_t reserved_0x24;
1830    register8_t reserved_0x25;
1831    _WORDREGISTER(PER);  /* Period */
1832    _WORDREGISTER(CCA);  /* Compare or Capture A */
1833    _WORDREGISTER(CCB);  /* Compare or Capture B */
1834    _WORDREGISTER(CCC);  /* Compare or Capture C */
1835    _WORDREGISTER(CCD);  /* Compare or Capture D */
1836    register8_t reserved_0x30;
1837    register8_t reserved_0x31;
1838    register8_t reserved_0x32;
1839    register8_t reserved_0x33;
1840    register8_t reserved_0x34;
1841    register8_t reserved_0x35;
1842    _WORDREGISTER(PERBUF);  /* Period Buffer */
1843    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
1844    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
1845    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
1846    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
1847} TC0_t;
1848
1849/*
1850--------------------------------------------------------------------------
1851TC - 16-bit Timer/Counter With PWM
1852--------------------------------------------------------------------------
1853*/
1854
1855/* 16-bit Timer/Counter 1 */
1856typedef struct TC1_struct
1857{
1858    register8_t CTRLA;  /* Control  Register A */
1859    register8_t CTRLB;  /* Control Register B */
1860    register8_t CTRLC;  /* Control register C */
1861    register8_t CTRLD;  /* Control Register D */
1862    register8_t CTRLE;  /* Control Register E */
1863    register8_t reserved_0x05;
1864    register8_t INTCTRLA;  /* Interrupt Control Register A */
1865    register8_t INTCTRLB;  /* Interrupt Control Register B */
1866    register8_t CTRLFCLR;  /* Control Register F Clear */
1867    register8_t CTRLFSET;  /* Control Register F Set */
1868    register8_t CTRLGCLR;  /* Control Register G Clear */
1869    register8_t CTRLGSET;  /* Control Register G Set */
1870    register8_t INTFLAGS;  /* Interrupt Flag Register */
1871    register8_t reserved_0x0D;
1872    register8_t reserved_0x0E;
1873    register8_t TEMP;  /* Temporary Register For 16-bit Access */
1874    register8_t reserved_0x10;
1875    register8_t reserved_0x11;
1876    register8_t reserved_0x12;
1877    register8_t reserved_0x13;
1878    register8_t reserved_0x14;
1879    register8_t reserved_0x15;
1880    register8_t reserved_0x16;
1881    register8_t reserved_0x17;
1882    register8_t reserved_0x18;
1883    register8_t reserved_0x19;
1884    register8_t reserved_0x1A;
1885    register8_t reserved_0x1B;
1886    register8_t reserved_0x1C;
1887    register8_t reserved_0x1D;
1888    register8_t reserved_0x1E;
1889    register8_t reserved_0x1F;
1890    _WORDREGISTER(CNT);  /* Count */
1891    register8_t reserved_0x22;
1892    register8_t reserved_0x23;
1893    register8_t reserved_0x24;
1894    register8_t reserved_0x25;
1895    _WORDREGISTER(PER);  /* Period */
1896    _WORDREGISTER(CCA);  /* Compare or Capture A */
1897    _WORDREGISTER(CCB);  /* Compare or Capture B */
1898    register8_t reserved_0x2C;
1899    register8_t reserved_0x2D;
1900    register8_t reserved_0x2E;
1901    register8_t reserved_0x2F;
1902    register8_t reserved_0x30;
1903    register8_t reserved_0x31;
1904    register8_t reserved_0x32;
1905    register8_t reserved_0x33;
1906    register8_t reserved_0x34;
1907    register8_t reserved_0x35;
1908    _WORDREGISTER(PERBUF);  /* Period Buffer */
1909    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
1910    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
1911} TC1_t;
1912
1913/*
1914--------------------------------------------------------------------------
1915TC - 16-bit Timer/Counter With PWM
1916--------------------------------------------------------------------------
1917*/
1918
1919/* Advanced Waveform Extension */
1920typedef struct AWEX_struct
1921{
1922    register8_t CTRL;  /* Control Register */
1923    register8_t reserved_0x01;
1924    register8_t FDEMASK;  /* Fault Detection Event Mask */
1925    register8_t FDCTRL;  /* Fault Detection Control Register */
1926    register8_t STATUS;  /* Status Register */
1927    register8_t reserved_0x05;
1928    register8_t DTBOTH;  /* Dead Time Both Sides */
1929    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
1930    register8_t DTLS;  /* Dead Time Low Side */
1931    register8_t DTHS;  /* Dead Time High Side */
1932    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
1933    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
1934    register8_t OUTOVEN;  /* Output Override Enable */
1935} AWEX_t;
1936
1937/*
1938--------------------------------------------------------------------------
1939TC - 16-bit Timer/Counter With PWM
1940--------------------------------------------------------------------------
1941*/
1942
1943/* High-Resolution Extension */
1944typedef struct HIRES_struct
1945{
1946    register8_t CTRLA;  /* Control Register */
1947} HIRES_t;
1948
1949/* Clock Selection */
1950typedef enum TC_CLKSEL_enum
1951{
1952    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
1953    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
1954    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
1955    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
1956    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
1957    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
1958    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
1959    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
1960    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
1961    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
1962    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
1963    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
1964    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
1965    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
1966    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
1967    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
1968} TC_CLKSEL_t;
1969
1970/* Waveform Generation Mode */
1971typedef enum TC_WGMODE_enum
1972{
1973    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
1974    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
1975    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
1976    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
1977    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
1978    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
1979} TC_WGMODE_t;
1980
1981/* Event Action */
1982typedef enum TC_EVACT_enum
1983{
1984    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
1985    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
1986    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
1987    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
1988    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
1989    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
1990    TC_EVACT_FRW_gc = (0x05<<5),  /* Frequency Capture (typo in earlier header file) */
1991    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
1992} TC_EVACT_t;
1993
1994/* Event Selection */
1995typedef enum TC_EVSEL_enum
1996{
1997    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
1998    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
1999    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
2000    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
2001    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
2002    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
2003    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
2004    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
2005    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
2006} TC_EVSEL_t;
2007
2008/* Error Interrupt Level */
2009typedef enum TC_ERRINTLVL_enum
2010{
2011    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
2012    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
2013    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
2014    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
2015} TC_ERRINTLVL_t;
2016
2017/* Overflow Interrupt Level */
2018typedef enum TC_OVFINTLVL_enum
2019{
2020    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2021    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
2022    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2023    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
2024} TC_OVFINTLVL_t;
2025
2026/* Compare or Capture D Interrupt Level */
2027typedef enum TC_CCDINTLVL_enum
2028{
2029    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
2030    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
2031    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
2032    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
2033} TC_CCDINTLVL_t;
2034
2035/* Compare or Capture C Interrupt Level */
2036typedef enum TC_CCCINTLVL_enum
2037{
2038    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
2039    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
2040    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
2041    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
2042} TC_CCCINTLVL_t;
2043
2044/* Compare or Capture B Interrupt Level */
2045typedef enum TC_CCBINTLVL_enum
2046{
2047    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
2048    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
2049    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
2050    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
2051} TC_CCBINTLVL_t;
2052
2053/* Compare or Capture A Interrupt Level */
2054typedef enum TC_CCAINTLVL_enum
2055{
2056    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2057    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
2058    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2059    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
2060} TC_CCAINTLVL_t;
2061
2062/* Timer/Counter Command */
2063typedef enum TC_CMD_enum
2064{
2065    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
2066    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
2067    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
2068    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
2069} TC_CMD_t;
2070
2071/* Fault Detect Action */
2072typedef enum AWEX_FDACT_enum
2073{
2074    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
2075    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
2076    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
2077} AWEX_FDACT_t;
2078
2079/* High Resolution Enable */
2080typedef enum HIRES_HREN_enum
2081{
2082    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
2083    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
2084    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
2085    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
2086} HIRES_HREN_t;
2087
2088
2089/*
2090--------------------------------------------------------------------------
2091USART - Universal Asynchronous Receiver-Transmitter
2092--------------------------------------------------------------------------
2093*/
2094
2095/* Universal Synchronous/Asynchronous Receiver/Transmitter */
2096typedef struct USART_struct
2097{
2098    register8_t DATA;  /* Data Register */
2099    register8_t STATUS;  /* Status Register */
2100    register8_t reserved_0x02;
2101    register8_t CTRLA;  /* Control Register A */
2102    register8_t CTRLB;  /* Control Register B */
2103    register8_t CTRLC;  /* Control Register C */
2104    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
2105    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
2106} USART_t;
2107
2108/* Receive Complete Interrupt level */
2109typedef enum USART_RXCINTLVL_enum
2110{
2111    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
2112    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
2113    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
2114    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
2115} USART_RXCINTLVL_t;
2116
2117/* Transmit Complete Interrupt level */
2118typedef enum USART_TXCINTLVL_enum
2119{
2120    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
2121    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
2122    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
2123    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
2124} USART_TXCINTLVL_t;
2125
2126/* Data Register Empty Interrupt level */
2127typedef enum USART_DREINTLVL_enum
2128{
2129    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2130    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
2131    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2132    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
2133} USART_DREINTLVL_t;
2134
2135/* Character Size */
2136typedef enum USART_CHSIZE_enum
2137{
2138    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
2139    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
2140    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
2141    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
2142    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
2143} USART_CHSIZE_t;
2144
2145/* Communication Mode */
2146typedef enum USART_CMODE_enum
2147{
2148    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
2149    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
2150    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
2151    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
2152} USART_CMODE_t;
2153
2154/* Parity Mode */
2155typedef enum USART_PMODE_enum
2156{
2157    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
2158    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
2159    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
2160} USART_PMODE_t;
2161
2162
2163/*
2164--------------------------------------------------------------------------
2165SPI - Serial Peripheral Interface
2166--------------------------------------------------------------------------
2167*/
2168
2169/* Serial Peripheral Interface */
2170typedef struct SPI_struct
2171{
2172    register8_t CTRL;  /* Control Register */
2173    register8_t INTCTRL;  /* Interrupt Control Register */
2174    register8_t STATUS;  /* Status Register */
2175    register8_t DATA;  /* Data Register */
2176} SPI_t;
2177
2178/* SPI Mode */
2179typedef enum SPI_MODE_enum
2180{
2181    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
2182    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
2183    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
2184    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
2185} SPI_MODE_t;
2186
2187/* Prescaler setting */
2188typedef enum SPI_PRESCALER_enum
2189{
2190    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
2191    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
2192    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
2193    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
2194} SPI_PRESCALER_t;
2195
2196/* Interrupt level */
2197typedef enum SPI_INTLVL_enum
2198{
2199    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2200    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
2201    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2202    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
2203} SPI_INTLVL_t;
2204
2205
2206/*
2207--------------------------------------------------------------------------
2208IRCOM - IR Communication Module
2209--------------------------------------------------------------------------
2210*/
2211
2212/* IR Communication Module */
2213typedef struct IRCOM_struct
2214{
2215    register8_t CTRL;  /* Control Register */
2216    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
2217    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
2218} IRCOM_t;
2219
2220/* Event channel selection */
2221typedef enum IRDA_EVSEL_enum
2222{
2223    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
2224    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
2225    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
2226    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
2227    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
2228    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
2229    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
2230    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
2231    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
2232} IRDA_EVSEL_t;
2233
2234
2235
2236/*
2237==========================================================================
2238IO Module Instances. Mapped to memory.
2239==========================================================================
2240*/
2241
2242#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
2243#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
2244#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
2245#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
2246#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
2247#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
2248#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
2249#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
2250#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
2251#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
2252#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
2253#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
2254#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
2255#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
2256#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
2257#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
2258#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
2259#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
2260#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
2261#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
2262#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
2263#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
2264#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
2265#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
2266#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
2267#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
2268#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
2269#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
2270#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
2271#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
2272#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
2273#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
2274#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
2275#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
2276#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
2277#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
2278#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
2279#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
2280#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
2281#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
2282
2283
2284#endif /* !defined (__ASSEMBLER__) */
2285
2286
2287/* ========== Flattened fully qualified IO register names ========== */
2288
2289/* GPIO - General Purpose IO Registers */
2290#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
2291#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
2292#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
2293#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
2294#define GPIO_GPIOR4  _SFR_MEM8(0x0004)
2295#define GPIO_GPIOR5  _SFR_MEM8(0x0005)
2296#define GPIO_GPIOR6  _SFR_MEM8(0x0006)
2297#define GPIO_GPIOR7  _SFR_MEM8(0x0007)
2298#define GPIO_GPIOR8  _SFR_MEM8(0x0008)
2299#define GPIO_GPIOR9  _SFR_MEM8(0x0009)
2300#define GPIO_GPIORA  _SFR_MEM8(0x000A)
2301#define GPIO_GPIORB  _SFR_MEM8(0x000B)
2302#define GPIO_GPIORC  _SFR_MEM8(0x000C)
2303#define GPIO_GPIORD  _SFR_MEM8(0x000D)
2304#define GPIO_GPIORE  _SFR_MEM8(0x000E)
2305#define GPIO_GPIORF  _SFR_MEM8(0x000F)
2306
2307/* Deprecated */
2308#define GPIO_GPIO0  _SFR_MEM8(0x0000)
2309#define GPIO_GPIO1  _SFR_MEM8(0x0001)
2310#define GPIO_GPIO2  _SFR_MEM8(0x0002)
2311#define GPIO_GPIO3  _SFR_MEM8(0x0003)
2312#define GPIO_GPIO4  _SFR_MEM8(0x0004)
2313#define GPIO_GPIO5  _SFR_MEM8(0x0005)
2314#define GPIO_GPIO6  _SFR_MEM8(0x0006)
2315#define GPIO_GPIO7  _SFR_MEM8(0x0007)
2316#define GPIO_GPIO8  _SFR_MEM8(0x0008)
2317#define GPIO_GPIO9  _SFR_MEM8(0x0009)
2318#define GPIO_GPIOA  _SFR_MEM8(0x000A)
2319#define GPIO_GPIOB  _SFR_MEM8(0x000B)
2320#define GPIO_GPIOC  _SFR_MEM8(0x000C)
2321#define GPIO_GPIOD  _SFR_MEM8(0x000D)
2322#define GPIO_GPIOE  _SFR_MEM8(0x000E)
2323#define GPIO_GPIOF  _SFR_MEM8(0x000F)
2324
2325/* VPORT0 - Virtual Port 0 */
2326#define VPORT0_DIR  _SFR_MEM8(0x0010)
2327#define VPORT0_OUT  _SFR_MEM8(0x0011)
2328#define VPORT0_IN  _SFR_MEM8(0x0012)
2329#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
2330
2331/* VPORT1 - Virtual Port 1 */
2332#define VPORT1_DIR  _SFR_MEM8(0x0014)
2333#define VPORT1_OUT  _SFR_MEM8(0x0015)
2334#define VPORT1_IN  _SFR_MEM8(0x0016)
2335#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
2336
2337/* VPORT2 - Virtual Port 2 */
2338#define VPORT2_DIR  _SFR_MEM8(0x0018)
2339#define VPORT2_OUT  _SFR_MEM8(0x0019)
2340#define VPORT2_IN  _SFR_MEM8(0x001A)
2341#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
2342
2343/* VPORT3 - Virtual Port 3 */
2344#define VPORT3_DIR  _SFR_MEM8(0x001C)
2345#define VPORT3_OUT  _SFR_MEM8(0x001D)
2346#define VPORT3_IN  _SFR_MEM8(0x001E)
2347#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
2348
2349/* OCD - On-Chip Debug System */
2350#define OCD_OCDR0  _SFR_MEM8(0x002E)
2351#define OCD_OCDR1  _SFR_MEM8(0x002F)
2352
2353/* CPU - CPU Registers */
2354#define CPU_CCP  _SFR_MEM8(0x0034)
2355#define CPU_RAMPD  _SFR_MEM8(0x0038)
2356#define CPU_RAMPX  _SFR_MEM8(0x0039)
2357#define CPU_RAMPY  _SFR_MEM8(0x003A)
2358#define CPU_RAMPZ  _SFR_MEM8(0x003B)
2359#define CPU_EIND  _SFR_MEM8(0x003C)
2360#define CPU_SPL  _SFR_MEM8(0x003D)
2361#define CPU_SPH  _SFR_MEM8(0x003E)
2362#define CPU_SREG  _SFR_MEM8(0x003F)
2363
2364/* CLK - Clock System */
2365#define CLK_CTRL  _SFR_MEM8(0x0040)
2366#define CLK_PSCTRL  _SFR_MEM8(0x0041)
2367#define CLK_LOCK  _SFR_MEM8(0x0042)
2368#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
2369
2370/* SLEEP - Sleep Controller */
2371#define SLEEP_CTRL  _SFR_MEM8(0x0048)
2372
2373/* OSC - Oscillator Control */
2374#define OSC_CTRL  _SFR_MEM8(0x0050)
2375#define OSC_STATUS  _SFR_MEM8(0x0051)
2376#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
2377#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
2378#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
2379#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
2380#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
2381
2382/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
2383#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
2384#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
2385#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
2386#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
2387#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
2388#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
2389
2390/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
2391#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
2392#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
2393#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
2394#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
2395#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
2396#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
2397
2398/* PR - Power Reduction */
2399#define PR_PRGEN  _SFR_MEM8(0x0070)
2400#define PR_PRPA  _SFR_MEM8(0x0071)
2401#define PR_PRPB  _SFR_MEM8(0x0072)
2402#define PR_PRPC  _SFR_MEM8(0x0073)
2403#define PR_PRPD  _SFR_MEM8(0x0074)
2404#define PR_PRPE  _SFR_MEM8(0x0075)
2405#define PR_PRPF  _SFR_MEM8(0x0076)
2406
2407/* RST - Reset Controller */
2408#define RST_STATUS  _SFR_MEM8(0x0078)
2409#define RST_CTRL  _SFR_MEM8(0x0079)
2410
2411/* WDT - Watch-Dog Timer */
2412#define WDT_CTRL  _SFR_MEM8(0x0080)
2413#define WDT_WINCTRL  _SFR_MEM8(0x0081)
2414#define WDT_STATUS  _SFR_MEM8(0x0082)
2415
2416/* MCU - MCU Control */
2417#define MCU_DEVID0  _SFR_MEM8(0x0090)
2418#define MCU_DEVID1  _SFR_MEM8(0x0091)
2419#define MCU_DEVID2  _SFR_MEM8(0x0092)
2420#define MCU_REVID  _SFR_MEM8(0x0093)
2421#define MCU_JTAGUID  _SFR_MEM8(0x0094)
2422#define MCU_MCUCR  _SFR_MEM8(0x0096)
2423#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
2424#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
2425
2426/* PMIC - Programmable Interrupt Controller */
2427#define PMIC_STATUS  _SFR_MEM8(0x00A0)
2428#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
2429#define PMIC_CTRL  _SFR_MEM8(0x00A2)
2430
2431/* PORTCFG - Port Configuration */
2432#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
2433#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
2434#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
2435#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
2436
2437/* EVSYS - Event System */
2438#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
2439#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
2440#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
2441#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
2442#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
2443#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
2444#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
2445#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
2446#define EVSYS_STROBE  _SFR_MEM8(0x0190)
2447#define EVSYS_DATA  _SFR_MEM8(0x0191)
2448
2449/* NVM - Non Volatile Memory Controller */
2450#define NVM_ADDR0  _SFR_MEM8(0x01C0)
2451#define NVM_ADDR1  _SFR_MEM8(0x01C1)
2452#define NVM_ADDR2  _SFR_MEM8(0x01C2)
2453#define NVM_DATA0  _SFR_MEM8(0x01C4)
2454#define NVM_DATA1  _SFR_MEM8(0x01C5)
2455#define NVM_DATA2  _SFR_MEM8(0x01C6)
2456#define NVM_CMD  _SFR_MEM8(0x01CA)
2457#define NVM_CTRLA  _SFR_MEM8(0x01CB)
2458#define NVM_CTRLB  _SFR_MEM8(0x01CC)
2459#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
2460#define NVM_STATUS  _SFR_MEM8(0x01CF)
2461#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
2462
2463/* ADCA - Analog to Digital Converter A */
2464#define ADCA_CTRLA  _SFR_MEM8(0x0200)
2465#define ADCA_CTRLB  _SFR_MEM8(0x0201)
2466#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
2467#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
2468#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
2469#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
2470#define ADCA_CAL  _SFR_MEM16(0x020C)
2471#define ADCA_CH0RES  _SFR_MEM16(0x0210)
2472#define ADCA_CMP  _SFR_MEM16(0x0218)
2473#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
2474#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
2475#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
2476#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
2477#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
2478
2479/* ACA - Analog Comparator A */
2480#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
2481#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
2482#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
2483#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
2484#define ACA_CTRLA  _SFR_MEM8(0x0384)
2485#define ACA_CTRLB  _SFR_MEM8(0x0385)
2486#define ACA_WINCTRL  _SFR_MEM8(0x0386)
2487#define ACA_STATUS  _SFR_MEM8(0x0387)
2488
2489/* RTC - Real-Time Counter */
2490#define RTC_CTRL  _SFR_MEM8(0x0400)
2491#define RTC_STATUS  _SFR_MEM8(0x0401)
2492#define RTC_INTCTRL  _SFR_MEM8(0x0402)
2493#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
2494#define RTC_TEMP  _SFR_MEM8(0x0404)
2495#define RTC_CNT  _SFR_MEM16(0x0408)
2496#define RTC_PER  _SFR_MEM16(0x040A)
2497#define RTC_COMP  _SFR_MEM16(0x040C)
2498
2499/* TWIC - Two-Wire Interface C */
2500#define TWIC_CTRL  _SFR_MEM8(0x0480)
2501#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
2502#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
2503#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
2504#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
2505#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
2506#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
2507#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
2508#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
2509#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
2510#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
2511#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
2512#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
2513#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
2514
2515/* TWIE - Two-Wire Interface E */
2516#define TWIE_CTRL  _SFR_MEM8(0x04A0)
2517#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
2518#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
2519#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
2520#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
2521#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
2522#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
2523#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
2524#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
2525#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
2526#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
2527#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
2528#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
2529#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
2530
2531
2532/* PORTA - Port A */
2533#define PORTA_DIR  _SFR_MEM8(0x0600)
2534#define PORTA_DIRSET  _SFR_MEM8(0x0601)
2535#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
2536#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
2537#define PORTA_OUT  _SFR_MEM8(0x0604)
2538#define PORTA_OUTSET  _SFR_MEM8(0x0605)
2539#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
2540#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
2541#define PORTA_IN  _SFR_MEM8(0x0608)
2542#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
2543#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
2544#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
2545#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
2546#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
2547#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
2548#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
2549#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
2550#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
2551#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
2552#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
2553#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
2554
2555/* PORTB - Port B */
2556#define PORTB_DIR  _SFR_MEM8(0x0620)
2557#define PORTB_DIRSET  _SFR_MEM8(0x0621)
2558#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
2559#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
2560#define PORTB_OUT  _SFR_MEM8(0x0624)
2561#define PORTB_OUTSET  _SFR_MEM8(0x0625)
2562#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
2563#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
2564#define PORTB_IN  _SFR_MEM8(0x0628)
2565#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
2566#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
2567#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
2568#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
2569#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
2570#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
2571#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
2572#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
2573#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
2574#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
2575#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
2576#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
2577
2578/* PORTC - Port C */
2579#define PORTC_DIR  _SFR_MEM8(0x0640)
2580#define PORTC_DIRSET  _SFR_MEM8(0x0641)
2581#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
2582#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
2583#define PORTC_OUT  _SFR_MEM8(0x0644)
2584#define PORTC_OUTSET  _SFR_MEM8(0x0645)
2585#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
2586#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
2587#define PORTC_IN  _SFR_MEM8(0x0648)
2588#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
2589#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
2590#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
2591#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
2592#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
2593#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
2594#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
2595#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
2596#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
2597#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
2598#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
2599#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
2600
2601/* PORTD - Port D */
2602#define PORTD_DIR  _SFR_MEM8(0x0660)
2603#define PORTD_DIRSET  _SFR_MEM8(0x0661)
2604#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
2605#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
2606#define PORTD_OUT  _SFR_MEM8(0x0664)
2607#define PORTD_OUTSET  _SFR_MEM8(0x0665)
2608#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
2609#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
2610#define PORTD_IN  _SFR_MEM8(0x0668)
2611#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
2612#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
2613#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
2614#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
2615#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
2616#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
2617#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
2618#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
2619#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
2620#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
2621#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
2622#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
2623
2624/* PORTE - Port E */
2625#define PORTE_DIR  _SFR_MEM8(0x0680)
2626#define PORTE_DIRSET  _SFR_MEM8(0x0681)
2627#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
2628#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
2629#define PORTE_OUT  _SFR_MEM8(0x0684)
2630#define PORTE_OUTSET  _SFR_MEM8(0x0685)
2631#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
2632#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
2633#define PORTE_IN  _SFR_MEM8(0x0688)
2634#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
2635#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
2636#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
2637#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
2638#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
2639#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
2640#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
2641#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
2642#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
2643#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
2644#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
2645#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
2646
2647/* PORTR - Port R */
2648#define PORTR_DIR  _SFR_MEM8(0x07E0)
2649#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
2650#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
2651#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
2652#define PORTR_OUT  _SFR_MEM8(0x07E4)
2653#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
2654#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
2655#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
2656#define PORTR_IN  _SFR_MEM8(0x07E8)
2657#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
2658#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
2659#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
2660#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
2661#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
2662#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
2663#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
2664#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
2665#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
2666#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
2667#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
2668#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
2669
2670/* TCC0 - Timer/Counter C0 */
2671#define TCC0_CTRLA  _SFR_MEM8(0x0800)
2672#define TCC0_CTRLB  _SFR_MEM8(0x0801)
2673#define TCC0_CTRLC  _SFR_MEM8(0x0802)
2674#define TCC0_CTRLD  _SFR_MEM8(0x0803)
2675#define TCC0_CTRLE  _SFR_MEM8(0x0804)
2676#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
2677#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
2678#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
2679#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
2680#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
2681#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
2682#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
2683#define TCC0_TEMP  _SFR_MEM8(0x080F)
2684#define TCC0_CNT  _SFR_MEM16(0x0820)
2685#define TCC0_PER  _SFR_MEM16(0x0826)
2686#define TCC0_CCA  _SFR_MEM16(0x0828)
2687#define TCC0_CCB  _SFR_MEM16(0x082A)
2688#define TCC0_CCC  _SFR_MEM16(0x082C)
2689#define TCC0_CCD  _SFR_MEM16(0x082E)
2690#define TCC0_PERBUF  _SFR_MEM16(0x0836)
2691#define TCC0_CCABUF  _SFR_MEM16(0x0838)
2692#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
2693#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
2694#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
2695
2696/* TCC1 - Timer/Counter C1 */
2697#define TCC1_CTRLA  _SFR_MEM8(0x0840)
2698#define TCC1_CTRLB  _SFR_MEM8(0x0841)
2699#define TCC1_CTRLC  _SFR_MEM8(0x0842)
2700#define TCC1_CTRLD  _SFR_MEM8(0x0843)
2701#define TCC1_CTRLE  _SFR_MEM8(0x0844)
2702#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
2703#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
2704#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
2705#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
2706#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
2707#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
2708#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
2709#define TCC1_TEMP  _SFR_MEM8(0x084F)
2710#define TCC1_CNT  _SFR_MEM16(0x0860)
2711#define TCC1_PER  _SFR_MEM16(0x0866)
2712#define TCC1_CCA  _SFR_MEM16(0x0868)
2713#define TCC1_CCB  _SFR_MEM16(0x086A)
2714#define TCC1_PERBUF  _SFR_MEM16(0x0876)
2715#define TCC1_CCABUF  _SFR_MEM16(0x0878)
2716#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
2717
2718/* AWEXC - Advanced Waveform Extension C */
2719#define AWEXC_CTRL  _SFR_MEM8(0x0880)
2720#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
2721#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
2722#define AWEXC_STATUS  _SFR_MEM8(0x0884)
2723#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
2724#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
2725#define AWEXC_DTLS  _SFR_MEM8(0x0888)
2726#define AWEXC_DTHS  _SFR_MEM8(0x0889)
2727#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
2728#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
2729#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
2730
2731/* HIRESC - High-Resolution Extension C */
2732#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
2733
2734/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
2735#define USARTC0_DATA  _SFR_MEM8(0x08A0)
2736#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
2737#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
2738#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
2739#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
2740#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
2741#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
2742
2743/* SPIC - Serial Peripheral Interface C */
2744#define SPIC_CTRL  _SFR_MEM8(0x08C0)
2745#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
2746#define SPIC_STATUS  _SFR_MEM8(0x08C2)
2747#define SPIC_DATA  _SFR_MEM8(0x08C3)
2748
2749/* IRCOM - IR Communication Module */
2750#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
2751#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
2752#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
2753
2754/* TCD0 - Timer/Counter D0 */
2755#define TCD0_CTRLA  _SFR_MEM8(0x0900)
2756#define TCD0_CTRLB  _SFR_MEM8(0x0901)
2757#define TCD0_CTRLC  _SFR_MEM8(0x0902)
2758#define TCD0_CTRLD  _SFR_MEM8(0x0903)
2759#define TCD0_CTRLE  _SFR_MEM8(0x0904)
2760#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
2761#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
2762#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
2763#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
2764#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
2765#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
2766#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
2767#define TCD0_TEMP  _SFR_MEM8(0x090F)
2768#define TCD0_CNT  _SFR_MEM16(0x0920)
2769#define TCD0_PER  _SFR_MEM16(0x0926)
2770#define TCD0_CCA  _SFR_MEM16(0x0928)
2771#define TCD0_CCB  _SFR_MEM16(0x092A)
2772#define TCD0_CCC  _SFR_MEM16(0x092C)
2773#define TCD0_CCD  _SFR_MEM16(0x092E)
2774#define TCD0_PERBUF  _SFR_MEM16(0x0936)
2775#define TCD0_CCABUF  _SFR_MEM16(0x0938)
2776#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
2777#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
2778#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
2779
2780/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
2781#define USARTD0_DATA  _SFR_MEM8(0x09A0)
2782#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
2783#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
2784#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
2785#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
2786#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
2787#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
2788
2789/* SPID - Serial Peripheral Interface D */
2790#define SPID_CTRL  _SFR_MEM8(0x09C0)
2791#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
2792#define SPID_STATUS  _SFR_MEM8(0x09C2)
2793#define SPID_DATA  _SFR_MEM8(0x09C3)
2794
2795/* TCE0 - Timer/Counter E0 */
2796#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
2797#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
2798#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
2799#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
2800#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
2801#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
2802#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
2803#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
2804#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
2805#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
2806#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
2807#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
2808#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
2809#define TCE0_CNT  _SFR_MEM16(0x0A20)
2810#define TCE0_PER  _SFR_MEM16(0x0A26)
2811#define TCE0_CCA  _SFR_MEM16(0x0A28)
2812#define TCE0_CCB  _SFR_MEM16(0x0A2A)
2813#define TCE0_CCC  _SFR_MEM16(0x0A2C)
2814#define TCE0_CCD  _SFR_MEM16(0x0A2E)
2815#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
2816#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
2817#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
2818#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
2819#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
2820
2821
2822
2823/*================== Bitfield Definitions ================== */
2824
2825/* XOCD - On-Chip Debug System */
2826/* OCD.OCDR1  bit masks and bit positions */
2827#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
2828#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
2829
2830
2831/* CPU - CPU */
2832/* CPU.CCP  bit masks and bit positions */
2833#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
2834#define CPU_CCP_gp  0  /* CCP signature group position. */
2835#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
2836#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
2837#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
2838#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
2839#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
2840#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
2841#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
2842#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
2843#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
2844#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
2845#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
2846#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
2847#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
2848#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
2849#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
2850#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
2851
2852
2853/* CPU.SREG  bit masks and bit positions */
2854#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
2855#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
2856
2857#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
2858#define CPU_T_bp  6  /* Transfer Bit bit position. */
2859
2860#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
2861#define CPU_H_bp  5  /* Half Carry Flag bit position. */
2862
2863#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
2864#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
2865
2866#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
2867#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
2868
2869#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
2870#define CPU_N_bp  2  /* Negative Flag bit position. */
2871
2872#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
2873#define CPU_Z_bp  1  /* Zero Flag bit position. */
2874
2875#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
2876#define CPU_C_bp  0  /* Carry Flag bit position. */
2877
2878
2879/* CLK - Clock System */
2880/* CLK.CTRL  bit masks and bit positions */
2881#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
2882#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
2883#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
2884#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
2885#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
2886#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
2887#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
2888#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
2889
2890
2891/* CLK.PSCTRL  bit masks and bit positions */
2892#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
2893#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
2894#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
2895#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
2896#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
2897#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
2898#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
2899#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
2900#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
2901#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
2902#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
2903#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
2904
2905#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
2906#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
2907#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
2908#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
2909#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
2910#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
2911
2912
2913/* CLK.LOCK  bit masks and bit positions */
2914#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
2915#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
2916
2917
2918/* CLK.RTCCTRL  bit masks and bit positions */
2919#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
2920#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
2921#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
2922#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
2923#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
2924#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
2925#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
2926#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
2927
2928#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
2929#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
2930
2931
2932/* PR.PRGEN  bit masks and bit positions */
2933#define PR_AES_bm  0x10  /* AES bit mask. */
2934#define PR_AES_bp  4  /* AES bit position. */
2935
2936#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
2937#define PR_EBI_bp  3  /* External Bus Interface bit position. */
2938
2939#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
2940#define PR_RTC_bp  2  /* Real-time Counter bit position. */
2941
2942#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
2943#define PR_EVSYS_bp  1  /* Event System bit position. */
2944
2945#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
2946#define PR_DMA_bp  0  /* DMA-Controller bit position. */
2947
2948
2949/* PR.PRPA  bit masks and bit positions */
2950#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
2951#define PR_DAC_bp  2  /* Port A DAC bit position. */
2952
2953#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
2954#define PR_ADC_bp  1  /* Port A ADC bit position. */
2955
2956#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
2957#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
2958
2959
2960/* PR.PRPB  bit masks and bit positions */
2961/* PR_DAC_bm  Predefined. */
2962/* PR_DAC_bp  Predefined. */
2963
2964/* PR_ADC_bm  Predefined. */
2965/* PR_ADC_bp  Predefined. */
2966
2967/* PR_AC_bm  Predefined. */
2968/* PR_AC_bp  Predefined. */
2969
2970
2971/* PR.PRPC  bit masks and bit positions */
2972#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
2973#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
2974
2975#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
2976#define PR_USART1_bp  5  /* Port C USART1 bit position. */
2977
2978#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
2979#define PR_USART0_bp  4  /* Port C USART0 bit position. */
2980
2981#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
2982#define PR_SPI_bp  3  /* Port C SPI bit position. */
2983
2984#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
2985#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
2986
2987#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
2988#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
2989
2990#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
2991#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
2992
2993
2994/* PR.PRPD  bit masks and bit positions */
2995/* PR_TWI_bm  Predefined. */
2996/* PR_TWI_bp  Predefined. */
2997
2998/* PR_USART1_bm  Predefined. */
2999/* PR_USART1_bp  Predefined. */
3000
3001/* PR_USART0_bm  Predefined. */
3002/* PR_USART0_bp  Predefined. */
3003
3004/* PR_SPI_bm  Predefined. */
3005/* PR_SPI_bp  Predefined. */
3006
3007/* PR_HIRES_bm  Predefined. */
3008/* PR_HIRES_bp  Predefined. */
3009
3010/* PR_TC1_bm  Predefined. */
3011/* PR_TC1_bp  Predefined. */
3012
3013/* PR_TC0_bm  Predefined. */
3014/* PR_TC0_bp  Predefined. */
3015
3016
3017/* PR.PRPE  bit masks and bit positions */
3018/* PR_TWI_bm  Predefined. */
3019/* PR_TWI_bp  Predefined. */
3020
3021/* PR_USART1_bm  Predefined. */
3022/* PR_USART1_bp  Predefined. */
3023
3024/* PR_USART0_bm  Predefined. */
3025/* PR_USART0_bp  Predefined. */
3026
3027/* PR_SPI_bm  Predefined. */
3028/* PR_SPI_bp  Predefined. */
3029
3030/* PR_HIRES_bm  Predefined. */
3031/* PR_HIRES_bp  Predefined. */
3032
3033/* PR_TC1_bm  Predefined. */
3034/* PR_TC1_bp  Predefined. */
3035
3036/* PR_TC0_bm  Predefined. */
3037/* PR_TC0_bp  Predefined. */
3038
3039
3040/* PR.PRPF  bit masks and bit positions */
3041/* PR_TWI_bm  Predefined. */
3042/* PR_TWI_bp  Predefined. */
3043
3044/* PR_USART1_bm  Predefined. */
3045/* PR_USART1_bp  Predefined. */
3046
3047/* PR_USART0_bm  Predefined. */
3048/* PR_USART0_bp  Predefined. */
3049
3050/* PR_SPI_bm  Predefined. */
3051/* PR_SPI_bp  Predefined. */
3052
3053/* PR_HIRES_bm  Predefined. */
3054/* PR_HIRES_bp  Predefined. */
3055
3056/* PR_TC1_bm  Predefined. */
3057/* PR_TC1_bp  Predefined. */
3058
3059/* PR_TC0_bm  Predefined. */
3060/* PR_TC0_bp  Predefined. */
3061
3062
3063/* SLEEP - Sleep Controller */
3064/* SLEEP.CTRL  bit masks and bit positions */
3065#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
3066#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
3067#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
3068#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
3069#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
3070#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
3071#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
3072#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
3073
3074#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
3075#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
3076
3077
3078/* OSC - Oscillator */
3079/* OSC.CTRL  bit masks and bit positions */
3080#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
3081#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
3082
3083#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
3084#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
3085
3086#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
3087#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
3088
3089#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
3090#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
3091
3092#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
3093#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
3094
3095
3096/* OSC.STATUS  bit masks and bit positions */
3097#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
3098#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
3099
3100#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
3101#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
3102
3103#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
3104#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
3105
3106#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
3107#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
3108
3109#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
3110#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
3111
3112
3113/* OSC.XOSCCTRL  bit masks and bit positions */
3114#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
3115#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
3116#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
3117#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
3118#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
3119#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
3120
3121#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
3122#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
3123
3124#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
3125#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
3126#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
3127#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
3128#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
3129#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
3130#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
3131#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
3132#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
3133#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
3134
3135
3136/* OSC.XOSCFAIL  bit masks and bit positions */
3137#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
3138#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
3139
3140#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
3141#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
3142
3143
3144/* OSC.PLLCTRL  bit masks and bit positions */
3145#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
3146#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
3147#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
3148#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
3149#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
3150#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
3151
3152#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
3153#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
3154#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
3155#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
3156#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
3157#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
3158#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
3159#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
3160#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
3161#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
3162#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
3163#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
3164
3165
3166/* OSC.DFLLCTRL  bit masks and bit positions */
3167#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
3168#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
3169
3170#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
3171#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
3172
3173
3174/* DFLL - DFLL */
3175/* DFLL.CTRL  bit masks and bit positions */
3176#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
3177#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
3178
3179
3180/* DFLL.CALA  bit masks and bit positions */
3181#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
3182#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
3183#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
3184#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
3185#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
3186#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
3187#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
3188#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
3189#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
3190#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
3191#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
3192#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
3193#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
3194#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
3195#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
3196#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
3197
3198
3199/* DFLL.CALB  bit masks and bit positions */
3200#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
3201#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
3202#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
3203#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
3204#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
3205#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
3206#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
3207#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
3208#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
3209#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
3210#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
3211#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
3212#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
3213#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
3214
3215
3216/* RST - Reset */
3217/* RST.STATUS  bit masks and bit positions */
3218#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
3219#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
3220
3221#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
3222#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
3223
3224#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
3225#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
3226
3227#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
3228#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
3229
3230#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
3231#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
3232
3233#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
3234#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
3235
3236#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
3237#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
3238
3239
3240/* RST.CTRL  bit masks and bit positions */
3241#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
3242#define RST_SWRST_bp  0  /* Software Reset bit position. */
3243
3244
3245/* WDT - Watch-Dog Timer */
3246/* WDT.CTRL  bit masks and bit positions */
3247#define WDT_PER_gm  0x3C  /* Period group mask. */
3248#define WDT_PER_gp  2  /* Period group position. */
3249#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
3250#define WDT_PER0_bp  2  /* Period bit 0 position. */
3251#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
3252#define WDT_PER1_bp  3  /* Period bit 1 position. */
3253#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
3254#define WDT_PER2_bp  4  /* Period bit 2 position. */
3255#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
3256#define WDT_PER3_bp  5  /* Period bit 3 position. */
3257
3258#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
3259#define WDT_ENABLE_bp  1  /* Enable bit position. */
3260
3261#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
3262#define WDT_CEN_bp  0  /* Change Enable bit position. */
3263
3264
3265/* WDT.WINCTRL  bit masks and bit positions */
3266#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
3267#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
3268#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
3269#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
3270#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
3271#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
3272#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
3273#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
3274#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
3275#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
3276
3277#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
3278#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
3279
3280#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
3281#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
3282
3283
3284/* WDT.STATUS  bit masks and bit positions */
3285#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
3286#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
3287
3288
3289/* MCU - MCU Control */
3290/* MCU.MCUCR  bit masks and bit positions */
3291#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
3292#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
3293
3294
3295/* MCU.EVSYSLOCK  bit masks and bit positions */
3296#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
3297#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
3298
3299#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
3300#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
3301
3302
3303/* MCU.AWEXLOCK  bit masks and bit positions */
3304#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
3305#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
3306
3307#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
3308#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
3309
3310
3311/* PMIC - Programmable Multi-level Interrupt Controller */
3312/* PMIC.STATUS  bit masks and bit positions */
3313#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
3314#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
3315
3316#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
3317#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
3318
3319#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
3320#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
3321
3322#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
3323#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
3324
3325
3326/* PMIC.CTRL  bit masks and bit positions */
3327#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
3328#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
3329
3330#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
3331#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
3332
3333#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
3334#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
3335
3336#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
3337#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
3338
3339#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
3340#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
3341
3342
3343/* EVSYS - Event System */
3344/* EVSYS.CH0MUX  bit masks and bit positions */
3345#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
3346#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
3347#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
3348#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
3349#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
3350#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
3351#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
3352#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
3353#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
3354#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
3355#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
3356#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
3357#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
3358#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
3359#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
3360#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
3361#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
3362#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
3363
3364
3365/* EVSYS.CH1MUX  bit masks and bit positions */
3366/* EVSYS_CHMUX_gm  Predefined. */
3367/* EVSYS_CHMUX_gp  Predefined. */
3368/* EVSYS_CHMUX0_bm  Predefined. */
3369/* EVSYS_CHMUX0_bp  Predefined. */
3370/* EVSYS_CHMUX1_bm  Predefined. */
3371/* EVSYS_CHMUX1_bp  Predefined. */
3372/* EVSYS_CHMUX2_bm  Predefined. */
3373/* EVSYS_CHMUX2_bp  Predefined. */
3374/* EVSYS_CHMUX3_bm  Predefined. */
3375/* EVSYS_CHMUX3_bp  Predefined. */
3376/* EVSYS_CHMUX4_bm  Predefined. */
3377/* EVSYS_CHMUX4_bp  Predefined. */
3378/* EVSYS_CHMUX5_bm  Predefined. */
3379/* EVSYS_CHMUX5_bp  Predefined. */
3380/* EVSYS_CHMUX6_bm  Predefined. */
3381/* EVSYS_CHMUX6_bp  Predefined. */
3382/* EVSYS_CHMUX7_bm  Predefined. */
3383/* EVSYS_CHMUX7_bp  Predefined. */
3384
3385
3386/* EVSYS.CH2MUX  bit masks and bit positions */
3387/* EVSYS_CHMUX_gm  Predefined. */
3388/* EVSYS_CHMUX_gp  Predefined. */
3389/* EVSYS_CHMUX0_bm  Predefined. */
3390/* EVSYS_CHMUX0_bp  Predefined. */
3391/* EVSYS_CHMUX1_bm  Predefined. */
3392/* EVSYS_CHMUX1_bp  Predefined. */
3393/* EVSYS_CHMUX2_bm  Predefined. */
3394/* EVSYS_CHMUX2_bp  Predefined. */
3395/* EVSYS_CHMUX3_bm  Predefined. */
3396/* EVSYS_CHMUX3_bp  Predefined. */
3397/* EVSYS_CHMUX4_bm  Predefined. */
3398/* EVSYS_CHMUX4_bp  Predefined. */
3399/* EVSYS_CHMUX5_bm  Predefined. */
3400/* EVSYS_CHMUX5_bp  Predefined. */
3401/* EVSYS_CHMUX6_bm  Predefined. */
3402/* EVSYS_CHMUX6_bp  Predefined. */
3403/* EVSYS_CHMUX7_bm  Predefined. */
3404/* EVSYS_CHMUX7_bp  Predefined. */
3405
3406
3407/* EVSYS.CH3MUX  bit masks and bit positions */
3408/* EVSYS_CHMUX_gm  Predefined. */
3409/* EVSYS_CHMUX_gp  Predefined. */
3410/* EVSYS_CHMUX0_bm  Predefined. */
3411/* EVSYS_CHMUX0_bp  Predefined. */
3412/* EVSYS_CHMUX1_bm  Predefined. */
3413/* EVSYS_CHMUX1_bp  Predefined. */
3414/* EVSYS_CHMUX2_bm  Predefined. */
3415/* EVSYS_CHMUX2_bp  Predefined. */
3416/* EVSYS_CHMUX3_bm  Predefined. */
3417/* EVSYS_CHMUX3_bp  Predefined. */
3418/* EVSYS_CHMUX4_bm  Predefined. */
3419/* EVSYS_CHMUX4_bp  Predefined. */
3420/* EVSYS_CHMUX5_bm  Predefined. */
3421/* EVSYS_CHMUX5_bp  Predefined. */
3422/* EVSYS_CHMUX6_bm  Predefined. */
3423/* EVSYS_CHMUX6_bp  Predefined. */
3424/* EVSYS_CHMUX7_bm  Predefined. */
3425/* EVSYS_CHMUX7_bp  Predefined. */
3426
3427
3428/* EVSYS.CH0CTRL  bit masks and bit positions */
3429#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
3430#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
3431#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
3432#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
3433#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
3434#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
3435
3436#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
3437#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
3438
3439#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
3440#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
3441
3442#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
3443#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
3444#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
3445#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
3446#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
3447#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
3448#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
3449#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
3450
3451
3452/* EVSYS.CH1CTRL  bit masks and bit positions */
3453/* EVSYS_DIGFILT_gm  Predefined. */
3454/* EVSYS_DIGFILT_gp  Predefined. */
3455/* EVSYS_DIGFILT0_bm  Predefined. */
3456/* EVSYS_DIGFILT0_bp  Predefined. */
3457/* EVSYS_DIGFILT1_bm  Predefined. */
3458/* EVSYS_DIGFILT1_bp  Predefined. */
3459/* EVSYS_DIGFILT2_bm  Predefined. */
3460/* EVSYS_DIGFILT2_bp  Predefined. */
3461
3462
3463/* EVSYS.CH2CTRL  bit masks and bit positions */
3464/* EVSYS_QDIRM_gm  Predefined. */
3465/* EVSYS_QDIRM_gp  Predefined. */
3466/* EVSYS_QDIRM0_bm  Predefined. */
3467/* EVSYS_QDIRM0_bp  Predefined. */
3468/* EVSYS_QDIRM1_bm  Predefined. */
3469/* EVSYS_QDIRM1_bp  Predefined. */
3470
3471/* EVSYS_QDIEN_bm  Predefined. */
3472/* EVSYS_QDIEN_bp  Predefined. */
3473
3474/* EVSYS_QDEN_bm  Predefined. */
3475/* EVSYS_QDEN_bp  Predefined. */
3476
3477/* EVSYS_DIGFILT_gm  Predefined. */
3478/* EVSYS_DIGFILT_gp  Predefined. */
3479/* EVSYS_DIGFILT0_bm  Predefined. */
3480/* EVSYS_DIGFILT0_bp  Predefined. */
3481/* EVSYS_DIGFILT1_bm  Predefined. */
3482/* EVSYS_DIGFILT1_bp  Predefined. */
3483/* EVSYS_DIGFILT2_bm  Predefined. */
3484/* EVSYS_DIGFILT2_bp  Predefined. */
3485
3486
3487/* EVSYS.CH3CTRL  bit masks and bit positions */
3488/* EVSYS_DIGFILT_gm  Predefined. */
3489/* EVSYS_DIGFILT_gp  Predefined. */
3490/* EVSYS_DIGFILT0_bm  Predefined. */
3491/* EVSYS_DIGFILT0_bp  Predefined. */
3492/* EVSYS_DIGFILT1_bm  Predefined. */
3493/* EVSYS_DIGFILT1_bp  Predefined. */
3494/* EVSYS_DIGFILT2_bm  Predefined. */
3495/* EVSYS_DIGFILT2_bp  Predefined. */
3496
3497
3498/* NVM - Non Volatile Memory Controller */
3499/* NVM.CMD  bit masks and bit positions */
3500#define NVM_CMD_gm  0xFF  /* Command group mask. */
3501#define NVM_CMD_gp  0  /* Command group position. */
3502#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
3503#define NVM_CMD0_bp  0  /* Command bit 0 position. */
3504#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
3505#define NVM_CMD1_bp  1  /* Command bit 1 position. */
3506#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
3507#define NVM_CMD2_bp  2  /* Command bit 2 position. */
3508#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
3509#define NVM_CMD3_bp  3  /* Command bit 3 position. */
3510#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
3511#define NVM_CMD4_bp  4  /* Command bit 4 position. */
3512#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
3513#define NVM_CMD5_bp  5  /* Command bit 5 position. */
3514#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
3515#define NVM_CMD6_bp  6  /* Command bit 6 position. */
3516#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
3517#define NVM_CMD7_bp  7  /* Command bit 7 position. */
3518
3519
3520/* NVM.CTRLA  bit masks and bit positions */
3521#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
3522#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
3523
3524
3525/* NVM.CTRLB  bit masks and bit positions */
3526#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
3527#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
3528
3529#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
3530#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
3531
3532#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
3533#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
3534
3535#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
3536#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
3537
3538
3539/* NVM.INTCTRL  bit masks and bit positions */
3540#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
3541#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
3542#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
3543#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
3544#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
3545#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
3546
3547#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
3548#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
3549#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
3550#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
3551#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
3552#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
3553
3554
3555/* NVM.STATUS  bit masks and bit positions */
3556#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
3557#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
3558
3559#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
3560#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
3561
3562#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
3563#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
3564
3565#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
3566#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
3567
3568
3569/* NVM.LOCKBITS  bit masks and bit positions */
3570#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
3571#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
3572#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
3573#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
3574#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
3575#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
3576
3577#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
3578#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
3579#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
3580#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
3581#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
3582#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
3583
3584#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
3585#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
3586#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
3587#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
3588#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
3589#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
3590
3591#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
3592#define NVM_LB_gp  0  /* Lock Bits group position. */
3593#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
3594#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
3595#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
3596#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
3597
3598
3599/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
3600#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
3601#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
3602#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
3603#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
3604#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
3605#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
3606
3607#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
3608#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
3609#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
3610#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
3611#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
3612#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
3613
3614#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
3615#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
3616#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
3617#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
3618#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
3619#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
3620
3621#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
3622#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
3623#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
3624#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
3625#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
3626#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
3627
3628
3629/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
3630#define NVM_FUSES_USERID_gm  0xFF  /* User ID group mask. */
3631#define NVM_FUSES_USERID_gp  0  /* User ID group position. */
3632#define NVM_FUSES_USERID0_bm  (1<<0)  /* User ID bit 0 mask. */
3633#define NVM_FUSES_USERID0_bp  0  /* User ID bit 0 position. */
3634#define NVM_FUSES_USERID1_bm  (1<<1)  /* User ID bit 1 mask. */
3635#define NVM_FUSES_USERID1_bp  1  /* User ID bit 1 position. */
3636#define NVM_FUSES_USERID2_bm  (1<<2)  /* User ID bit 2 mask. */
3637#define NVM_FUSES_USERID2_bp  2  /* User ID bit 2 position. */
3638#define NVM_FUSES_USERID3_bm  (1<<3)  /* User ID bit 3 mask. */
3639#define NVM_FUSES_USERID3_bp  3  /* User ID bit 3 position. */
3640#define NVM_FUSES_USERID4_bm  (1<<4)  /* User ID bit 4 mask. */
3641#define NVM_FUSES_USERID4_bp  4  /* User ID bit 4 position. */
3642#define NVM_FUSES_USERID5_bm  (1<<5)  /* User ID bit 5 mask. */
3643#define NVM_FUSES_USERID5_bp  5  /* User ID bit 5 position. */
3644#define NVM_FUSES_USERID6_bm  (1<<6)  /* User ID bit 6 mask. */
3645#define NVM_FUSES_USERID6_bp  6  /* User ID bit 6 position. */
3646#define NVM_FUSES_USERID7_bm  (1<<7)  /* User ID bit 7 mask. */
3647#define NVM_FUSES_USERID7_bp  7  /* User ID bit 7 position. */
3648
3649
3650/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
3651#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
3652#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
3653#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
3654#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
3655#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
3656#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
3657#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
3658#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
3659#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
3660#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
3661
3662#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
3663#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
3664#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
3665#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
3666#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
3667#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
3668#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
3669#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
3670#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
3671#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
3672
3673
3674/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
3675#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
3676#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
3677
3678#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
3679#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
3680
3681#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
3682#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
3683#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
3684#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
3685#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
3686#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
3687
3688
3689/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
3690#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
3691#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
3692#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
3693#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
3694#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
3695#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
3696
3697#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
3698#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
3699
3700
3701/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
3702#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
3703#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
3704#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
3705#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
3706#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
3707#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
3708
3709#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
3710#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
3711
3712#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
3713#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
3714#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
3715#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
3716#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
3717#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
3718#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
3719#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
3720
3721
3722/* AC - Analog Comparator */
3723/* AC.AC0CTRL  bit masks and bit positions */
3724#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
3725#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
3726#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
3727#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
3728#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
3729#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
3730
3731#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
3732#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
3733#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
3734#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
3735#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
3736#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
3737
3738#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
3739#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
3740
3741#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
3742#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
3743#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
3744#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
3745#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
3746#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
3747
3748#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
3749#define AC_ENABLE_bp  0  /* Enable bit position. */
3750
3751
3752/* AC.AC1CTRL  bit masks and bit positions */
3753/* AC_INTMODE_gm  Predefined. */
3754/* AC_INTMODE_gp  Predefined. */
3755/* AC_INTMODE0_bm  Predefined. */
3756/* AC_INTMODE0_bp  Predefined. */
3757/* AC_INTMODE1_bm  Predefined. */
3758/* AC_INTMODE1_bp  Predefined. */
3759
3760/* AC_INTLVL_gm  Predefined. */
3761/* AC_INTLVL_gp  Predefined. */
3762/* AC_INTLVL0_bm  Predefined. */
3763/* AC_INTLVL0_bp  Predefined. */
3764/* AC_INTLVL1_bm  Predefined. */
3765/* AC_INTLVL1_bp  Predefined. */
3766
3767/* AC_HSMODE_bm  Predefined. */
3768/* AC_HSMODE_bp  Predefined. */
3769
3770/* AC_HYSMODE_gm  Predefined. */
3771/* AC_HYSMODE_gp  Predefined. */
3772/* AC_HYSMODE0_bm  Predefined. */
3773/* AC_HYSMODE0_bp  Predefined. */
3774/* AC_HYSMODE1_bm  Predefined. */
3775/* AC_HYSMODE1_bp  Predefined. */
3776
3777/* AC_ENABLE_bm  Predefined. */
3778/* AC_ENABLE_bp  Predefined. */
3779
3780
3781/* AC.AC0MUXCTRL  bit masks and bit positions */
3782#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
3783#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
3784#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
3785#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
3786#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
3787#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
3788#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
3789#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
3790
3791#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
3792#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
3793#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
3794#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
3795#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
3796#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
3797#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
3798#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
3799
3800
3801/* AC.AC1MUXCTRL  bit masks and bit positions */
3802/* AC_MUXPOS_gm  Predefined. */
3803/* AC_MUXPOS_gp  Predefined. */
3804/* AC_MUXPOS0_bm  Predefined. */
3805/* AC_MUXPOS0_bp  Predefined. */
3806/* AC_MUXPOS1_bm  Predefined. */
3807/* AC_MUXPOS1_bp  Predefined. */
3808/* AC_MUXPOS2_bm  Predefined. */
3809/* AC_MUXPOS2_bp  Predefined. */
3810
3811/* AC_MUXNEG_gm  Predefined. */
3812/* AC_MUXNEG_gp  Predefined. */
3813/* AC_MUXNEG0_bm  Predefined. */
3814/* AC_MUXNEG0_bp  Predefined. */
3815/* AC_MUXNEG1_bm  Predefined. */
3816/* AC_MUXNEG1_bp  Predefined. */
3817/* AC_MUXNEG2_bm  Predefined. */
3818/* AC_MUXNEG2_bp  Predefined. */
3819
3820
3821/* AC.CTRLA  bit masks and bit positions */
3822#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
3823#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
3824
3825
3826/* AC.CTRLB  bit masks and bit positions */
3827#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
3828#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
3829#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
3830#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
3831#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
3832#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
3833#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
3834#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
3835#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
3836#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
3837#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
3838#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
3839#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
3840#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
3841
3842
3843/* AC.WINCTRL  bit masks and bit positions */
3844#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
3845#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
3846
3847#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
3848#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
3849#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
3850#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
3851#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
3852#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
3853
3854#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
3855#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
3856#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
3857#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
3858#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
3859#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
3860
3861
3862/* AC.STATUS  bit masks and bit positions */
3863#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
3864#define AC_WSTATE_gp  6  /* Window Mode State group position. */
3865#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
3866#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
3867#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
3868#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
3869
3870#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
3871#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
3872
3873#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
3874#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
3875
3876#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
3877#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
3878
3879#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
3880#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
3881
3882#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
3883#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
3884
3885
3886/* ADC - Analog/Digital Converter */
3887/* ADC_CH.CTRL  bit masks and bit positions */
3888#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
3889#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
3890
3891#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
3892#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
3893#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
3894#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
3895#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
3896#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
3897#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
3898#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
3899
3900#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
3901#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
3902#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
3903#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
3904#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
3905#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
3906
3907
3908/* ADC_CH.MUXCTRL  bit masks and bit positions */
3909#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
3910#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
3911#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
3912#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
3913#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
3914#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
3915#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
3916#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
3917#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
3918#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
3919#define ADC_CH_MUXPOS4_bm  (1<<7)  /* Positive Input Select bit 3 mask. */
3920#define ADC_CH_MUXPOS4_bp  7  /* Positive Input Select bit 3 position. */
3921
3922#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
3923#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
3924#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
3925#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
3926#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
3927#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
3928#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
3929#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
3930#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
3931#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
3932
3933#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
3934#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
3935#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
3936#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
3937#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
3938#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
3939
3940
3941/* ADC_CH.INTCTRL  bit masks and bit positions */
3942#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
3943#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
3944#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
3945#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
3946#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
3947#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
3948
3949#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
3950#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
3951#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
3952#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
3953#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
3954#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
3955
3956
3957/* ADC_CH.INTFLAGS  bit masks and bit positions */
3958#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
3959#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
3960
3961
3962/* ADC.CTRLA  bit masks and bit positions */
3963#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
3964#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
3965
3966#define ADC_FLUSH_bm  0x02  /* ADC Flush bit mask. */
3967#define ADC_FLUSH_bp  1  /* ADC Flush bit position. */
3968
3969#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
3970#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
3971
3972
3973/* ADC.CTRLB  bit masks and bit positions */
3974#define ADC_IMPMODE_bm  0x80  /* Impedance Mode bit mask. */
3975#define ADC_IMPMODE_bp  7  /* Impedance Mode bit position. */
3976
3977#define ADC_CURRENT_bm  0x60  /* Current bit mask. */
3978#define ADC_CURRENT1_bp  6  /* Current bit position. */
3979#define ADC_CURRENT0_bp  5  /* Current bit position. */
3980
3981#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
3982#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
3983
3984#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
3985#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
3986
3987#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
3988#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
3989#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
3990#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
3991#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
3992#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
3993
3994
3995/* ADC.REFCTRL  bit masks and bit positions */
3996#define ADC_REFSEL_gm  0x70  /* Reference Selection group mask. */
3997#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
3998#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
3999#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
4000#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
4001#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
4002#define ADC_REFSEL2_bm  (1<<6)  /* Reference Selection bit 2 mask. */
4003#define ADC_REFSEL2_bp  6  /* Reference Selection bit 2 position. */
4004
4005#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
4006#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
4007
4008#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
4009#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
4010
4011
4012/* ADC.EVCTRL  bit masks and bit positions */
4013#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
4014#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
4015#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
4016#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
4017#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
4018#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
4019
4020#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
4021#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
4022#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
4023#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
4024#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
4025#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
4026#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
4027#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
4028
4029#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
4030#define ADC_EVACT_gp  0  /* Event Action Select group position. */
4031#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
4032#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
4033#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
4034#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
4035#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
4036#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
4037
4038
4039/* ADC.PRESCALER  bit masks and bit positions */
4040#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
4041#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
4042#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
4043#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
4044#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
4045#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
4046#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
4047#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
4048
4049
4050/* ADC.INTFLAGS  bit masks and bit positions */
4051#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
4052#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
4053
4054
4055/* RTC - Real-Time Clounter */
4056/* RTC.CTRL  bit masks and bit positions */
4057#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
4058#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
4059#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
4060#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
4061#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
4062#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
4063#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
4064#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
4065
4066
4067/* RTC.STATUS  bit masks and bit positions */
4068#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
4069#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
4070
4071
4072/* RTC.INTCTRL  bit masks and bit positions */
4073#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
4074#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
4075#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
4076#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
4077#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
4078#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
4079
4080#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
4081#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
4082#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
4083#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
4084#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
4085#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
4086
4087
4088/* RTC.INTFLAGS  bit masks and bit positions */
4089#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
4090#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
4091
4092#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
4093#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
4094
4095
4096/* EBI - External Bus Interface */
4097/* EBI_CS.CTRLA  bit masks and bit positions */
4098#define EBI_CS_ASIZE_gm  0x7C  /* Address Size group mask. */
4099#define EBI_CS_ASIZE_gp  2  /* Address Size group position. */
4100#define EBI_CS_ASIZE0_bm  (1<<2)  /* Address Size bit 0 mask. */
4101#define EBI_CS_ASIZE0_bp  2  /* Address Size bit 0 position. */
4102#define EBI_CS_ASIZE1_bm  (1<<3)  /* Address Size bit 1 mask. */
4103#define EBI_CS_ASIZE1_bp  3  /* Address Size bit 1 position. */
4104#define EBI_CS_ASIZE2_bm  (1<<4)  /* Address Size bit 2 mask. */
4105#define EBI_CS_ASIZE2_bp  4  /* Address Size bit 2 position. */
4106#define EBI_CS_ASIZE3_bm  (1<<5)  /* Address Size bit 3 mask. */
4107#define EBI_CS_ASIZE3_bp  5  /* Address Size bit 3 position. */
4108#define EBI_CS_ASIZE4_bm  (1<<6)  /* Address Size bit 4 mask. */
4109#define EBI_CS_ASIZE4_bp  6  /* Address Size bit 4 position. */
4110
4111#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
4112#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
4113#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
4114#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
4115#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
4116#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
4117
4118
4119/* EBI_CS.CTRLB  bit masks and bit positions */
4120#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
4121#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
4122#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
4123#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
4124#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
4125#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
4126#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
4127#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
4128
4129#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
4130#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
4131
4132#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
4133#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
4134
4135#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
4136#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
4137#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
4138#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
4139#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
4140#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
4141
4142
4143/* EBI.CTRL  bit masks and bit positions */
4144#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
4145#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
4146#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
4147#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
4148#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
4149#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
4150
4151#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
4152#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
4153#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
4154#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
4155#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
4156#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
4157
4158#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
4159#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
4160#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
4161#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
4162#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
4163#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
4164
4165#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
4166#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
4167#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
4168#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
4169#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
4170#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
4171
4172
4173/* EBI.SDRAMCTRLA  bit masks and bit positions */
4174#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
4175#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
4176
4177#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
4178#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
4179
4180#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
4181#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
4182#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
4183#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
4184#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
4185#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
4186
4187
4188/* EBI.SDRAMCTRLB  bit masks and bit positions */
4189#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
4190#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
4191#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
4192#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
4193#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
4194#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
4195
4196#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
4197#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
4198#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
4199#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
4200#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
4201#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
4202#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
4203#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
4204
4205#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
4206#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
4207#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
4208#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
4209#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
4210#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
4211#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
4212#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
4213
4214
4215/* EBI.SDRAMCTRLC  bit masks and bit positions */
4216#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
4217#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
4218#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
4219#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
4220#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
4221#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
4222
4223#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
4224#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
4225#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
4226#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
4227#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
4228#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
4229#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
4230#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
4231
4232#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
4233#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
4234#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
4235#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
4236#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
4237#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
4238#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
4239#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
4240
4241
4242/* TWI - Two-Wire Interface */
4243/* TWI_MASTER.CTRLA  bit masks and bit positions */
4244#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
4245#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
4246#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
4247#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
4248#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
4249#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
4250
4251#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
4252#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
4253
4254#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
4255#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
4256
4257#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
4258#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
4259
4260
4261/* TWI_MASTER.CTRLB  bit masks and bit positions */
4262#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
4263#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
4264#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
4265#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
4266#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
4267#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
4268
4269#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
4270#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
4271
4272#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
4273#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
4274
4275
4276/* TWI_MASTER.CTRLC  bit masks and bit positions */
4277#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
4278#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
4279
4280#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
4281#define TWI_MASTER_CMD_gp  0  /* Command group position. */
4282#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
4283#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
4284#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
4285#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
4286
4287
4288/* TWI_MASTER.STATUS  bit masks and bit positions */
4289#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
4290#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
4291
4292#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
4293#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
4294
4295#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
4296#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
4297
4298#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
4299#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
4300
4301#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
4302#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
4303
4304#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
4305#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
4306
4307#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
4308#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
4309#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
4310#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
4311#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
4312#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
4313
4314
4315/* TWI_SLAVE.CTRLA  bit masks and bit positions */
4316#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
4317#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
4318#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
4319#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
4320#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
4321#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
4322
4323#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
4324#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
4325
4326#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
4327#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
4328
4329#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
4330#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
4331
4332#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
4333#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
4334
4335#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
4336#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
4337
4338#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
4339#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
4340
4341
4342/* TWI_SLAVE.CTRLB  bit masks and bit positions */
4343#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
4344#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
4345
4346#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
4347#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
4348#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
4349#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
4350#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
4351#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
4352
4353
4354/* TWI_SLAVE.STATUS  bit masks and bit positions */
4355#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
4356#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
4357
4358#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
4359#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
4360
4361#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
4362#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
4363
4364#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
4365#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
4366
4367#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
4368#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
4369
4370#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
4371#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
4372
4373#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
4374#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
4375
4376#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
4377#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
4378
4379
4380/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
4381#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
4382#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
4383#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
4384#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
4385#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
4386#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
4387#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
4388#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
4389#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
4390#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
4391#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
4392#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
4393#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
4394#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
4395#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
4396#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
4397
4398#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
4399#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
4400
4401
4402/* TWI.CTRL  bit masks and bit positions */
4403#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
4404#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
4405
4406#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
4407#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
4408
4409
4410/* PORT - Port Configuration */
4411/* PORTCFG.VPCTRLA  bit masks and bit positions */
4412#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
4413#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
4414#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
4415#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
4416#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
4417#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
4418#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
4419#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
4420#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
4421#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
4422
4423#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
4424#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
4425#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
4426#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
4427#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
4428#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
4429#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
4430#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
4431#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
4432#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
4433
4434
4435/* PORTCFG.VPCTRLB  bit masks and bit positions */
4436#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
4437#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
4438#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
4439#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
4440#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
4441#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
4442#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
4443#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
4444#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
4445#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
4446
4447#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
4448#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
4449#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
4450#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
4451#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
4452#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
4453#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
4454#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
4455#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
4456#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
4457
4458
4459/* PORTCFG.CLKEVOUT  bit masks and bit positions */
4460#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
4461#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
4462#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
4463#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
4464#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
4465#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
4466
4467#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
4468#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
4469#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
4470#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
4471#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
4472#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
4473
4474
4475/* VPORT.INTFLAGS  bit masks and bit positions */
4476#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
4477#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
4478
4479#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
4480#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
4481
4482
4483/* PORT.INTCTRL  bit masks and bit positions */
4484#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
4485#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
4486#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
4487#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
4488#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
4489#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
4490
4491#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
4492#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
4493#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
4494#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
4495#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
4496#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
4497
4498
4499/* PORT.INTFLAGS  bit masks and bit positions */
4500#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
4501#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
4502
4503#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
4504#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
4505
4506
4507/* PORT.PIN0CTRL  bit masks and bit positions */
4508#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
4509#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
4510
4511#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
4512#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
4513
4514#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
4515#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
4516#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
4517#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
4518#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
4519#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
4520#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
4521#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
4522
4523#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
4524#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
4525#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
4526#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
4527#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
4528#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
4529#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
4530#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
4531
4532
4533/* PORT.PIN1CTRL  bit masks and bit positions */
4534/* PORT_SRLEN_bm  Predefined. */
4535/* PORT_SRLEN_bp  Predefined. */
4536
4537/* PORT_INVEN_bm  Predefined. */
4538/* PORT_INVEN_bp  Predefined. */
4539
4540/* PORT_OPC_gm  Predefined. */
4541/* PORT_OPC_gp  Predefined. */
4542/* PORT_OPC0_bm  Predefined. */
4543/* PORT_OPC0_bp  Predefined. */
4544/* PORT_OPC1_bm  Predefined. */
4545/* PORT_OPC1_bp  Predefined. */
4546/* PORT_OPC2_bm  Predefined. */
4547/* PORT_OPC2_bp  Predefined. */
4548
4549/* PORT_ISC_gm  Predefined. */
4550/* PORT_ISC_gp  Predefined. */
4551/* PORT_ISC0_bm  Predefined. */
4552/* PORT_ISC0_bp  Predefined. */
4553/* PORT_ISC1_bm  Predefined. */
4554/* PORT_ISC1_bp  Predefined. */
4555/* PORT_ISC2_bm  Predefined. */
4556/* PORT_ISC2_bp  Predefined. */
4557
4558
4559/* PORT.PIN2CTRL  bit masks and bit positions */
4560/* PORT_SRLEN_bm  Predefined. */
4561/* PORT_SRLEN_bp  Predefined. */
4562
4563/* PORT_INVEN_bm  Predefined. */
4564/* PORT_INVEN_bp  Predefined. */
4565
4566/* PORT_OPC_gm  Predefined. */
4567/* PORT_OPC_gp  Predefined. */
4568/* PORT_OPC0_bm  Predefined. */
4569/* PORT_OPC0_bp  Predefined. */
4570/* PORT_OPC1_bm  Predefined. */
4571/* PORT_OPC1_bp  Predefined. */
4572/* PORT_OPC2_bm  Predefined. */
4573/* PORT_OPC2_bp  Predefined. */
4574
4575/* PORT_ISC_gm  Predefined. */
4576/* PORT_ISC_gp  Predefined. */
4577/* PORT_ISC0_bm  Predefined. */
4578/* PORT_ISC0_bp  Predefined. */
4579/* PORT_ISC1_bm  Predefined. */
4580/* PORT_ISC1_bp  Predefined. */
4581/* PORT_ISC2_bm  Predefined. */
4582/* PORT_ISC2_bp  Predefined. */
4583
4584
4585/* PORT.PIN3CTRL  bit masks and bit positions */
4586/* PORT_SRLEN_bm  Predefined. */
4587/* PORT_SRLEN_bp  Predefined. */
4588
4589/* PORT_INVEN_bm  Predefined. */
4590/* PORT_INVEN_bp  Predefined. */
4591
4592/* PORT_OPC_gm  Predefined. */
4593/* PORT_OPC_gp  Predefined. */
4594/* PORT_OPC0_bm  Predefined. */
4595/* PORT_OPC0_bp  Predefined. */
4596/* PORT_OPC1_bm  Predefined. */
4597/* PORT_OPC1_bp  Predefined. */
4598/* PORT_OPC2_bm  Predefined. */
4599/* PORT_OPC2_bp  Predefined. */
4600
4601/* PORT_ISC_gm  Predefined. */
4602/* PORT_ISC_gp  Predefined. */
4603/* PORT_ISC0_bm  Predefined. */
4604/* PORT_ISC0_bp  Predefined. */
4605/* PORT_ISC1_bm  Predefined. */
4606/* PORT_ISC1_bp  Predefined. */
4607/* PORT_ISC2_bm  Predefined. */
4608/* PORT_ISC2_bp  Predefined. */
4609
4610
4611/* PORT.PIN4CTRL  bit masks and bit positions */
4612/* PORT_SRLEN_bm  Predefined. */
4613/* PORT_SRLEN_bp  Predefined. */
4614
4615/* PORT_INVEN_bm  Predefined. */
4616/* PORT_INVEN_bp  Predefined. */
4617
4618/* PORT_OPC_gm  Predefined. */
4619/* PORT_OPC_gp  Predefined. */
4620/* PORT_OPC0_bm  Predefined. */
4621/* PORT_OPC0_bp  Predefined. */
4622/* PORT_OPC1_bm  Predefined. */
4623/* PORT_OPC1_bp  Predefined. */
4624/* PORT_OPC2_bm  Predefined. */
4625/* PORT_OPC2_bp  Predefined. */
4626
4627/* PORT_ISC_gm  Predefined. */
4628/* PORT_ISC_gp  Predefined. */
4629/* PORT_ISC0_bm  Predefined. */
4630/* PORT_ISC0_bp  Predefined. */
4631/* PORT_ISC1_bm  Predefined. */
4632/* PORT_ISC1_bp  Predefined. */
4633/* PORT_ISC2_bm  Predefined. */
4634/* PORT_ISC2_bp  Predefined. */
4635
4636
4637/* PORT.PIN5CTRL  bit masks and bit positions */
4638/* PORT_SRLEN_bm  Predefined. */
4639/* PORT_SRLEN_bp  Predefined. */
4640
4641/* PORT_INVEN_bm  Predefined. */
4642/* PORT_INVEN_bp  Predefined. */
4643
4644/* PORT_OPC_gm  Predefined. */
4645/* PORT_OPC_gp  Predefined. */
4646/* PORT_OPC0_bm  Predefined. */
4647/* PORT_OPC0_bp  Predefined. */
4648/* PORT_OPC1_bm  Predefined. */
4649/* PORT_OPC1_bp  Predefined. */
4650/* PORT_OPC2_bm  Predefined. */
4651/* PORT_OPC2_bp  Predefined. */
4652
4653/* PORT_ISC_gm  Predefined. */
4654/* PORT_ISC_gp  Predefined. */
4655/* PORT_ISC0_bm  Predefined. */
4656/* PORT_ISC0_bp  Predefined. */
4657/* PORT_ISC1_bm  Predefined. */
4658/* PORT_ISC1_bp  Predefined. */
4659/* PORT_ISC2_bm  Predefined. */
4660/* PORT_ISC2_bp  Predefined. */
4661
4662
4663/* PORT.PIN6CTRL  bit masks and bit positions */
4664/* PORT_SRLEN_bm  Predefined. */
4665/* PORT_SRLEN_bp  Predefined. */
4666
4667/* PORT_INVEN_bm  Predefined. */
4668/* PORT_INVEN_bp  Predefined. */
4669
4670/* PORT_OPC_gm  Predefined. */
4671/* PORT_OPC_gp  Predefined. */
4672/* PORT_OPC0_bm  Predefined. */
4673/* PORT_OPC0_bp  Predefined. */
4674/* PORT_OPC1_bm  Predefined. */
4675/* PORT_OPC1_bp  Predefined. */
4676/* PORT_OPC2_bm  Predefined. */
4677/* PORT_OPC2_bp  Predefined. */
4678
4679/* PORT_ISC_gm  Predefined. */
4680/* PORT_ISC_gp  Predefined. */
4681/* PORT_ISC0_bm  Predefined. */
4682/* PORT_ISC0_bp  Predefined. */
4683/* PORT_ISC1_bm  Predefined. */
4684/* PORT_ISC1_bp  Predefined. */
4685/* PORT_ISC2_bm  Predefined. */
4686/* PORT_ISC2_bp  Predefined. */
4687
4688
4689/* PORT.PIN7CTRL  bit masks and bit positions */
4690/* PORT_SRLEN_bm  Predefined. */
4691/* PORT_SRLEN_bp  Predefined. */
4692
4693/* PORT_INVEN_bm  Predefined. */
4694/* PORT_INVEN_bp  Predefined. */
4695
4696/* PORT_OPC_gm  Predefined. */
4697/* PORT_OPC_gp  Predefined. */
4698/* PORT_OPC0_bm  Predefined. */
4699/* PORT_OPC0_bp  Predefined. */
4700/* PORT_OPC1_bm  Predefined. */
4701/* PORT_OPC1_bp  Predefined. */
4702/* PORT_OPC2_bm  Predefined. */
4703/* PORT_OPC2_bp  Predefined. */
4704
4705/* PORT_ISC_gm  Predefined. */
4706/* PORT_ISC_gp  Predefined. */
4707/* PORT_ISC0_bm  Predefined. */
4708/* PORT_ISC0_bp  Predefined. */
4709/* PORT_ISC1_bm  Predefined. */
4710/* PORT_ISC1_bp  Predefined. */
4711/* PORT_ISC2_bm  Predefined. */
4712/* PORT_ISC2_bp  Predefined. */
4713
4714
4715/* TC - 16-bit Timer/Counter With PWM */
4716/* TC0.CTRLA  bit masks and bit positions */
4717#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4718#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
4719#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4720#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4721#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4722#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4723#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4724#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4725#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4726#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4727
4728
4729/* TC0.CTRLB  bit masks and bit positions */
4730#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
4731#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
4732
4733#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
4734#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
4735
4736#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
4737#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
4738
4739#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
4740#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
4741
4742#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
4743#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
4744#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
4745#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
4746#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
4747#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
4748#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
4749#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
4750
4751
4752/* TC0.CTRLC  bit masks and bit positions */
4753#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
4754#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
4755
4756#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
4757#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
4758
4759#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
4760#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
4761
4762#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
4763#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
4764
4765
4766/* TC0.CTRLD  bit masks and bit positions */
4767#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
4768#define TC0_EVACT_gp  5  /* Event Action group position. */
4769#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
4770#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
4771#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
4772#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
4773#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
4774#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
4775
4776#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
4777#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
4778
4779#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
4780#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
4781#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
4782#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
4783#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
4784#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
4785#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
4786#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
4787#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
4788#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
4789
4790
4791/* TC0.CTRLE  bit masks and bit positions */
4792#define TC0_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
4793#define TC0_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
4794
4795#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
4796#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
4797
4798
4799/* TC0.INTCTRLA  bit masks and bit positions */
4800#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
4801#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
4802#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
4803#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
4804#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
4805#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
4806
4807#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
4808#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
4809#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
4810#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
4811#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
4812#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
4813
4814
4815/* TC0.INTCTRLB  bit masks and bit positions */
4816#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
4817#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
4818#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
4819#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
4820#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
4821#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
4822
4823#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
4824#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
4825#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
4826#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
4827#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
4828#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
4829
4830#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
4831#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
4832#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
4833#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
4834#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
4835#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
4836
4837#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
4838#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
4839#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
4840#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
4841#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
4842#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
4843
4844
4845/* TC0.CTRLFCLR  bit masks and bit positions */
4846#define TC0_CMD_gm  0x0C  /* Command group mask. */
4847#define TC0_CMD_gp  2  /* Command group position. */
4848#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
4849#define TC0_CMD0_bp  2  /* Command bit 0 position. */
4850#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
4851#define TC0_CMD1_bp  3  /* Command bit 1 position. */
4852
4853#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
4854#define TC0_LUPD_bp  1  /* Lock Update bit position. */
4855
4856#define TC0_DIR_bm  0x01  /* Direction bit mask. */
4857#define TC0_DIR_bp  0  /* Direction bit position. */
4858
4859
4860/* TC0.CTRLFSET  bit masks and bit positions */
4861/* TC0_CMD_gm  Predefined. */
4862/* TC0_CMD_gp  Predefined. */
4863/* TC0_CMD0_bm  Predefined. */
4864/* TC0_CMD0_bp  Predefined. */
4865/* TC0_CMD1_bm  Predefined. */
4866/* TC0_CMD1_bp  Predefined. */
4867
4868/* TC0_LUPD_bm  Predefined. */
4869/* TC0_LUPD_bp  Predefined. */
4870
4871/* TC0_DIR_bm  Predefined. */
4872/* TC0_DIR_bp  Predefined. */
4873
4874
4875/* TC0.CTRLGCLR  bit masks and bit positions */
4876#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
4877#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
4878
4879#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
4880#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
4881
4882#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
4883#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
4884
4885#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
4886#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
4887
4888#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
4889#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
4890
4891
4892/* TC0.CTRLGSET  bit masks and bit positions */
4893/* TC0_CCDBV_bm  Predefined. */
4894/* TC0_CCDBV_bp  Predefined. */
4895
4896/* TC0_CCCBV_bm  Predefined. */
4897/* TC0_CCCBV_bp  Predefined. */
4898
4899/* TC0_CCBBV_bm  Predefined. */
4900/* TC0_CCBBV_bp  Predefined. */
4901
4902/* TC0_CCABV_bm  Predefined. */
4903/* TC0_CCABV_bp  Predefined. */
4904
4905/* TC0_PERBV_bm  Predefined. */
4906/* TC0_PERBV_bp  Predefined. */
4907
4908
4909/* TC0.INTFLAGS  bit masks and bit positions */
4910#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
4911#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
4912
4913#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
4914#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
4915
4916#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
4917#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
4918
4919#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
4920#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
4921
4922#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
4923#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
4924
4925#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
4926#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
4927
4928
4929/* TC1.CTRLA  bit masks and bit positions */
4930#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4931#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
4932#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4933#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4934#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4935#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4936#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4937#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4938#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4939#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4940
4941
4942/* TC1.CTRLB  bit masks and bit positions */
4943#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
4944#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
4945
4946#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
4947#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
4948
4949#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
4950#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
4951#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
4952#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
4953#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
4954#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
4955#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
4956#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
4957
4958
4959/* TC1.CTRLC  bit masks and bit positions */
4960#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
4961#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
4962
4963#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
4964#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
4965
4966
4967/* TC1.CTRLD  bit masks and bit positions */
4968#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
4969#define TC1_EVACT_gp  5  /* Event Action group position. */
4970#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
4971#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
4972#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
4973#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
4974#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
4975#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
4976
4977#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
4978#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
4979
4980#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
4981#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
4982#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
4983#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
4984#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
4985#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
4986#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
4987#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
4988#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
4989#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
4990
4991
4992/* TC1.CTRLE  bit masks and bit positions */
4993#define TC1_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
4994#define TC1_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
4995
4996#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
4997#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
4998
4999
5000/* TC1.INTCTRLA  bit masks and bit positions */
5001#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
5002#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
5003#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
5004#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
5005#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
5006#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
5007
5008#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
5009#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
5010#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
5011#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
5012#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
5013#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
5014
5015
5016/* TC1.INTCTRLB  bit masks and bit positions */
5017#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
5018#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
5019#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
5020#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
5021#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
5022#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
5023
5024#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
5025#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
5026#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
5027#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
5028#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
5029#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
5030
5031
5032/* TC1.CTRLFCLR  bit masks and bit positions */
5033#define TC1_CMD_gm  0x0C  /* Command group mask. */
5034#define TC1_CMD_gp  2  /* Command group position. */
5035#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
5036#define TC1_CMD0_bp  2  /* Command bit 0 position. */
5037#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
5038#define TC1_CMD1_bp  3  /* Command bit 1 position. */
5039
5040#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
5041#define TC1_LUPD_bp  1  /* Lock Update bit position. */
5042
5043#define TC1_DIR_bm  0x01  /* Direction bit mask. */
5044#define TC1_DIR_bp  0  /* Direction bit position. */
5045
5046
5047/* TC1.CTRLFSET  bit masks and bit positions */
5048/* TC1_CMD_gm  Predefined. */
5049/* TC1_CMD_gp  Predefined. */
5050/* TC1_CMD0_bm  Predefined. */
5051/* TC1_CMD0_bp  Predefined. */
5052/* TC1_CMD1_bm  Predefined. */
5053/* TC1_CMD1_bp  Predefined. */
5054
5055/* TC1_LUPD_bm  Predefined. */
5056/* TC1_LUPD_bp  Predefined. */
5057
5058/* TC1_DIR_bm  Predefined. */
5059/* TC1_DIR_bp  Predefined. */
5060
5061
5062/* TC1.CTRLGCLR  bit masks and bit positions */
5063#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
5064#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
5065
5066#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
5067#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
5068
5069#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
5070#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
5071
5072
5073/* TC1.CTRLGSET  bit masks and bit positions */
5074/* TC1_CCBBV_bm  Predefined. */
5075/* TC1_CCBBV_bp  Predefined. */
5076
5077/* TC1_CCABV_bm  Predefined. */
5078/* TC1_CCABV_bp  Predefined. */
5079
5080/* TC1_PERBV_bm  Predefined. */
5081/* TC1_PERBV_bp  Predefined. */
5082
5083
5084/* TC1.INTFLAGS  bit masks and bit positions */
5085#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
5086#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
5087
5088#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
5089#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
5090
5091#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
5092#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
5093
5094#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
5095#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
5096
5097
5098/* AWEX.CTRL  bit masks and bit positions */
5099#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
5100#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
5101
5102#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
5103#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
5104
5105#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
5106#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
5107
5108#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
5109#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
5110
5111#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
5112#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
5113
5114#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
5115#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
5116
5117
5118/* AWEX.FDCTRL  bit masks and bit positions */
5119#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
5120#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
5121
5122#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
5123#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
5124
5125#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
5126#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
5127#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
5128#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
5129#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
5130#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
5131
5132
5133/* AWEX.STATUS  bit masks and bit positions */
5134#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
5135#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
5136
5137#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
5138#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
5139
5140#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
5141#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
5142
5143
5144/* HIRES.CTRL  bit masks and bit positions */
5145#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
5146#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
5147#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
5148#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
5149#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
5150#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
5151
5152
5153/* USART - Universal Asynchronous Receiver-Transmitter */
5154/* USART.STATUS  bit masks and bit positions */
5155#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
5156#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
5157
5158#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
5159#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
5160
5161#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
5162#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
5163
5164#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
5165#define USART_FERR_bp  4  /* Frame Error bit position. */
5166
5167#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
5168#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
5169
5170#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
5171#define USART_PERR_bp  2  /* Parity Error bit position. */
5172
5173#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
5174#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
5175
5176
5177/* USART.CTRLA  bit masks and bit positions */
5178#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
5179#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
5180#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
5181#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
5182#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
5183#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
5184
5185#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
5186#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
5187#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
5188#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
5189#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
5190#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
5191
5192#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
5193#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
5194#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
5195#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
5196#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
5197#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
5198
5199
5200/* USART.CTRLB  bit masks and bit positions */
5201#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
5202#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
5203
5204#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
5205#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
5206
5207#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
5208#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
5209
5210#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
5211#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
5212
5213#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
5214#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
5215
5216
5217/* USART.CTRLC  bit masks and bit positions */
5218#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
5219#define USART_CMODE_gp  6  /* Communication Mode group position. */
5220#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
5221#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
5222#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
5223#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
5224
5225#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
5226#define USART_PMODE_gp  4  /* Parity Mode group position. */
5227#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
5228#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
5229#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
5230#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
5231
5232#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
5233#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
5234
5235#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
5236#define USART_CHSIZE_gp  0  /* Character Size group position. */
5237#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
5238#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
5239#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
5240#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
5241#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
5242#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
5243
5244
5245/* USART.BAUDCTRLA  bit masks and bit positions */
5246#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
5247#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
5248#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
5249#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
5250#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
5251#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
5252#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
5253#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
5254#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
5255#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
5256#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
5257#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
5258#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
5259#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
5260#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
5261#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
5262#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
5263#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
5264
5265
5266/* USART.BAUDCTRLB  bit masks and bit positions */
5267#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
5268#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
5269#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
5270#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
5271#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
5272#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
5273#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
5274#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
5275#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
5276#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
5277
5278/* USART_BSEL_gm  Predefined. */
5279/* USART_BSEL_gp  Predefined. */
5280/* USART_BSEL0_bm  Predefined. */
5281/* USART_BSEL0_bp  Predefined. */
5282/* USART_BSEL1_bm  Predefined. */
5283/* USART_BSEL1_bp  Predefined. */
5284/* USART_BSEL2_bm  Predefined. */
5285/* USART_BSEL2_bp  Predefined. */
5286/* USART_BSEL3_bm  Predefined. */
5287/* USART_BSEL3_bp  Predefined. */
5288
5289
5290/* SPI - Serial Peripheral Interface */
5291/* SPI.CTRL  bit masks and bit positions */
5292#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
5293#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
5294
5295#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
5296#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
5297
5298#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
5299#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
5300
5301#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
5302#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
5303
5304#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
5305#define SPI_MODE_gp  2  /* SPI Mode group position. */
5306#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
5307#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
5308#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
5309#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
5310
5311#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
5312#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
5313#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
5314#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
5315#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
5316#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
5317
5318
5319/* SPI.INTCTRL  bit masks and bit positions */
5320#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
5321#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
5322#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
5323#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
5324#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
5325#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
5326
5327
5328/* SPI.STATUS  bit masks and bit positions */
5329#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
5330#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
5331
5332#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
5333#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
5334
5335
5336/* IRCOM - IR Communication Module */
5337/* IRCOM.CTRL  bit masks and bit positions */
5338#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
5339#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
5340#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
5341#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
5342#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
5343#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
5344#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
5345#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
5346#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
5347#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
5348
5349
5350
5351// Generic Port Pins
5352
5353#define PIN0_bm 0x01
5354#define PIN0_bp 0
5355#define PIN1_bm 0x02
5356#define PIN1_bp 1
5357#define PIN2_bm 0x04
5358#define PIN2_bp 2
5359#define PIN3_bm 0x08
5360#define PIN3_bp 3
5361#define PIN4_bm 0x10
5362#define PIN4_bp 4
5363#define PIN5_bm 0x20
5364#define PIN5_bp 5
5365#define PIN6_bm 0x40
5366#define PIN6_bp 6
5367#define PIN7_bm 0x80
5368#define PIN7_bp 7
5369
5370
5371/* ========== Interrupt Vector Definitions ========== */
5372/* Vector 0 is the reset vector */
5373
5374/* OSC interrupt vectors */
5375#define OSC_XOSCF_vect_num  1
5376#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
5377
5378/* PORTC interrupt vectors */
5379#define PORTC_INT0_vect_num  2
5380#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
5381#define PORTC_INT1_vect_num  3
5382#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
5383
5384/* PORTR interrupt vectors */
5385#define PORTR_INT0_vect_num  4
5386#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
5387#define PORTR_INT1_vect_num  5
5388#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
5389
5390/* RTC interrupt vectors */
5391#define RTC_OVF_vect_num  10
5392#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
5393#define RTC_COMP_vect_num  11
5394#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
5395
5396/* TWIC interrupt vectors */
5397#define TWIC_TWIS_vect_num  12
5398#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
5399#define TWIC_TWIM_vect_num  13
5400#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
5401
5402/* TCC0 interrupt vectors */
5403#define TCC0_OVF_vect_num  14
5404#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
5405#define TCC0_ERR_vect_num  15
5406#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
5407#define TCC0_CCA_vect_num  16
5408#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
5409#define TCC0_CCB_vect_num  17
5410#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
5411#define TCC0_CCC_vect_num  18
5412#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
5413#define TCC0_CCD_vect_num  19
5414#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
5415
5416/* TCC1 interrupt vectors */
5417#define TCC1_OVF_vect_num  20
5418#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
5419#define TCC1_ERR_vect_num  21
5420#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
5421#define TCC1_CCA_vect_num  22
5422#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
5423#define TCC1_CCB_vect_num  23
5424#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
5425
5426/* SPIC interrupt vectors */
5427#define SPIC_INT_vect_num  24
5428#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
5429
5430/* USARTC0 interrupt vectors */
5431#define USARTC0_RXC_vect_num  25
5432#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
5433#define USARTC0_DRE_vect_num  26
5434#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
5435#define USARTC0_TXC_vect_num  27
5436#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
5437
5438/* NVM interrupt vectors */
5439#define NVM_EE_vect_num  32
5440#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
5441#define NVM_SPM_vect_num  33
5442#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
5443
5444/* PORTB interrupt vectors */
5445#define PORTB_INT0_vect_num  34
5446#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
5447#define PORTB_INT1_vect_num  35
5448#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
5449
5450/* PORTE interrupt vectors */
5451#define PORTE_INT0_vect_num  43
5452#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
5453#define PORTE_INT1_vect_num  44
5454#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
5455
5456/* TWIE interrupt vectors */
5457#define TWIE_TWIS_vect_num  45
5458#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
5459#define TWIE_TWIM_vect_num  46
5460#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
5461
5462/* TCE0 interrupt vectors */
5463#define TCE0_OVF_vect_num  47
5464#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
5465#define TCE0_ERR_vect_num  48
5466#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
5467#define TCE0_CCA_vect_num  49
5468#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
5469#define TCE0_CCB_vect_num  50
5470#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
5471#define TCE0_CCC_vect_num  51
5472#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
5473#define TCE0_CCD_vect_num  52
5474#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
5475
5476/* PORTD interrupt vectors */
5477#define PORTD_INT0_vect_num  64
5478#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
5479#define PORTD_INT1_vect_num  65
5480#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
5481
5482/* PORTA interrupt vectors */
5483#define PORTA_INT0_vect_num  66
5484#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
5485#define PORTA_INT1_vect_num  67
5486#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
5487
5488/* ACA interrupt vectors */
5489#define ACA_AC0_vect_num  68
5490#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
5491#define ACA_AC1_vect_num  69
5492#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
5493#define ACA_ACW_vect_num  70
5494#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
5495
5496/* ADCA interrupt vectors */
5497#define ADCA_CH0_vect_num  71
5498#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
5499
5500/* TCD0 interrupt vectors */
5501#define TCD0_OVF_vect_num  77
5502#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
5503#define TCD0_ERR_vect_num  78
5504#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
5505#define TCD0_CCA_vect_num  79
5506#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
5507#define TCD0_CCB_vect_num  80
5508#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
5509#define TCD0_CCC_vect_num  81
5510#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
5511#define TCD0_CCD_vect_num  82
5512#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
5513
5514/* SPID interrupt vectors */
5515#define SPID_INT_vect_num  87
5516#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
5517
5518/* USARTD0 interrupt vectors */
5519#define USARTD0_RXC_vect_num  88
5520#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
5521#define USARTD0_DRE_vect_num  89
5522#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
5523#define USARTD0_TXC_vect_num  90
5524#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
5525
5526
5527#define _VECTOR_SIZE 4 /* Size of individual vector. */
5528#define _VECTORS_SIZE (91 * _VECTOR_SIZE)
5529
5530
5531/* ========== Constants ========== */
5532
5533#define PROGMEM_START     (0x0000)
5534#define PROGMEM_SIZE      (20480)
5535#define PROGMEM_PAGE_SIZE (256)
5536#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
5537
5538#define APP_SECTION_START     (0x0000)
5539#define APP_SECTION_SIZE      (16384)
5540#define APP_SECTION_PAGE_SIZE (256)
5541#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
5542
5543#define APPTABLE_SECTION_START     (0x3000)
5544#define APPTABLE_SECTION_SIZE      (4096)
5545#define APPTABLE_SECTION_PAGE_SIZE (256)
5546#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
5547
5548#define BOOT_SECTION_START     (0x4000)
5549#define BOOT_SECTION_SIZE      (4096)
5550#define BOOT_SECTION_PAGE_SIZE (256)
5551#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
5552
5553#define DATAMEM_START     (0x0000)
5554#define DATAMEM_SIZE      (10240)
5555#define DATAMEM_PAGE_SIZE (0)
5556#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
5557
5558#define IO_START     (0x0000)
5559#define IO_SIZE      (4096)
5560#define IO_PAGE_SIZE (0)
5561#define IO_END       (IO_START + IO_SIZE - 1)
5562
5563#define MAPPED_EEPROM_START     (0x1000)
5564#define MAPPED_EEPROM_SIZE      (1024)
5565#define MAPPED_EEPROM_PAGE_SIZE (0)
5566#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
5567
5568#define INTERNAL_SRAM_START     (0x2000)
5569#define INTERNAL_SRAM_SIZE      (2048)
5570#define INTERNAL_SRAM_PAGE_SIZE (0)
5571#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
5572
5573#define EEPROM_START     (0x0000)
5574#define EEPROM_SIZE      (1024)
5575#define EEPROM_PAGE_SIZE (32)
5576#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
5577
5578#define FUSE_START     (0x0000)
5579#define FUSE_SIZE      (6)
5580#define FUSE_PAGE_SIZE (0)
5581#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
5582
5583#define LOCKBIT_START     (0x0000)
5584#define LOCKBIT_SIZE      (1)
5585#define LOCKBIT_PAGE_SIZE (0)
5586#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
5587
5588#define SIGNATURES_START     (0x0000)
5589#define SIGNATURES_SIZE      (3)
5590#define SIGNATURES_PAGE_SIZE (0)
5591#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
5592
5593#define USER_SIGNATURES_START     (0x0000)
5594#define USER_SIGNATURES_SIZE      (256)
5595#define USER_SIGNATURES_PAGE_SIZE (0)
5596#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
5597
5598#define PROD_SIGNATURES_START     (0x0000)
5599#define PROD_SIGNATURES_SIZE      (52)
5600#define PROD_SIGNATURES_PAGE_SIZE (0)
5601#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
5602
5603#define FLASHEND     PROGMEM_END
5604#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
5605#define RAMSTART     INTERNAL_SRAM_START
5606#define RAMSIZE      INTERNAL_SRAM_SIZE
5607#define RAMEND       INTERNAL_SRAM_END
5608#define XRAMSTART    EXTERNAL_SRAM_START
5609#define XRAMSIZE     EXTERNAL_SRAM_SIZE
5610#define XRAMEND      INTERNAL_SRAM_END
5611#define E2END        EEPROM_END
5612#define E2PAGESIZE   EEPROM_PAGE_SIZE
5613
5614
5615/* ========== Fuses ========== */
5616#define FUSE_MEMORY_SIZE 6
5617
5618/* Fuse Byte 0 */
5619#define FUSE_USERID0  (unsigned char)~_BV(0)  /* User ID Bit 0 */
5620#define FUSE_USERID1  (unsigned char)~_BV(1)  /* User ID Bit 1 */
5621#define FUSE_USERID2  (unsigned char)~_BV(2)  /* User ID Bit 2 */
5622#define FUSE_USERID3  (unsigned char)~_BV(3)  /* User ID Bit 3 */
5623#define FUSE_USERID4  (unsigned char)~_BV(4)  /* User ID Bit 4 */
5624#define FUSE_USERID5  (unsigned char)~_BV(5)  /* User ID Bit 5 */
5625#define FUSE_USERID6  (unsigned char)~_BV(6)  /* User ID Bit 6 */
5626#define FUSE_USERID7  (unsigned char)~_BV(7)  /* User ID Bit 7 */
5627#define FUSE0_DEFAULT  (0xFF)
5628
5629/* Fuse Byte 1 */
5630#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
5631#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
5632#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
5633#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
5634#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
5635#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
5636#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
5637#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
5638#define FUSE1_DEFAULT  (0xFF)
5639
5640/* Fuse Byte 2 */
5641#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
5642#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
5643#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
5644#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
5645#define FUSE2_DEFAULT  (0xFF)
5646
5647/* Fuse Byte 3 Reserved */
5648
5649/* Fuse Byte 4 */
5650#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
5651#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
5652#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
5653#define FUSE4_DEFAULT  (0xFF)
5654
5655/* Fuse Byte 5 */
5656#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
5657#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
5658#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
5659#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
5660#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
5661#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
5662#define FUSE5_DEFAULT  (0xFF)
5663
5664
5665/* ========== Lock Bits ========== */
5666#define __LOCK_BITS_EXIST
5667#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
5668#define __BOOT_LOCK_APPLICATION_BITS_EXIST
5669#define __BOOT_LOCK_BOOT_BITS_EXIST
5670
5671
5672/* ========== Signature ========== */
5673#define SIGNATURE_0 0x1E
5674#define SIGNATURE_1 0x94
5675#define SIGNATURE_2 0x42
5676
5677/* ========== Power Reduction Condition Definitions ========== */
5678
5679/* PR.PRGEN */
5680#define __AVR_HAVE_PRGEN        (PR_RTC_bm|PR_EVSYS_bm)
5681#define __AVR_HAVE_PRGEN_RTC
5682#define __AVR_HAVE_PRGEN_EVSYS
5683
5684/* PR.PRPA */
5685#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm)
5686#define __AVR_HAVE_PRPA_ADC
5687#define __AVR_HAVE_PRPA_AC
5688
5689/* PR.PRPC */
5690#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
5691#define __AVR_HAVE_PRPC_TWI
5692#define __AVR_HAVE_PRPC_USART0
5693#define __AVR_HAVE_PRPC_SPI
5694#define __AVR_HAVE_PRPC_HIRES
5695#define __AVR_HAVE_PRPC_TC1
5696#define __AVR_HAVE_PRPC_TC0
5697
5698/* PR.PRPD */
5699#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm)
5700#define __AVR_HAVE_PRPD_USART0
5701#define __AVR_HAVE_PRPD_SPI
5702#define __AVR_HAVE_PRPD_TC0
5703
5704/* PR.PRPE */
5705#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm)
5706#define __AVR_HAVE_PRPE_TWI
5707#define __AVR_HAVE_PRPE_USART0
5708#define __AVR_HAVE_PRPE_TC0
5709
5710/* PR.PRPF */
5711#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm)
5712#define __AVR_HAVE_PRPF_USART0
5713#define __AVR_HAVE_PRPF_TC0
5714
5715
5716#endif /* _AVR_ATxmega16D4_H_ */
5717
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