source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iox192d3.h @ 46

Last change on this file since 46 was 46, checked in by jrpelegrina, 4 years ago

First release to Xenial

File size: 245.0 KB
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1/* Copyright (c) 2009-2010 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iox192d3.h 2194 2010-11-16 15:10:51Z arcanum $ */
32
33/* avr/iox192d3.h - definitions for ATxmega192D3 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iox192d3.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_ATxmega192D3_H_
49#define _AVR_ATxmega192D3_H_ 1
50
51
52/* Ungrouped common registers */
53#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
54#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
55#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
56#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
57#define GPIOR4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
58#define GPIOR5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
59#define GPIOR6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
60#define GPIOR7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
61#define GPIOR8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
62#define GPIOR9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
63#define GPIORA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
64#define GPIORB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
65#define GPIORC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
66#define GPIORD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
67#define GPIORE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
68#define GPIORF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
69
70#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
71#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
72#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
73#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
74#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
75#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
76#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
77#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
78#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
79
80
81/* C Language Only */
82#if !defined (__ASSEMBLER__)
83
84#include <stdint.h>
85
86typedef volatile uint8_t register8_t;
87typedef volatile uint16_t register16_t;
88typedef volatile uint32_t register32_t;
89
90
91#ifdef _WORDREGISTER
92#undef _WORDREGISTER
93#endif
94#define _WORDREGISTER(regname)   \
95   __extension__ union \
96    { \
97        register16_t regname; \
98        struct \
99        { \
100            register8_t regname ## L; \
101            register8_t regname ## H; \
102        }; \
103    }
104
105#ifdef _DWORDREGISTER
106#undef _DWORDREGISTER
107#endif
108#define _DWORDREGISTER(regname)  \
109   __extension__  union \
110    { \
111        register32_t regname; \
112        struct \
113        { \
114            register8_t regname ## 0; \
115            register8_t regname ## 1; \
116            register8_t regname ## 2; \
117            register8_t regname ## 3; \
118        }; \
119    }
120
121
122/*
123==========================================================================
124IO Module Structures
125==========================================================================
126*/
127
128
129/*
130--------------------------------------------------------------------------
131XOCD - On-Chip Debug System
132--------------------------------------------------------------------------
133*/
134
135/* On-Chip Debug System */
136typedef struct OCD_struct
137{
138    register8_t OCDR0;  /* OCD Register 0 */
139    register8_t OCDR1;  /* OCD Register 1 */
140} OCD_t;
141
142
143/* CCP signatures */
144typedef enum CCP_enum
145{
146    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
147    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
148} CCP_t;
149
150
151/*
152--------------------------------------------------------------------------
153CLK - Clock System
154--------------------------------------------------------------------------
155*/
156
157/* Clock System */
158typedef struct CLK_struct
159{
160    register8_t CTRL;  /* Control Register */
161    register8_t PSCTRL;  /* Prescaler Control Register */
162    register8_t LOCK;  /* Lock register */
163    register8_t RTCCTRL;  /* RTC Control Register */
164} CLK_t;
165
166/*
167--------------------------------------------------------------------------
168CLK - Clock System
169--------------------------------------------------------------------------
170*/
171
172/* Power Reduction */
173typedef struct PR_struct
174{
175    register8_t PRGEN;  /* General Power Reduction */
176    register8_t PRPA;  /* Power Reduction Port A */
177    register8_t reserved_0x02;
178    register8_t PRPC;  /* Power Reduction Port C */
179    register8_t PRPD;  /* Power Reduction Port D */
180    register8_t PRPE;  /* Power Reduction Port E */
181    register8_t PRPF;  /* Power Reduction Port F */
182} PR_t;
183
184/* System Clock Selection */
185typedef enum CLK_SCLKSEL_enum
186{
187    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
188    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
189    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
190    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
191    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
192} CLK_SCLKSEL_t;
193
194/* Prescaler A Division Factor */
195typedef enum CLK_PSADIV_enum
196{
197    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
198    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
199    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
200    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
201    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
202    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
203    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
204    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
205    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
206    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
207} CLK_PSADIV_t;
208
209/* Prescaler B and C Division Factor */
210typedef enum CLK_PSBCDIV_enum
211{
212    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
213    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
214    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
215    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
216} CLK_PSBCDIV_t;
217
218/* RTC Clock Source */
219typedef enum CLK_RTCSRC_enum
220{
221    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
222    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
223    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
224    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
225} CLK_RTCSRC_t;
226
227
228/*
229--------------------------------------------------------------------------
230SLEEP - Sleep Controller
231--------------------------------------------------------------------------
232*/
233
234/* Sleep Controller */
235typedef struct SLEEP_struct
236{
237    register8_t CTRL;  /* Control Register */
238} SLEEP_t;
239
240/* Sleep Mode */
241typedef enum SLEEP_SMODE_enum
242{
243    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
244    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
245    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
246    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
247    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
248} SLEEP_SMODE_t;
249
250
251/*
252--------------------------------------------------------------------------
253OSC - Oscillator
254--------------------------------------------------------------------------
255*/
256
257/* Oscillator */
258typedef struct OSC_struct
259{
260    register8_t CTRL;  /* Control Register */
261    register8_t STATUS;  /* Status Register */
262    register8_t XOSCCTRL;  /* External Oscillator Control Register */
263    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
264    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
265    register8_t PLLCTRL;  /* PLL Control REgister */
266    register8_t DFLLCTRL;  /* DFLL Control Register */
267} OSC_t;
268
269/* Oscillator Frequency Range */
270typedef enum OSC_FRQRANGE_enum
271{
272    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
273    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
274    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
275    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
276} OSC_FRQRANGE_t;
277
278/* External Oscillator Selection and Startup Time */
279typedef enum OSC_XOSCSEL_enum
280{
281    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
282    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
283    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
284    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
285    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
286} OSC_XOSCSEL_t;
287
288/* PLL Clock Source */
289typedef enum OSC_PLLSRC_enum
290{
291    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
292    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
293    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
294} OSC_PLLSRC_t;
295
296
297/*
298--------------------------------------------------------------------------
299DFLL - DFLL
300--------------------------------------------------------------------------
301*/
302
303/* DFLL */
304typedef struct DFLL_struct
305{
306    register8_t CTRL;  /* Control Register */
307    register8_t reserved_0x01;
308    register8_t CALA;  /* Calibration Register A */
309    register8_t CALB;  /* Calibration Register B */
310    register8_t COMP0;  /* Oscillator Compare Register 0 */
311    register8_t COMP1;  /* Oscillator Compare Register 1 */
312    register8_t COMP2;  /* Oscillator Compare Register 2 */
313    register8_t reserved_0x07;
314} DFLL_t;
315
316
317/*
318--------------------------------------------------------------------------
319RST - Reset
320--------------------------------------------------------------------------
321*/
322
323/* Reset */
324typedef struct RST_struct
325{
326    register8_t STATUS;  /* Status Register */
327    register8_t CTRL;  /* Control Register */
328} RST_t;
329
330
331/*
332--------------------------------------------------------------------------
333WDT - Watch-Dog Timer
334--------------------------------------------------------------------------
335*/
336
337/* Watch-Dog Timer */
338typedef struct WDT_struct
339{
340    register8_t CTRL;  /* Control */
341    register8_t WINCTRL;  /* Windowed Mode Control */
342    register8_t STATUS;  /* Status */
343} WDT_t;
344
345/* Period setting */
346typedef enum WDT_PER_enum
347{
348    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
349    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
350    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
351    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
352    WDT_PER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
353    WDT_PER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
354    WDT_PER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
355    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
356    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
357    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
358    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
359} WDT_PER_t;
360
361/* Closed window period */
362typedef enum WDT_WPER_enum
363{
364    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
365    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
366    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
367    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
368    WDT_WPER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
369    WDT_WPER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
370    WDT_WPER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
371    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
372    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
373    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
374    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
375} WDT_WPER_t;
376
377
378/*
379--------------------------------------------------------------------------
380MCU - MCU Control
381--------------------------------------------------------------------------
382*/
383
384/* MCU Control */
385typedef struct MCU_struct
386{
387    register8_t DEVID0;  /* Device ID byte 0 */
388    register8_t DEVID1;  /* Device ID byte 1 */
389    register8_t DEVID2;  /* Device ID byte 2 */
390    register8_t REVID;  /* Revision ID */
391    register8_t JTAGUID;  /* JTAG User ID */
392    register8_t reserved_0x05;
393    register8_t MCUCR;  /* MCU Control */
394    register8_t reserved_0x07;
395    register8_t EVSYSLOCK;  /* Event System Lock */
396    register8_t AWEXLOCK;  /* AWEX Lock */
397    register8_t reserved_0x0A;
398    register8_t reserved_0x0B;
399} MCU_t;
400
401
402/*
403--------------------------------------------------------------------------
404PMIC - Programmable Multi-level Interrupt Controller
405--------------------------------------------------------------------------
406*/
407
408/* Programmable Multi-level Interrupt Controller */
409typedef struct PMIC_struct
410{
411    register8_t STATUS;  /* Status Register */
412    register8_t INTPRI;  /* Interrupt Priority */
413    register8_t CTRL;  /* Control Register */
414} PMIC_t;
415
416
417/*
418--------------------------------------------------------------------------
419CRC - Cyclic Redundancy Checker
420--------------------------------------------------------------------------
421*/
422
423/* Cyclic Redundancy Checker */
424typedef struct CRC_struct
425{
426    register8_t CTRL;  /* Control Register */
427    register8_t STATUS;  /* Status Register */
428    register8_t reserved_0x02;
429    register8_t DATAIN;  /* Data Input */
430    register8_t CHECKSUM0;  /* Checksum byte 0 */
431    register8_t CHECKSUM1;  /* Checksum byte 1 */
432    register8_t CHECKSUM2;  /* Checksum byte 2 */
433    register8_t CHECKSUM3;  /* Checksum byte 3 */
434} CRC_t;
435
436/* Reset */
437typedef enum CRC_RESET_enum
438{
439    CRC_RESET_NO_gc = (0x00<<6),  /* No Reset */
440    CRC_RESET_RESET0_gc = (0x02<<6),  /* Reset CRC with CHECKSUM to all zeros */
441    CRC_RESET_RESET1_gc = (0x03<<6),  /* Reset CRC with CHECKSUM to all ones */
442} CRC_RESET_t;
443
444/* Input Source */
445typedef enum CRC_SOURCE_enum
446{
447    CRC_SOURCE_DISABLE_gc = (0x00<<0),  /* Disabled */
448    CRC_SOURCE_IO_gc = (0x01<<0),  /* I/O Interface */
449    CRC_SOURCE_FLASH_gc = (0x02<<0),  /* Flash */
450    CRC_SOURCE_DMAC0_gc = (0x04<<0),  /* DMAC Channel 0 */
451    CRC_SOURCE_DMAC1_gc = (0x05<<0),  /* DMAC Channel 1 */
452    CRC_SOURCE_DMAC2_gc = (0x06<<0),  /* DMAC Channel 2 */
453    CRC_SOURCE_DMAC3_gc = (0x07<<0),  /* DMAC Channel 3 */
454} CRC_SOURCE_t;
455
456
457/*
458--------------------------------------------------------------------------
459EVSYS - Event System
460--------------------------------------------------------------------------
461*/
462
463/* Event System */
464typedef struct EVSYS_struct
465{
466    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
467    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
468    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
469    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
470    register8_t reserved_0x04;
471    register8_t reserved_0x05;
472    register8_t reserved_0x06;
473    register8_t reserved_0x07;
474    register8_t CH0CTRL;  /* Channel 0 Control Register */
475    register8_t CH1CTRL;  /* Channel 1 Control Register */
476    register8_t CH2CTRL;  /* Channel 2 Control Register */
477    register8_t CH3CTRL;  /* Channel 3 Control Register */
478    register8_t reserved_0x0C;
479    register8_t reserved_0x0D;
480    register8_t reserved_0x0E;
481    register8_t reserved_0x0F;
482    register8_t STROBE;  /* Event Strobe */
483    register8_t DATA;  /* Event Data */
484} EVSYS_t;
485
486/* Quadrature Decoder Index Recognition Mode */
487typedef enum EVSYS_QDIRM_enum
488{
489    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
490    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
491    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
492    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
493} EVSYS_QDIRM_t;
494
495/* Digital filter coefficient */
496typedef enum EVSYS_DIGFILT_enum
497{
498    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
499    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
500    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
501    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
502    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
503    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
504    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
505    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
506} EVSYS_DIGFILT_t;
507
508/* Event Channel multiplexer input selection */
509typedef enum EVSYS_CHMUX_enum
510{
511    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
512    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
513    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
514    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
515    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
516    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
517    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
518    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
519    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
520    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
521    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
522    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
523    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
524    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
525    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
526    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
527    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
528    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
529    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
530    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
531    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
532    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
533    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
534    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
535    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
536    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
537    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
538    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
539    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
540    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
541    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
542    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
543    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
544    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
545    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
546    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
547    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
548    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
549    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
550    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
551    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
552    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
553    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
554    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
555    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
556    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
557    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
558    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
559    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
560    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
561    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
562    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
563    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
564    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
565    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
566    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
567    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
568    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
569    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
570    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
571    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
572    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
573    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
574    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
575    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
576    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
577    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
578    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
579    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
580    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
581    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
582    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
583    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
584    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
585    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
586    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
587    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
588    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
589    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
590    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
591    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
592    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
593    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
594    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
595    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
596    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
597    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
598    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
599    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
600    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
601    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
602    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
603    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
604    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
605    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
606    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
607    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
608    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
609    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
610    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
611    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
612    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
613    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
614    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
615    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
616    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
617    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
618    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
619    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
620    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
621    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
622} EVSYS_CHMUX_t;
623
624
625/*
626--------------------------------------------------------------------------
627NVM - Non Volatile Memory Controller
628--------------------------------------------------------------------------
629*/
630
631/* Non-volatile Memory Controller */
632typedef struct NVM_struct
633{
634    register8_t ADDR0;  /* Address Register 0 */
635    register8_t ADDR1;  /* Address Register 1 */
636    register8_t ADDR2;  /* Address Register 2 */
637    register8_t reserved_0x03;
638    register8_t DATA0;  /* Data Register 0 */
639    register8_t DATA1;  /* Data Register 1 */
640    register8_t DATA2;  /* Data Register 2 */
641    register8_t reserved_0x07;
642    register8_t reserved_0x08;
643    register8_t reserved_0x09;
644    register8_t CMD;  /* Command */
645    register8_t CTRLA;  /* Control Register A */
646    register8_t CTRLB;  /* Control Register B */
647    register8_t INTCTRL;  /* Interrupt Control */
648    register8_t reserved_0x0E;
649    register8_t STATUS;  /* Status */
650    register8_t LOCKBITS;  /* Lock Bits */
651} NVM_t;
652
653/*
654--------------------------------------------------------------------------
655NVM - Non Volatile Memory Controller
656--------------------------------------------------------------------------
657*/
658
659/* Lock Bits */
660typedef struct NVM_LOCKBITS_struct
661{
662    register8_t LOCKBITS;  /* Lock Bits */
663} NVM_LOCKBITS_t;
664
665/*
666--------------------------------------------------------------------------
667NVM - Non Volatile Memory Controller
668--------------------------------------------------------------------------
669*/
670
671/* Fuses */
672typedef struct NVM_FUSES_struct
673{
674    register8_t FUSEBYTE0;  /* User ID */
675    register8_t FUSEBYTE1;  /* Watchdog Configuration */
676    register8_t FUSEBYTE2;  /* Reset Configuration */
677    register8_t reserved_0x03;
678    register8_t FUSEBYTE4;  /* Start-up Configuration */
679    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
680} NVM_FUSES_t;
681
682/*
683--------------------------------------------------------------------------
684NVM - Non Volatile Memory Controller
685--------------------------------------------------------------------------
686*/
687
688/* Production Signatures */
689typedef struct NVM_PROD_SIGNATURES_struct
690{
691    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
692    register8_t reserved_0x01;
693    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
694    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
695    register8_t reserved_0x04;
696    register8_t reserved_0x05;
697    register8_t reserved_0x06;
698    register8_t reserved_0x07;
699    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
700    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
701    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
702    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
703    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
704    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
705    register8_t reserved_0x0E;
706    register8_t reserved_0x0F;
707    register8_t WAFNUM;  /* Wafer Number */
708    register8_t reserved_0x11;
709    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
710    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
711    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
712    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
713    register8_t reserved_0x16;
714    register8_t reserved_0x17;
715    register8_t reserved_0x18;
716    register8_t reserved_0x19;
717    register8_t reserved_0x1A;
718    register8_t reserved_0x1B;
719    register8_t reserved_0x1C;
720    register8_t reserved_0x1D;
721    register8_t reserved_0x1E;
722    register8_t reserved_0x1F;
723    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
724    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
725    register8_t reserved_0x22;
726    register8_t reserved_0x23;
727    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
728    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
729    register8_t reserved_0x26;
730    register8_t reserved_0x27;
731    register8_t reserved_0x28;
732    register8_t reserved_0x29;
733    register8_t reserved_0x2A;
734    register8_t reserved_0x2B;
735    register8_t reserved_0x2C;
736    register8_t reserved_0x2D;
737    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
738    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
739    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
740    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
741    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
742    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
743    register8_t reserved_0x34;
744    register8_t reserved_0x35;
745    register8_t reserved_0x36;
746    register8_t reserved_0x37;
747    register8_t reserved_0x38;
748    register8_t reserved_0x39;
749    register8_t reserved_0x3A;
750    register8_t reserved_0x3B;
751    register8_t reserved_0x3C;
752    register8_t reserved_0x3D;
753    register8_t reserved_0x3E;
754} NVM_PROD_SIGNATURES_t;
755
756/* NVM Command */
757typedef enum NVM_CMD_enum
758{
759    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
760    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
761    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
762    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
763    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
764    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
765    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
766    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
767    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
768    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
769    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
770    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
771    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
772    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
773    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
774    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
775    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
776    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
777    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
778    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
779    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
780    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
781    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
782    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
783    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
784    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
785} NVM_CMD_t;
786
787/* SPM ready interrupt level */
788typedef enum NVM_SPMLVL_enum
789{
790    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
791    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
792    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
793    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
794} NVM_SPMLVL_t;
795
796/* EEPROM ready interrupt level */
797typedef enum NVM_EELVL_enum
798{
799    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
800    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
801    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
802    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
803} NVM_EELVL_t;
804
805/* Boot lock bits - boot setcion */
806typedef enum NVM_BLBB_enum
807{
808    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
809    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
810    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
811    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
812} NVM_BLBB_t;
813
814/* Boot lock bits - application section */
815typedef enum NVM_BLBA_enum
816{
817    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
818    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
819    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
820    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
821} NVM_BLBA_t;
822
823/* Boot lock bits - application table section */
824typedef enum NVM_BLBAT_enum
825{
826    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
827    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
828    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
829    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
830} NVM_BLBAT_t;
831
832/* Lock bits */
833typedef enum NVM_LB_enum
834{
835    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
836    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
837    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
838} NVM_LB_t;
839
840/* Boot Loader Section Reset Vector */
841typedef enum BOOTRST_enum
842{
843    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
844    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
845} BOOTRST_t;
846
847/* BOD operation */
848typedef enum BOD_enum
849{
850    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
851    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
852    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
853} BOD_t;
854
855/* Watchdog (Window) Timeout Period */
856typedef enum WD_enum
857{
858    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
859    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
860    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
861    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
862    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
863    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
864    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
865    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
866    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
867    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
868    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
869} WD_t;
870
871/* Start-up Time */
872typedef enum SUT_enum
873{
874    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
875    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
876    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
877} SUT_t;
878
879/* Brown Out Detection Voltage Level */
880typedef enum BODLVL_enum
881{
882    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
883    BODLVL_1V9_gc = (0x06<<0),  /* 1.9 V */
884    BODLVL_2V1_gc = (0x05<<0),  /* 2.1 V */
885    BODLVL_2V4_gc = (0x04<<0),  /* 2.4 V */
886    BODLVL_2V6_gc = (0x03<<0),  /* 2.6 V */
887    BODLVL_2V9_gc = (0x02<<0),  /* 2.9 V */
888    BODLVL_3V2_gc = (0x01<<0),  /* 3.2 V */
889} BODLVL_t;
890
891
892/*
893--------------------------------------------------------------------------
894AC - Analog Comparator
895--------------------------------------------------------------------------
896*/
897
898/* Analog Comparator */
899typedef struct AC_struct
900{
901    register8_t AC0CTRL;  /* Comparator 0 Control */
902    register8_t AC1CTRL;  /* Comparator 1 Control */
903    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
904    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
905    register8_t CTRLA;  /* Control Register A */
906    register8_t CTRLB;  /* Control Register B */
907    register8_t WINCTRL;  /* Window Mode Control */
908    register8_t STATUS;  /* Status */
909} AC_t;
910
911/* Interrupt mode */
912typedef enum AC_INTMODE_enum
913{
914    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
915    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
916    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
917} AC_INTMODE_t;
918
919/* Interrupt level */
920typedef enum AC_INTLVL_enum
921{
922    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
923    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
924    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
925    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
926} AC_INTLVL_t;
927
928/* Hysteresis mode selection */
929typedef enum AC_HYSMODE_enum
930{
931    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
932    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
933    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
934} AC_HYSMODE_t;
935
936/* Positive input multiplexer selection */
937typedef enum AC_MUXPOS_enum
938{
939    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
940    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
941    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
942    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
943    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
944    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
945    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
946    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
947} AC_MUXPOS_t;
948
949/* Negative input multiplexer selection */
950typedef enum AC_MUXNEG_enum
951{
952    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
953    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
954    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
955    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
956    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
957    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
958    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
959    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
960} AC_MUXNEG_t;
961
962/* Windows interrupt mode */
963typedef enum AC_WINTMODE_enum
964{
965    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
966    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
967    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
968    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
969} AC_WINTMODE_t;
970
971/* Window interrupt level */
972typedef enum AC_WINTLVL_enum
973{
974    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
975    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
976    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
977    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
978} AC_WINTLVL_t;
979
980/* Window mode state */
981typedef enum AC_WSTATE_enum
982{
983    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
984    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
985    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
986} AC_WSTATE_t;
987
988
989/*
990--------------------------------------------------------------------------
991ADC - Analog/Digital Converter
992--------------------------------------------------------------------------
993*/
994
995/* ADC Channel */
996typedef struct ADC_CH_struct
997{
998    register8_t CTRL;  /* Control Register */
999    register8_t MUXCTRL;  /* MUX Control */
1000    register8_t INTCTRL;  /* Channel Interrupt Control */
1001    register8_t INTFLAGS;  /* Interrupt Flags */
1002    _WORDREGISTER(RES);  /* Channel Result */
1003    register8_t reserved_0x6;
1004    register8_t reserved_0x7;
1005} ADC_CH_t;
1006
1007/*
1008--------------------------------------------------------------------------
1009ADC - Analog/Digital Converter
1010--------------------------------------------------------------------------
1011*/
1012
1013/* Analog-to-Digital Converter */
1014typedef struct ADC_struct
1015{
1016    register8_t CTRLA;  /* Control Register A */
1017    register8_t CTRLB;  /* Control Register B */
1018    register8_t REFCTRL;  /* Reference Control */
1019    register8_t EVCTRL;  /* Event Control */
1020    register8_t PRESCALER;  /* Clock Prescaler */
1021    register8_t reserved_0x05;
1022    register8_t INTFLAGS;  /* Interrupt Flags */
1023    register8_t reserved_0x07;
1024    register8_t reserved_0x08;
1025    register8_t reserved_0x09;
1026    register8_t reserved_0x0A;
1027    register8_t reserved_0x0B;
1028    _WORDREGISTER(CAL);  /* Calibration Value */
1029    register8_t reserved_0x0E;
1030    register8_t reserved_0x0F;
1031    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
1032    register8_t reserved_0x12;
1033    register8_t reserved_0x13;
1034    register8_t reserved_0x14;
1035    register8_t reserved_0x15;
1036    register8_t reserved_0x16;
1037    register8_t reserved_0x17;
1038    _WORDREGISTER(CMP);  /* Compare Value */
1039    register8_t reserved_0x1A;
1040    register8_t reserved_0x1B;
1041    register8_t reserved_0x1C;
1042    register8_t reserved_0x1D;
1043    register8_t reserved_0x1E;
1044    register8_t reserved_0x1F;
1045    ADC_CH_t CH0;  /* ADC Channel 0 */
1046} ADC_t;
1047
1048/* Current Limitation */
1049typedef enum ADC_CURRLIMIT_enum
1050{
1051    ADC_CURRLIMIT_NO_gc = (0x00<<5),  /* No current limit,     300ksps max sampling rate */
1052    ADC_CURRLIMIT_LOW_gc = (0x01<<5),  /* Low current limit,    225ksps max sampling rate */
1053    ADC_CURRLIMIT_MED_gc = (0x02<<5),  /* Medium current limit, 150ksps max sampling rate */
1054    ADC_CURRLIMIT_HIGH_gc = (0x03<<5),  /* High current limit,   75ksps max sampling rate */
1055} ADC_CURRLIMIT_t;
1056
1057/* Positive input multiplexer selection */
1058typedef enum ADC_CH_MUXPOS_enum
1059{
1060    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
1061    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
1062    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
1063    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
1064    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
1065    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
1066    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
1067    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
1068} ADC_CH_MUXPOS_t;
1069
1070/* Internal input multiplexer selections */
1071typedef enum ADC_CH_MUXINT_enum
1072{
1073    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
1074    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
1075    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
1076    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
1077} ADC_CH_MUXINT_t;
1078
1079/* Negative input multiplexer selection */
1080typedef enum ADC_CH_MUXNEG_enum
1081{
1082    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
1083    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
1084    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
1085    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
1086    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
1087    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
1088    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
1089    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
1090} ADC_CH_MUXNEG_t;
1091
1092/* Input mode */
1093typedef enum ADC_CH_INPUTMODE_enum
1094{
1095    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
1096    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
1097    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
1098    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
1099} ADC_CH_INPUTMODE_t;
1100
1101/* Gain factor */
1102typedef enum ADC_CH_GAIN_enum
1103{
1104    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
1105    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
1106    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
1107    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
1108    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
1109    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
1110    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
1111    ADC_CH_GAIN_DIV2_gc = (0x07<<2),  /* x/2 gain */           
1112} ADC_CH_GAIN_t;
1113
1114/* Conversion result resolution */
1115typedef enum ADC_RESOLUTION_enum
1116{
1117    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
1118    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
1119    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
1120} ADC_RESOLUTION_t;
1121
1122/* Voltage reference selection */
1123typedef enum ADC_REFSEL_enum
1124{
1125    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
1126    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC/1.6V */
1127    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
1128    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
1129} ADC_REFSEL_t;
1130
1131/* Channel sweep selection */
1132typedef enum ADC_SWEEP_enum
1133{
1134    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
1135} ADC_SWEEP_t;
1136
1137/* Event channel input selection */
1138typedef enum ADC_EVSEL_enum
1139{
1140    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
1141    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
1142    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
1143    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
1144    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
1145    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
1146    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
1147    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
1148} ADC_EVSEL_t;
1149
1150/* Event action selection */
1151typedef enum ADC_EVACT_enum
1152{
1153    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
1154    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
1155} ADC_EVACT_t;
1156
1157/* Interupt mode */
1158typedef enum ADC_CH_INTMODE_enum
1159{
1160    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
1161    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
1162    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
1163} ADC_CH_INTMODE_t;
1164
1165/* Interrupt level */
1166typedef enum ADC_CH_INTLVL_enum
1167{
1168    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
1169    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
1170    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
1171    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
1172} ADC_CH_INTLVL_t;
1173
1174/* Clock prescaler */
1175typedef enum ADC_PRESCALER_enum
1176{
1177    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
1178    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
1179    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
1180    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
1181    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
1182    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
1183    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
1184    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
1185} ADC_PRESCALER_t;
1186
1187
1188/*
1189--------------------------------------------------------------------------
1190RTC - Real-Time Clounter
1191--------------------------------------------------------------------------
1192*/
1193
1194/* Real-Time Counter */
1195typedef struct RTC_struct
1196{
1197    register8_t CTRL;  /* Control Register */
1198    register8_t STATUS;  /* Status Register */
1199    register8_t INTCTRL;  /* Interrupt Control Register */
1200    register8_t INTFLAGS;  /* Interrupt Flags */
1201    register8_t TEMP;  /* Temporary register */
1202    register8_t reserved_0x05;
1203    register8_t reserved_0x06;
1204    register8_t reserved_0x07;
1205    _WORDREGISTER(CNT);  /* Count Register */
1206    _WORDREGISTER(PER);  /* Period Register */
1207    _WORDREGISTER(COMP);  /* Compare Register */
1208} RTC_t;
1209
1210/* Prescaler Factor */
1211typedef enum RTC_PRESCALER_enum
1212{
1213    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
1214    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
1215    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
1216    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
1217    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
1218    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
1219    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
1220    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
1221} RTC_PRESCALER_t;
1222
1223/* Compare Interrupt level */
1224typedef enum RTC_COMPINTLVL_enum
1225{
1226    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1227    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1228    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1229    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
1230} RTC_COMPINTLVL_t;
1231
1232/* Overflow Interrupt level */
1233typedef enum RTC_OVFINTLVL_enum
1234{
1235    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1236    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1237    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1238    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
1239} RTC_OVFINTLVL_t;
1240
1241
1242/*
1243--------------------------------------------------------------------------
1244EBI - External Bus Interface
1245--------------------------------------------------------------------------
1246*/
1247
1248/* EBI Chip Select Module */
1249typedef struct EBI_CS_struct
1250{
1251    register8_t CTRLA;  /* Chip Select Control Register A */
1252    register8_t CTRLB;  /* Chip Select Control Register B */
1253    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
1254} EBI_CS_t;
1255
1256/*
1257--------------------------------------------------------------------------
1258EBI - External Bus Interface
1259--------------------------------------------------------------------------
1260*/
1261
1262/* External Bus Interface */
1263typedef struct EBI_struct
1264{
1265    register8_t CTRL;  /* Control */
1266    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
1267    register8_t reserved_0x02;
1268    register8_t reserved_0x03;
1269    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
1270    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
1271    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
1272    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
1273    register8_t reserved_0x0A;
1274    register8_t reserved_0x0B;
1275    register8_t reserved_0x0C;
1276    register8_t reserved_0x0D;
1277    register8_t reserved_0x0E;
1278    register8_t reserved_0x0F;
1279    EBI_CS_t CS0;  /* Chip Select 0 */
1280    EBI_CS_t CS1;  /* Chip Select 1 */
1281    EBI_CS_t CS2;  /* Chip Select 2 */
1282    EBI_CS_t CS3;  /* Chip Select 3 */
1283} EBI_t;
1284
1285/* Chip Select adress space */
1286typedef enum EBI_CS_ASIZE_enum
1287{
1288    EBI_CS_ASIZE_256B_gc = (0x00<<2),  /* 256 bytes */
1289    EBI_CS_ASIZE_512B_gc = (0x01<<2),  /* 512 bytes */
1290    EBI_CS_ASIZE_1KB_gc = (0x02<<2),  /* 1K bytes */
1291    EBI_CS_ASIZE_2KB_gc = (0x03<<2),  /* 2K bytes */
1292    EBI_CS_ASIZE_4KB_gc = (0x04<<2),  /* 4K bytes */
1293    EBI_CS_ASIZE_8KB_gc = (0x05<<2),  /* 8K bytes */
1294    EBI_CS_ASIZE_16KB_gc = (0x06<<2),  /* 16K bytes */
1295    EBI_CS_ASIZE_32KB_gc = (0x07<<2),  /* 32K bytes */
1296    EBI_CS_ASIZE_64KB_gc = (0x08<<2),  /* 64K bytes */
1297    EBI_CS_ASIZE_128KB_gc = (0x09<<2),  /* 128K bytes */
1298    EBI_CS_ASIZE_256KB_gc = (0x0A<<2),  /* 256K bytes */
1299    EBI_CS_ASIZE_512KB_gc = (0x0B<<2),  /* 512K bytes */
1300    EBI_CS_ASIZE_1MB_gc = (0x0C<<2),  /* 1M bytes */
1301    EBI_CS_ASIZE_2MB_gc = (0x0D<<2),  /* 2M bytes */
1302    EBI_CS_ASIZE_4MB_gc = (0x0E<<2),  /* 4M bytes */
1303    EBI_CS_ASIZE_8MB_gc = (0x0F<<2),  /* 8M bytes */
1304    EBI_CS_ASIZE_16M_gc = (0x10<<2),  /* 16M bytes */
1305} EBI_CS_ASIZE_t;
1306
1307/*  */
1308typedef enum EBI_CS_SRWS_enum
1309{
1310    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
1311    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
1312    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
1313    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
1314    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
1315    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
1316    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
1317    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
1318} EBI_CS_SRWS_t;
1319
1320/* Chip Select address mode */
1321typedef enum EBI_CS_MODE_enum
1322{
1323    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
1324    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
1325    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
1326    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
1327} EBI_CS_MODE_t;
1328
1329/* Chip Select SDRAM mode */
1330typedef enum EBI_CS_SDMODE_enum
1331{
1332    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
1333    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
1334} EBI_CS_SDMODE_t;
1335
1336/*  */
1337typedef enum EBI_SDDATAW_enum
1338{
1339    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
1340    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
1341} EBI_SDDATAW_t;
1342
1343/*  */
1344typedef enum EBI_LPCMODE_enum
1345{
1346    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
1347    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
1348} EBI_LPCMODE_t;
1349
1350/*  */
1351typedef enum EBI_SRMODE_enum
1352{
1353    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
1354    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
1355    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
1356    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
1357} EBI_SRMODE_t;
1358
1359/*  */
1360typedef enum EBI_IFMODE_enum
1361{
1362    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
1363    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
1364    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
1365    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
1366} EBI_IFMODE_t;
1367
1368/*  */
1369typedef enum EBI_SDCOL_enum
1370{
1371    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
1372    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
1373    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
1374    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
1375} EBI_SDCOL_t;
1376
1377/*  */
1378typedef enum EBI_MRDLY_enum
1379{
1380    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
1381    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
1382    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
1383    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
1384} EBI_MRDLY_t;
1385
1386/*  */
1387typedef enum EBI_ROWCYCDLY_enum
1388{
1389    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
1390    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
1391    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
1392    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
1393    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
1394    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
1395    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
1396    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
1397} EBI_ROWCYCDLY_t;
1398
1399/*  */
1400typedef enum EBI_RPDLY_enum
1401{
1402    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
1403    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
1404    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
1405    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
1406    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
1407    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
1408    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
1409    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
1410} EBI_RPDLY_t;
1411
1412/*  */
1413typedef enum EBI_WRDLY_enum
1414{
1415    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
1416    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
1417    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
1418    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
1419} EBI_WRDLY_t;
1420
1421/*  */
1422typedef enum EBI_ESRDLY_enum
1423{
1424    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
1425    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
1426    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
1427    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
1428    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
1429    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
1430    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
1431    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
1432} EBI_ESRDLY_t;
1433
1434/*  */
1435typedef enum EBI_ROWCOLDLY_enum
1436{
1437    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
1438    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
1439    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
1440    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
1441    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
1442    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
1443    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
1444    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
1445} EBI_ROWCOLDLY_t;
1446
1447
1448/*
1449--------------------------------------------------------------------------
1450TWI - Two-Wire Interface
1451--------------------------------------------------------------------------
1452*/
1453
1454/*  */
1455typedef struct TWI_MASTER_struct
1456{
1457    register8_t CTRLA;  /* Control Register A */
1458    register8_t CTRLB;  /* Control Register B */
1459    register8_t CTRLC;  /* Control Register C */
1460    register8_t STATUS;  /* Status Register */
1461    register8_t BAUD;  /* Baurd Rate Control Register */
1462    register8_t ADDR;  /* Address Register */
1463    register8_t DATA;  /* Data Register */
1464} TWI_MASTER_t;
1465
1466/*
1467--------------------------------------------------------------------------
1468TWI - Two-Wire Interface
1469--------------------------------------------------------------------------
1470*/
1471
1472/*  */
1473typedef struct TWI_SLAVE_struct
1474{
1475    register8_t CTRLA;  /* Control Register A */
1476    register8_t CTRLB;  /* Control Register B */
1477    register8_t STATUS;  /* Status Register */
1478    register8_t ADDR;  /* Address Register */
1479    register8_t DATA;  /* Data Register */
1480    register8_t ADDRMASK;  /* Address Mask Register */
1481} TWI_SLAVE_t;
1482
1483/*
1484--------------------------------------------------------------------------
1485TWI - Two-Wire Interface
1486--------------------------------------------------------------------------
1487*/
1488
1489/* Two-Wire Interface */
1490typedef struct TWI_struct
1491{
1492    register8_t CTRL;  /* TWI Common Control Register */
1493    TWI_MASTER_t MASTER;  /* TWI master module */
1494    TWI_SLAVE_t SLAVE;  /* TWI slave module */
1495} TWI_t;
1496
1497/* Master Interrupt Level */
1498typedef enum TWI_MASTER_INTLVL_enum
1499{
1500    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1501    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
1502    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1503    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
1504} TWI_MASTER_INTLVL_t;
1505
1506/* Inactive Timeout */
1507typedef enum TWI_MASTER_TIMEOUT_enum
1508{
1509    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
1510    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
1511    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
1512    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
1513} TWI_MASTER_TIMEOUT_t;
1514
1515/* Master Command */
1516typedef enum TWI_MASTER_CMD_enum
1517{
1518    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
1519    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
1520    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
1521    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
1522} TWI_MASTER_CMD_t;
1523
1524/* Master Bus State */
1525typedef enum TWI_MASTER_BUSSTATE_enum
1526{
1527    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
1528    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
1529    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
1530    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
1531} TWI_MASTER_BUSSTATE_t;
1532
1533/* Slave Interrupt Level */
1534typedef enum TWI_SLAVE_INTLVL_enum
1535{
1536    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1537    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
1538    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1539    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
1540} TWI_SLAVE_INTLVL_t;
1541
1542/* Slave Command */
1543typedef enum TWI_SLAVE_CMD_enum
1544{
1545    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
1546    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
1547    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
1548} TWI_SLAVE_CMD_t;
1549
1550
1551/*
1552--------------------------------------------------------------------------
1553PORT - Port Configuration
1554--------------------------------------------------------------------------
1555*/
1556
1557/* I/O port Configuration */
1558typedef struct PORTCFG_struct
1559{
1560    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
1561    register8_t reserved_0x01;
1562    register8_t VPCTRLA;  /* Virtual Port Control Register A */
1563    register8_t VPCTRLB;  /* Virtual Port Control Register B */
1564    register8_t CLKEVOUT;  /* Clock and Event Out Register */
1565} PORTCFG_t;
1566
1567/*
1568--------------------------------------------------------------------------
1569PORT - Port Configuration
1570--------------------------------------------------------------------------
1571*/
1572
1573/* Virtual Port */
1574typedef struct VPORT_struct
1575{
1576    register8_t DIR;  /* I/O Port Data Direction */
1577    register8_t OUT;  /* I/O Port Output */
1578    register8_t IN;  /* I/O Port Input */
1579    register8_t INTFLAGS;  /* Interrupt Flag Register */
1580} VPORT_t;
1581
1582/*
1583--------------------------------------------------------------------------
1584PORT - Port Configuration
1585--------------------------------------------------------------------------
1586*/
1587
1588/* I/O Ports */
1589typedef struct PORT_struct
1590{
1591    register8_t DIR;  /* I/O Port Data Direction */
1592    register8_t DIRSET;  /* I/O Port Data Direction Set */
1593    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
1594    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
1595    register8_t OUT;  /* I/O Port Output */
1596    register8_t OUTSET;  /* I/O Port Output Set */
1597    register8_t OUTCLR;  /* I/O Port Output Clear */
1598    register8_t OUTTGL;  /* I/O Port Output Toggle */
1599    register8_t IN;  /* I/O port Input */
1600    register8_t INTCTRL;  /* Interrupt Control Register */
1601    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
1602    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
1603    register8_t INTFLAGS;  /* Interrupt Flag Register */
1604    register8_t reserved_0x0D;
1605    register8_t reserved_0x0E;
1606    register8_t reserved_0x0F;
1607    register8_t PIN0CTRL;  /* Pin 0 Control Register */
1608    register8_t PIN1CTRL;  /* Pin 1 Control Register */
1609    register8_t PIN2CTRL;  /* Pin 2 Control Register */
1610    register8_t PIN3CTRL;  /* Pin 3 Control Register */
1611    register8_t PIN4CTRL;  /* Pin 4 Control Register */
1612    register8_t PIN5CTRL;  /* Pin 5 Control Register */
1613    register8_t PIN6CTRL;  /* Pin 6 Control Register */
1614    register8_t PIN7CTRL;  /* Pin 7 Control Register */
1615} PORT_t;
1616
1617/* Virtual Port 0 Mapping */
1618typedef enum PORTCFG_VP0MAP_enum
1619{
1620    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
1621    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
1622    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
1623    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
1624    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
1625    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
1626    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
1627    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
1628    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
1629    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
1630    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
1631    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
1632    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
1633    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
1634    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
1635    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
1636} PORTCFG_VP0MAP_t;
1637
1638/* Virtual Port 1 Mapping */
1639typedef enum PORTCFG_VP1MAP_enum
1640{
1641    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
1642    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
1643    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
1644    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
1645    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
1646    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
1647    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
1648    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
1649    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
1650    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
1651    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
1652    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
1653    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
1654    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
1655    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
1656    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
1657} PORTCFG_VP1MAP_t;
1658
1659/* Virtual Port 2 Mapping */
1660typedef enum PORTCFG_VP2MAP_enum
1661{
1662    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
1663    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
1664    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
1665    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
1666    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
1667    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
1668    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
1669    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
1670    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
1671    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
1672    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
1673    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
1674    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
1675    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
1676    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
1677    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
1678} PORTCFG_VP2MAP_t;
1679
1680/* Virtual Port 3 Mapping */
1681typedef enum PORTCFG_VP3MAP_enum
1682{
1683    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
1684    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
1685    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
1686    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
1687    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
1688    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
1689    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
1690    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
1691    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
1692    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
1693    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
1694    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
1695    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
1696    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
1697    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
1698    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
1699} PORTCFG_VP3MAP_t;
1700
1701/* Clock Output Port */
1702typedef enum PORTCFG_CLKOUT_enum
1703{
1704    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
1705    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
1706    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
1707    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
1708} PORTCFG_CLKOUT_t;
1709
1710/* Event Output Port */
1711typedef enum PORTCFG_EVOUT_enum
1712{
1713    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
1714    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
1715    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
1716    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
1717} PORTCFG_EVOUT_t;
1718
1719/* Port Interrupt 0 Level */
1720typedef enum PORT_INT0LVL_enum
1721{
1722    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1723    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
1724    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
1725    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
1726} PORT_INT0LVL_t;
1727
1728/* Port Interrupt 1 Level */
1729typedef enum PORT_INT1LVL_enum
1730{
1731    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1732    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
1733    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
1734    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
1735} PORT_INT1LVL_t;
1736
1737/* Output/Pull Configuration */
1738typedef enum PORT_OPC_enum
1739{
1740    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
1741    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
1742    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
1743    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
1744    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
1745    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
1746    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
1747    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
1748} PORT_OPC_t;
1749
1750/* Input/Sense Configuration */
1751typedef enum PORT_ISC_enum
1752{
1753    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
1754    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
1755    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
1756    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
1757    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
1758} PORT_ISC_t;
1759
1760
1761/*
1762--------------------------------------------------------------------------
1763TC - 16-bit Timer/Counter With PWM
1764--------------------------------------------------------------------------
1765*/
1766
1767/* 16-bit Timer/Counter 0 */
1768typedef struct TC0_struct
1769{
1770    register8_t CTRLA;  /* Control  Register A */
1771    register8_t CTRLB;  /* Control Register B */
1772    register8_t CTRLC;  /* Control register C */
1773    register8_t CTRLD;  /* Control Register D */
1774    register8_t CTRLE;  /* Control Register E */
1775    register8_t reserved_0x05;
1776    register8_t INTCTRLA;  /* Interrupt Control Register A */
1777    register8_t INTCTRLB;  /* Interrupt Control Register B */
1778    register8_t CTRLFCLR;  /* Control Register F Clear */
1779    register8_t CTRLFSET;  /* Control Register F Set */
1780    register8_t CTRLGCLR;  /* Control Register G Clear */
1781    register8_t CTRLGSET;  /* Control Register G Set */
1782    register8_t INTFLAGS;  /* Interrupt Flag Register */
1783    register8_t reserved_0x0D;
1784    register8_t reserved_0x0E;
1785    register8_t TEMP;  /* Temporary Register For 16-bit Access */
1786    register8_t reserved_0x10;
1787    register8_t reserved_0x11;
1788    register8_t reserved_0x12;
1789    register8_t reserved_0x13;
1790    register8_t reserved_0x14;
1791    register8_t reserved_0x15;
1792    register8_t reserved_0x16;
1793    register8_t reserved_0x17;
1794    register8_t reserved_0x18;
1795    register8_t reserved_0x19;
1796    register8_t reserved_0x1A;
1797    register8_t reserved_0x1B;
1798    register8_t reserved_0x1C;
1799    register8_t reserved_0x1D;
1800    register8_t reserved_0x1E;
1801    register8_t reserved_0x1F;
1802    _WORDREGISTER(CNT);  /* Count */
1803    register8_t reserved_0x22;
1804    register8_t reserved_0x23;
1805    register8_t reserved_0x24;
1806    register8_t reserved_0x25;
1807    _WORDREGISTER(PER);  /* Period */
1808    _WORDREGISTER(CCA);  /* Compare or Capture A */
1809    _WORDREGISTER(CCB);  /* Compare or Capture B */
1810    _WORDREGISTER(CCC);  /* Compare or Capture C */
1811    _WORDREGISTER(CCD);  /* Compare or Capture D */
1812    register8_t reserved_0x30;
1813    register8_t reserved_0x31;
1814    register8_t reserved_0x32;
1815    register8_t reserved_0x33;
1816    register8_t reserved_0x34;
1817    register8_t reserved_0x35;
1818    _WORDREGISTER(PERBUF);  /* Period Buffer */
1819    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
1820    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
1821    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
1822    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
1823} TC0_t;
1824
1825/*
1826--------------------------------------------------------------------------
1827TC - 16-bit Timer/Counter With PWM
1828--------------------------------------------------------------------------
1829*/
1830
1831/* 16-bit Timer/Counter 1 */
1832typedef struct TC1_struct
1833{
1834    register8_t CTRLA;  /* Control  Register A */
1835    register8_t CTRLB;  /* Control Register B */
1836    register8_t CTRLC;  /* Control register C */
1837    register8_t CTRLD;  /* Control Register D */
1838    register8_t CTRLE;  /* Control Register E */
1839    register8_t reserved_0x05;
1840    register8_t INTCTRLA;  /* Interrupt Control Register A */
1841    register8_t INTCTRLB;  /* Interrupt Control Register B */
1842    register8_t CTRLFCLR;  /* Control Register F Clear */
1843    register8_t CTRLFSET;  /* Control Register F Set */
1844    register8_t CTRLGCLR;  /* Control Register G Clear */
1845    register8_t CTRLGSET;  /* Control Register G Set */
1846    register8_t INTFLAGS;  /* Interrupt Flag Register */
1847    register8_t reserved_0x0D;
1848    register8_t reserved_0x0E;
1849    register8_t TEMP;  /* Temporary Register For 16-bit Access */
1850    register8_t reserved_0x10;
1851    register8_t reserved_0x11;
1852    register8_t reserved_0x12;
1853    register8_t reserved_0x13;
1854    register8_t reserved_0x14;
1855    register8_t reserved_0x15;
1856    register8_t reserved_0x16;
1857    register8_t reserved_0x17;
1858    register8_t reserved_0x18;
1859    register8_t reserved_0x19;
1860    register8_t reserved_0x1A;
1861    register8_t reserved_0x1B;
1862    register8_t reserved_0x1C;
1863    register8_t reserved_0x1D;
1864    register8_t reserved_0x1E;
1865    register8_t reserved_0x1F;
1866    _WORDREGISTER(CNT);  /* Count */
1867    register8_t reserved_0x22;
1868    register8_t reserved_0x23;
1869    register8_t reserved_0x24;
1870    register8_t reserved_0x25;
1871    _WORDREGISTER(PER);  /* Period */
1872    _WORDREGISTER(CCA);  /* Compare or Capture A */
1873    _WORDREGISTER(CCB);  /* Compare or Capture B */
1874    register8_t reserved_0x2C;
1875    register8_t reserved_0x2D;
1876    register8_t reserved_0x2E;
1877    register8_t reserved_0x2F;
1878    register8_t reserved_0x30;
1879    register8_t reserved_0x31;
1880    register8_t reserved_0x32;
1881    register8_t reserved_0x33;
1882    register8_t reserved_0x34;
1883    register8_t reserved_0x35;
1884    _WORDREGISTER(PERBUF);  /* Period Buffer */
1885    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
1886    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
1887} TC1_t;
1888
1889/*
1890--------------------------------------------------------------------------
1891TC - 16-bit Timer/Counter With PWM
1892--------------------------------------------------------------------------
1893*/
1894
1895/* Advanced Waveform Extension */
1896typedef struct AWEX_struct
1897{
1898    register8_t CTRL;  /* Control Register */
1899    register8_t reserved_0x01;
1900    register8_t FDEMASK;  /* Fault Detection Event Mask */
1901    register8_t FDCTRL;  /* Fault Detection Control Register */
1902    register8_t STATUS;  /* Status Register */
1903    register8_t reserved_0x05;
1904    register8_t DTBOTH;  /* Dead Time Both Sides */
1905    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
1906    register8_t DTLS;  /* Dead Time Low Side */
1907    register8_t DTHS;  /* Dead Time High Side */
1908    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
1909    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
1910    register8_t OUTOVEN;  /* Output Override Enable */
1911} AWEX_t;
1912
1913/*
1914--------------------------------------------------------------------------
1915TC - 16-bit Timer/Counter With PWM
1916--------------------------------------------------------------------------
1917*/
1918
1919/* High-Resolution Extension */
1920typedef struct HIRES_struct
1921{
1922    register8_t CTRLA;  /* Control Register */
1923} HIRES_t;
1924
1925/* Clock Selection */
1926typedef enum TC_CLKSEL_enum
1927{
1928    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
1929    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
1930    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
1931    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
1932    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
1933    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
1934    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
1935    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
1936    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
1937    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
1938    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
1939    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
1940    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
1941    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
1942    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
1943    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
1944} TC_CLKSEL_t;
1945
1946/* Waveform Generation Mode */
1947typedef enum TC_WGMODE_enum
1948{
1949    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
1950    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
1951    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
1952    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
1953    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
1954    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
1955} TC_WGMODE_t;
1956
1957/* Event Action */
1958typedef enum TC_EVACT_enum
1959{
1960    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
1961    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
1962    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
1963    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
1964    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
1965    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
1966    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
1967} TC_EVACT_t;
1968
1969/* Event Selection */
1970typedef enum TC_EVSEL_enum
1971{
1972    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
1973    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
1974    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
1975    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
1976    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
1977    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
1978    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
1979    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
1980    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
1981} TC_EVSEL_t;
1982
1983/* Error Interrupt Level */
1984typedef enum TC_ERRINTLVL_enum
1985{
1986    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1987    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1988    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1989    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
1990} TC_ERRINTLVL_t;
1991
1992/* Overflow Interrupt Level */
1993typedef enum TC_OVFINTLVL_enum
1994{
1995    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1996    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1997    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1998    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
1999} TC_OVFINTLVL_t;
2000
2001/* Compare or Capture D Interrupt Level */
2002typedef enum TC_CCDINTLVL_enum
2003{
2004    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
2005    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
2006    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
2007    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
2008} TC_CCDINTLVL_t;
2009
2010/* Compare or Capture C Interrupt Level */
2011typedef enum TC_CCCINTLVL_enum
2012{
2013    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
2014    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
2015    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
2016    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
2017} TC_CCCINTLVL_t;
2018
2019/* Compare or Capture B Interrupt Level */
2020typedef enum TC_CCBINTLVL_enum
2021{
2022    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
2023    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
2024    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
2025    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
2026} TC_CCBINTLVL_t;
2027
2028/* Compare or Capture A Interrupt Level */
2029typedef enum TC_CCAINTLVL_enum
2030{
2031    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2032    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
2033    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2034    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
2035} TC_CCAINTLVL_t;
2036
2037/* Timer/Counter Command */
2038typedef enum TC_CMD_enum
2039{
2040    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
2041    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
2042    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
2043    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
2044} TC_CMD_t;
2045
2046/* Fault Detect Action */
2047typedef enum AWEX_FDACT_enum
2048{
2049    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
2050    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
2051    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
2052} AWEX_FDACT_t;
2053
2054/* High Resolution Enable */
2055typedef enum HIRES_HREN_enum
2056{
2057    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
2058    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
2059    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
2060    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
2061} HIRES_HREN_t;
2062
2063
2064/*
2065--------------------------------------------------------------------------
2066USART - Universal Asynchronous Receiver-Transmitter
2067--------------------------------------------------------------------------
2068*/
2069
2070/* Universal Synchronous/Asynchronous Receiver/Transmitter */
2071typedef struct USART_struct
2072{
2073    register8_t DATA;  /* Data Register */
2074    register8_t STATUS;  /* Status Register */
2075    register8_t reserved_0x02;
2076    register8_t CTRLA;  /* Control Register A */
2077    register8_t CTRLB;  /* Control Register B */
2078    register8_t CTRLC;  /* Control Register C */
2079    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
2080    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
2081} USART_t;
2082
2083/* Receive Complete Interrupt level */
2084typedef enum USART_RXCINTLVL_enum
2085{
2086    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
2087    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
2088    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
2089    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
2090} USART_RXCINTLVL_t;
2091
2092/* Transmit Complete Interrupt level */
2093typedef enum USART_TXCINTLVL_enum
2094{
2095    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
2096    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
2097    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
2098    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
2099} USART_TXCINTLVL_t;
2100
2101/* Data Register Empty Interrupt level */
2102typedef enum USART_DREINTLVL_enum
2103{
2104    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2105    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
2106    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2107    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
2108} USART_DREINTLVL_t;
2109
2110/* Character Size */
2111typedef enum USART_CHSIZE_enum
2112{
2113    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
2114    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
2115    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
2116    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
2117    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
2118} USART_CHSIZE_t;
2119
2120/* Communication Mode */
2121typedef enum USART_CMODE_enum
2122{
2123    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
2124    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
2125    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
2126    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
2127} USART_CMODE_t;
2128
2129/* Parity Mode */
2130typedef enum USART_PMODE_enum
2131{
2132    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
2133    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
2134    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
2135} USART_PMODE_t;
2136
2137
2138/*
2139--------------------------------------------------------------------------
2140SPI - Serial Peripheral Interface
2141--------------------------------------------------------------------------
2142*/
2143
2144/* Serial Peripheral Interface */
2145typedef struct SPI_struct
2146{
2147    register8_t CTRL;  /* Control Register */
2148    register8_t INTCTRL;  /* Interrupt Control Register */
2149    register8_t STATUS;  /* Status Register */
2150    register8_t DATA;  /* Data Register */
2151} SPI_t;
2152
2153/* SPI Mode */
2154typedef enum SPI_MODE_enum
2155{
2156    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
2157    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
2158    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
2159    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
2160} SPI_MODE_t;
2161
2162/* Prescaler setting */
2163typedef enum SPI_PRESCALER_enum
2164{
2165    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
2166    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
2167    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
2168    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
2169} SPI_PRESCALER_t;
2170
2171/* Interrupt level */
2172typedef enum SPI_INTLVL_enum
2173{
2174    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2175    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
2176    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2177    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
2178} SPI_INTLVL_t;
2179
2180
2181/*
2182--------------------------------------------------------------------------
2183IRCOM - IR Communication Module
2184--------------------------------------------------------------------------
2185*/
2186
2187/* IR Communication Module */
2188typedef struct IRCOM_struct
2189{
2190    register8_t CTRL;  /* Control Register */
2191    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
2192    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
2193} IRCOM_t;
2194
2195/* Event channel selection */
2196typedef enum IRDA_EVSEL_enum
2197{
2198    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
2199    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
2200    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
2201    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
2202    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
2203    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
2204    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
2205    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
2206    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
2207} IRDA_EVSEL_t;
2208
2209
2210
2211/*
2212==========================================================================
2213IO Module Instances. Mapped to memory.
2214==========================================================================
2215*/
2216
2217#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
2218#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
2219#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
2220#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
2221#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
2222#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
2223#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
2224#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
2225#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
2226#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
2227#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
2228#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
2229#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
2230#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
2231#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
2232#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
2233#define CRC    (*(CRC_t *) 0x00D0)  /* Cyclic Redundancy Checker */
2234#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
2235#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
2236#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
2237#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
2238#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
2239#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
2240#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
2241#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
2242#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
2243#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
2244#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
2245#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
2246#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
2247#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
2248#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
2249#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
2250#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
2251#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
2252#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
2253#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
2254#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
2255#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
2256#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
2257#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
2258#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
2259#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
2260#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
2261#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
2262#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
2263
2264
2265#endif /* !defined (__ASSEMBLER__) */
2266
2267
2268/* ========== Flattened fully qualified IO register names ========== */
2269
2270/* GPIO - General Purpose IO Registers */
2271#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
2272#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
2273#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
2274#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
2275#define GPIO_GPIOR4  _SFR_MEM8(0x0004)
2276#define GPIO_GPIOR5  _SFR_MEM8(0x0005)
2277#define GPIO_GPIOR6  _SFR_MEM8(0x0006)
2278#define GPIO_GPIOR7  _SFR_MEM8(0x0007)
2279#define GPIO_GPIOR8  _SFR_MEM8(0x0008)
2280#define GPIO_GPIOR9  _SFR_MEM8(0x0009)
2281#define GPIO_GPIORA  _SFR_MEM8(0x000A)
2282#define GPIO_GPIORB  _SFR_MEM8(0x000B)
2283#define GPIO_GPIORC  _SFR_MEM8(0x000C)
2284#define GPIO_GPIORD  _SFR_MEM8(0x000D)
2285#define GPIO_GPIORE  _SFR_MEM8(0x000E)
2286#define GPIO_GPIORF  _SFR_MEM8(0x000F)
2287
2288/* VPORT0 - Virtual Port 0 */
2289#define VPORT0_DIR  _SFR_MEM8(0x0010)
2290#define VPORT0_OUT  _SFR_MEM8(0x0011)
2291#define VPORT0_IN  _SFR_MEM8(0x0012)
2292#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
2293
2294/* VPORT1 - Virtual Port 1 */
2295#define VPORT1_DIR  _SFR_MEM8(0x0014)
2296#define VPORT1_OUT  _SFR_MEM8(0x0015)
2297#define VPORT1_IN  _SFR_MEM8(0x0016)
2298#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
2299
2300/* VPORT2 - Virtual Port 2 */
2301#define VPORT2_DIR  _SFR_MEM8(0x0018)
2302#define VPORT2_OUT  _SFR_MEM8(0x0019)
2303#define VPORT2_IN  _SFR_MEM8(0x001A)
2304#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
2305
2306/* VPORT3 - Virtual Port 3 */
2307#define VPORT3_DIR  _SFR_MEM8(0x001C)
2308#define VPORT3_OUT  _SFR_MEM8(0x001D)
2309#define VPORT3_IN  _SFR_MEM8(0x001E)
2310#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
2311
2312/* OCD - On-Chip Debug System */
2313#define OCD_OCDR0  _SFR_MEM8(0x002E)
2314#define OCD_OCDR1  _SFR_MEM8(0x002F)
2315
2316/* CPU - CPU Registers */
2317#define CPU_CCP  _SFR_MEM8(0x0034)
2318#define CPU_RAMPD  _SFR_MEM8(0x0038)
2319#define CPU_RAMPX  _SFR_MEM8(0x0039)
2320#define CPU_RAMPY  _SFR_MEM8(0x003A)
2321#define CPU_RAMPZ  _SFR_MEM8(0x003B)
2322#define CPU_EIND  _SFR_MEM8(0x003C)
2323#define CPU_SPL  _SFR_MEM8(0x003D)
2324#define CPU_SPH  _SFR_MEM8(0x003E)
2325#define CPU_SREG  _SFR_MEM8(0x003F)
2326
2327/* CLK - Clock System */
2328#define CLK_CTRL  _SFR_MEM8(0x0040)
2329#define CLK_PSCTRL  _SFR_MEM8(0x0041)
2330#define CLK_LOCK  _SFR_MEM8(0x0042)
2331#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
2332
2333/* SLEEP - Sleep Controller */
2334#define SLEEP_CTRL  _SFR_MEM8(0x0048)
2335
2336/* OSC - Oscillator Control */
2337#define OSC_CTRL  _SFR_MEM8(0x0050)
2338#define OSC_STATUS  _SFR_MEM8(0x0051)
2339#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
2340#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
2341#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
2342#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
2343#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
2344
2345/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
2346#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
2347#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
2348#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
2349#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
2350#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
2351#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
2352
2353/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
2354#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
2355#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
2356#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
2357#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
2358#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
2359#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
2360
2361/* PR - Power Reduction */
2362#define PR_PRGEN  _SFR_MEM8(0x0070)
2363#define PR_PRPA  _SFR_MEM8(0x0071)
2364#define PR_PRPC  _SFR_MEM8(0x0073)
2365#define PR_PRPD  _SFR_MEM8(0x0074)
2366#define PR_PRPE  _SFR_MEM8(0x0075)
2367#define PR_PRPF  _SFR_MEM8(0x0076)
2368
2369/* RST - Reset Controller */
2370#define RST_STATUS  _SFR_MEM8(0x0078)
2371#define RST_CTRL  _SFR_MEM8(0x0079)
2372
2373/* WDT - Watch-Dog Timer */
2374#define WDT_CTRL  _SFR_MEM8(0x0080)
2375#define WDT_WINCTRL  _SFR_MEM8(0x0081)
2376#define WDT_STATUS  _SFR_MEM8(0x0082)
2377
2378/* MCU - MCU Control */
2379#define MCU_DEVID0  _SFR_MEM8(0x0090)
2380#define MCU_DEVID1  _SFR_MEM8(0x0091)
2381#define MCU_DEVID2  _SFR_MEM8(0x0092)
2382#define MCU_REVID  _SFR_MEM8(0x0093)
2383#define MCU_JTAGUID  _SFR_MEM8(0x0094)
2384#define MCU_MCUCR  _SFR_MEM8(0x0096)
2385#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
2386#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
2387
2388/* PMIC - Programmable Interrupt Controller */
2389#define PMIC_STATUS  _SFR_MEM8(0x00A0)
2390#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
2391#define PMIC_CTRL  _SFR_MEM8(0x00A2)
2392
2393/* PORTCFG - Port Configuration */
2394#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
2395#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
2396#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
2397#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
2398
2399/* CRC - Cyclic Redundancy Checker */
2400#define CRC_CTRL  _SFR_MEM8(0x00D0)
2401#define CRC_STATUS  _SFR_MEM8(0x00D1)
2402#define CRC_DATAIN  _SFR_MEM8(0x00D3)
2403#define CRC_CHECKSUM0  _SFR_MEM8(0x00D4)
2404#define CRC_CHECKSUM1  _SFR_MEM8(0x00D5)
2405#define CRC_CHECKSUM2  _SFR_MEM8(0x00D6)
2406#define CRC_CHECKSUM3  _SFR_MEM8(0x00D7)
2407
2408/* EVSYS - Event System */
2409#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
2410#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
2411#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
2412#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
2413#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
2414#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
2415#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
2416#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
2417#define EVSYS_STROBE  _SFR_MEM8(0x0190)
2418#define EVSYS_DATA  _SFR_MEM8(0x0191)
2419
2420/* NVM - Non Volatile Memory Controller */
2421#define NVM_ADDR0  _SFR_MEM8(0x01C0)
2422#define NVM_ADDR1  _SFR_MEM8(0x01C1)
2423#define NVM_ADDR2  _SFR_MEM8(0x01C2)
2424#define NVM_DATA0  _SFR_MEM8(0x01C4)
2425#define NVM_DATA1  _SFR_MEM8(0x01C5)
2426#define NVM_DATA2  _SFR_MEM8(0x01C6)
2427#define NVM_CMD  _SFR_MEM8(0x01CA)
2428#define NVM_CTRLA  _SFR_MEM8(0x01CB)
2429#define NVM_CTRLB  _SFR_MEM8(0x01CC)
2430#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
2431#define NVM_STATUS  _SFR_MEM8(0x01CF)
2432#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
2433
2434/* ADCA - Analog to Digital Converter A */
2435#define ADCA_CTRLA  _SFR_MEM8(0x0200)
2436#define ADCA_CTRLB  _SFR_MEM8(0x0201)
2437#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
2438#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
2439#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
2440#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
2441#define ADCA_CAL  _SFR_MEM16(0x020C)
2442#define ADCA_CH0RES  _SFR_MEM16(0x0210)
2443#define ADCA_CMP  _SFR_MEM16(0x0218)
2444#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
2445#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
2446#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
2447#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
2448#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
2449
2450/* ACA - Analog Comparator A */
2451#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
2452#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
2453#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
2454#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
2455#define ACA_CTRLA  _SFR_MEM8(0x0384)
2456#define ACA_CTRLB  _SFR_MEM8(0x0385)
2457#define ACA_WINCTRL  _SFR_MEM8(0x0386)
2458#define ACA_STATUS  _SFR_MEM8(0x0387)
2459
2460/* RTC - Real-Time Counter */
2461#define RTC_CTRL  _SFR_MEM8(0x0400)
2462#define RTC_STATUS  _SFR_MEM8(0x0401)
2463#define RTC_INTCTRL  _SFR_MEM8(0x0402)
2464#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
2465#define RTC_TEMP  _SFR_MEM8(0x0404)
2466#define RTC_CNT  _SFR_MEM16(0x0408)
2467#define RTC_PER  _SFR_MEM16(0x040A)
2468#define RTC_COMP  _SFR_MEM16(0x040C)
2469
2470/* TWIC - Two-Wire Interface C */
2471#define TWIC_CTRL  _SFR_MEM8(0x0480)
2472#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0482)
2473#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0483)
2474#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0484)
2475#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0485)
2476#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0486)
2477#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0487)
2478#define TWIC_MASTER_DATA  _SFR_MEM8(0x0488)
2479#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
2480#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
2481#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
2482#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
2483#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
2484#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
2485
2486/* TWIE - Two-Wire Interface E */
2487#define TWIE_CTRL  _SFR_MEM8(0x04A0)
2488#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
2489#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
2490#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
2491#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
2492#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
2493#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
2494#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
2495#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
2496#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
2497#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
2498#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
2499#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
2500#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
2501
2502/* PORTA - Port A */
2503#define PORTA_DIR  _SFR_MEM8(0x0600)
2504#define PORTA_DIRSET  _SFR_MEM8(0x0601)
2505#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
2506#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
2507#define PORTA_OUT  _SFR_MEM8(0x0604)
2508#define PORTA_OUTSET  _SFR_MEM8(0x0605)
2509#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
2510#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
2511#define PORTA_IN  _SFR_MEM8(0x0608)
2512#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
2513#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
2514#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
2515#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
2516#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
2517#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
2518#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
2519#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
2520#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
2521#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
2522#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
2523#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
2524
2525/* PORTB - Port B */
2526#define PORTB_DIR  _SFR_MEM8(0x0620)
2527#define PORTB_DIRSET  _SFR_MEM8(0x0621)
2528#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
2529#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
2530#define PORTB_OUT  _SFR_MEM8(0x0624)
2531#define PORTB_OUTSET  _SFR_MEM8(0x0625)
2532#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
2533#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
2534#define PORTB_IN  _SFR_MEM8(0x0628)
2535#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
2536#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
2537#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
2538#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
2539#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
2540#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
2541#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
2542#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
2543#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
2544#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
2545#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
2546#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
2547
2548/* PORTC - Port C */
2549#define PORTC_DIR  _SFR_MEM8(0x0640)
2550#define PORTC_DIRSET  _SFR_MEM8(0x0641)
2551#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
2552#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
2553#define PORTC_OUT  _SFR_MEM8(0x0644)
2554#define PORTC_OUTSET  _SFR_MEM8(0x0645)
2555#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
2556#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
2557#define PORTC_IN  _SFR_MEM8(0x0648)
2558#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
2559#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
2560#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
2561#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
2562#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
2563#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
2564#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
2565#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
2566#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
2567#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
2568#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
2569#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
2570
2571/* PORTD - Port D */
2572#define PORTD_DIR  _SFR_MEM8(0x0660)
2573#define PORTD_DIRSET  _SFR_MEM8(0x0661)
2574#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
2575#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
2576#define PORTD_OUT  _SFR_MEM8(0x0664)
2577#define PORTD_OUTSET  _SFR_MEM8(0x0665)
2578#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
2579#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
2580#define PORTD_IN  _SFR_MEM8(0x0668)
2581#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
2582#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
2583#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
2584#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
2585#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
2586#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
2587#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
2588#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
2589#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
2590#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
2591#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
2592#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
2593
2594/* PORTE - Port E */
2595#define PORTE_DIR  _SFR_MEM8(0x0680)
2596#define PORTE_DIRSET  _SFR_MEM8(0x0681)
2597#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
2598#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
2599#define PORTE_OUT  _SFR_MEM8(0x0684)
2600#define PORTE_OUTSET  _SFR_MEM8(0x0685)
2601#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
2602#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
2603#define PORTE_IN  _SFR_MEM8(0x0688)
2604#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
2605#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
2606#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
2607#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
2608#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
2609#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
2610#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
2611#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
2612#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
2613#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
2614#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
2615#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
2616
2617/* PORTF - Port F */
2618#define PORTF_DIR  _SFR_MEM8(0x06A0)
2619#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
2620#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
2621#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
2622#define PORTF_OUT  _SFR_MEM8(0x06A4)
2623#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
2624#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
2625#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
2626#define PORTF_IN  _SFR_MEM8(0x06A8)
2627#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
2628#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
2629#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
2630#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
2631#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
2632#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
2633#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
2634#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
2635#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
2636#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
2637#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
2638#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
2639
2640/* PORTR - Port R */
2641#define PORTR_DIR  _SFR_MEM8(0x07E0)
2642#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
2643#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
2644#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
2645#define PORTR_OUT  _SFR_MEM8(0x07E4)
2646#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
2647#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
2648#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
2649#define PORTR_IN  _SFR_MEM8(0x07E8)
2650#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
2651#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
2652#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
2653#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
2654#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
2655#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
2656#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
2657#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
2658#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
2659#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
2660#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
2661#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
2662
2663/* TCC0 - Timer/Counter C0 */
2664#define TCC0_CTRLA  _SFR_MEM8(0x0800)
2665#define TCC0_CTRLB  _SFR_MEM8(0x0801)
2666#define TCC0_CTRLC  _SFR_MEM8(0x0802)
2667#define TCC0_CTRLD  _SFR_MEM8(0x0803)
2668#define TCC0_CTRLE  _SFR_MEM8(0x0804)
2669#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
2670#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
2671#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
2672#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
2673#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
2674#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
2675#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
2676#define TCC0_TEMP  _SFR_MEM8(0x080F)
2677#define TCC0_CNT  _SFR_MEM16(0x0820)
2678#define TCC0_PER  _SFR_MEM16(0x0826)
2679#define TCC0_CCA  _SFR_MEM16(0x0828)
2680#define TCC0_CCB  _SFR_MEM16(0x082A)
2681#define TCC0_CCC  _SFR_MEM16(0x082C)
2682#define TCC0_CCD  _SFR_MEM16(0x082E)
2683#define TCC0_PERBUF  _SFR_MEM16(0x0836)
2684#define TCC0_CCABUF  _SFR_MEM16(0x0838)
2685#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
2686#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
2687#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
2688
2689/* TCC1 - Timer/Counter C1 */
2690#define TCC1_CTRLA  _SFR_MEM8(0x0840)
2691#define TCC1_CTRLB  _SFR_MEM8(0x0841)
2692#define TCC1_CTRLC  _SFR_MEM8(0x0842)
2693#define TCC1_CTRLD  _SFR_MEM8(0x0843)
2694#define TCC1_CTRLE  _SFR_MEM8(0x0844)
2695#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
2696#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
2697#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
2698#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
2699#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
2700#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
2701#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
2702#define TCC1_TEMP  _SFR_MEM8(0x084F)
2703#define TCC1_CNT  _SFR_MEM16(0x0860)
2704#define TCC1_PER  _SFR_MEM16(0x0866)
2705#define TCC1_CCA  _SFR_MEM16(0x0868)
2706#define TCC1_CCB  _SFR_MEM16(0x086A)
2707#define TCC1_PERBUF  _SFR_MEM16(0x0876)
2708#define TCC1_CCABUF  _SFR_MEM16(0x0878)
2709#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
2710
2711/* AWEXC - Advanced Waveform Extension C */
2712#define AWEXC_CTRL  _SFR_MEM8(0x0880)
2713#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
2714#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
2715#define AWEXC_STATUS  _SFR_MEM8(0x0884)
2716#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
2717#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
2718#define AWEXC_DTLS  _SFR_MEM8(0x0888)
2719#define AWEXC_DTHS  _SFR_MEM8(0x0889)
2720#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
2721#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
2722#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
2723
2724/* HIRESC - High-Resolution Extension C */
2725#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
2726
2727/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
2728#define USARTC0_DATA  _SFR_MEM8(0x08A0)
2729#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
2730#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
2731#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
2732#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
2733#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
2734#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
2735
2736/* SPIC - Serial Peripheral Interface C */
2737#define SPIC_CTRL  _SFR_MEM8(0x08C0)
2738#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
2739#define SPIC_STATUS  _SFR_MEM8(0x08C2)
2740#define SPIC_DATA  _SFR_MEM8(0x08C3)
2741
2742/* IRCOM - IR Communication Module */
2743#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
2744#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
2745#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
2746
2747/* TCD0 - Timer/Counter D0 */
2748#define TCD0_CTRLA  _SFR_MEM8(0x0900)
2749#define TCD0_CTRLB  _SFR_MEM8(0x0901)
2750#define TCD0_CTRLC  _SFR_MEM8(0x0902)
2751#define TCD0_CTRLD  _SFR_MEM8(0x0903)
2752#define TCD0_CTRLE  _SFR_MEM8(0x0904)
2753#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
2754#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
2755#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
2756#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
2757#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
2758#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
2759#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
2760#define TCD0_TEMP  _SFR_MEM8(0x090F)
2761#define TCD0_CNT  _SFR_MEM16(0x0920)
2762#define TCD0_PER  _SFR_MEM16(0x0926)
2763#define TCD0_CCA  _SFR_MEM16(0x0928)
2764#define TCD0_CCB  _SFR_MEM16(0x092A)
2765#define TCD0_CCC  _SFR_MEM16(0x092C)
2766#define TCD0_CCD  _SFR_MEM16(0x092E)
2767#define TCD0_PERBUF  _SFR_MEM16(0x0936)
2768#define TCD0_CCABUF  _SFR_MEM16(0x0938)
2769#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
2770#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
2771#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
2772
2773/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
2774#define USARTD0_DATA  _SFR_MEM8(0x09A0)
2775#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
2776#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
2777#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
2778#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
2779#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
2780#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
2781
2782/* SPID - Serial Peripheral Interface D */
2783#define SPID_CTRL  _SFR_MEM8(0x09C0)
2784#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
2785#define SPID_STATUS  _SFR_MEM8(0x09C2)
2786#define SPID_DATA  _SFR_MEM8(0x09C3)
2787
2788/* TCE0 - Timer/Counter E0 */
2789#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
2790#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
2791#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
2792#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
2793#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
2794#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
2795#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
2796#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
2797#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
2798#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
2799#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
2800#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
2801#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
2802#define TCE0_CNT  _SFR_MEM16(0x0A20)
2803#define TCE0_PER  _SFR_MEM16(0x0A26)
2804#define TCE0_CCA  _SFR_MEM16(0x0A28)
2805#define TCE0_CCB  _SFR_MEM16(0x0A2A)
2806#define TCE0_CCC  _SFR_MEM16(0x0A2C)
2807#define TCE0_CCD  _SFR_MEM16(0x0A2E)
2808#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
2809#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
2810#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
2811#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
2812#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
2813
2814/* AWEXE - Advanced Waveform Extension E */
2815#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
2816#define AWEXE_FDEMASK  _SFR_MEM8(0x0A82)
2817#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
2818#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
2819#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
2820#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
2821#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
2822#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
2823#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
2824#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
2825#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
2826
2827/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
2828#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
2829#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
2830#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
2831#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
2832#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
2833#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
2834#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
2835
2836/* SPIE - Serial Peripheral Interface E */
2837#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
2838#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
2839#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
2840#define SPIE_DATA  _SFR_MEM8(0x0AC3)
2841
2842/* TCF0 - Timer/Counter F0 */
2843#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
2844#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
2845#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
2846#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
2847#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
2848#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
2849#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
2850#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
2851#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
2852#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
2853#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
2854#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
2855#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
2856#define TCF0_CNT  _SFR_MEM16(0x0B20)
2857#define TCF0_PER  _SFR_MEM16(0x0B26)
2858#define TCF0_CCA  _SFR_MEM16(0x0B28)
2859#define TCF0_CCB  _SFR_MEM16(0x0B2A)
2860#define TCF0_CCC  _SFR_MEM16(0x0B2C)
2861#define TCF0_CCD  _SFR_MEM16(0x0B2E)
2862#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
2863#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
2864#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
2865#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
2866#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
2867
2868
2869
2870/*================== Bitfield Definitions ================== */
2871
2872/* XOCD - On-Chip Debug System */
2873/* OCD.OCDR1  bit masks and bit positions */
2874#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
2875#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
2876
2877
2878/* CPU - CPU */
2879/* CPU.CCP  bit masks and bit positions */
2880#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
2881#define CPU_CCP_gp  0  /* CCP signature group position. */
2882#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
2883#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
2884#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
2885#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
2886#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
2887#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
2888#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
2889#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
2890#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
2891#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
2892#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
2893#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
2894#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
2895#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
2896#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
2897#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
2898
2899
2900/* CPU.SREG  bit masks and bit positions */
2901#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
2902#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
2903
2904#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
2905#define CPU_T_bp  6  /* Transfer Bit bit position. */
2906
2907#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
2908#define CPU_H_bp  5  /* Half Carry Flag bit position. */
2909
2910#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
2911#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
2912
2913#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
2914#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
2915
2916#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
2917#define CPU_N_bp  2  /* Negative Flag bit position. */
2918
2919#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
2920#define CPU_Z_bp  1  /* Zero Flag bit position. */
2921
2922#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
2923#define CPU_C_bp  0  /* Carry Flag bit position. */
2924
2925
2926/* CLK - Clock System */
2927/* CLK.CTRL  bit masks and bit positions */
2928#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
2929#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
2930#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
2931#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
2932#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
2933#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
2934#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
2935#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
2936
2937
2938/* CLK.PSCTRL  bit masks and bit positions */
2939#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
2940#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
2941#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
2942#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
2943#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
2944#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
2945#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
2946#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
2947#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
2948#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
2949#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
2950#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
2951
2952#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
2953#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
2954#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
2955#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
2956#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
2957#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
2958
2959
2960/* CLK.LOCK  bit masks and bit positions */
2961#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
2962#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
2963
2964
2965/* CLK.RTCCTRL  bit masks and bit positions */
2966#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
2967#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
2968#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
2969#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
2970#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
2971#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
2972#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
2973#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
2974
2975#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
2976#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
2977
2978
2979/* PR.PRGEN  bit masks and bit positions */
2980#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
2981#define PR_RTC_bp  2  /* Real-time Counter bit position. */
2982
2983#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
2984#define PR_EVSYS_bp  1  /* Event System bit position. */
2985
2986/* PR.PRPA  bit masks and bit positions */
2987#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
2988#define PR_ADC_bp  1  /* Port A ADC bit position. */
2989
2990#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
2991#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
2992
2993/* PR.PRPC  bit masks and bit positions */
2994#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
2995#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
2996
2997#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
2998#define PR_USART0_bp  4  /* Port C USART0 bit position. */
2999
3000#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
3001#define PR_SPI_bp  3  /* Port C SPI bit position. */
3002
3003#define PR_HIRES_bm  0x04  /* Port C HIRES bit mask. */
3004#define PR_HIRES_bp  2  /* Port C HIRES bit position. */
3005
3006#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
3007#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
3008
3009#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
3010#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
3011
3012/* PR.PRPD  bit masks and bit positions */
3013/* PR_USART0_bm  Predefined. */
3014/* PR_USART0_bp  Predefined. */
3015
3016/* PR_SPI_bm  Predefined. */
3017/* PR_SPI_bp  Predefined. */
3018
3019/* PR_TC0_bm  Predefined. */
3020/* PR_TC0_bp  Predefined. */
3021
3022/* PR.PRPE  bit masks and bit positions */
3023/* PR_TWI_bm  Predefined. */
3024/* PR_TWI_bp  Predefined. */
3025
3026/* PR_USART0_bm  Predefined. */
3027/* PR_USART0_bp  Predefined. */
3028
3029/* PR_TC0_bm  Predefined. */
3030/* PR_TC0_bp  Predefined. */
3031
3032/* PR.PRPF  bit masks and bit positions */
3033/* PR_USART0_bm  Predefined. */
3034/* PR_USART0_bp  Predefined. */
3035
3036/* PR_TC0_bm  Predefined. */
3037/* PR_TC0_bp  Predefined. */
3038
3039/* SLEEP - Sleep Controller */
3040/* SLEEP.CTRL  bit masks and bit positions */
3041#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
3042#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
3043#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
3044#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
3045#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
3046#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
3047#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
3048#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
3049
3050#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
3051#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
3052
3053
3054/* OSC - Oscillator */
3055/* OSC.CTRL  bit masks and bit positions */
3056#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
3057#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
3058
3059#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
3060#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
3061
3062#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
3063#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
3064
3065#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
3066#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
3067
3068#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
3069#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
3070
3071
3072/* OSC.STATUS  bit masks and bit positions */
3073#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
3074#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
3075
3076#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
3077#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
3078
3079#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
3080#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
3081
3082#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
3083#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
3084
3085#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
3086#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
3087
3088
3089/* OSC.XOSCCTRL  bit masks and bit positions */
3090#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
3091#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
3092#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
3093#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
3094#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
3095#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
3096
3097#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
3098#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
3099
3100#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
3101#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
3102#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
3103#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
3104#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
3105#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
3106#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
3107#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
3108#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
3109#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
3110
3111
3112/* OSC.XOSCFAIL  bit masks and bit positions */
3113#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
3114#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
3115
3116#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
3117#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
3118
3119
3120/* OSC.PLLCTRL  bit masks and bit positions */
3121#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
3122#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
3123#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
3124#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
3125#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
3126#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
3127
3128#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
3129#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
3130#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
3131#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
3132#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
3133#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
3134#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
3135#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
3136#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
3137#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
3138#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
3139#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
3140
3141
3142/* OSC.DFLLCTRL  bit masks and bit positions */
3143#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
3144#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
3145
3146#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
3147#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
3148
3149
3150/* DFLL - DFLL */
3151/* DFLL.CTRL  bit masks and bit positions */
3152#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
3153#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
3154
3155
3156/* DFLL.CALA  bit masks and bit positions */
3157#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
3158#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
3159#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
3160#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
3161#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
3162#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
3163#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
3164#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
3165#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
3166#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
3167#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
3168#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
3169#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
3170#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
3171#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
3172#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
3173
3174
3175/* DFLL.CALB  bit masks and bit positions */
3176#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
3177#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
3178#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
3179#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
3180#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
3181#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
3182#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
3183#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
3184#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
3185#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
3186#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
3187#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
3188#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
3189#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
3190
3191
3192/* RST - Reset */
3193/* RST.STATUS  bit masks and bit positions */
3194#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
3195#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
3196
3197#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
3198#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
3199
3200#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
3201#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
3202
3203#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
3204#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
3205
3206#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
3207#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
3208
3209#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
3210#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
3211
3212#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
3213#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
3214
3215
3216/* RST.CTRL  bit masks and bit positions */
3217#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
3218#define RST_SWRST_bp  0  /* Software Reset bit position. */
3219
3220
3221/* WDT - Watch-Dog Timer */
3222/* WDT.CTRL  bit masks and bit positions */
3223#define WDT_PER_gm  0x3C  /* Period group mask. */
3224#define WDT_PER_gp  2  /* Period group position. */
3225#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
3226#define WDT_PER0_bp  2  /* Period bit 0 position. */
3227#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
3228#define WDT_PER1_bp  3  /* Period bit 1 position. */
3229#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
3230#define WDT_PER2_bp  4  /* Period bit 2 position. */
3231#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
3232#define WDT_PER3_bp  5  /* Period bit 3 position. */
3233
3234#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
3235#define WDT_ENABLE_bp  1  /* Enable bit position. */
3236
3237#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
3238#define WDT_CEN_bp  0  /* Change Enable bit position. */
3239
3240
3241/* WDT.WINCTRL  bit masks and bit positions */
3242#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
3243#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
3244#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
3245#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
3246#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
3247#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
3248#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
3249#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
3250#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
3251#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
3252
3253#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
3254#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
3255
3256#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
3257#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
3258
3259
3260/* WDT.STATUS  bit masks and bit positions */
3261#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
3262#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
3263
3264
3265/* MCU - MCU Control */
3266/* MCU.MCUCR  bit masks and bit positions */
3267#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
3268#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
3269
3270
3271/* MCU.EVSYSLOCK  bit masks and bit positions */
3272#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
3273#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
3274
3275#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
3276#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
3277
3278
3279/* MCU.AWEXLOCK  bit masks and bit positions */
3280#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
3281#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
3282
3283#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
3284#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
3285
3286
3287/* PMIC - Programmable Multi-level Interrupt Controller */
3288/* PMIC.STATUS  bit masks and bit positions */
3289#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
3290#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
3291
3292#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
3293#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
3294
3295#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
3296#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
3297
3298#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
3299#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
3300
3301
3302/* PMIC.CTRL  bit masks and bit positions */
3303#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
3304#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
3305
3306#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
3307#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
3308
3309#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
3310#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
3311
3312#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
3313#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
3314
3315#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
3316#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
3317
3318
3319/* CRC - Cyclic Redundancy Checker */
3320/* CRC.CTRL  bit masks and bit positions */
3321#define CRC_RESET_gm  0xC0  /* Reset group mask. */
3322#define CRC_RESET_gp  6  /* Reset group position. */
3323#define CRC_RESET0_bm  (1<<6)  /* Reset bit 0 mask. */
3324#define CRC_RESET0_bp  6  /* Reset bit 0 position. */
3325#define CRC_RESET1_bm  (1<<7)  /* Reset bit 1 mask. */
3326#define CRC_RESET1_bp  7  /* Reset bit 1 position. */
3327
3328#define CRC_CRC32_bm  0x20  /* CRC Mode bit mask. */
3329#define CRC_CRC32_bp  5  /* CRC Mode bit position. */
3330
3331#define CRC_SOURCE_gm  0x0F  /* Input Source group mask. */
3332#define CRC_SOURCE_gp  0  /* Input Source group position. */
3333#define CRC_SOURCE0_bm  (1<<0)  /* Input Source bit 0 mask. */
3334#define CRC_SOURCE0_bp  0  /* Input Source bit 0 position. */
3335#define CRC_SOURCE1_bm  (1<<1)  /* Input Source bit 1 mask. */
3336#define CRC_SOURCE1_bp  1  /* Input Source bit 1 position. */
3337#define CRC_SOURCE2_bm  (1<<2)  /* Input Source bit 2 mask. */
3338#define CRC_SOURCE2_bp  2  /* Input Source bit 2 position. */
3339#define CRC_SOURCE3_bm  (1<<3)  /* Input Source bit 3 mask. */
3340#define CRC_SOURCE3_bp  3  /* Input Source bit 3 position. */
3341
3342/* CRC.STATUS  bit masks and bit positions */
3343#define CRC_ZERO_bm  0x02  /* Zero detection bit mask. */
3344#define CRC_ZERO_bp  1  /* Zero detection bit position. */
3345
3346#define CRC_BUSY_bm  0x01  /* Busy bit mask. */
3347#define CRC_BUSY_bp  0  /* Busy bit position. */
3348
3349
3350/* EVSYS - Event System */
3351/* EVSYS.CH0MUX  bit masks and bit positions */
3352#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
3353#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
3354#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
3355#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
3356#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
3357#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
3358#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
3359#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
3360#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
3361#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
3362#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
3363#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
3364#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
3365#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
3366#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
3367#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
3368#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
3369#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
3370
3371
3372/* EVSYS.CH1MUX  bit masks and bit positions */
3373/* EVSYS_CHMUX_gm  Predefined. */
3374/* EVSYS_CHMUX_gp  Predefined. */
3375/* EVSYS_CHMUX0_bm  Predefined. */
3376/* EVSYS_CHMUX0_bp  Predefined. */
3377/* EVSYS_CHMUX1_bm  Predefined. */
3378/* EVSYS_CHMUX1_bp  Predefined. */
3379/* EVSYS_CHMUX2_bm  Predefined. */
3380/* EVSYS_CHMUX2_bp  Predefined. */
3381/* EVSYS_CHMUX3_bm  Predefined. */
3382/* EVSYS_CHMUX3_bp  Predefined. */
3383/* EVSYS_CHMUX4_bm  Predefined. */
3384/* EVSYS_CHMUX4_bp  Predefined. */
3385/* EVSYS_CHMUX5_bm  Predefined. */
3386/* EVSYS_CHMUX5_bp  Predefined. */
3387/* EVSYS_CHMUX6_bm  Predefined. */
3388/* EVSYS_CHMUX6_bp  Predefined. */
3389/* EVSYS_CHMUX7_bm  Predefined. */
3390/* EVSYS_CHMUX7_bp  Predefined. */
3391
3392
3393/* EVSYS.CH2MUX  bit masks and bit positions */
3394/* EVSYS_CHMUX_gm  Predefined. */
3395/* EVSYS_CHMUX_gp  Predefined. */
3396/* EVSYS_CHMUX0_bm  Predefined. */
3397/* EVSYS_CHMUX0_bp  Predefined. */
3398/* EVSYS_CHMUX1_bm  Predefined. */
3399/* EVSYS_CHMUX1_bp  Predefined. */
3400/* EVSYS_CHMUX2_bm  Predefined. */
3401/* EVSYS_CHMUX2_bp  Predefined. */
3402/* EVSYS_CHMUX3_bm  Predefined. */
3403/* EVSYS_CHMUX3_bp  Predefined. */
3404/* EVSYS_CHMUX4_bm  Predefined. */
3405/* EVSYS_CHMUX4_bp  Predefined. */
3406/* EVSYS_CHMUX5_bm  Predefined. */
3407/* EVSYS_CHMUX5_bp  Predefined. */
3408/* EVSYS_CHMUX6_bm  Predefined. */
3409/* EVSYS_CHMUX6_bp  Predefined. */
3410/* EVSYS_CHMUX7_bm  Predefined. */
3411/* EVSYS_CHMUX7_bp  Predefined. */
3412
3413
3414/* EVSYS.CH3MUX  bit masks and bit positions */
3415/* EVSYS_CHMUX_gm  Predefined. */
3416/* EVSYS_CHMUX_gp  Predefined. */
3417/* EVSYS_CHMUX0_bm  Predefined. */
3418/* EVSYS_CHMUX0_bp  Predefined. */
3419/* EVSYS_CHMUX1_bm  Predefined. */
3420/* EVSYS_CHMUX1_bp  Predefined. */
3421/* EVSYS_CHMUX2_bm  Predefined. */
3422/* EVSYS_CHMUX2_bp  Predefined. */
3423/* EVSYS_CHMUX3_bm  Predefined. */
3424/* EVSYS_CHMUX3_bp  Predefined. */
3425/* EVSYS_CHMUX4_bm  Predefined. */
3426/* EVSYS_CHMUX4_bp  Predefined. */
3427/* EVSYS_CHMUX5_bm  Predefined. */
3428/* EVSYS_CHMUX5_bp  Predefined. */
3429/* EVSYS_CHMUX6_bm  Predefined. */
3430/* EVSYS_CHMUX6_bp  Predefined. */
3431/* EVSYS_CHMUX7_bm  Predefined. */
3432/* EVSYS_CHMUX7_bp  Predefined. */
3433
3434
3435/* EVSYS.CH0CTRL  bit masks and bit positions */
3436#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
3437#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
3438#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
3439#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
3440#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
3441#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
3442
3443#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
3444#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
3445
3446#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
3447#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
3448
3449#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
3450#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
3451#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
3452#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
3453#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
3454#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
3455#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
3456#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
3457
3458
3459/* EVSYS.CH1CTRL  bit masks and bit positions */
3460/* EVSYS_DIGFILT_gm  Predefined. */
3461/* EVSYS_DIGFILT_gp  Predefined. */
3462/* EVSYS_DIGFILT0_bm  Predefined. */
3463/* EVSYS_DIGFILT0_bp  Predefined. */
3464/* EVSYS_DIGFILT1_bm  Predefined. */
3465/* EVSYS_DIGFILT1_bp  Predefined. */
3466/* EVSYS_DIGFILT2_bm  Predefined. */
3467/* EVSYS_DIGFILT2_bp  Predefined. */
3468
3469
3470/* EVSYS.CH2CTRL  bit masks and bit positions */
3471/* EVSYS_QDIRM_gm  Predefined. */
3472/* EVSYS_QDIRM_gp  Predefined. */
3473/* EVSYS_QDIRM0_bm  Predefined. */
3474/* EVSYS_QDIRM0_bp  Predefined. */
3475/* EVSYS_QDIRM1_bm  Predefined. */
3476/* EVSYS_QDIRM1_bp  Predefined. */
3477
3478/* EVSYS_QDIEN_bm  Predefined. */
3479/* EVSYS_QDIEN_bp  Predefined. */
3480
3481/* EVSYS_QDEN_bm  Predefined. */
3482/* EVSYS_QDEN_bp  Predefined. */
3483
3484/* EVSYS_DIGFILT_gm  Predefined. */
3485/* EVSYS_DIGFILT_gp  Predefined. */
3486/* EVSYS_DIGFILT0_bm  Predefined. */
3487/* EVSYS_DIGFILT0_bp  Predefined. */
3488/* EVSYS_DIGFILT1_bm  Predefined. */
3489/* EVSYS_DIGFILT1_bp  Predefined. */
3490/* EVSYS_DIGFILT2_bm  Predefined. */
3491/* EVSYS_DIGFILT2_bp  Predefined. */
3492
3493
3494/* EVSYS.CH3CTRL  bit masks and bit positions */
3495/* EVSYS_DIGFILT_gm  Predefined. */
3496/* EVSYS_DIGFILT_gp  Predefined. */
3497/* EVSYS_DIGFILT0_bm  Predefined. */
3498/* EVSYS_DIGFILT0_bp  Predefined. */
3499/* EVSYS_DIGFILT1_bm  Predefined. */
3500/* EVSYS_DIGFILT1_bp  Predefined. */
3501/* EVSYS_DIGFILT2_bm  Predefined. */
3502/* EVSYS_DIGFILT2_bp  Predefined. */
3503
3504
3505/* NVM - Non Volatile Memory Controller */
3506/* NVM.CMD  bit masks and bit positions */
3507#define NVM_CMD_gm  0xFF  /* Command group mask. */
3508#define NVM_CMD_gp  0  /* Command group position. */
3509#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
3510#define NVM_CMD0_bp  0  /* Command bit 0 position. */
3511#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
3512#define NVM_CMD1_bp  1  /* Command bit 1 position. */
3513#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
3514#define NVM_CMD2_bp  2  /* Command bit 2 position. */
3515#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
3516#define NVM_CMD3_bp  3  /* Command bit 3 position. */
3517#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
3518#define NVM_CMD4_bp  4  /* Command bit 4 position. */
3519#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
3520#define NVM_CMD5_bp  5  /* Command bit 5 position. */
3521#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
3522#define NVM_CMD6_bp  6  /* Command bit 6 position. */
3523#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
3524#define NVM_CMD7_bp  7  /* Command bit 7 position. */
3525
3526
3527/* NVM.CTRLA  bit masks and bit positions */
3528#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
3529#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
3530
3531
3532/* NVM.CTRLB  bit masks and bit positions */
3533#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
3534#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
3535
3536#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
3537#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
3538
3539#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
3540#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
3541
3542#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
3543#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
3544
3545
3546/* NVM.INTCTRL  bit masks and bit positions */
3547#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
3548#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
3549#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
3550#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
3551#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
3552#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
3553
3554#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
3555#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
3556#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
3557#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
3558#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
3559#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
3560
3561
3562/* NVM.STATUS  bit masks and bit positions */
3563#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
3564#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
3565
3566#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
3567#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
3568
3569#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
3570#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
3571
3572#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
3573#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
3574
3575
3576/* NVM.LOCKBITS  bit masks and bit positions */
3577#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
3578#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
3579#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
3580#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
3581#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
3582#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
3583
3584#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
3585#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
3586#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
3587#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
3588#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
3589#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
3590
3591#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
3592#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
3593#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
3594#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
3595#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
3596#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
3597
3598#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
3599#define NVM_LB_gp  0  /* Lock Bits group position. */
3600#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
3601#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
3602#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
3603#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
3604
3605
3606/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
3607#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
3608#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
3609#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
3610#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
3611#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
3612#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
3613
3614#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
3615#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
3616#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
3617#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
3618#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
3619#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
3620
3621#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
3622#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
3623#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
3624#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
3625#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
3626#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
3627
3628#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
3629#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
3630#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
3631#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
3632#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
3633#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
3634
3635
3636/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
3637#define NVM_FUSES_USERID_gm  0xFF  /* User ID group mask. */
3638#define NVM_FUSES_USERID_gp  0  /* User ID group position. */
3639#define NVM_FUSES_USERID0_bm  (1<<0)  /* User ID bit 0 mask. */
3640#define NVM_FUSES_USERID0_bp  0  /* User ID bit 0 position. */
3641#define NVM_FUSES_USERID1_bm  (1<<1)  /* User ID bit 1 mask. */
3642#define NVM_FUSES_USERID1_bp  1  /* User ID bit 1 position. */
3643#define NVM_FUSES_USERID2_bm  (1<<2)  /* User ID bit 2 mask. */
3644#define NVM_FUSES_USERID2_bp  2  /* User ID bit 2 position. */
3645#define NVM_FUSES_USERID3_bm  (1<<3)  /* User ID bit 3 mask. */
3646#define NVM_FUSES_USERID3_bp  3  /* User ID bit 3 position. */
3647#define NVM_FUSES_USERID4_bm  (1<<4)  /* User ID bit 4 mask. */
3648#define NVM_FUSES_USERID4_bp  4  /* User ID bit 4 position. */
3649#define NVM_FUSES_USERID5_bm  (1<<5)  /* User ID bit 5 mask. */
3650#define NVM_FUSES_USERID5_bp  5  /* User ID bit 5 position. */
3651#define NVM_FUSES_USERID6_bm  (1<<6)  /* User ID bit 6 mask. */
3652#define NVM_FUSES_USERID6_bp  6  /* User ID bit 6 position. */
3653#define NVM_FUSES_USERID7_bm  (1<<7)  /* User ID bit 7 mask. */
3654#define NVM_FUSES_USERID7_bp  7  /* User ID bit 7 position. */
3655
3656
3657/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
3658#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
3659#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
3660#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
3661#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
3662#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
3663#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
3664#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
3665#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
3666#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
3667#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
3668
3669#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
3670#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
3671#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
3672#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
3673#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
3674#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
3675#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
3676#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
3677#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
3678#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
3679
3680
3681/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
3682#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
3683#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
3684
3685#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
3686#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
3687
3688#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
3689#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
3690#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
3691#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
3692#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
3693#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
3694
3695
3696/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
3697#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
3698#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
3699#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
3700#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
3701#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
3702#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
3703
3704#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
3705#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
3706
3707
3708/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
3709#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
3710#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
3711#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
3712#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
3713#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
3714#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
3715
3716#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
3717#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
3718
3719#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
3720#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
3721#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
3722#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
3723#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
3724#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
3725#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
3726#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
3727
3728
3729/* AC - Analog Comparator */
3730/* AC.AC0CTRL  bit masks and bit positions */
3731#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
3732#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
3733#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
3734#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
3735#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
3736#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
3737
3738#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
3739#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
3740#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
3741#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
3742#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
3743#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
3744
3745#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
3746#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
3747
3748#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
3749#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
3750#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
3751#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
3752#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
3753#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
3754
3755#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
3756#define AC_ENABLE_bp  0  /* Enable bit position. */
3757
3758
3759/* AC.AC1CTRL  bit masks and bit positions */
3760/* AC_INTMODE_gm  Predefined. */
3761/* AC_INTMODE_gp  Predefined. */
3762/* AC_INTMODE0_bm  Predefined. */
3763/* AC_INTMODE0_bp  Predefined. */
3764/* AC_INTMODE1_bm  Predefined. */
3765/* AC_INTMODE1_bp  Predefined. */
3766
3767/* AC_INTLVL_gm  Predefined. */
3768/* AC_INTLVL_gp  Predefined. */
3769/* AC_INTLVL0_bm  Predefined. */
3770/* AC_INTLVL0_bp  Predefined. */
3771/* AC_INTLVL1_bm  Predefined. */
3772/* AC_INTLVL1_bp  Predefined. */
3773
3774/* AC_HSMODE_bm  Predefined. */
3775/* AC_HSMODE_bp  Predefined. */
3776
3777/* AC_HYSMODE_gm  Predefined. */
3778/* AC_HYSMODE_gp  Predefined. */
3779/* AC_HYSMODE0_bm  Predefined. */
3780/* AC_HYSMODE0_bp  Predefined. */
3781/* AC_HYSMODE1_bm  Predefined. */
3782/* AC_HYSMODE1_bp  Predefined. */
3783
3784/* AC_ENABLE_bm  Predefined. */
3785/* AC_ENABLE_bp  Predefined. */
3786
3787
3788/* AC.AC0MUXCTRL  bit masks and bit positions */
3789#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
3790#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
3791#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
3792#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
3793#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
3794#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
3795#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
3796#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
3797
3798#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
3799#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
3800#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
3801#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
3802#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
3803#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
3804#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
3805#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
3806
3807
3808/* AC.AC1MUXCTRL  bit masks and bit positions */
3809/* AC_MUXPOS_gm  Predefined. */
3810/* AC_MUXPOS_gp  Predefined. */
3811/* AC_MUXPOS0_bm  Predefined. */
3812/* AC_MUXPOS0_bp  Predefined. */
3813/* AC_MUXPOS1_bm  Predefined. */
3814/* AC_MUXPOS1_bp  Predefined. */
3815/* AC_MUXPOS2_bm  Predefined. */
3816/* AC_MUXPOS2_bp  Predefined. */
3817
3818/* AC_MUXNEG_gm  Predefined. */
3819/* AC_MUXNEG_gp  Predefined. */
3820/* AC_MUXNEG0_bm  Predefined. */
3821/* AC_MUXNEG0_bp  Predefined. */
3822/* AC_MUXNEG1_bm  Predefined. */
3823/* AC_MUXNEG1_bp  Predefined. */
3824/* AC_MUXNEG2_bm  Predefined. */
3825/* AC_MUXNEG2_bp  Predefined. */
3826
3827
3828/* AC.CTRLA  bit masks and bit positions */
3829#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
3830#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
3831
3832
3833/* AC.CTRLB  bit masks and bit positions */
3834#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
3835#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
3836#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
3837#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
3838#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
3839#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
3840#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
3841#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
3842#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
3843#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
3844#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
3845#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
3846#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
3847#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
3848
3849
3850/* AC.WINCTRL  bit masks and bit positions */
3851#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
3852#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
3853
3854#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
3855#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
3856#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
3857#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
3858#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
3859#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
3860
3861#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
3862#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
3863#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
3864#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
3865#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
3866#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
3867
3868
3869/* AC.STATUS  bit masks and bit positions */
3870#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
3871#define AC_WSTATE_gp  6  /* Window Mode State group position. */
3872#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
3873#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
3874#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
3875#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
3876
3877#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
3878#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
3879
3880#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
3881#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
3882
3883#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
3884#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
3885
3886#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
3887#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
3888
3889#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
3890#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
3891
3892
3893/* ADC - Analog/Digital Converter */
3894/* ADC_CH.CTRL  bit masks and bit positions */
3895#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
3896#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
3897
3898#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
3899#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
3900#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
3901#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
3902#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
3903#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
3904#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
3905#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
3906
3907#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
3908#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
3909#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
3910#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
3911#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
3912#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
3913
3914
3915/* ADC_CH.MUXCTRL  bit masks and bit positions */
3916#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
3917#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
3918#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
3919#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
3920#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
3921#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
3922#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
3923#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
3924#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
3925#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
3926
3927#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
3928#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
3929#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
3930#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
3931#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
3932#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
3933#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
3934#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
3935#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
3936#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
3937
3938#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
3939#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
3940#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
3941#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
3942#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
3943#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
3944
3945
3946/* ADC_CH.INTCTRL  bit masks and bit positions */
3947#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
3948#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
3949#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
3950#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
3951#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
3952#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
3953
3954#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
3955#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
3956#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
3957#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
3958#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
3959#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
3960
3961
3962/* ADC_CH.INTFLAGS  bit masks and bit positions */
3963#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
3964#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
3965
3966
3967/* ADC.CTRLA  bit masks and bit positions */
3968#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
3969#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
3970
3971#define ADC_FLUSH_bm  0x02  /* ADC Flush bit mask. */
3972#define ADC_FLUSH_bp  1  /* ADC Flush bit position. */
3973
3974#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
3975#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
3976
3977
3978/* ADC.CTRLB  bit masks and bit positions */
3979#define ADC_CURRLIMIT_gm  0x60  /* Current Limitation group mask. */
3980#define ADC_CURRLIMIT_gp  5  /* Current Limitation group position. */
3981#define ADC_CURRLIMIT0_bm  (1<<5)  /* Current Limitation bit 0 mask. */
3982#define ADC_CURRLIMIT0_bp  5  /* Current Limitation bit 0 position. */
3983#define ADC_CURRLIMIT1_bm  (1<<6)  /* Current Limitation bit 1 mask. */
3984#define ADC_CURRLIMIT1_bp  6  /* Current Limitation bit 1 position. */
3985
3986#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
3987#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
3988
3989#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
3990#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
3991
3992#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
3993#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
3994#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
3995#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
3996#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
3997#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
3998
3999
4000/* ADC.REFCTRL  bit masks and bit positions */
4001#define ADC_REFSEL_gm  0x30  /* Reference Selection group mask. */
4002#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
4003#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
4004#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
4005#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
4006#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
4007
4008#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
4009#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
4010
4011#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
4012#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
4013
4014
4015/* ADC.EVCTRL  bit masks and bit positions */
4016#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
4017#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
4018#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
4019#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
4020#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
4021#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
4022
4023#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
4024#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
4025#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
4026#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
4027#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
4028#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
4029#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
4030#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
4031
4032#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
4033#define ADC_EVACT_gp  0  /* Event Action Select group position. */
4034#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
4035#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
4036#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
4037#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
4038#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
4039#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
4040
4041
4042/* ADC.PRESCALER  bit masks and bit positions */
4043#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
4044#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
4045#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
4046#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
4047#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
4048#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
4049#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
4050#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
4051
4052
4053/* ADC.INTFLAGS  bit masks and bit positions */
4054#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
4055#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
4056
4057
4058/* RTC - Real-Time Clounter */
4059/* RTC.CTRL  bit masks and bit positions */
4060#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
4061#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
4062#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
4063#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
4064#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
4065#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
4066#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
4067#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
4068
4069
4070/* RTC.STATUS  bit masks and bit positions */
4071#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
4072#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
4073
4074
4075/* RTC.INTCTRL  bit masks and bit positions */
4076#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
4077#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
4078#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
4079#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
4080#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
4081#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
4082
4083#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
4084#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
4085#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
4086#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
4087#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
4088#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
4089
4090
4091/* RTC.INTFLAGS  bit masks and bit positions */
4092#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
4093#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
4094
4095#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
4096#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
4097
4098
4099/* EBI - External Bus Interface */
4100/* EBI_CS.CTRLA  bit masks and bit positions */
4101#define EBI_CS_ASIZE_gm  0x7C  /* Address Size group mask. */
4102#define EBI_CS_ASIZE_gp  2  /* Address Size group position. */
4103#define EBI_CS_ASIZE0_bm  (1<<2)  /* Address Size bit 0 mask. */
4104#define EBI_CS_ASIZE0_bp  2  /* Address Size bit 0 position. */
4105#define EBI_CS_ASIZE1_bm  (1<<3)  /* Address Size bit 1 mask. */
4106#define EBI_CS_ASIZE1_bp  3  /* Address Size bit 1 position. */
4107#define EBI_CS_ASIZE2_bm  (1<<4)  /* Address Size bit 2 mask. */
4108#define EBI_CS_ASIZE2_bp  4  /* Address Size bit 2 position. */
4109#define EBI_CS_ASIZE3_bm  (1<<5)  /* Address Size bit 3 mask. */
4110#define EBI_CS_ASIZE3_bp  5  /* Address Size bit 3 position. */
4111#define EBI_CS_ASIZE4_bm  (1<<6)  /* Address Size bit 4 mask. */
4112#define EBI_CS_ASIZE4_bp  6  /* Address Size bit 4 position. */
4113
4114#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
4115#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
4116#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
4117#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
4118#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
4119#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
4120
4121
4122/* EBI_CS.CTRLB  bit masks and bit positions */
4123#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
4124#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
4125#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
4126#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
4127#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
4128#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
4129#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
4130#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
4131
4132#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
4133#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
4134
4135#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
4136#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
4137
4138#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
4139#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
4140#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
4141#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
4142#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
4143#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
4144
4145
4146/* EBI.CTRL  bit masks and bit positions */
4147#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
4148#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
4149#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
4150#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
4151#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
4152#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
4153
4154#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
4155#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
4156#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
4157#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
4158#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
4159#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
4160
4161#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
4162#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
4163#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
4164#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
4165#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
4166#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
4167
4168#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
4169#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
4170#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
4171#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
4172#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
4173#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
4174
4175
4176/* EBI.SDRAMCTRLA  bit masks and bit positions */
4177#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
4178#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
4179
4180#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
4181#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
4182
4183#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
4184#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
4185#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
4186#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
4187#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
4188#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
4189
4190
4191/* EBI.SDRAMCTRLB  bit masks and bit positions */
4192#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
4193#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
4194#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
4195#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
4196#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
4197#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
4198
4199#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
4200#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
4201#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
4202#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
4203#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
4204#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
4205#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
4206#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
4207
4208#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
4209#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
4210#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
4211#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
4212#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
4213#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
4214#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
4215#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
4216
4217
4218/* EBI.SDRAMCTRLC  bit masks and bit positions */
4219#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
4220#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
4221#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
4222#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
4223#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
4224#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
4225
4226#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
4227#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
4228#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
4229#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
4230#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
4231#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
4232#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
4233#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
4234
4235#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
4236#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
4237#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
4238#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
4239#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
4240#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
4241#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
4242#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
4243
4244
4245/* TWI - Two-Wire Interface */
4246/* TWI_MASTER.CTRLA  bit masks and bit positions */
4247#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
4248#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
4249#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
4250#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
4251#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
4252#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
4253
4254#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
4255#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
4256
4257#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
4258#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
4259
4260#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
4261#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
4262
4263
4264/* TWI_MASTER.CTRLB  bit masks and bit positions */
4265#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
4266#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
4267#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
4268#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
4269#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
4270#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
4271
4272#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
4273#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
4274
4275#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
4276#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
4277
4278
4279/* TWI_MASTER.CTRLC  bit masks and bit positions */
4280#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
4281#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
4282
4283#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
4284#define TWI_MASTER_CMD_gp  0  /* Command group position. */
4285#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
4286#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
4287#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
4288#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
4289
4290
4291/* TWI_MASTER.STATUS  bit masks and bit positions */
4292#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
4293#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
4294
4295#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
4296#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
4297
4298#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
4299#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
4300
4301#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
4302#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
4303
4304#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
4305#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
4306
4307#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
4308#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
4309
4310#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
4311#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
4312#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
4313#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
4314#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
4315#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
4316
4317
4318/* TWI_SLAVE.CTRLA  bit masks and bit positions */
4319#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
4320#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
4321#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
4322#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
4323#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
4324#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
4325
4326#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
4327#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
4328
4329#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
4330#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
4331
4332#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
4333#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
4334
4335#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
4336#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
4337
4338#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
4339#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
4340
4341#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
4342#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
4343
4344
4345/* TWI_SLAVE.CTRLB  bit masks and bit positions */
4346#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
4347#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
4348
4349#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
4350#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
4351#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
4352#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
4353#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
4354#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
4355
4356
4357/* TWI_SLAVE.STATUS  bit masks and bit positions */
4358#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
4359#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
4360
4361#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
4362#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
4363
4364#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
4365#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
4366
4367#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
4368#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
4369
4370#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
4371#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
4372
4373#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
4374#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
4375
4376#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
4377#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
4378
4379#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
4380#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
4381
4382
4383/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
4384#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
4385#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
4386#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
4387#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
4388#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
4389#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
4390#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
4391#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
4392#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
4393#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
4394#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
4395#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
4396#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
4397#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
4398#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
4399#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
4400
4401#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
4402#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
4403
4404
4405/* TWI.CTRL  bit masks and bit positions */
4406#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
4407#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
4408
4409#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
4410#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
4411
4412
4413/* PORT - Port Configuration */
4414/* PORTCFG.VPCTRLA  bit masks and bit positions */
4415#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
4416#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
4417#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
4418#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
4419#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
4420#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
4421#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
4422#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
4423#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
4424#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
4425
4426#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
4427#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
4428#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
4429#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
4430#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
4431#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
4432#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
4433#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
4434#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
4435#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
4436
4437
4438/* PORTCFG.VPCTRLB  bit masks and bit positions */
4439#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
4440#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
4441#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
4442#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
4443#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
4444#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
4445#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
4446#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
4447#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
4448#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
4449
4450#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
4451#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
4452#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
4453#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
4454#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
4455#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
4456#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
4457#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
4458#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
4459#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
4460
4461
4462/* PORTCFG.CLKEVOUT  bit masks and bit positions */
4463#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
4464#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
4465#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
4466#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
4467#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
4468#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
4469
4470#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
4471#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
4472#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
4473#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
4474#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
4475#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
4476
4477
4478/* VPORT.INTFLAGS  bit masks and bit positions */
4479#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
4480#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
4481
4482#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
4483#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
4484
4485
4486/* PORT.INTCTRL  bit masks and bit positions */
4487#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
4488#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
4489#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
4490#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
4491#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
4492#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
4493
4494#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
4495#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
4496#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
4497#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
4498#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
4499#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
4500
4501
4502/* PORT.INTFLAGS  bit masks and bit positions */
4503#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
4504#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
4505
4506#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
4507#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
4508
4509
4510/* PORT.PIN0CTRL  bit masks and bit positions */
4511#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
4512#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
4513
4514#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
4515#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
4516
4517#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
4518#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
4519#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
4520#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
4521#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
4522#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
4523#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
4524#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
4525
4526#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
4527#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
4528#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
4529#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
4530#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
4531#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
4532#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
4533#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
4534
4535
4536/* PORT.PIN1CTRL  bit masks and bit positions */
4537/* PORT_SRLEN_bm  Predefined. */
4538/* PORT_SRLEN_bp  Predefined. */
4539
4540/* PORT_INVEN_bm  Predefined. */
4541/* PORT_INVEN_bp  Predefined. */
4542
4543/* PORT_OPC_gm  Predefined. */
4544/* PORT_OPC_gp  Predefined. */
4545/* PORT_OPC0_bm  Predefined. */
4546/* PORT_OPC0_bp  Predefined. */
4547/* PORT_OPC1_bm  Predefined. */
4548/* PORT_OPC1_bp  Predefined. */
4549/* PORT_OPC2_bm  Predefined. */
4550/* PORT_OPC2_bp  Predefined. */
4551
4552/* PORT_ISC_gm  Predefined. */
4553/* PORT_ISC_gp  Predefined. */
4554/* PORT_ISC0_bm  Predefined. */
4555/* PORT_ISC0_bp  Predefined. */
4556/* PORT_ISC1_bm  Predefined. */
4557/* PORT_ISC1_bp  Predefined. */
4558/* PORT_ISC2_bm  Predefined. */
4559/* PORT_ISC2_bp  Predefined. */
4560
4561
4562/* PORT.PIN2CTRL  bit masks and bit positions */
4563/* PORT_SRLEN_bm  Predefined. */
4564/* PORT_SRLEN_bp  Predefined. */
4565
4566/* PORT_INVEN_bm  Predefined. */
4567/* PORT_INVEN_bp  Predefined. */
4568
4569/* PORT_OPC_gm  Predefined. */
4570/* PORT_OPC_gp  Predefined. */
4571/* PORT_OPC0_bm  Predefined. */
4572/* PORT_OPC0_bp  Predefined. */
4573/* PORT_OPC1_bm  Predefined. */
4574/* PORT_OPC1_bp  Predefined. */
4575/* PORT_OPC2_bm  Predefined. */
4576/* PORT_OPC2_bp  Predefined. */
4577
4578/* PORT_ISC_gm  Predefined. */
4579/* PORT_ISC_gp  Predefined. */
4580/* PORT_ISC0_bm  Predefined. */
4581/* PORT_ISC0_bp  Predefined. */
4582/* PORT_ISC1_bm  Predefined. */
4583/* PORT_ISC1_bp  Predefined. */
4584/* PORT_ISC2_bm  Predefined. */
4585/* PORT_ISC2_bp  Predefined. */
4586
4587
4588/* PORT.PIN3CTRL  bit masks and bit positions */
4589/* PORT_SRLEN_bm  Predefined. */
4590/* PORT_SRLEN_bp  Predefined. */
4591
4592/* PORT_INVEN_bm  Predefined. */
4593/* PORT_INVEN_bp  Predefined. */
4594
4595/* PORT_OPC_gm  Predefined. */
4596/* PORT_OPC_gp  Predefined. */
4597/* PORT_OPC0_bm  Predefined. */
4598/* PORT_OPC0_bp  Predefined. */
4599/* PORT_OPC1_bm  Predefined. */
4600/* PORT_OPC1_bp  Predefined. */
4601/* PORT_OPC2_bm  Predefined. */
4602/* PORT_OPC2_bp  Predefined. */
4603
4604/* PORT_ISC_gm  Predefined. */
4605/* PORT_ISC_gp  Predefined. */
4606/* PORT_ISC0_bm  Predefined. */
4607/* PORT_ISC0_bp  Predefined. */
4608/* PORT_ISC1_bm  Predefined. */
4609/* PORT_ISC1_bp  Predefined. */
4610/* PORT_ISC2_bm  Predefined. */
4611/* PORT_ISC2_bp  Predefined. */
4612
4613
4614/* PORT.PIN4CTRL  bit masks and bit positions */
4615/* PORT_SRLEN_bm  Predefined. */
4616/* PORT_SRLEN_bp  Predefined. */
4617
4618/* PORT_INVEN_bm  Predefined. */
4619/* PORT_INVEN_bp  Predefined. */
4620
4621/* PORT_OPC_gm  Predefined. */
4622/* PORT_OPC_gp  Predefined. */
4623/* PORT_OPC0_bm  Predefined. */
4624/* PORT_OPC0_bp  Predefined. */
4625/* PORT_OPC1_bm  Predefined. */
4626/* PORT_OPC1_bp  Predefined. */
4627/* PORT_OPC2_bm  Predefined. */
4628/* PORT_OPC2_bp  Predefined. */
4629
4630/* PORT_ISC_gm  Predefined. */
4631/* PORT_ISC_gp  Predefined. */
4632/* PORT_ISC0_bm  Predefined. */
4633/* PORT_ISC0_bp  Predefined. */
4634/* PORT_ISC1_bm  Predefined. */
4635/* PORT_ISC1_bp  Predefined. */
4636/* PORT_ISC2_bm  Predefined. */
4637/* PORT_ISC2_bp  Predefined. */
4638
4639
4640/* PORT.PIN5CTRL  bit masks and bit positions */
4641/* PORT_SRLEN_bm  Predefined. */
4642/* PORT_SRLEN_bp  Predefined. */
4643
4644/* PORT_INVEN_bm  Predefined. */
4645/* PORT_INVEN_bp  Predefined. */
4646
4647/* PORT_OPC_gm  Predefined. */
4648/* PORT_OPC_gp  Predefined. */
4649/* PORT_OPC0_bm  Predefined. */
4650/* PORT_OPC0_bp  Predefined. */
4651/* PORT_OPC1_bm  Predefined. */
4652/* PORT_OPC1_bp  Predefined. */
4653/* PORT_OPC2_bm  Predefined. */
4654/* PORT_OPC2_bp  Predefined. */
4655
4656/* PORT_ISC_gm  Predefined. */
4657/* PORT_ISC_gp  Predefined. */
4658/* PORT_ISC0_bm  Predefined. */
4659/* PORT_ISC0_bp  Predefined. */
4660/* PORT_ISC1_bm  Predefined. */
4661/* PORT_ISC1_bp  Predefined. */
4662/* PORT_ISC2_bm  Predefined. */
4663/* PORT_ISC2_bp  Predefined. */
4664
4665
4666/* PORT.PIN6CTRL  bit masks and bit positions */
4667/* PORT_SRLEN_bm  Predefined. */
4668/* PORT_SRLEN_bp  Predefined. */
4669
4670/* PORT_INVEN_bm  Predefined. */
4671/* PORT_INVEN_bp  Predefined. */
4672
4673/* PORT_OPC_gm  Predefined. */
4674/* PORT_OPC_gp  Predefined. */
4675/* PORT_OPC0_bm  Predefined. */
4676/* PORT_OPC0_bp  Predefined. */
4677/* PORT_OPC1_bm  Predefined. */
4678/* PORT_OPC1_bp  Predefined. */
4679/* PORT_OPC2_bm  Predefined. */
4680/* PORT_OPC2_bp  Predefined. */
4681
4682/* PORT_ISC_gm  Predefined. */
4683/* PORT_ISC_gp  Predefined. */
4684/* PORT_ISC0_bm  Predefined. */
4685/* PORT_ISC0_bp  Predefined. */
4686/* PORT_ISC1_bm  Predefined. */
4687/* PORT_ISC1_bp  Predefined. */
4688/* PORT_ISC2_bm  Predefined. */
4689/* PORT_ISC2_bp  Predefined. */
4690
4691
4692/* PORT.PIN7CTRL  bit masks and bit positions */
4693/* PORT_SRLEN_bm  Predefined. */
4694/* PORT_SRLEN_bp  Predefined. */
4695
4696/* PORT_INVEN_bm  Predefined. */
4697/* PORT_INVEN_bp  Predefined. */
4698
4699/* PORT_OPC_gm  Predefined. */
4700/* PORT_OPC_gp  Predefined. */
4701/* PORT_OPC0_bm  Predefined. */
4702/* PORT_OPC0_bp  Predefined. */
4703/* PORT_OPC1_bm  Predefined. */
4704/* PORT_OPC1_bp  Predefined. */
4705/* PORT_OPC2_bm  Predefined. */
4706/* PORT_OPC2_bp  Predefined. */
4707
4708/* PORT_ISC_gm  Predefined. */
4709/* PORT_ISC_gp  Predefined. */
4710/* PORT_ISC0_bm  Predefined. */
4711/* PORT_ISC0_bp  Predefined. */
4712/* PORT_ISC1_bm  Predefined. */
4713/* PORT_ISC1_bp  Predefined. */
4714/* PORT_ISC2_bm  Predefined. */
4715/* PORT_ISC2_bp  Predefined. */
4716
4717
4718/* TC - 16-bit Timer/Counter With PWM */
4719/* TC0.CTRLA  bit masks and bit positions */
4720#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4721#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
4722#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4723#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4724#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4725#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4726#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4727#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4728#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4729#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4730
4731
4732/* TC0.CTRLB  bit masks and bit positions */
4733#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
4734#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
4735
4736#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
4737#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
4738
4739#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
4740#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
4741
4742#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
4743#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
4744
4745#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
4746#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
4747#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
4748#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
4749#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
4750#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
4751#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
4752#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
4753
4754
4755/* TC0.CTRLC  bit masks and bit positions */
4756#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
4757#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
4758
4759#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
4760#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
4761
4762#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
4763#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
4764
4765#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
4766#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
4767
4768
4769/* TC0.CTRLD  bit masks and bit positions */
4770#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
4771#define TC0_EVACT_gp  5  /* Event Action group position. */
4772#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
4773#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
4774#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
4775#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
4776#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
4777#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
4778
4779#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
4780#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
4781
4782#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
4783#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
4784#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
4785#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
4786#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
4787#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
4788#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
4789#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
4790#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
4791#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
4792
4793
4794/* TC0.CTRLE  bit masks and bit positions */
4795#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
4796#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
4797
4798
4799/* TC0.INTCTRLA  bit masks and bit positions */
4800#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
4801#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
4802#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
4803#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
4804#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
4805#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
4806
4807#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
4808#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
4809#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
4810#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
4811#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
4812#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
4813
4814
4815/* TC0.INTCTRLB  bit masks and bit positions */
4816#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
4817#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
4818#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
4819#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
4820#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
4821#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
4822
4823#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
4824#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
4825#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
4826#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
4827#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
4828#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
4829
4830#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
4831#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
4832#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
4833#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
4834#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
4835#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
4836
4837#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
4838#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
4839#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
4840#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
4841#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
4842#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
4843
4844
4845/* TC0.CTRLFCLR  bit masks and bit positions */
4846#define TC0_CMD_gm  0x0C  /* Command group mask. */
4847#define TC0_CMD_gp  2  /* Command group position. */
4848#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
4849#define TC0_CMD0_bp  2  /* Command bit 0 position. */
4850#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
4851#define TC0_CMD1_bp  3  /* Command bit 1 position. */
4852
4853#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
4854#define TC0_LUPD_bp  1  /* Lock Update bit position. */
4855
4856#define TC0_DIR_bm  0x01  /* Direction bit mask. */
4857#define TC0_DIR_bp  0  /* Direction bit position. */
4858
4859
4860/* TC0.CTRLFSET  bit masks and bit positions */
4861/* TC0_CMD_gm  Predefined. */
4862/* TC0_CMD_gp  Predefined. */
4863/* TC0_CMD0_bm  Predefined. */
4864/* TC0_CMD0_bp  Predefined. */
4865/* TC0_CMD1_bm  Predefined. */
4866/* TC0_CMD1_bp  Predefined. */
4867
4868/* TC0_LUPD_bm  Predefined. */
4869/* TC0_LUPD_bp  Predefined. */
4870
4871/* TC0_DIR_bm  Predefined. */
4872/* TC0_DIR_bp  Predefined. */
4873
4874
4875/* TC0.CTRLGCLR  bit masks and bit positions */
4876#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
4877#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
4878
4879#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
4880#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
4881
4882#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
4883#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
4884
4885#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
4886#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
4887
4888#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
4889#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
4890
4891
4892/* TC0.CTRLGSET  bit masks and bit positions */
4893/* TC0_CCDBV_bm  Predefined. */
4894/* TC0_CCDBV_bp  Predefined. */
4895
4896/* TC0_CCCBV_bm  Predefined. */
4897/* TC0_CCCBV_bp  Predefined. */
4898
4899/* TC0_CCBBV_bm  Predefined. */
4900/* TC0_CCBBV_bp  Predefined. */
4901
4902/* TC0_CCABV_bm  Predefined. */
4903/* TC0_CCABV_bp  Predefined. */
4904
4905/* TC0_PERBV_bm  Predefined. */
4906/* TC0_PERBV_bp  Predefined. */
4907
4908
4909/* TC0.INTFLAGS  bit masks and bit positions */
4910#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
4911#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
4912
4913#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
4914#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
4915
4916#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
4917#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
4918
4919#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
4920#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
4921
4922#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
4923#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
4924
4925#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
4926#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
4927
4928
4929/* TC1.CTRLA  bit masks and bit positions */
4930#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4931#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
4932#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4933#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4934#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4935#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4936#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4937#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4938#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4939#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4940
4941
4942/* TC1.CTRLB  bit masks and bit positions */
4943#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
4944#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
4945
4946#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
4947#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
4948
4949#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
4950#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
4951#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
4952#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
4953#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
4954#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
4955#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
4956#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
4957
4958
4959/* TC1.CTRLC  bit masks and bit positions */
4960#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
4961#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
4962
4963#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
4964#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
4965
4966
4967/* TC1.CTRLD  bit masks and bit positions */
4968#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
4969#define TC1_EVACT_gp  5  /* Event Action group position. */
4970#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
4971#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
4972#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
4973#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
4974#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
4975#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
4976
4977#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
4978#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
4979
4980#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
4981#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
4982#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
4983#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
4984#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
4985#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
4986#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
4987#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
4988#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
4989#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
4990
4991
4992/* TC1.CTRLE  bit masks and bit positions */
4993#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
4994#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
4995
4996
4997/* TC1.INTCTRLA  bit masks and bit positions */
4998#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
4999#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
5000#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
5001#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
5002#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
5003#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
5004
5005#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
5006#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
5007#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
5008#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
5009#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
5010#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
5011
5012
5013/* TC1.INTCTRLB  bit masks and bit positions */
5014#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
5015#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
5016#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
5017#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
5018#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
5019#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
5020
5021#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
5022#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
5023#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
5024#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
5025#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
5026#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
5027
5028
5029/* TC1.CTRLFCLR  bit masks and bit positions */
5030#define TC1_CMD_gm  0x0C  /* Command group mask. */
5031#define TC1_CMD_gp  2  /* Command group position. */
5032#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
5033#define TC1_CMD0_bp  2  /* Command bit 0 position. */
5034#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
5035#define TC1_CMD1_bp  3  /* Command bit 1 position. */
5036
5037#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
5038#define TC1_LUPD_bp  1  /* Lock Update bit position. */
5039
5040#define TC1_DIR_bm  0x01  /* Direction bit mask. */
5041#define TC1_DIR_bp  0  /* Direction bit position. */
5042
5043
5044/* TC1.CTRLFSET  bit masks and bit positions */
5045/* TC1_CMD_gm  Predefined. */
5046/* TC1_CMD_gp  Predefined. */
5047/* TC1_CMD0_bm  Predefined. */
5048/* TC1_CMD0_bp  Predefined. */
5049/* TC1_CMD1_bm  Predefined. */
5050/* TC1_CMD1_bp  Predefined. */
5051
5052/* TC1_LUPD_bm  Predefined. */
5053/* TC1_LUPD_bp  Predefined. */
5054
5055/* TC1_DIR_bm  Predefined. */
5056/* TC1_DIR_bp  Predefined. */
5057
5058
5059/* TC1.CTRLGCLR  bit masks and bit positions */
5060#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
5061#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
5062
5063#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
5064#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
5065
5066#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
5067#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
5068
5069
5070/* TC1.CTRLGSET  bit masks and bit positions */
5071/* TC1_CCBBV_bm  Predefined. */
5072/* TC1_CCBBV_bp  Predefined. */
5073
5074/* TC1_CCABV_bm  Predefined. */
5075/* TC1_CCABV_bp  Predefined. */
5076
5077/* TC1_PERBV_bm  Predefined. */
5078/* TC1_PERBV_bp  Predefined. */
5079
5080
5081/* TC1.INTFLAGS  bit masks and bit positions */
5082#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
5083#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
5084
5085#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
5086#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
5087
5088#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
5089#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
5090
5091#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
5092#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
5093
5094
5095/* AWEX.CTRL  bit masks and bit positions */
5096#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
5097#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
5098
5099#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
5100#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
5101
5102#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
5103#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
5104
5105#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
5106#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
5107
5108#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
5109#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
5110
5111#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
5112#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
5113
5114
5115/* AWEX.FDCTRL  bit masks and bit positions */
5116#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
5117#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
5118
5119#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
5120#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
5121
5122#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
5123#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
5124#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
5125#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
5126#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
5127#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
5128
5129
5130/* AWEX.STATUS  bit masks and bit positions */
5131#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
5132#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
5133
5134#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
5135#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
5136
5137#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
5138#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
5139
5140
5141/* HIRES.CTRLA  bit masks and bit positions */
5142#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
5143#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
5144#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
5145#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
5146#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
5147#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
5148
5149
5150/* USART - Universal Asynchronous Receiver-Transmitter */
5151/* USART.STATUS  bit masks and bit positions */
5152#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
5153#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
5154
5155#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
5156#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
5157
5158#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
5159#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
5160
5161#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
5162#define USART_FERR_bp  4  /* Frame Error bit position. */
5163
5164#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
5165#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
5166
5167#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
5168#define USART_PERR_bp  2  /* Parity Error bit position. */
5169
5170#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
5171#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
5172
5173
5174/* USART.CTRLA  bit masks and bit positions */
5175#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
5176#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
5177#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
5178#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
5179#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
5180#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
5181
5182#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
5183#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
5184#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
5185#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
5186#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
5187#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
5188
5189#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
5190#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
5191#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
5192#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
5193#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
5194#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
5195
5196
5197/* USART.CTRLB  bit masks and bit positions */
5198#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
5199#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
5200
5201#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
5202#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
5203
5204#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
5205#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
5206
5207#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
5208#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
5209
5210#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
5211#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
5212
5213
5214/* USART.CTRLC  bit masks and bit positions */
5215#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
5216#define USART_CMODE_gp  6  /* Communication Mode group position. */
5217#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
5218#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
5219#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
5220#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
5221
5222#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
5223#define USART_PMODE_gp  4  /* Parity Mode group position. */
5224#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
5225#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
5226#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
5227#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
5228
5229#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
5230#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
5231
5232#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
5233#define USART_CHSIZE_gp  0  /* Character Size group position. */
5234#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
5235#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
5236#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
5237#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
5238#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
5239#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
5240
5241
5242/* USART.BAUDCTRLA  bit masks and bit positions */
5243#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
5244#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
5245#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
5246#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
5247#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
5248#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
5249#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
5250#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
5251#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
5252#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
5253#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
5254#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
5255#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
5256#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
5257#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
5258#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
5259#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
5260#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
5261
5262
5263/* USART.BAUDCTRLB  bit masks and bit positions */
5264#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
5265#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
5266#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
5267#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
5268#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
5269#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
5270#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
5271#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
5272#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
5273#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
5274
5275/* USART_BSEL_gm  Predefined. */
5276/* USART_BSEL_gp  Predefined. */
5277/* USART_BSEL0_bm  Predefined. */
5278/* USART_BSEL0_bp  Predefined. */
5279/* USART_BSEL1_bm  Predefined. */
5280/* USART_BSEL1_bp  Predefined. */
5281/* USART_BSEL2_bm  Predefined. */
5282/* USART_BSEL2_bp  Predefined. */
5283/* USART_BSEL3_bm  Predefined. */
5284/* USART_BSEL3_bp  Predefined. */
5285
5286
5287/* SPI - Serial Peripheral Interface */
5288/* SPI.CTRL  bit masks and bit positions */
5289#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
5290#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
5291
5292#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
5293#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
5294
5295#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
5296#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
5297
5298#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
5299#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
5300
5301#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
5302#define SPI_MODE_gp  2  /* SPI Mode group position. */
5303#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
5304#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
5305#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
5306#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
5307
5308#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
5309#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
5310#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
5311#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
5312#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
5313#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
5314
5315
5316/* SPI.INTCTRL  bit masks and bit positions */
5317#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
5318#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
5319#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
5320#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
5321#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
5322#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
5323
5324
5325/* SPI.STATUS  bit masks and bit positions */
5326#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
5327#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
5328
5329#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
5330#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
5331
5332
5333/* IRCOM - IR Communication Module */
5334/* IRCOM.CTRL  bit masks and bit positions */
5335#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
5336#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
5337#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
5338#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
5339#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
5340#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
5341#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
5342#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
5343#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
5344#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
5345
5346
5347
5348// Generic Port Pins
5349
5350#define PIN0_bm 0x01
5351#define PIN0_bp 0
5352#define PIN1_bm 0x02
5353#define PIN1_bp 1
5354#define PIN2_bm 0x04
5355#define PIN2_bp 2
5356#define PIN3_bm 0x08
5357#define PIN3_bp 3
5358#define PIN4_bm 0x10
5359#define PIN4_bp 4
5360#define PIN5_bm 0x20
5361#define PIN5_bp 5
5362#define PIN6_bm 0x40
5363#define PIN6_bp 6
5364#define PIN7_bm 0x80
5365#define PIN7_bp 7
5366
5367
5368/* ========== Interrupt Vector Definitions ========== */
5369/* Vector 0 is the reset vector */
5370
5371/* OSC interrupt vectors */
5372#define OSC_XOSCF_vect_num  1
5373#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
5374
5375/* PORTC interrupt vectors */
5376#define PORTC_INT0_vect_num  2
5377#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
5378#define PORTC_INT1_vect_num  3
5379#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
5380
5381/* PORTR interrupt vectors */
5382#define PORTR_INT0_vect_num  4
5383#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
5384#define PORTR_INT1_vect_num  5
5385#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
5386
5387/* RTC interrupt vectors */
5388#define RTC_OVF_vect_num  10
5389#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
5390#define RTC_COMP_vect_num  11
5391#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
5392
5393/* TWIC interrupt vectors */
5394#define TWIC_TWIS_vect_num  12
5395#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
5396#define TWIC_TWIM_vect_num  13
5397#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
5398
5399/* TCC0 interrupt vectors */
5400#define TCC0_OVF_vect_num  14
5401#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
5402#define TCC0_ERR_vect_num  15
5403#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
5404#define TCC0_CCA_vect_num  16
5405#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
5406#define TCC0_CCB_vect_num  17
5407#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
5408#define TCC0_CCC_vect_num  18
5409#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
5410#define TCC0_CCD_vect_num  19
5411#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
5412
5413/* TCC1 interrupt vectors */
5414#define TCC1_OVF_vect_num  20
5415#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
5416#define TCC1_ERR_vect_num  21
5417#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
5418#define TCC1_CCA_vect_num  22
5419#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
5420#define TCC1_CCB_vect_num  23
5421#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
5422
5423/* SPIC interrupt vectors */
5424#define SPIC_INT_vect_num  24
5425#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
5426
5427/* USARTC0 interrupt vectors */
5428#define USARTC0_RXC_vect_num  25
5429#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
5430#define USARTC0_DRE_vect_num  26
5431#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
5432#define USARTC0_TXC_vect_num  27
5433#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
5434
5435/* NVM interrupt vectors */
5436#define NVM_EE_vect_num  32
5437#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
5438#define NVM_SPM_vect_num  33
5439#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
5440
5441/* PORTB interrupt vectors */
5442#define PORTB_INT0_vect_num  34
5443#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
5444#define PORTB_INT1_vect_num  35
5445#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
5446
5447/* PORTE interrupt vectors */
5448#define PORTE_INT0_vect_num  43
5449#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
5450#define PORTE_INT1_vect_num  44
5451#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
5452
5453/* TWIE interrupt vectors */
5454#define TWIE_TWIS_vect_num  45
5455#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
5456#define TWIE_TWIM_vect_num  46
5457#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
5458
5459/* TCE0 interrupt vectors */
5460#define TCE0_OVF_vect_num  47
5461#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
5462#define TCE0_ERR_vect_num  48
5463#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
5464#define TCE0_CCA_vect_num  49
5465#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
5466#define TCE0_CCB_vect_num  50
5467#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
5468#define TCE0_CCC_vect_num  51
5469#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
5470#define TCE0_CCD_vect_num  52
5471#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
5472
5473/* USARTE0 interrupt vectors */
5474#define USARTE0_RXC_vect_num  58
5475#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
5476#define USARTE0_DRE_vect_num  59
5477#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
5478#define USARTE0_TXC_vect_num  60
5479#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
5480
5481/* PORTD interrupt vectors */
5482#define PORTD_INT0_vect_num  64
5483#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
5484#define PORTD_INT1_vect_num  65
5485#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
5486
5487/* PORTA interrupt vectors */
5488#define PORTA_INT0_vect_num  66
5489#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
5490#define PORTA_INT1_vect_num  67
5491#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
5492
5493/* ACA interrupt vectors */
5494#define ACA_AC0_vect_num  68
5495#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
5496#define ACA_AC1_vect_num  69
5497#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
5498#define ACA_ACW_vect_num  70
5499#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
5500
5501/* ADCA interrupt vectors */
5502#define ADCA_CH0_vect_num  71
5503#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
5504
5505/* TCD0 interrupt vectors */
5506#define TCD0_OVF_vect_num  77
5507#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
5508#define TCD0_ERR_vect_num  78
5509#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
5510#define TCD0_CCA_vect_num  79
5511#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
5512#define TCD0_CCB_vect_num  80
5513#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
5514#define TCD0_CCC_vect_num  81
5515#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
5516#define TCD0_CCD_vect_num  82
5517#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
5518
5519/* SPID interrupt vectors */
5520#define SPID_INT_vect_num  87
5521#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
5522
5523/* USARTD0 interrupt vectors */
5524#define USARTD0_RXC_vect_num  88
5525#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
5526#define USARTD0_DRE_vect_num  89
5527#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
5528#define USARTD0_TXC_vect_num  90
5529#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
5530
5531/* PORTF interrupt vectors */
5532#define PORTF_INT0_vect_num  104
5533#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
5534#define PORTF_INT1_vect_num  105
5535#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
5536
5537/* TCF0 interrupt vectors */
5538#define TCF0_OVF_vect_num  108
5539#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
5540#define TCF0_ERR_vect_num  109
5541#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
5542#define TCF0_CCA_vect_num  110
5543#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
5544#define TCF0_CCB_vect_num  111
5545#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
5546#define TCF0_CCC_vect_num  112
5547#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
5548#define TCF0_CCD_vect_num  113
5549#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
5550
5551
5552#define _VECTOR_SIZE 4 /* Size of individual vector. */
5553#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
5554
5555
5556/* ========== Constants ========== */
5557
5558#define PROGMEM_START     (0x0000)
5559#define PROGMEM_SIZE      (204800)
5560#define PROGMEM_PAGE_SIZE (512)
5561#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
5562
5563#define APP_SECTION_START     (0x0000)
5564#define APP_SECTION_SIZE      (196608)
5565#define APP_SECTION_PAGE_SIZE (512)
5566#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
5567
5568#define APPTABLE_SECTION_START     (0x2E000)
5569#define APPTABLE_SECTION_SIZE      (8192)
5570#define APPTABLE_SECTION_PAGE_SIZE (512)
5571#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
5572
5573#define BOOT_SECTION_START     (0x30000)
5574#define BOOT_SECTION_SIZE      (8192)
5575#define BOOT_SECTION_PAGE_SIZE (512)
5576#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
5577
5578#define DATAMEM_START     (0x0000)
5579#define DATAMEM_SIZE      (24576)
5580#define DATAMEM_PAGE_SIZE (0)
5581#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
5582
5583#define IO_START     (0x0000)
5584#define IO_SIZE      (4096)
5585#define IO_PAGE_SIZE (0)
5586#define IO_END       (IO_START + IO_SIZE - 1)
5587
5588#define MAPPED_EEPROM_START     (0x1000)
5589#define MAPPED_EEPROM_SIZE      (2048)
5590#define MAPPED_EEPROM_PAGE_SIZE (0)
5591#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
5592
5593#define INTERNAL_SRAM_START     (0x2000)
5594#define INTERNAL_SRAM_SIZE      (16384)
5595#define INTERNAL_SRAM_PAGE_SIZE (0)
5596#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
5597
5598#define EEPROM_START     (0x0000)
5599#define EEPROM_SIZE      (2048)
5600#define EEPROM_PAGE_SIZE (32)
5601#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
5602
5603#define FUSE_START     (0x0000)
5604#define FUSE_SIZE      (6)
5605#define FUSE_PAGE_SIZE (0)
5606#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
5607
5608#define LOCKBIT_START     (0x0000)
5609#define LOCKBIT_SIZE      (1)
5610#define LOCKBIT_PAGE_SIZE (0)
5611#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
5612
5613#define SIGNATURES_START     (0x0000)
5614#define SIGNATURES_SIZE      (3)
5615#define SIGNATURES_PAGE_SIZE (0)
5616#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
5617
5618#define USER_SIGNATURES_START     (0x0000)
5619#define USER_SIGNATURES_SIZE      (512)
5620#define USER_SIGNATURES_PAGE_SIZE (0)
5621#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
5622
5623#define PROD_SIGNATURES_START     (0x0000)
5624#define PROD_SIGNATURES_SIZE      (52)
5625#define PROD_SIGNATURES_PAGE_SIZE (0)
5626#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
5627
5628#define FLASHEND     PROGMEM_END
5629#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
5630#define RAMSTART     INTERNAL_SRAM_START
5631#define RAMSIZE      INTERNAL_SRAM_SIZE
5632#define RAMEND       INTERNAL_SRAM_END
5633#define XRAMSTART    EXTERNAL_SRAM_START
5634#define XRAMSIZE     EXTERNAL_SRAM_SIZE
5635#define XRAMEND      INTERNAL_SRAM_END
5636#define E2END        EEPROM_END
5637#define E2PAGESIZE   EEPROM_PAGE_SIZE
5638
5639
5640/* ========== Fuses ========== */
5641#define FUSE_MEMORY_SIZE 6
5642
5643/* Fuse Byte 0 */
5644#define FUSE_USERID0  (unsigned char)~_BV(0)  /* User ID Bit 0 */
5645#define FUSE_USERID1  (unsigned char)~_BV(1)  /* User ID Bit 1 */
5646#define FUSE_USERID2  (unsigned char)~_BV(2)  /* User ID Bit 2 */
5647#define FUSE_USERID3  (unsigned char)~_BV(3)  /* User ID Bit 3 */
5648#define FUSE_USERID4  (unsigned char)~_BV(4)  /* User ID Bit 4 */
5649#define FUSE_USERID5  (unsigned char)~_BV(5)  /* User ID Bit 5 */
5650#define FUSE_USERID6  (unsigned char)~_BV(6)  /* User ID Bit 6 */
5651#define FUSE_USERID7  (unsigned char)~_BV(7)  /* User ID Bit 7 */
5652#define FUSE0_DEFAULT  (0xFF)
5653
5654/* Fuse Byte 1 */
5655#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
5656#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
5657#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
5658#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
5659#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
5660#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
5661#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
5662#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
5663#define FUSE1_DEFAULT  (0xFF)
5664
5665/* Fuse Byte 2 */
5666#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
5667#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
5668#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
5669#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
5670#define FUSE2_DEFAULT  (0xFF)
5671
5672/* Fuse Byte 3 Reserved */
5673
5674/* Fuse Byte 4 */
5675#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
5676#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
5677#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
5678#define FUSE4_DEFAULT  (0xFF)
5679
5680/* Fuse Byte 5 */
5681#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
5682#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
5683#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
5684#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
5685#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
5686#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
5687#define FUSE5_DEFAULT  (0xFF)
5688
5689
5690/* ========== Lock Bits ========== */
5691#define __LOCK_BITS_EXIST
5692#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
5693#define __BOOT_LOCK_APPLICATION_BITS_EXIST
5694#define __BOOT_LOCK_BOOT_BITS_EXIST
5695
5696
5697/* ========== Signature ========== */
5698#define SIGNATURE_0 0x1E
5699#define SIGNATURE_1 0x97
5700#define SIGNATURE_2 0x49
5701
5702
5703#endif /* _AVR_ATxmega192D3_H_ */
5704
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