source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iox256d3.h @ 46

Last change on this file since 46 was 46, checked in by jrpelegrina, 4 years ago

First release to Xenial

File size: 242.9 KB
Line 
1/* Copyright (c) 2009-2010 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iox256d3.h 2162 2010-06-11 17:26:12Z arcanum $ */
32
33/* avr/iox256d3.h - definitions for ATxmega256D3 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iox256d3.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_ATxmega256D3_H_
49#define _AVR_ATxmega256D3_H_ 1
50
51
52/* Ungrouped common registers */
53#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
54#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
55#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
56#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
57#define GPIOR4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
58#define GPIOR5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
59#define GPIOR6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
60#define GPIOR7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
61#define GPIOR8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
62#define GPIOR9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
63#define GPIORA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
64#define GPIORB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
65#define GPIORC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
66#define GPIORD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
67#define GPIORE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
68#define GPIORF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
69
70#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
71#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
72#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
73#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
74#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
75#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
76#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
77#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
78#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
79
80
81/* C Language Only */
82#if !defined (__ASSEMBLER__)
83
84#include <stdint.h>
85
86typedef volatile uint8_t register8_t;
87typedef volatile uint16_t register16_t;
88typedef volatile uint32_t register32_t;
89
90
91#ifdef _WORDREGISTER
92#undef _WORDREGISTER
93#endif
94#define _WORDREGISTER(regname)   \
95    __extension__ union \
96    { \
97        register16_t regname; \
98        struct \
99        { \
100            register8_t regname ## L; \
101            register8_t regname ## H; \
102        }; \
103    }
104
105#ifdef _DWORDREGISTER
106#undef _DWORDREGISTER
107#endif
108#define _DWORDREGISTER(regname)  \
109    __extension__ union \
110    { \
111        register32_t regname; \
112        struct \
113        { \
114            register8_t regname ## 0; \
115            register8_t regname ## 1; \
116            register8_t regname ## 2; \
117            register8_t regname ## 3; \
118        }; \
119    }
120
121
122/*
123==========================================================================
124IO Module Structures
125==========================================================================
126*/
127
128
129/*
130--------------------------------------------------------------------------
131XOCD - On-Chip Debug System
132--------------------------------------------------------------------------
133*/
134
135/* On-Chip Debug System */
136typedef struct OCD_struct
137{
138    register8_t OCDR0;  /* OCD Register 0 */
139    register8_t OCDR1;  /* OCD Register 1 */
140} OCD_t;
141
142
143/* CCP signatures */
144typedef enum CCP_enum
145{
146    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
147    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
148} CCP_t;
149
150
151/*
152--------------------------------------------------------------------------
153CLK - Clock System
154--------------------------------------------------------------------------
155*/
156
157/* Clock System */
158typedef struct CLK_struct
159{
160    register8_t CTRL;  /* Control Register */
161    register8_t PSCTRL;  /* Prescaler Control Register */
162    register8_t LOCK;  /* Lock register */
163    register8_t RTCCTRL;  /* RTC Control Register */
164} CLK_t;
165
166
167/* Power Reduction */
168typedef struct PR_struct
169{
170    register8_t PRGEN;  /* General Power Reduction */
171    register8_t PRPA;  /* Power Reduction Port A */
172    register8_t reserved_0x02;
173    register8_t PRPC;  /* Power Reduction Port C */
174    register8_t PRPD;  /* Power Reduction Port D */
175    register8_t PRPE;  /* Power Reduction Port E */
176    register8_t PRPF;  /* Power Reduction Port F */
177} PR_t;
178
179/* System Clock Selection */
180typedef enum CLK_SCLKSEL_enum
181{
182    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
183    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
184    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
185    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
186    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
187} CLK_SCLKSEL_t;
188
189/* Prescaler A Division Factor */
190typedef enum CLK_PSADIV_enum
191{
192    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
193    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
194    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
195    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
196    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
197    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
198    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
199    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
200    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
201    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
202} CLK_PSADIV_t;
203
204/* Prescaler B and C Division Factor */
205typedef enum CLK_PSBCDIV_enum
206{
207    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
208    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
209    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
210    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
211} CLK_PSBCDIV_t;
212
213/* RTC Clock Source */
214typedef enum CLK_RTCSRC_enum
215{
216    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
217    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
218    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
219    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
220} CLK_RTCSRC_t;
221
222
223/*
224--------------------------------------------------------------------------
225SLEEP - Sleep Controller
226--------------------------------------------------------------------------
227*/
228
229/* Sleep Controller */
230typedef struct SLEEP_struct
231{
232    register8_t CTRL;  /* Control Register */
233} SLEEP_t;
234
235/* Sleep Mode */
236typedef enum SLEEP_SMODE_enum
237{
238    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
239    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
240    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
241    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
242    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
243} SLEEP_SMODE_t;
244
245
246/*
247--------------------------------------------------------------------------
248OSC - Oscillator
249--------------------------------------------------------------------------
250*/
251
252/* Oscillator */
253typedef struct OSC_struct
254{
255    register8_t CTRL;  /* Control Register */
256    register8_t STATUS;  /* Status Register */
257    register8_t XOSCCTRL;  /* External Oscillator Control Register */
258    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
259    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
260    register8_t PLLCTRL;  /* PLL Control REgister */
261    register8_t DFLLCTRL;  /* DFLL Control Register */
262} OSC_t;
263
264/* Oscillator Frequency Range */
265typedef enum OSC_FRQRANGE_enum
266{
267    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
268    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
269    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
270    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
271} OSC_FRQRANGE_t;
272
273/* External Oscillator Selection and Startup Time */
274typedef enum OSC_XOSCSEL_enum
275{
276    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
277    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
278    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
279    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
280    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
281} OSC_XOSCSEL_t;
282
283/* PLL Clock Source */
284typedef enum OSC_PLLSRC_enum
285{
286    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
287    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
288    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
289} OSC_PLLSRC_t;
290
291
292/*
293--------------------------------------------------------------------------
294DFLL - DFLL
295--------------------------------------------------------------------------
296*/
297
298/* DFLL */
299typedef struct DFLL_struct
300{
301    register8_t CTRL;  /* Control Register */
302    register8_t reserved_0x01;
303    register8_t CALA;  /* Calibration Register A */
304    register8_t CALB;  /* Calibration Register B */
305    register8_t COMP0;  /* Oscillator Compare Register 0 */
306    register8_t COMP1;  /* Oscillator Compare Register 1 */
307    register8_t COMP2;  /* Oscillator Compare Register 2 */
308    register8_t reserved_0x07;
309} DFLL_t;
310
311
312/*
313--------------------------------------------------------------------------
314RST - Reset
315--------------------------------------------------------------------------
316*/
317
318/* Reset */
319typedef struct RST_struct
320{
321    register8_t STATUS;  /* Status Register */
322    register8_t CTRL;  /* Control Register */
323} RST_t;
324
325
326/*
327--------------------------------------------------------------------------
328WDT - Watch-Dog Timer
329--------------------------------------------------------------------------
330*/
331
332/* Watch-Dog Timer */
333typedef struct WDT_struct
334{
335    register8_t CTRL;  /* Control */
336    register8_t WINCTRL;  /* Windowed Mode Control */
337    register8_t STATUS;  /* Status */
338} WDT_t;
339
340/* Period setting */
341typedef enum WDT_PER_enum
342{
343    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
344    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
345    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
346    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
347    WDT_PER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
348    WDT_PER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
349    WDT_PER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
350    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
351    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
352    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
353    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
354} WDT_PER_t;
355
356/* Closed window period */
357typedef enum WDT_WPER_enum
358{
359    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
360    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
361    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
362    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
363    WDT_WPER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
364    WDT_WPER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
365    WDT_WPER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
366    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
367    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
368    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
369    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
370} WDT_WPER_t;
371
372
373/*
374--------------------------------------------------------------------------
375MCU - MCU Control
376--------------------------------------------------------------------------
377*/
378
379/* MCU Control */
380typedef struct MCU_struct
381{
382    register8_t DEVID0;  /* Device ID byte 0 */
383    register8_t DEVID1;  /* Device ID byte 1 */
384    register8_t DEVID2;  /* Device ID byte 2 */
385    register8_t REVID;  /* Revision ID */
386    register8_t JTAGUID;  /* JTAG User ID */
387    register8_t reserved_0x05;
388    register8_t MCUCR;  /* MCU Control */
389    register8_t reserved_0x07;
390    register8_t EVSYSLOCK;  /* Event System Lock */
391    register8_t AWEXLOCK;  /* AWEX Lock */
392    register8_t reserved_0x0A;
393    register8_t reserved_0x0B;
394} MCU_t;
395
396
397/*
398--------------------------------------------------------------------------
399PMIC - Programmable Multi-level Interrupt Controller
400--------------------------------------------------------------------------
401*/
402
403/* Programmable Multi-level Interrupt Controller */
404typedef struct PMIC_struct
405{
406    register8_t STATUS;  /* Status Register */
407    register8_t INTPRI;  /* Interrupt Priority */
408    register8_t CTRL;  /* Control Register */
409} PMIC_t;
410
411
412/*
413--------------------------------------------------------------------------
414CRC - Cyclic Redundancy Checker
415--------------------------------------------------------------------------
416*/
417
418/* Cyclic Redundancy Checker */
419typedef struct CRC_struct
420{
421    register8_t CTRL;  /* Control Register */
422    register8_t STATUS;  /* Status Register */
423    register8_t reserved_0x02;
424    register8_t DATAIN;  /* Data Input */
425    register8_t CHECKSUM0;  /* Checksum byte 0 */
426    register8_t CHECKSUM1;  /* Checksum byte 1 */
427    register8_t CHECKSUM2;  /* Checksum byte 2 */
428    register8_t CHECKSUM3;  /* Checksum byte 3 */
429} CRC_t;
430
431/* Reset */
432typedef enum CRC_RESET_enum
433{
434    CRC_RESET_NO_gc = (0x00<<6),  /* No Reset */
435    CRC_RESET_RESET0_gc = (0x02<<6),  /* Reset CRC with CHECKSUM to all zeros */
436    CRC_RESET_RESET1_gc = (0x03<<6),  /* Reset CRC with CHECKSUM to all ones */
437} CRC_RESET_t;
438
439/* Input Source */
440typedef enum CRC_SOURCE_enum
441{
442    CRC_SOURCE_DISABLE_gc = (0x00<<0),  /* Disabled */
443    CRC_SOURCE_IO_gc = (0x01<<0),  /* I/O Interface */
444    CRC_SOURCE_FLASH_gc = (0x02<<0),  /* Flash */
445    CRC_SOURCE_DMAC0_gc = (0x04<<0),  /* DMAC Channel 0 */
446    CRC_SOURCE_DMAC1_gc = (0x05<<0),  /* DMAC Channel 1 */
447    CRC_SOURCE_DMAC2_gc = (0x06<<0),  /* DMAC Channel 2 */
448    CRC_SOURCE_DMAC3_gc = (0x07<<0),  /* DMAC Channel 3 */
449} CRC_SOURCE_t;
450
451
452/*
453--------------------------------------------------------------------------
454EVSYS - Event System
455--------------------------------------------------------------------------
456*/
457
458/* Event System */
459typedef struct EVSYS_struct
460{
461    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
462    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
463    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
464    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
465    register8_t reserved_0x04;
466    register8_t reserved_0x05;
467    register8_t reserved_0x06;
468    register8_t reserved_0x07;
469    register8_t CH0CTRL;  /* Channel 0 Control Register */
470    register8_t CH1CTRL;  /* Channel 1 Control Register */
471    register8_t CH2CTRL;  /* Channel 2 Control Register */
472    register8_t CH3CTRL;  /* Channel 3 Control Register */
473    register8_t reserved_0x0C;
474    register8_t reserved_0x0D;
475    register8_t reserved_0x0E;
476    register8_t reserved_0x0F;
477    register8_t STROBE;  /* Event Strobe */
478    register8_t DATA;  /* Event Data */
479} EVSYS_t;
480
481/* Quadrature Decoder Index Recognition Mode */
482typedef enum EVSYS_QDIRM_enum
483{
484    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
485    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
486    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
487    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
488} EVSYS_QDIRM_t;
489
490/* Digital filter coefficient */
491typedef enum EVSYS_DIGFILT_enum
492{
493    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
494    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
495    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
496    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
497    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
498    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
499    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
500    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
501} EVSYS_DIGFILT_t;
502
503/* Event Channel multiplexer input selection */
504typedef enum EVSYS_CHMUX_enum
505{
506    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
507    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
508    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
509    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
510    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
511    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
512    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
513    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
514    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
515    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
516    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
517    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
518    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
519    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
520    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
521    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
522    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
523    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
524    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
525    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
526    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
527    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
528    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
529    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
530    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
531    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
532    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
533    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
534    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
535    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
536    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
537    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
538    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
539    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
540    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
541    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
542    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
543    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
544    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
545    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
546    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
547    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
548    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
549    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
550    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
551    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
552    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
553    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
554    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
555    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
556    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
557    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
558    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
559    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
560    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
561    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
562    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
563    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
564    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
565    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
566    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
567    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
568    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
569    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
570    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
571    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
572    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
573    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
574    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
575    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
576    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
577    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
578    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
579    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
580    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
581    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
582    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
583    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
584    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
585    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
586    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
587    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
588    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
589    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
590    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
591    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
592    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
593    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
594    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
595    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
596    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
597    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
598    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
599    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
600    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
601    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
602    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
603    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
604    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
605    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
606    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
607    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
608    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
609    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
610    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
611    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
612    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
613    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
614    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
615    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
616    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
617} EVSYS_CHMUX_t;
618
619
620/*
621--------------------------------------------------------------------------
622NVM - Non Volatile Memory Controller
623--------------------------------------------------------------------------
624*/
625
626/* Non-volatile Memory Controller */
627typedef struct NVM_struct
628{
629    register8_t ADDR0;  /* Address Register 0 */
630    register8_t ADDR1;  /* Address Register 1 */
631    register8_t ADDR2;  /* Address Register 2 */
632    register8_t reserved_0x03;
633    register8_t DATA0;  /* Data Register 0 */
634    register8_t DATA1;  /* Data Register 1 */
635    register8_t DATA2;  /* Data Register 2 */
636    register8_t reserved_0x07;
637    register8_t reserved_0x08;
638    register8_t reserved_0x09;
639    register8_t CMD;  /* Command */
640    register8_t CTRLA;  /* Control Register A */
641    register8_t CTRLB;  /* Control Register B */
642    register8_t INTCTRL;  /* Interrupt Control */
643    register8_t reserved_0x0E;
644    register8_t STATUS;  /* Status */
645    register8_t LOCKBITS;  /* Lock Bits */
646} NVM_t;
647
648/*
649--------------------------------------------------------------------------
650NVM - Non Volatile Memory Controller
651--------------------------------------------------------------------------
652*/
653
654/* Lock Bits */
655typedef struct NVM_LOCKBITS_struct
656{
657    register8_t LOCKBITS;  /* Lock Bits */
658} NVM_LOCKBITS_t;
659
660/*
661--------------------------------------------------------------------------
662NVM - Non Volatile Memory Controller
663--------------------------------------------------------------------------
664*/
665
666/* Fuses */
667typedef struct NVM_FUSES_struct
668{
669    register8_t FUSEBYTE0;  /* User ID */
670    register8_t FUSEBYTE1;  /* Watchdog Configuration */
671    register8_t FUSEBYTE2;  /* Reset Configuration */
672    register8_t reserved_0x03;
673    register8_t FUSEBYTE4;  /* Start-up Configuration */
674    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
675} NVM_FUSES_t;
676
677/*
678--------------------------------------------------------------------------
679NVM - Non Volatile Memory Controller
680--------------------------------------------------------------------------
681*/
682
683/* Production Signatures */
684typedef struct NVM_PROD_SIGNATURES_struct
685{
686    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
687    register8_t reserved_0x01;
688    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
689    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
690    register8_t reserved_0x04;
691    register8_t reserved_0x05;
692    register8_t reserved_0x06;
693    register8_t reserved_0x07;
694    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
695    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
696    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
697    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
698    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
699    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
700    register8_t reserved_0x0E;
701    register8_t reserved_0x0F;
702    register8_t WAFNUM;  /* Wafer Number */
703    register8_t reserved_0x11;
704    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
705    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
706    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
707    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
708    register8_t reserved_0x16;
709    register8_t reserved_0x17;
710    register8_t reserved_0x18;
711    register8_t reserved_0x19;
712    register8_t reserved_0x1A;
713    register8_t reserved_0x1B;
714    register8_t reserved_0x1C;
715    register8_t reserved_0x1D;
716    register8_t reserved_0x1E;
717    register8_t reserved_0x1F;
718    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
719    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
720    register8_t reserved_0x22;
721    register8_t reserved_0x23;
722    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
723    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
724    register8_t reserved_0x26;
725    register8_t reserved_0x27;
726    register8_t reserved_0x28;
727    register8_t reserved_0x29;
728    register8_t reserved_0x2A;
729    register8_t reserved_0x2B;
730    register8_t reserved_0x2C;
731    register8_t reserved_0x2D;
732    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
733    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
734    register8_t reserved_0x30;
735    register8_t reserved_0x31;
736    register8_t reserved_0x32;
737    register8_t reserved_0x33;
738    register8_t reserved_0x34;
739    register8_t reserved_0x35;
740    register8_t reserved_0x36;
741    register8_t reserved_0x37;
742    register8_t reserved_0x38;
743    register8_t reserved_0x39;
744    register8_t reserved_0x3A;
745    register8_t reserved_0x3B;
746    register8_t reserved_0x3C;
747    register8_t reserved_0x3D;
748    register8_t reserved_0x3E;
749} NVM_PROD_SIGNATURES_t;
750
751/* NVM Command */
752typedef enum NVM_CMD_enum
753{
754    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
755    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
756    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
757    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
758    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
759    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
760    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
761    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
762    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
763    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
764    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
765    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
766    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
767    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
768    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
769    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
770    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
771    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
772    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
773    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
774    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
775    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
776    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
777    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
778    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
779    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
780} NVM_CMD_t;
781
782/* SPM ready interrupt level */
783typedef enum NVM_SPMLVL_enum
784{
785    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
786    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
787    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
788    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
789} NVM_SPMLVL_t;
790
791/* EEPROM ready interrupt level */
792typedef enum NVM_EELVL_enum
793{
794    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
795    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
796    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
797    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
798} NVM_EELVL_t;
799
800/* Boot lock bits - boot setcion */
801typedef enum NVM_BLBB_enum
802{
803    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
804    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
805    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
806    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
807} NVM_BLBB_t;
808
809/* Boot lock bits - application section */
810typedef enum NVM_BLBA_enum
811{
812    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
813    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
814    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
815    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
816} NVM_BLBA_t;
817
818/* Boot lock bits - application table section */
819typedef enum NVM_BLBAT_enum
820{
821    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
822    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
823    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
824    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
825} NVM_BLBAT_t;
826
827/* Lock bits */
828typedef enum NVM_LB_enum
829{
830    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
831    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
832    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
833} NVM_LB_t;
834
835/* Boot Loader Section Reset Vector */
836typedef enum BOOTRST_enum
837{
838    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
839    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
840} BOOTRST_t;
841
842/* BOD operation */
843typedef enum BOD_enum
844{
845    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
846    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
847    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
848} BOD_t;
849
850/* Watchdog (Window) Timeout Period */
851typedef enum WD_enum
852{
853    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
854    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
855    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
856    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
857    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
858    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
859    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
860    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
861    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
862    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
863    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
864} WD_t;
865
866/* Start-up Time */
867typedef enum SUT_enum
868{
869    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
870    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
871    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
872} SUT_t;
873
874/* Brown Out Detection Voltage Level */
875typedef enum BODLVL_enum
876{
877    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
878    BODLVL_1V9_gc = (0x06<<0),  /* 1.9 V */
879    BODLVL_2V1_gc = (0x05<<0),  /* 2.1 V */
880    BODLVL_2V4_gc = (0x04<<0),  /* 2.4 V */
881    BODLVL_2V6_gc = (0x03<<0),  /* 2.6 V */
882    BODLVL_2V9_gc = (0x02<<0),  /* 2.9 V */
883    BODLVL_3V2_gc = (0x01<<0),  /* 3.2 V */
884} BODLVL_t;
885
886
887/*
888--------------------------------------------------------------------------
889AC - Analog Comparator
890--------------------------------------------------------------------------
891*/
892
893/* Analog Comparator */
894typedef struct AC_struct
895{
896    register8_t AC0CTRL;  /* Comparator 0 Control */
897    register8_t AC1CTRL;  /* Comparator 1 Control */
898    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
899    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
900    register8_t CTRLA;  /* Control Register A */
901    register8_t CTRLB;  /* Control Register B */
902    register8_t WINCTRL;  /* Window Mode Control */
903    register8_t STATUS;  /* Status */
904} AC_t;
905
906/* Interrupt mode */
907typedef enum AC_INTMODE_enum
908{
909    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
910    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
911    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
912} AC_INTMODE_t;
913
914/* Interrupt level */
915typedef enum AC_INTLVL_enum
916{
917    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
918    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
919    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
920    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
921} AC_INTLVL_t;
922
923/* Hysteresis mode selection */
924typedef enum AC_HYSMODE_enum
925{
926    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
927    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
928    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
929} AC_HYSMODE_t;
930
931/* Positive input multiplexer selection */
932typedef enum AC_MUXPOS_enum
933{
934    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
935    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
936    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
937    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
938    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
939    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
940    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
941} AC_MUXPOS_t;
942
943/* Negative input multiplexer selection */
944typedef enum AC_MUXNEG_enum
945{
946    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
947    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
948    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
949    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
950    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
951    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
952    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
953} AC_MUXNEG_t;
954
955/* Windows interrupt mode */
956typedef enum AC_WINTMODE_enum
957{
958    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
959    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
960    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
961    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
962} AC_WINTMODE_t;
963
964/* Window interrupt level */
965typedef enum AC_WINTLVL_enum
966{
967    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
968    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
969    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
970    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
971} AC_WINTLVL_t;
972
973/* Window mode state */
974typedef enum AC_WSTATE_enum
975{
976    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
977    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
978    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
979} AC_WSTATE_t;
980
981
982/*
983--------------------------------------------------------------------------
984ADC - Analog/Digital Converter
985--------------------------------------------------------------------------
986*/
987
988/* ADC Channel */
989typedef struct ADC_CH_struct
990{
991    register8_t CTRL;  /* Control Register */
992    register8_t MUXCTRL;  /* MUX Control */
993    register8_t INTCTRL;  /* Channel Interrupt Control */
994    register8_t INTFLAGS;  /* Interrupt Flags */
995    _WORDREGISTER(RES);  /* Channel Result */
996    register8_t reserved_0x6;
997    register8_t reserved_0x7;
998} ADC_CH_t;
999
1000/*
1001--------------------------------------------------------------------------
1002ADC - Analog/Digital Converter
1003--------------------------------------------------------------------------
1004*/
1005
1006/* Analog-to-Digital Converter */
1007typedef struct ADC_struct
1008{
1009    register8_t CTRLA;  /* Control Register A */
1010    register8_t CTRLB;  /* Control Register B */
1011    register8_t REFCTRL;  /* Reference Control */
1012    register8_t EVCTRL;  /* Event Control */
1013    register8_t PRESCALER;  /* Clock Prescaler */
1014    register8_t reserved_0x05;
1015    register8_t INTFLAGS;  /* Interrupt Flags */
1016    register8_t TEMP;  /* ACD Temporary Register */
1017    register8_t reserved_0x08;
1018    register8_t reserved_0x09;
1019    register8_t reserved_0x0A;
1020    register8_t reserved_0x0B;
1021    _WORDREGISTER(CAL);  /* Calibration Value */
1022    register8_t reserved_0x0E;
1023    register8_t reserved_0x0F;
1024    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
1025    register8_t reserved_0x12;
1026    register8_t reserved_0x13;
1027    register8_t reserved_0x14;
1028    register8_t reserved_0x15;
1029    register8_t reserved_0x16;
1030    register8_t reserved_0x17;
1031    _WORDREGISTER(CMP);  /* Compare Value */
1032    register8_t reserved_0x1A;
1033    register8_t reserved_0x1B;
1034    register8_t reserved_0x1C;
1035    register8_t reserved_0x1D;
1036    register8_t reserved_0x1E;
1037    register8_t reserved_0x1F;
1038    ADC_CH_t CH0;  /* ADC Channel 0 */
1039} ADC_t;
1040
1041/* Current Limitation */
1042typedef enum ADC_CURRLIMIT_enum
1043{
1044    ADC_CURRLIMIT_NO_gc = (0x00<<5),  /* No current limit,     300ksps max sampling rate */
1045    ADC_CURRLIMIT_LOW_gc = (0x01<<5),  /* Low current limit,    225ksps max sampling rate */
1046    ADC_CURRLIMIT_MED_gc = (0x02<<5),  /* Medium current limit, 150ksps max sampling rate */
1047    ADC_CURRLIMIT_HIGH_gc = (0x03<<5),  /* High current limit,   75ksps max sampling rate */
1048} ADC_CURRLIMIT_t;
1049
1050/* Positive input multiplexer selection */
1051typedef enum ADC_CH_MUXPOS_enum
1052{
1053    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
1054    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
1055    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
1056    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
1057    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
1058    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
1059    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
1060    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
1061} ADC_CH_MUXPOS_t;
1062
1063/* Negative input multiplexer selection */
1064typedef enum ADC_CH_MUXNEG_enum
1065{
1066    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
1067    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
1068    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
1069    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
1070    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
1071    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
1072    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
1073    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
1074} ADC_CH_MUXNEG_t;
1075
1076/* Input mode */
1077typedef enum ADC_CH_INPUTMODE_enum
1078{
1079    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
1080    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
1081    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
1082    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
1083} ADC_CH_INPUTMODE_t;
1084
1085/* Gain factor */
1086typedef enum ADC_CH_GAIN_enum
1087{
1088    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
1089    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
1090    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
1091    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
1092    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
1093    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
1094    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
1095    ADC_CH_GAIN_DIV2_gc = (0x07<<2),  /* x/2 gain */           
1096} ADC_CH_GAIN_t;
1097
1098/* Conversion result resolution */
1099typedef enum ADC_RESOLUTION_enum
1100{
1101    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
1102    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
1103    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
1104} ADC_RESOLUTION_t;
1105
1106/* Voltage reference selection */
1107typedef enum ADC_REFSEL_enum
1108{
1109    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
1110    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC/1.6V */
1111    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
1112    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
1113} ADC_REFSEL_t;
1114
1115/* Event channel input selection */
1116typedef enum ADC_EVSEL_enum
1117{
1118    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
1119    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
1120    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
1121    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
1122    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
1123    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
1124    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
1125    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
1126} ADC_EVSEL_t;
1127
1128/* Event action selection */
1129typedef enum ADC_EVACT_enum
1130{
1131    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
1132    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
1133} ADC_EVACT_t;
1134
1135/* Interupt mode */
1136typedef enum ADC_CH_INTMODE_enum
1137{
1138    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
1139    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
1140    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
1141} ADC_CH_INTMODE_t;
1142
1143/* Interrupt level */
1144typedef enum ADC_CH_INTLVL_enum
1145{
1146    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
1147    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
1148    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
1149    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
1150} ADC_CH_INTLVL_t;
1151
1152/* Clock prescaler */
1153typedef enum ADC_PRESCALER_enum
1154{
1155    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
1156    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
1157    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
1158    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
1159    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
1160    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
1161    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
1162    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
1163} ADC_PRESCALER_t;
1164
1165
1166/*
1167--------------------------------------------------------------------------
1168RTC - Real-Time Clounter
1169--------------------------------------------------------------------------
1170*/
1171
1172/* Real-Time Counter */
1173typedef struct RTC_struct
1174{
1175    register8_t CTRL;  /* Control Register */
1176    register8_t STATUS;  /* Status Register */
1177    register8_t INTCTRL;  /* Interrupt Control Register */
1178    register8_t INTFLAGS;  /* Interrupt Flags */
1179    register8_t TEMP;  /* Temporary register */
1180    register8_t reserved_0x05;
1181    register8_t reserved_0x06;
1182    register8_t reserved_0x07;
1183    _WORDREGISTER(CNT);  /* Count Register */
1184    _WORDREGISTER(PER);  /* Period Register */
1185    _WORDREGISTER(COMP);  /* Compare Register */
1186} RTC_t;
1187
1188/* Prescaler Factor */
1189typedef enum RTC_PRESCALER_enum
1190{
1191    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
1192    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
1193    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
1194    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
1195    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
1196    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
1197    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
1198    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
1199} RTC_PRESCALER_t;
1200
1201/* Compare Interrupt level */
1202typedef enum RTC_COMPINTLVL_enum
1203{
1204    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1205    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1206    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1207    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
1208} RTC_COMPINTLVL_t;
1209
1210/* Overflow Interrupt level */
1211typedef enum RTC_OVFINTLVL_enum
1212{
1213    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1214    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1215    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1216    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
1217} RTC_OVFINTLVL_t;
1218
1219
1220/*
1221--------------------------------------------------------------------------
1222EBI - External Bus Interface
1223--------------------------------------------------------------------------
1224*/
1225
1226/* EBI Chip Select Module */
1227typedef struct EBI_CS_struct
1228{
1229    register8_t CTRLA;  /* Chip Select Control Register A */
1230    register8_t CTRLB;  /* Chip Select Control Register B */
1231    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
1232} EBI_CS_t;
1233
1234/*
1235--------------------------------------------------------------------------
1236EBI - External Bus Interface
1237--------------------------------------------------------------------------
1238*/
1239
1240/* External Bus Interface */
1241typedef struct EBI_struct
1242{
1243    register8_t CTRL;  /* Control */
1244    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
1245    register8_t reserved_0x02;
1246    register8_t reserved_0x03;
1247    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
1248    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
1249    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
1250    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
1251    register8_t reserved_0x0A;
1252    register8_t reserved_0x0B;
1253    register8_t reserved_0x0C;
1254    register8_t reserved_0x0D;
1255    register8_t reserved_0x0E;
1256    register8_t reserved_0x0F;
1257    EBI_CS_t CS0;  /* Chip Select 0 */
1258    EBI_CS_t CS1;  /* Chip Select 1 */
1259    EBI_CS_t CS2;  /* Chip Select 2 */
1260    EBI_CS_t CS3;  /* Chip Select 3 */
1261} EBI_t;
1262
1263/* Chip Select adress space */
1264typedef enum EBI_CS_ASIZE_enum
1265{
1266    EBI_CS_ASIZE_256B_gc = (0x00<<2),  /* 256 bytes */
1267    EBI_CS_ASIZE_512B_gc = (0x01<<2),  /* 512 bytes */
1268    EBI_CS_ASIZE_1KB_gc = (0x02<<2),  /* 1K bytes */
1269    EBI_CS_ASIZE_2KB_gc = (0x03<<2),  /* 2K bytes */
1270    EBI_CS_ASIZE_4KB_gc = (0x04<<2),  /* 4K bytes */
1271    EBI_CS_ASIZE_8KB_gc = (0x05<<2),  /* 8K bytes */
1272    EBI_CS_ASIZE_16KB_gc = (0x06<<2),  /* 16K bytes */
1273    EBI_CS_ASIZE_32KB_gc = (0x07<<2),  /* 32K bytes */
1274    EBI_CS_ASIZE_64KB_gc = (0x08<<2),  /* 64K bytes */
1275    EBI_CS_ASIZE_128KB_gc = (0x09<<2),  /* 128K bytes */
1276    EBI_CS_ASIZE_256KB_gc = (0x0A<<2),  /* 256K bytes */
1277    EBI_CS_ASIZE_512KB_gc = (0x0B<<2),  /* 512K bytes */
1278    EBI_CS_ASIZE_1MB_gc = (0x0C<<2),  /* 1M bytes */
1279    EBI_CS_ASIZE_2MB_gc = (0x0D<<2),  /* 2M bytes */
1280    EBI_CS_ASIZE_4MB_gc = (0x0E<<2),  /* 4M bytes */
1281    EBI_CS_ASIZE_8MB_gc = (0x0F<<2),  /* 8M bytes */
1282    EBI_CS_ASIZE_16M_gc = (0x10<<2),  /* 16M bytes */
1283} EBI_CS_ASIZE_t;
1284
1285/*  */
1286typedef enum EBI_CS_SRWS_enum
1287{
1288    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
1289    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
1290    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
1291    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
1292    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
1293    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
1294    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
1295    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
1296} EBI_CS_SRWS_t;
1297
1298/* Chip Select address mode */
1299typedef enum EBI_CS_MODE_enum
1300{
1301    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
1302    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
1303    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
1304    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
1305} EBI_CS_MODE_t;
1306
1307/* Chip Select SDRAM mode */
1308typedef enum EBI_CS_SDMODE_enum
1309{
1310    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
1311    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
1312} EBI_CS_SDMODE_t;
1313
1314/*  */
1315typedef enum EBI_SDDATAW_enum
1316{
1317    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
1318    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
1319} EBI_SDDATAW_t;
1320
1321/*  */
1322typedef enum EBI_LPCMODE_enum
1323{
1324    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
1325    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
1326} EBI_LPCMODE_t;
1327
1328/*  */
1329typedef enum EBI_SRMODE_enum
1330{
1331    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
1332    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
1333    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
1334    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
1335} EBI_SRMODE_t;
1336
1337/*  */
1338typedef enum EBI_IFMODE_enum
1339{
1340    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
1341    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
1342    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
1343    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
1344} EBI_IFMODE_t;
1345
1346/*  */
1347typedef enum EBI_SDCOL_enum
1348{
1349    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
1350    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
1351    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
1352    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
1353} EBI_SDCOL_t;
1354
1355/*  */
1356typedef enum EBI_MRDLY_enum
1357{
1358    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
1359    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
1360    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
1361    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
1362} EBI_MRDLY_t;
1363
1364/*  */
1365typedef enum EBI_ROWCYCDLY_enum
1366{
1367    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
1368    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
1369    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
1370    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
1371    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
1372    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
1373    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
1374    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
1375} EBI_ROWCYCDLY_t;
1376
1377/*  */
1378typedef enum EBI_RPDLY_enum
1379{
1380    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
1381    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
1382    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
1383    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
1384    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
1385    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
1386    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
1387    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
1388} EBI_RPDLY_t;
1389
1390/*  */
1391typedef enum EBI_WRDLY_enum
1392{
1393    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
1394    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
1395    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
1396    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
1397} EBI_WRDLY_t;
1398
1399/*  */
1400typedef enum EBI_ESRDLY_enum
1401{
1402    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
1403    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
1404    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
1405    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
1406    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
1407    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
1408    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
1409    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
1410} EBI_ESRDLY_t;
1411
1412/*  */
1413typedef enum EBI_ROWCOLDLY_enum
1414{
1415    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
1416    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
1417    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
1418    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
1419    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
1420    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
1421    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
1422    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
1423} EBI_ROWCOLDLY_t;
1424
1425
1426/*
1427--------------------------------------------------------------------------
1428TWI - Two-Wire Interface
1429--------------------------------------------------------------------------
1430*/
1431
1432/*  */
1433typedef struct TWI_MASTER_struct
1434{
1435    register8_t CTRLA;  /* Control Register A */
1436    register8_t CTRLB;  /* Control Register B */
1437    register8_t CTRLC;  /* Control Register C */
1438    register8_t STATUS;  /* Status Register */
1439    register8_t BAUD;  /* Baurd Rate Control Register */
1440    register8_t ADDR;  /* Address Register */
1441    register8_t DATA;  /* Data Register */
1442} TWI_MASTER_t;
1443
1444/*
1445--------------------------------------------------------------------------
1446TWI - Two-Wire Interface
1447--------------------------------------------------------------------------
1448*/
1449
1450/*  */
1451typedef struct TWI_SLAVE_struct
1452{
1453    register8_t CTRLA;  /* Control Register A */
1454    register8_t CTRLB;  /* Control Register B */
1455    register8_t STATUS;  /* Status Register */
1456    register8_t ADDR;  /* Address Register */
1457    register8_t DATA;  /* Data Register */
1458    register8_t ADDRMASK;  /* Address Mask Register */
1459} TWI_SLAVE_t;
1460
1461/*
1462--------------------------------------------------------------------------
1463TWI - Two-Wire Interface
1464--------------------------------------------------------------------------
1465*/
1466
1467/* Two-Wire Interface */
1468typedef struct TWI_struct
1469{
1470    register8_t CTRL;  /* TWI Common Control Register */
1471    TWI_MASTER_t MASTER;  /* TWI master module */
1472    TWI_SLAVE_t SLAVE;  /* TWI slave module */
1473} TWI_t;
1474
1475/* Master Interrupt Level */
1476typedef enum TWI_MASTER_INTLVL_enum
1477{
1478    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1479    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
1480    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1481    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
1482} TWI_MASTER_INTLVL_t;
1483
1484/* Inactive Timeout */
1485typedef enum TWI_MASTER_TIMEOUT_enum
1486{
1487    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
1488    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
1489    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
1490    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
1491} TWI_MASTER_TIMEOUT_t;
1492
1493/* Master Command */
1494typedef enum TWI_MASTER_CMD_enum
1495{
1496    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
1497    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
1498    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
1499    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
1500} TWI_MASTER_CMD_t;
1501
1502/* Master Bus State */
1503typedef enum TWI_MASTER_BUSSTATE_enum
1504{
1505    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
1506    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
1507    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
1508    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
1509} TWI_MASTER_BUSSTATE_t;
1510
1511/* Slave Interrupt Level */
1512typedef enum TWI_SLAVE_INTLVL_enum
1513{
1514    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1515    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
1516    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1517    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
1518} TWI_SLAVE_INTLVL_t;
1519
1520/* Slave Command */
1521typedef enum TWI_SLAVE_CMD_enum
1522{
1523    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
1524    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
1525    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
1526} TWI_SLAVE_CMD_t;
1527
1528
1529/*
1530--------------------------------------------------------------------------
1531PORT - Port Configuration
1532--------------------------------------------------------------------------
1533*/
1534
1535/* I/O port Configuration */
1536typedef struct PORTCFG_struct
1537{
1538    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
1539    register8_t reserved_0x01;
1540    register8_t VPCTRLA;  /* Virtual Port Control Register A */
1541    register8_t VPCTRLB;  /* Virtual Port Control Register B */
1542    register8_t CLKEVOUT;  /* Clock and Event Out Register */
1543} PORTCFG_t;
1544
1545/*
1546--------------------------------------------------------------------------
1547PORT - Port Configuration
1548--------------------------------------------------------------------------
1549*/
1550
1551/* Virtual Port */
1552typedef struct VPORT_struct
1553{
1554    register8_t DIR;  /* I/O Port Data Direction */
1555    register8_t OUT;  /* I/O Port Output */
1556    register8_t IN;  /* I/O Port Input */
1557    register8_t INTFLAGS;  /* Interrupt Flag Register */
1558} VPORT_t;
1559
1560/*
1561--------------------------------------------------------------------------
1562PORT - Port Configuration
1563--------------------------------------------------------------------------
1564*/
1565
1566/* I/O Ports */
1567typedef struct PORT_struct
1568{
1569    register8_t DIR;  /* I/O Port Data Direction */
1570    register8_t DIRSET;  /* I/O Port Data Direction Set */
1571    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
1572    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
1573    register8_t OUT;  /* I/O Port Output */
1574    register8_t OUTSET;  /* I/O Port Output Set */
1575    register8_t OUTCLR;  /* I/O Port Output Clear */
1576    register8_t OUTTGL;  /* I/O Port Output Toggle */
1577    register8_t IN;  /* I/O port Input */
1578    register8_t INTCTRL;  /* Interrupt Control Register */
1579    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
1580    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
1581    register8_t INTFLAGS;  /* Interrupt Flag Register */
1582    register8_t reserved_0x0D;
1583    register8_t reserved_0x0E;
1584    register8_t reserved_0x0F;
1585    register8_t PIN0CTRL;  /* Pin 0 Control Register */
1586    register8_t PIN1CTRL;  /* Pin 1 Control Register */
1587    register8_t PIN2CTRL;  /* Pin 2 Control Register */
1588    register8_t PIN3CTRL;  /* Pin 3 Control Register */
1589    register8_t PIN4CTRL;  /* Pin 4 Control Register */
1590    register8_t PIN5CTRL;  /* Pin 5 Control Register */
1591    register8_t PIN6CTRL;  /* Pin 6 Control Register */
1592    register8_t PIN7CTRL;  /* Pin 7 Control Register */
1593} PORT_t;
1594
1595/* Virtual Port 0 Mapping */
1596typedef enum PORTCFG_VP0MAP_enum
1597{
1598    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
1599    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
1600    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
1601    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
1602    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
1603    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
1604    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
1605    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
1606    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
1607    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
1608    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
1609    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
1610    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
1611    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
1612    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
1613    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
1614} PORTCFG_VP0MAP_t;
1615
1616/* Virtual Port 1 Mapping */
1617typedef enum PORTCFG_VP1MAP_enum
1618{
1619    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
1620    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
1621    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
1622    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
1623    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
1624    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
1625    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
1626    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
1627    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
1628    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
1629    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
1630    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
1631    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
1632    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
1633    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
1634    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
1635} PORTCFG_VP1MAP_t;
1636
1637/* Virtual Port 2 Mapping */
1638typedef enum PORTCFG_VP2MAP_enum
1639{
1640    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
1641    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
1642    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
1643    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
1644    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
1645    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
1646    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
1647    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
1648    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
1649    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
1650    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
1651    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
1652    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
1653    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
1654    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
1655    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
1656} PORTCFG_VP2MAP_t;
1657
1658/* Virtual Port 3 Mapping */
1659typedef enum PORTCFG_VP3MAP_enum
1660{
1661    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
1662    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
1663    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
1664    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
1665    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
1666    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
1667    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
1668    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
1669    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
1670    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
1671    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
1672    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
1673    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
1674    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
1675    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
1676    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
1677} PORTCFG_VP3MAP_t;
1678
1679/* Clock Output Port */
1680typedef enum PORTCFG_CLKOUT_enum
1681{
1682    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
1683    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
1684    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
1685    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
1686} PORTCFG_CLKOUT_t;
1687
1688/* Event Output Port */
1689typedef enum PORTCFG_EVOUT_enum
1690{
1691    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
1692    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
1693    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
1694    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
1695} PORTCFG_EVOUT_t;
1696
1697/* Port Interrupt 0 Level */
1698typedef enum PORT_INT0LVL_enum
1699{
1700    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1701    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
1702    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
1703    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
1704} PORT_INT0LVL_t;
1705
1706/* Port Interrupt 1 Level */
1707typedef enum PORT_INT1LVL_enum
1708{
1709    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1710    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
1711    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
1712    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
1713} PORT_INT1LVL_t;
1714
1715/* Output/Pull Configuration */
1716typedef enum PORT_OPC_enum
1717{
1718    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
1719    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
1720    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
1721    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
1722    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
1723    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
1724    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
1725    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
1726} PORT_OPC_t;
1727
1728/* Input/Sense Configuration */
1729typedef enum PORT_ISC_enum
1730{
1731    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
1732    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
1733    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
1734    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
1735    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
1736} PORT_ISC_t;
1737
1738
1739/*
1740--------------------------------------------------------------------------
1741TC - 16-bit Timer/Counter With PWM
1742--------------------------------------------------------------------------
1743*/
1744
1745/* 16-bit Timer/Counter 0 */
1746typedef struct TC0_struct
1747{
1748    register8_t CTRLA;  /* Control  Register A */
1749    register8_t CTRLB;  /* Control Register B */
1750    register8_t CTRLC;  /* Control register C */
1751    register8_t CTRLD;  /* Control Register D */
1752    register8_t CTRLE;  /* Control Register E */
1753    register8_t reserved_0x05;
1754    register8_t INTCTRLA;  /* Interrupt Control Register A */
1755    register8_t INTCTRLB;  /* Interrupt Control Register B */
1756    register8_t CTRLFCLR;  /* Control Register F Clear */
1757    register8_t CTRLFSET;  /* Control Register F Set */
1758    register8_t CTRLGCLR;  /* Control Register G Clear */
1759    register8_t CTRLGSET;  /* Control Register G Set */
1760    register8_t INTFLAGS;  /* Interrupt Flag Register */
1761    register8_t reserved_0x0D;
1762    register8_t reserved_0x0E;
1763    register8_t TEMP;  /* Temporary Register For 16-bit Access */
1764    register8_t reserved_0x10;
1765    register8_t reserved_0x11;
1766    register8_t reserved_0x12;
1767    register8_t reserved_0x13;
1768    register8_t reserved_0x14;
1769    register8_t reserved_0x15;
1770    register8_t reserved_0x16;
1771    register8_t reserved_0x17;
1772    register8_t reserved_0x18;
1773    register8_t reserved_0x19;
1774    register8_t reserved_0x1A;
1775    register8_t reserved_0x1B;
1776    register8_t reserved_0x1C;
1777    register8_t reserved_0x1D;
1778    register8_t reserved_0x1E;
1779    register8_t reserved_0x1F;
1780    _WORDREGISTER(CNT);  /* Count */
1781    register8_t reserved_0x22;
1782    register8_t reserved_0x23;
1783    register8_t reserved_0x24;
1784    register8_t reserved_0x25;
1785    _WORDREGISTER(PER);  /* Period */
1786    _WORDREGISTER(CCA);  /* Compare or Capture A */
1787    _WORDREGISTER(CCB);  /* Compare or Capture B */
1788    _WORDREGISTER(CCC);  /* Compare or Capture C */
1789    _WORDREGISTER(CCD);  /* Compare or Capture D */
1790    register8_t reserved_0x30;
1791    register8_t reserved_0x31;
1792    register8_t reserved_0x32;
1793    register8_t reserved_0x33;
1794    register8_t reserved_0x34;
1795    register8_t reserved_0x35;
1796    _WORDREGISTER(PERBUF);  /* Period Buffer */
1797    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
1798    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
1799    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
1800    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
1801} TC0_t;
1802
1803/*
1804--------------------------------------------------------------------------
1805TC - 16-bit Timer/Counter With PWM
1806--------------------------------------------------------------------------
1807*/
1808
1809/* 16-bit Timer/Counter 1 */
1810typedef struct TC1_struct
1811{
1812    register8_t CTRLA;  /* Control  Register A */
1813    register8_t CTRLB;  /* Control Register B */
1814    register8_t CTRLC;  /* Control register C */
1815    register8_t CTRLD;  /* Control Register D */
1816    register8_t CTRLE;  /* Control Register E */
1817    register8_t reserved_0x05;
1818    register8_t INTCTRLA;  /* Interrupt Control Register A */
1819    register8_t INTCTRLB;  /* Interrupt Control Register B */
1820    register8_t CTRLFCLR;  /* Control Register F Clear */
1821    register8_t CTRLFSET;  /* Control Register F Set */
1822    register8_t CTRLGCLR;  /* Control Register G Clear */
1823    register8_t CTRLGSET;  /* Control Register G Set */
1824    register8_t INTFLAGS;  /* Interrupt Flag Register */
1825    register8_t reserved_0x0D;
1826    register8_t reserved_0x0E;
1827    register8_t TEMP;  /* Temporary Register For 16-bit Access */
1828    register8_t reserved_0x10;
1829    register8_t reserved_0x11;
1830    register8_t reserved_0x12;
1831    register8_t reserved_0x13;
1832    register8_t reserved_0x14;
1833    register8_t reserved_0x15;
1834    register8_t reserved_0x16;
1835    register8_t reserved_0x17;
1836    register8_t reserved_0x18;
1837    register8_t reserved_0x19;
1838    register8_t reserved_0x1A;
1839    register8_t reserved_0x1B;
1840    register8_t reserved_0x1C;
1841    register8_t reserved_0x1D;
1842    register8_t reserved_0x1E;
1843    register8_t reserved_0x1F;
1844    _WORDREGISTER(CNT);  /* Count */
1845    register8_t reserved_0x22;
1846    register8_t reserved_0x23;
1847    register8_t reserved_0x24;
1848    register8_t reserved_0x25;
1849    _WORDREGISTER(PER);  /* Period */
1850    _WORDREGISTER(CCA);  /* Compare or Capture A */
1851    _WORDREGISTER(CCB);  /* Compare or Capture B */
1852    register8_t reserved_0x2C;
1853    register8_t reserved_0x2D;
1854    register8_t reserved_0x2E;
1855    register8_t reserved_0x2F;
1856    register8_t reserved_0x30;
1857    register8_t reserved_0x31;
1858    register8_t reserved_0x32;
1859    register8_t reserved_0x33;
1860    register8_t reserved_0x34;
1861    register8_t reserved_0x35;
1862    _WORDREGISTER(PERBUF);  /* Period Buffer */
1863    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
1864    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
1865} TC1_t;
1866
1867/*
1868--------------------------------------------------------------------------
1869TC - 16-bit Timer/Counter With PWM
1870--------------------------------------------------------------------------
1871*/
1872
1873/* Advanced Waveform Extension */
1874typedef struct AWEX_struct
1875{
1876    register8_t CTRL;  /* Control Register */
1877    register8_t reserved_0x01;
1878    register8_t FDEMASK;  /* Fault Detection Event Mask */
1879    register8_t FDCTRL;  /* Fault Detection Control Register */
1880    register8_t STATUS;  /* Status Register */
1881    register8_t reserved_0x05;
1882    register8_t DTBOTH;  /* Dead Time Both Sides */
1883    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
1884    register8_t DTLS;  /* Dead Time Low Side */
1885    register8_t DTHS;  /* Dead Time High Side */
1886    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
1887    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
1888    register8_t OUTOVEN;  /* Output Override Enable */
1889} AWEX_t;
1890
1891/*
1892--------------------------------------------------------------------------
1893TC - 16-bit Timer/Counter With PWM
1894--------------------------------------------------------------------------
1895*/
1896
1897/* High-Resolution Extension */
1898typedef struct HIRES_struct
1899{
1900    register8_t CTRLA;  /* Control Register */
1901} HIRES_t;
1902
1903/* Clock Selection */
1904typedef enum TC_CLKSEL_enum
1905{
1906    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
1907    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
1908    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
1909    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
1910    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
1911    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
1912    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
1913    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
1914    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
1915    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
1916    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
1917    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
1918    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
1919    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
1920    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
1921    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
1922} TC_CLKSEL_t;
1923
1924/* Waveform Generation Mode */
1925typedef enum TC_WGMODE_enum
1926{
1927    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
1928    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
1929    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
1930    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
1931    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
1932    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
1933} TC_WGMODE_t;
1934
1935/* Event Action */
1936typedef enum TC_EVACT_enum
1937{
1938    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
1939    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
1940    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
1941    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
1942    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
1943    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
1944    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
1945} TC_EVACT_t;
1946
1947/* Event Selection */
1948typedef enum TC_EVSEL_enum
1949{
1950    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
1951    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
1952    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
1953    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
1954    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
1955    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
1956    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
1957    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
1958    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
1959} TC_EVSEL_t;
1960
1961/* Error Interrupt Level */
1962typedef enum TC_ERRINTLVL_enum
1963{
1964    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1965    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1966    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1967    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
1968} TC_ERRINTLVL_t;
1969
1970/* Overflow Interrupt Level */
1971typedef enum TC_OVFINTLVL_enum
1972{
1973    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1974    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1975    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1976    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
1977} TC_OVFINTLVL_t;
1978
1979/* Compare or Capture D Interrupt Level */
1980typedef enum TC_CCDINTLVL_enum
1981{
1982    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1983    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
1984    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1985    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
1986} TC_CCDINTLVL_t;
1987
1988/* Compare or Capture C Interrupt Level */
1989typedef enum TC_CCCINTLVL_enum
1990{
1991    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
1992    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
1993    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
1994    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
1995} TC_CCCINTLVL_t;
1996
1997/* Compare or Capture B Interrupt Level */
1998typedef enum TC_CCBINTLVL_enum
1999{
2000    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
2001    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
2002    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
2003    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
2004} TC_CCBINTLVL_t;
2005
2006/* Compare or Capture A Interrupt Level */
2007typedef enum TC_CCAINTLVL_enum
2008{
2009    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2010    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
2011    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2012    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
2013} TC_CCAINTLVL_t;
2014
2015/* Timer/Counter Command */
2016typedef enum TC_CMD_enum
2017{
2018    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
2019    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
2020    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
2021    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
2022} TC_CMD_t;
2023
2024/* Fault Detect Action */
2025typedef enum AWEX_FDACT_enum
2026{
2027    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
2028    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
2029    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
2030} AWEX_FDACT_t;
2031
2032/* High Resolution Enable */
2033typedef enum HIRES_HREN_enum
2034{
2035    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
2036    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
2037    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
2038    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
2039} HIRES_HREN_t;
2040
2041
2042/*
2043--------------------------------------------------------------------------
2044USART - Universal Asynchronous Receiver-Transmitter
2045--------------------------------------------------------------------------
2046*/
2047
2048/* Universal Synchronous/Asynchronous Receiver/Transmitter */
2049typedef struct USART_struct
2050{
2051    register8_t DATA;  /* Data Register */
2052    register8_t STATUS;  /* Status Register */
2053    register8_t reserved_0x02;
2054    register8_t CTRLA;  /* Control Register A */
2055    register8_t CTRLB;  /* Control Register B */
2056    register8_t CTRLC;  /* Control Register C */
2057    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
2058    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
2059} USART_t;
2060
2061/* Receive Complete Interrupt level */
2062typedef enum USART_RXCINTLVL_enum
2063{
2064    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
2065    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
2066    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
2067    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
2068} USART_RXCINTLVL_t;
2069
2070/* Transmit Complete Interrupt level */
2071typedef enum USART_TXCINTLVL_enum
2072{
2073    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
2074    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
2075    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
2076    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
2077} USART_TXCINTLVL_t;
2078
2079/* Data Register Empty Interrupt level */
2080typedef enum USART_DREINTLVL_enum
2081{
2082    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2083    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
2084    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2085    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
2086} USART_DREINTLVL_t;
2087
2088/* Character Size */
2089typedef enum USART_CHSIZE_enum
2090{
2091    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
2092    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
2093    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
2094    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
2095    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
2096} USART_CHSIZE_t;
2097
2098/* Communication Mode */
2099typedef enum USART_CMODE_enum
2100{
2101    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
2102    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
2103    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
2104    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
2105} USART_CMODE_t;
2106
2107/* Parity Mode */
2108typedef enum USART_PMODE_enum
2109{
2110    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
2111    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
2112    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
2113} USART_PMODE_t;
2114
2115
2116/*
2117--------------------------------------------------------------------------
2118SPI - Serial Peripheral Interface
2119--------------------------------------------------------------------------
2120*/
2121
2122/* Serial Peripheral Interface */
2123typedef struct SPI_struct
2124{
2125    register8_t CTRL;  /* Control Register */
2126    register8_t INTCTRL;  /* Interrupt Control Register */
2127    register8_t STATUS;  /* Status Register */
2128    register8_t DATA;  /* Data Register */
2129} SPI_t;
2130
2131/* SPI Mode */
2132typedef enum SPI_MODE_enum
2133{
2134    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
2135    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
2136    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
2137    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
2138} SPI_MODE_t;
2139
2140/* Prescaler setting */
2141typedef enum SPI_PRESCALER_enum
2142{
2143    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
2144    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
2145    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
2146    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
2147} SPI_PRESCALER_t;
2148
2149/* Interrupt level */
2150typedef enum SPI_INTLVL_enum
2151{
2152    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2153    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
2154    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2155    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
2156} SPI_INTLVL_t;
2157
2158
2159/*
2160--------------------------------------------------------------------------
2161IRCOM - IR Communication Module
2162--------------------------------------------------------------------------
2163*/
2164
2165/* IR Communication Module */
2166typedef struct IRCOM_struct
2167{
2168    register8_t CTRL;  /* Control Register */
2169    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
2170    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
2171} IRCOM_t;
2172
2173/* Event channel selection */
2174typedef enum IRDA_EVSEL_enum
2175{
2176    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
2177    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
2178    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
2179    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
2180    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
2181    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
2182    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
2183    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
2184    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
2185} IRDA_EVSEL_t;
2186
2187
2188
2189/*
2190==========================================================================
2191IO Module Instances. Mapped to memory.
2192==========================================================================
2193*/
2194
2195#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
2196#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
2197#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
2198#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
2199#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
2200#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
2201#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
2202#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
2203#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
2204#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
2205#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
2206#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
2207#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
2208#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
2209#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
2210#define CRC    (*(CRC_t *) 0x00D0)  /* Cyclic Redundancy Checker */
2211#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
2212#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
2213#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
2214#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
2215#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
2216#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
2217#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
2218#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
2219#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
2220#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
2221#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
2222#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
2223#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
2224#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
2225#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
2226#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
2227#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
2228#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
2229#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
2230#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
2231#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
2232#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
2233#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
2234#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
2235#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
2236#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
2237#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
2238#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
2239#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
2240
2241
2242#endif /* !defined (__ASSEMBLER__) */
2243
2244
2245/* ========== Flattened fully qualified IO register names ========== */
2246
2247/* GPIO - General Purpose IO Registers */
2248#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
2249#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
2250#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
2251#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
2252#define GPIO_GPIOR4  _SFR_MEM8(0x0004)
2253#define GPIO_GPIOR5  _SFR_MEM8(0x0005)
2254#define GPIO_GPIOR6  _SFR_MEM8(0x0006)
2255#define GPIO_GPIOR7  _SFR_MEM8(0x0007)
2256#define GPIO_GPIOR8  _SFR_MEM8(0x0008)
2257#define GPIO_GPIOR9  _SFR_MEM8(0x0009)
2258#define GPIO_GPIORA  _SFR_MEM8(0x000A)
2259#define GPIO_GPIORB  _SFR_MEM8(0x000B)
2260#define GPIO_GPIORC  _SFR_MEM8(0x000C)
2261#define GPIO_GPIORD  _SFR_MEM8(0x000D)
2262#define GPIO_GPIORE  _SFR_MEM8(0x000E)
2263#define GPIO_GPIORF  _SFR_MEM8(0x000F)
2264
2265/* VPORT0 - Virtual Port 0 */
2266#define VPORT0_DIR  _SFR_MEM8(0x0010)
2267#define VPORT0_OUT  _SFR_MEM8(0x0011)
2268#define VPORT0_IN  _SFR_MEM8(0x0012)
2269#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
2270
2271/* VPORT1 - Virtual Port 1 */
2272#define VPORT1_DIR  _SFR_MEM8(0x0014)
2273#define VPORT1_OUT  _SFR_MEM8(0x0015)
2274#define VPORT1_IN  _SFR_MEM8(0x0016)
2275#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
2276
2277/* VPORT2 - Virtual Port 2 */
2278#define VPORT2_DIR  _SFR_MEM8(0x0018)
2279#define VPORT2_OUT  _SFR_MEM8(0x0019)
2280#define VPORT2_IN  _SFR_MEM8(0x001A)
2281#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
2282
2283/* VPORT3 - Virtual Port 3 */
2284#define VPORT3_DIR  _SFR_MEM8(0x001C)
2285#define VPORT3_OUT  _SFR_MEM8(0x001D)
2286#define VPORT3_IN  _SFR_MEM8(0x001E)
2287#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
2288
2289/* OCD - On-Chip Debug System */
2290#define OCD_OCDR0  _SFR_MEM8(0x002E)
2291#define OCD_OCDR1  _SFR_MEM8(0x002F)
2292
2293/* CPU - CPU Registers */
2294#define CPU_CCP  _SFR_MEM8(0x0034)
2295#define CPU_RAMPD  _SFR_MEM8(0x0038)
2296#define CPU_RAMPX  _SFR_MEM8(0x0039)
2297#define CPU_RAMPY  _SFR_MEM8(0x003A)
2298#define CPU_RAMPZ  _SFR_MEM8(0x003B)
2299#define CPU_EIND  _SFR_MEM8(0x003C)
2300#define CPU_SPL  _SFR_MEM8(0x003D)
2301#define CPU_SPH  _SFR_MEM8(0x003E)
2302#define CPU_SREG  _SFR_MEM8(0x003F)
2303
2304/* CLK - Clock System */
2305#define CLK_CTRL  _SFR_MEM8(0x0040)
2306#define CLK_PSCTRL  _SFR_MEM8(0x0041)
2307#define CLK_LOCK  _SFR_MEM8(0x0042)
2308#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
2309
2310/* SLEEP - Sleep Controller */
2311#define SLEEP_CTRL  _SFR_MEM8(0x0048)
2312
2313/* OSC - Oscillator Control */
2314#define OSC_CTRL  _SFR_MEM8(0x0050)
2315#define OSC_STATUS  _SFR_MEM8(0x0051)
2316#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
2317#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
2318#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
2319#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
2320#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
2321
2322/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
2323#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
2324#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
2325#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
2326#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
2327#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
2328#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
2329
2330/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
2331#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
2332#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
2333#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
2334#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
2335#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
2336#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
2337
2338/* PR - Power Reduction */
2339#define PR_PRGEN  _SFR_MEM8(0x0070)
2340#define PR_PRPA  _SFR_MEM8(0x0071)
2341#define PR_PRPC  _SFR_MEM8(0x0073)
2342#define PR_PRPD  _SFR_MEM8(0x0074)
2343#define PR_PRPE  _SFR_MEM8(0x0075)
2344#define PR_PRPF  _SFR_MEM8(0x0076)
2345
2346/* RST - Reset Controller */
2347#define RST_STATUS  _SFR_MEM8(0x0078)
2348#define RST_CTRL  _SFR_MEM8(0x0079)
2349
2350/* WDT - Watch-Dog Timer */
2351#define WDT_CTRL  _SFR_MEM8(0x0080)
2352#define WDT_WINCTRL  _SFR_MEM8(0x0081)
2353#define WDT_STATUS  _SFR_MEM8(0x0082)
2354
2355/* MCU - MCU Control */
2356#define MCU_DEVID0  _SFR_MEM8(0x0090)
2357#define MCU_DEVID1  _SFR_MEM8(0x0091)
2358#define MCU_DEVID2  _SFR_MEM8(0x0092)
2359#define MCU_REVID  _SFR_MEM8(0x0093)
2360#define MCU_JTAGUID  _SFR_MEM8(0x0094)
2361#define MCU_MCUCR  _SFR_MEM8(0x0096)
2362#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
2363#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
2364
2365/* PMIC - Programmable Interrupt Controller */
2366#define PMIC_STATUS  _SFR_MEM8(0x00A0)
2367#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
2368#define PMIC_CTRL  _SFR_MEM8(0x00A2)
2369
2370/* PORTCFG - Port Configuration */
2371#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
2372#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
2373#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
2374#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
2375
2376/* CRC - Cyclic Redundancy Checker */
2377#define CRC_CTRL  _SFR_MEM8(0x00D0)
2378#define CRC_STATUS  _SFR_MEM8(0x00D1)
2379#define CRC_DATAIN  _SFR_MEM8(0x00D3)
2380#define CRC_CHECKSUM0  _SFR_MEM8(0x00D4)
2381#define CRC_CHECKSUM1  _SFR_MEM8(0x00D5)
2382#define CRC_CHECKSUM2  _SFR_MEM8(0x00D6)
2383#define CRC_CHECKSUM3  _SFR_MEM8(0x00D7)
2384
2385/* EVSYS - Event System */
2386#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
2387#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
2388#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
2389#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
2390#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
2391#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
2392#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
2393#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
2394#define EVSYS_STROBE  _SFR_MEM8(0x0190)
2395#define EVSYS_DATA  _SFR_MEM8(0x0191)
2396
2397/* NVM - Non Volatile Memory Controller */
2398#define NVM_ADDR0  _SFR_MEM8(0x01C0)
2399#define NVM_ADDR1  _SFR_MEM8(0x01C1)
2400#define NVM_ADDR2  _SFR_MEM8(0x01C2)
2401#define NVM_DATA0  _SFR_MEM8(0x01C4)
2402#define NVM_DATA1  _SFR_MEM8(0x01C5)
2403#define NVM_DATA2  _SFR_MEM8(0x01C6)
2404#define NVM_CMD  _SFR_MEM8(0x01CA)
2405#define NVM_CTRLA  _SFR_MEM8(0x01CB)
2406#define NVM_CTRLB  _SFR_MEM8(0x01CC)
2407#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
2408#define NVM_STATUS  _SFR_MEM8(0x01CF)
2409#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
2410
2411/* ADCA - Analog to Digital Converter A */
2412#define ADCA_CTRLA  _SFR_MEM8(0x0200)
2413#define ADCA_CTRLB  _SFR_MEM8(0x0201)
2414#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
2415#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
2416#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
2417#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
2418#define ADCA_TEMP  _SFR_MEM8(0x0207)
2419#define ADCA_CAL  _SFR_MEM16(0x020C)
2420#define ADCA_CH0RES  _SFR_MEM16(0x0210)
2421#define ADCA_CMP  _SFR_MEM16(0x0218)
2422#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
2423#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
2424#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
2425#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
2426#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
2427
2428/* ACA - Analog Comparator A */
2429#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
2430#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
2431#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
2432#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
2433#define ACA_CTRLA  _SFR_MEM8(0x0384)
2434#define ACA_CTRLB  _SFR_MEM8(0x0385)
2435#define ACA_WINCTRL  _SFR_MEM8(0x0386)
2436#define ACA_STATUS  _SFR_MEM8(0x0387)
2437
2438/* RTC - Real-Time Counter */
2439#define RTC_CTRL  _SFR_MEM8(0x0400)
2440#define RTC_STATUS  _SFR_MEM8(0x0401)
2441#define RTC_INTCTRL  _SFR_MEM8(0x0402)
2442#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
2443#define RTC_TEMP  _SFR_MEM8(0x0404)
2444#define RTC_CNT  _SFR_MEM16(0x0408)
2445#define RTC_PER  _SFR_MEM16(0x040A)
2446#define RTC_COMP  _SFR_MEM16(0x040C)
2447
2448/* TWIC - Two-Wire Interface C */
2449#define TWIC_CTRL  _SFR_MEM8(0x0480)
2450#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
2451#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
2452#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
2453#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
2454#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
2455#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
2456#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
2457#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
2458#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
2459#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
2460#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
2461#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
2462#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
2463
2464/* TWIE - Two-Wire Interface E */
2465#define TWIE_CTRL  _SFR_MEM8(0x04A0)
2466#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
2467#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
2468#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
2469#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
2470#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
2471#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
2472#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
2473#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
2474#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
2475#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
2476#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
2477#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
2478#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
2479
2480/* PORTA - Port A */
2481#define PORTA_DIR  _SFR_MEM8(0x0600)
2482#define PORTA_DIRSET  _SFR_MEM8(0x0601)
2483#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
2484#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
2485#define PORTA_OUT  _SFR_MEM8(0x0604)
2486#define PORTA_OUTSET  _SFR_MEM8(0x0605)
2487#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
2488#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
2489#define PORTA_IN  _SFR_MEM8(0x0608)
2490#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
2491#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
2492#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
2493#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
2494#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
2495#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
2496#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
2497#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
2498#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
2499#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
2500#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
2501#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
2502
2503/* PORTB - Port B */
2504#define PORTB_DIR  _SFR_MEM8(0x0620)
2505#define PORTB_DIRSET  _SFR_MEM8(0x0621)
2506#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
2507#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
2508#define PORTB_OUT  _SFR_MEM8(0x0624)
2509#define PORTB_OUTSET  _SFR_MEM8(0x0625)
2510#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
2511#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
2512#define PORTB_IN  _SFR_MEM8(0x0628)
2513#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
2514#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
2515#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
2516#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
2517#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
2518#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
2519#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
2520#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
2521#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
2522#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
2523#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
2524#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
2525
2526/* PORTC - Port C */
2527#define PORTC_DIR  _SFR_MEM8(0x0640)
2528#define PORTC_DIRSET  _SFR_MEM8(0x0641)
2529#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
2530#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
2531#define PORTC_OUT  _SFR_MEM8(0x0644)
2532#define PORTC_OUTSET  _SFR_MEM8(0x0645)
2533#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
2534#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
2535#define PORTC_IN  _SFR_MEM8(0x0648)
2536#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
2537#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
2538#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
2539#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
2540#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
2541#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
2542#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
2543#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
2544#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
2545#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
2546#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
2547#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
2548
2549/* PORTD - Port D */
2550#define PORTD_DIR  _SFR_MEM8(0x0660)
2551#define PORTD_DIRSET  _SFR_MEM8(0x0661)
2552#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
2553#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
2554#define PORTD_OUT  _SFR_MEM8(0x0664)
2555#define PORTD_OUTSET  _SFR_MEM8(0x0665)
2556#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
2557#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
2558#define PORTD_IN  _SFR_MEM8(0x0668)
2559#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
2560#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
2561#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
2562#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
2563#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
2564#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
2565#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
2566#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
2567#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
2568#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
2569#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
2570#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
2571
2572/* PORTE - Port E */
2573#define PORTE_DIR  _SFR_MEM8(0x0680)
2574#define PORTE_DIRSET  _SFR_MEM8(0x0681)
2575#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
2576#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
2577#define PORTE_OUT  _SFR_MEM8(0x0684)
2578#define PORTE_OUTSET  _SFR_MEM8(0x0685)
2579#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
2580#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
2581#define PORTE_IN  _SFR_MEM8(0x0688)
2582#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
2583#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
2584#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
2585#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
2586#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
2587#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
2588#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
2589#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
2590#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
2591#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
2592#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
2593#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
2594
2595/* PORTF - Port F */
2596#define PORTF_DIR  _SFR_MEM8(0x06A0)
2597#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
2598#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
2599#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
2600#define PORTF_OUT  _SFR_MEM8(0x06A4)
2601#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
2602#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
2603#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
2604#define PORTF_IN  _SFR_MEM8(0x06A8)
2605#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
2606#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
2607#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
2608#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
2609#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
2610#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
2611#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
2612#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
2613#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
2614#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
2615#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
2616#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
2617
2618/* PORTR - Port R */
2619#define PORTR_DIR  _SFR_MEM8(0x07E0)
2620#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
2621#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
2622#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
2623#define PORTR_OUT  _SFR_MEM8(0x07E4)
2624#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
2625#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
2626#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
2627#define PORTR_IN  _SFR_MEM8(0x07E8)
2628#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
2629#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
2630#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
2631#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
2632#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
2633#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
2634#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
2635#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
2636#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
2637#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
2638#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
2639#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
2640
2641/* TCC0 - Timer/Counter C0 */
2642#define TCC0_CTRLA  _SFR_MEM8(0x0800)
2643#define TCC0_CTRLB  _SFR_MEM8(0x0801)
2644#define TCC0_CTRLC  _SFR_MEM8(0x0802)
2645#define TCC0_CTRLD  _SFR_MEM8(0x0803)
2646#define TCC0_CTRLE  _SFR_MEM8(0x0804)
2647#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
2648#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
2649#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
2650#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
2651#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
2652#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
2653#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
2654#define TCC0_TEMP  _SFR_MEM8(0x080F)
2655#define TCC0_CNT  _SFR_MEM16(0x0820)
2656#define TCC0_PER  _SFR_MEM16(0x0826)
2657#define TCC0_CCA  _SFR_MEM16(0x0828)
2658#define TCC0_CCB  _SFR_MEM16(0x082A)
2659#define TCC0_CCC  _SFR_MEM16(0x082C)
2660#define TCC0_CCD  _SFR_MEM16(0x082E)
2661#define TCC0_PERBUF  _SFR_MEM16(0x0836)
2662#define TCC0_CCABUF  _SFR_MEM16(0x0838)
2663#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
2664#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
2665#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
2666
2667/* TCC1 - Timer/Counter C1 */
2668#define TCC1_CTRLA  _SFR_MEM8(0x0840)
2669#define TCC1_CTRLB  _SFR_MEM8(0x0841)
2670#define TCC1_CTRLC  _SFR_MEM8(0x0842)
2671#define TCC1_CTRLD  _SFR_MEM8(0x0843)
2672#define TCC1_CTRLE  _SFR_MEM8(0x0844)
2673#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
2674#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
2675#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
2676#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
2677#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
2678#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
2679#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
2680#define TCC1_TEMP  _SFR_MEM8(0x084F)
2681#define TCC1_CNT  _SFR_MEM16(0x0860)
2682#define TCC1_PER  _SFR_MEM16(0x0866)
2683#define TCC1_CCA  _SFR_MEM16(0x0868)
2684#define TCC1_CCB  _SFR_MEM16(0x086A)
2685#define TCC1_PERBUF  _SFR_MEM16(0x0876)
2686#define TCC1_CCABUF  _SFR_MEM16(0x0878)
2687#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
2688
2689/* AWEXC - Advanced Waveform Extension C */
2690#define AWEXC_CTRL  _SFR_MEM8(0x0880)
2691#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
2692#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
2693#define AWEXC_STATUS  _SFR_MEM8(0x0884)
2694#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
2695#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
2696#define AWEXC_DTLS  _SFR_MEM8(0x0888)
2697#define AWEXC_DTHS  _SFR_MEM8(0x0889)
2698#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
2699#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
2700#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
2701
2702/* HIRESC - High-Resolution Extension C */
2703#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
2704
2705/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
2706#define USARTC0_DATA  _SFR_MEM8(0x08A0)
2707#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
2708#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
2709#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
2710#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
2711#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
2712#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
2713
2714/* SPIC - Serial Peripheral Interface C */
2715#define SPIC_CTRL  _SFR_MEM8(0x08C0)
2716#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
2717#define SPIC_STATUS  _SFR_MEM8(0x08C2)
2718#define SPIC_DATA  _SFR_MEM8(0x08C3)
2719
2720/* IRCOM - IR Communication Module */
2721#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
2722#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
2723#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
2724
2725/* TCD0 - Timer/Counter D0 */
2726#define TCD0_CTRLA  _SFR_MEM8(0x0900)
2727#define TCD0_CTRLB  _SFR_MEM8(0x0901)
2728#define TCD0_CTRLC  _SFR_MEM8(0x0902)
2729#define TCD0_CTRLD  _SFR_MEM8(0x0903)
2730#define TCD0_CTRLE  _SFR_MEM8(0x0904)
2731#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
2732#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
2733#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
2734#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
2735#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
2736#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
2737#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
2738#define TCD0_TEMP  _SFR_MEM8(0x090F)
2739#define TCD0_CNT  _SFR_MEM16(0x0920)
2740#define TCD0_PER  _SFR_MEM16(0x0926)
2741#define TCD0_CCA  _SFR_MEM16(0x0928)
2742#define TCD0_CCB  _SFR_MEM16(0x092A)
2743#define TCD0_CCC  _SFR_MEM16(0x092C)
2744#define TCD0_CCD  _SFR_MEM16(0x092E)
2745#define TCD0_PERBUF  _SFR_MEM16(0x0936)
2746#define TCD0_CCABUF  _SFR_MEM16(0x0938)
2747#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
2748#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
2749#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
2750
2751/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
2752#define USARTD0_DATA  _SFR_MEM8(0x09A0)
2753#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
2754#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
2755#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
2756#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
2757#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
2758#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
2759
2760/* SPID - Serial Peripheral Interface D */
2761#define SPID_CTRL  _SFR_MEM8(0x09C0)
2762#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
2763#define SPID_STATUS  _SFR_MEM8(0x09C2)
2764#define SPID_DATA  _SFR_MEM8(0x09C3)
2765
2766/* TCE0 - Timer/Counter E0 */
2767#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
2768#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
2769#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
2770#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
2771#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
2772#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
2773#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
2774#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
2775#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
2776#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
2777#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
2778#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
2779#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
2780#define TCE0_CNT  _SFR_MEM16(0x0A20)
2781#define TCE0_PER  _SFR_MEM16(0x0A26)
2782#define TCE0_CCA  _SFR_MEM16(0x0A28)
2783#define TCE0_CCB  _SFR_MEM16(0x0A2A)
2784#define TCE0_CCC  _SFR_MEM16(0x0A2C)
2785#define TCE0_CCD  _SFR_MEM16(0x0A2E)
2786#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
2787#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
2788#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
2789#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
2790#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
2791
2792/* AWEXE - Advanced Waveform Extension E */
2793#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
2794#define AWEXE_FDEMASK  _SFR_MEM8(0x0A82)
2795#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
2796#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
2797#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
2798#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
2799#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
2800#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
2801#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
2802#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
2803#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
2804
2805/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
2806#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
2807#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
2808#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
2809#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
2810#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
2811#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
2812#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
2813
2814/* SPIE - Serial Peripheral Interface E */
2815#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
2816#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
2817#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
2818#define SPIE_DATA  _SFR_MEM8(0x0AC3)
2819
2820/* TCF0 - Timer/Counter F0 */
2821#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
2822#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
2823#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
2824#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
2825#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
2826#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
2827#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
2828#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
2829#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
2830#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
2831#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
2832#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
2833#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
2834#define TCF0_CNT  _SFR_MEM16(0x0B20)
2835#define TCF0_PER  _SFR_MEM16(0x0B26)
2836#define TCF0_CCA  _SFR_MEM16(0x0B28)
2837#define TCF0_CCB  _SFR_MEM16(0x0B2A)
2838#define TCF0_CCC  _SFR_MEM16(0x0B2C)
2839#define TCF0_CCD  _SFR_MEM16(0x0B2E)
2840#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
2841#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
2842#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
2843#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
2844#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
2845
2846
2847
2848/*================== Bitfield Definitions ================== */
2849
2850/* XOCD - On-Chip Debug System */
2851/* OCD.OCDR1  bit masks and bit positions */
2852#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
2853#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
2854
2855
2856/* CPU - CPU */
2857/* CPU.CCP  bit masks and bit positions */
2858#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
2859#define CPU_CCP_gp  0  /* CCP signature group position. */
2860#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
2861#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
2862#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
2863#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
2864#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
2865#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
2866#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
2867#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
2868#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
2869#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
2870#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
2871#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
2872#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
2873#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
2874#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
2875#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
2876
2877
2878/* CPU.SREG  bit masks and bit positions */
2879#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
2880#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
2881
2882#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
2883#define CPU_T_bp  6  /* Transfer Bit bit position. */
2884
2885#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
2886#define CPU_H_bp  5  /* Half Carry Flag bit position. */
2887
2888#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
2889#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
2890
2891#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
2892#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
2893
2894#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
2895#define CPU_N_bp  2  /* Negative Flag bit position. */
2896
2897#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
2898#define CPU_Z_bp  1  /* Zero Flag bit position. */
2899
2900#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
2901#define CPU_C_bp  0  /* Carry Flag bit position. */
2902
2903
2904/* CLK - Clock System */
2905/* CLK.CTRL  bit masks and bit positions */
2906#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
2907#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
2908#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
2909#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
2910#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
2911#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
2912#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
2913#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
2914
2915
2916/* CLK.PSCTRL  bit masks and bit positions */
2917#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
2918#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
2919#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
2920#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
2921#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
2922#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
2923#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
2924#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
2925#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
2926#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
2927#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
2928#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
2929
2930#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
2931#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
2932#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
2933#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
2934#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
2935#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
2936
2937
2938/* CLK.LOCK  bit masks and bit positions */
2939#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
2940#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
2941
2942
2943/* CLK.RTCCTRL  bit masks and bit positions */
2944#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
2945#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
2946#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
2947#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
2948#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
2949#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
2950#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
2951#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
2952
2953#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
2954#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
2955
2956/* PR.PRGEN  bit masks and bit positions */
2957#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
2958#define PR_RTC_bp  2  /* Real-time Counter bit position. */
2959
2960#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
2961#define PR_EVSYS_bp  1  /* Event System bit position. */
2962
2963/* PR.PRPA  bit masks and bit positions */
2964#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
2965#define PR_ADC_bp  1  /* Port A ADC bit position. */
2966
2967#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
2968#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
2969
2970/* PR.PRPC  bit masks and bit positions */
2971#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
2972#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
2973
2974#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
2975#define PR_USART0_bp  4  /* Port C USART0 bit position. */
2976
2977#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
2978#define PR_SPI_bp  3  /* Port C SPI bit position. */
2979
2980#define PR_HIRES_bm  0x04  /* Port C HIRES bit mask. */
2981#define PR_HIRES_bp  2  /* Port C HIRES bit position. */
2982
2983#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
2984#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
2985
2986#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
2987#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
2988
2989/* PR.PRPD  bit masks and bit positions */
2990/* PR_USART0  Predefined. */
2991/* PR_USART0  Predefined. */
2992
2993/* PR_SPI  Predefined. */
2994/* PR_SPI  Predefined. */
2995
2996/* PR_TC0  Predefined. */
2997/* PR_TC0  Predefined. */
2998
2999/* PR.PRPE  bit masks and bit positions */
3000/* PR_TWI  Predefined. */
3001/* PR_TWI  Predefined. */
3002
3003/* PR_USART0  Predefined. */
3004/* PR_USART0  Predefined. */
3005
3006/* PR_TC0  Predefined. */
3007/* PR_TC0  Predefined. */
3008
3009/* PR.PRPF  bit masks and bit positions */
3010/* PR_USART0  Predefined. */
3011/* PR_USART0  Predefined. */
3012
3013/* PR_TC0  Predefined. */
3014/* PR_TC0  Predefined. */
3015
3016/* SLEEP - Sleep Controller */
3017/* SLEEP.CTRL  bit masks and bit positions */
3018#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
3019#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
3020#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
3021#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
3022#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
3023#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
3024#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
3025#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
3026
3027#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
3028#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
3029
3030
3031/* OSC - Oscillator */
3032/* OSC.CTRL  bit masks and bit positions */
3033#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
3034#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
3035
3036#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
3037#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
3038
3039#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
3040#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
3041
3042#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
3043#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
3044
3045#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
3046#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
3047
3048
3049/* OSC.STATUS  bit masks and bit positions */
3050#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
3051#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
3052
3053#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
3054#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
3055
3056#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
3057#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
3058
3059#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
3060#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
3061
3062#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
3063#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
3064
3065
3066/* OSC.XOSCCTRL  bit masks and bit positions */
3067#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
3068#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
3069#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
3070#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
3071#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
3072#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
3073
3074#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
3075#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
3076
3077#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
3078#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
3079#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
3080#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
3081#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
3082#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
3083#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
3084#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
3085#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
3086#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
3087
3088
3089/* OSC.XOSCFAIL  bit masks and bit positions */
3090#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
3091#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
3092
3093#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
3094#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
3095
3096
3097/* OSC.PLLCTRL  bit masks and bit positions */
3098#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
3099#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
3100#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
3101#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
3102#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
3103#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
3104
3105#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
3106#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
3107#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
3108#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
3109#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
3110#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
3111#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
3112#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
3113#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
3114#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
3115#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
3116#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
3117
3118
3119/* OSC.DFLLCTRL  bit masks and bit positions */
3120#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
3121#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
3122
3123#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
3124#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
3125
3126
3127/* DFLL - DFLL */
3128/* DFLL.CTRL  bit masks and bit positions */
3129#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
3130#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
3131
3132
3133/* DFLL.CALA  bit masks and bit positions */
3134#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
3135#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
3136#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
3137#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
3138#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
3139#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
3140#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
3141#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
3142#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
3143#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
3144#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
3145#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
3146#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
3147#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
3148#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
3149#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
3150
3151
3152/* DFLL.CALB  bit masks and bit positions */
3153#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
3154#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
3155#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
3156#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
3157#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
3158#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
3159#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
3160#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
3161#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
3162#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
3163#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
3164#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
3165#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
3166#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
3167
3168
3169/* RST - Reset */
3170/* RST.STATUS  bit masks and bit positions */
3171#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
3172#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
3173
3174#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
3175#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
3176
3177#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
3178#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
3179
3180#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
3181#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
3182
3183#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
3184#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
3185
3186#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
3187#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
3188
3189#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
3190#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
3191
3192
3193/* RST.CTRL  bit masks and bit positions */
3194#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
3195#define RST_SWRST_bp  0  /* Software Reset bit position. */
3196
3197
3198/* WDT - Watch-Dog Timer */
3199/* WDT.CTRL  bit masks and bit positions */
3200#define WDT_PER_gm  0x3C  /* Period group mask. */
3201#define WDT_PER_gp  2  /* Period group position. */
3202#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
3203#define WDT_PER0_bp  2  /* Period bit 0 position. */
3204#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
3205#define WDT_PER1_bp  3  /* Period bit 1 position. */
3206#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
3207#define WDT_PER2_bp  4  /* Period bit 2 position. */
3208#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
3209#define WDT_PER3_bp  5  /* Period bit 3 position. */
3210
3211#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
3212#define WDT_ENABLE_bp  1  /* Enable bit position. */
3213
3214#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
3215#define WDT_CEN_bp  0  /* Change Enable bit position. */
3216
3217
3218/* WDT.WINCTRL  bit masks and bit positions */
3219#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
3220#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
3221#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
3222#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
3223#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
3224#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
3225#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
3226#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
3227#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
3228#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
3229
3230#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
3231#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
3232
3233#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
3234#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
3235
3236
3237/* WDT.STATUS  bit masks and bit positions */
3238#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
3239#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
3240
3241
3242/* MCU - MCU Control */
3243/* MCU.MCUCR  bit masks and bit positions */
3244#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
3245#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
3246
3247
3248/* MCU.EVSYSLOCK  bit masks and bit positions */
3249#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
3250#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
3251
3252#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
3253#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
3254
3255
3256/* MCU.AWEXLOCK  bit masks and bit positions */
3257#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
3258#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
3259
3260#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
3261#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
3262
3263
3264/* PMIC - Programmable Multi-level Interrupt Controller */
3265/* PMIC.STATUS  bit masks and bit positions */
3266#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
3267#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
3268
3269#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
3270#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
3271
3272#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
3273#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
3274
3275#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
3276#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
3277
3278
3279/* PMIC.CTRL  bit masks and bit positions */
3280#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
3281#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
3282
3283#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
3284#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
3285
3286#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
3287#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
3288
3289#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
3290#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
3291
3292#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
3293#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
3294
3295
3296/* CRC - Cyclic Redundancy Checker */
3297/* CRC.CTRL  bit masks and bit positions */
3298#define CRC_RESET_gm  0xC0  /* Reset group mask. */
3299#define CRC_RESET_gp  6  /* Reset group position. */
3300#define CRC_RESET0_bm  (1<<6)  /* Reset bit 0 mask. */
3301#define CRC_RESET0_bp  6  /* Reset bit 0 position. */
3302#define CRC_RESET1_bm  (1<<7)  /* Reset bit 1 mask. */
3303#define CRC_RESET1_bp  7  /* Reset bit 1 position. */
3304
3305#define CRC_CRC32_bm  0x20  /* CRC Mode bit mask. */
3306#define CRC_CRC32_bp  5  /* CRC Mode bit position. */
3307
3308#define CRC_SOURCE_gm  0x0F  /* Input Source group mask. */
3309#define CRC_SOURCE_gp  0  /* Input Source group position. */
3310#define CRC_SOURCE0_bm  (1<<0)  /* Input Source bit 0 mask. */
3311#define CRC_SOURCE0_bp  0  /* Input Source bit 0 position. */
3312#define CRC_SOURCE1_bm  (1<<1)  /* Input Source bit 1 mask. */
3313#define CRC_SOURCE1_bp  1  /* Input Source bit 1 position. */
3314#define CRC_SOURCE2_bm  (1<<2)  /* Input Source bit 2 mask. */
3315#define CRC_SOURCE2_bp  2  /* Input Source bit 2 position. */
3316#define CRC_SOURCE3_bm  (1<<3)  /* Input Source bit 3 mask. */
3317#define CRC_SOURCE3_bp  3  /* Input Source bit 3 position. */
3318
3319/* CRC.STATUS  bit masks and bit positions */
3320#define CRC_ZERO_bm  0x02  /* Zero detection bit mask. */
3321#define CRC_ZERO_bp  1  /* Zero detection bit position. */
3322
3323#define CRC_BUSY_bm  0x01  /* Busy bit mask. */
3324#define CRC_BUSY_bp  0  /* Busy bit position. */
3325
3326
3327/* EVSYS - Event System */
3328/* EVSYS.CH0MUX  bit masks and bit positions */
3329#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
3330#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
3331#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
3332#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
3333#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
3334#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
3335#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
3336#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
3337#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
3338#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
3339#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
3340#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
3341#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
3342#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
3343#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
3344#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
3345#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
3346#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
3347
3348
3349/* EVSYS.CH1MUX  bit masks and bit positions */
3350/* EVSYS_CHMUX_gm  Predefined. */
3351/* EVSYS_CHMUX_gp  Predefined. */
3352/* EVSYS_CHMUX0_bm  Predefined. */
3353/* EVSYS_CHMUX0_bp  Predefined. */
3354/* EVSYS_CHMUX1_bm  Predefined. */
3355/* EVSYS_CHMUX1_bp  Predefined. */
3356/* EVSYS_CHMUX2_bm  Predefined. */
3357/* EVSYS_CHMUX2_bp  Predefined. */
3358/* EVSYS_CHMUX3_bm  Predefined. */
3359/* EVSYS_CHMUX3_bp  Predefined. */
3360/* EVSYS_CHMUX4_bm  Predefined. */
3361/* EVSYS_CHMUX4_bp  Predefined. */
3362/* EVSYS_CHMUX5_bm  Predefined. */
3363/* EVSYS_CHMUX5_bp  Predefined. */
3364/* EVSYS_CHMUX6_bm  Predefined. */
3365/* EVSYS_CHMUX6_bp  Predefined. */
3366/* EVSYS_CHMUX7_bm  Predefined. */
3367/* EVSYS_CHMUX7_bp  Predefined. */
3368
3369
3370/* EVSYS.CH2MUX  bit masks and bit positions */
3371/* EVSYS_CHMUX_gm  Predefined. */
3372/* EVSYS_CHMUX_gp  Predefined. */
3373/* EVSYS_CHMUX0_bm  Predefined. */
3374/* EVSYS_CHMUX0_bp  Predefined. */
3375/* EVSYS_CHMUX1_bm  Predefined. */
3376/* EVSYS_CHMUX1_bp  Predefined. */
3377/* EVSYS_CHMUX2_bm  Predefined. */
3378/* EVSYS_CHMUX2_bp  Predefined. */
3379/* EVSYS_CHMUX3_bm  Predefined. */
3380/* EVSYS_CHMUX3_bp  Predefined. */
3381/* EVSYS_CHMUX4_bm  Predefined. */
3382/* EVSYS_CHMUX4_bp  Predefined. */
3383/* EVSYS_CHMUX5_bm  Predefined. */
3384/* EVSYS_CHMUX5_bp  Predefined. */
3385/* EVSYS_CHMUX6_bm  Predefined. */
3386/* EVSYS_CHMUX6_bp  Predefined. */
3387/* EVSYS_CHMUX7_bm  Predefined. */
3388/* EVSYS_CHMUX7_bp  Predefined. */
3389
3390
3391/* EVSYS.CH3MUX  bit masks and bit positions */
3392/* EVSYS_CHMUX_gm  Predefined. */
3393/* EVSYS_CHMUX_gp  Predefined. */
3394/* EVSYS_CHMUX0_bm  Predefined. */
3395/* EVSYS_CHMUX0_bp  Predefined. */
3396/* EVSYS_CHMUX1_bm  Predefined. */
3397/* EVSYS_CHMUX1_bp  Predefined. */
3398/* EVSYS_CHMUX2_bm  Predefined. */
3399/* EVSYS_CHMUX2_bp  Predefined. */
3400/* EVSYS_CHMUX3_bm  Predefined. */
3401/* EVSYS_CHMUX3_bp  Predefined. */
3402/* EVSYS_CHMUX4_bm  Predefined. */
3403/* EVSYS_CHMUX4_bp  Predefined. */
3404/* EVSYS_CHMUX5_bm  Predefined. */
3405/* EVSYS_CHMUX5_bp  Predefined. */
3406/* EVSYS_CHMUX6_bm  Predefined. */
3407/* EVSYS_CHMUX6_bp  Predefined. */
3408/* EVSYS_CHMUX7_bm  Predefined. */
3409/* EVSYS_CHMUX7_bp  Predefined. */
3410
3411
3412/* EVSYS.CH0CTRL  bit masks and bit positions */
3413#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
3414#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
3415#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
3416#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
3417#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
3418#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
3419
3420#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
3421#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
3422
3423#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
3424#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
3425
3426#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
3427#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
3428#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
3429#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
3430#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
3431#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
3432#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
3433#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
3434
3435
3436/* EVSYS.CH1CTRL  bit masks and bit positions */
3437/* EVSYS_DIGFILT_gm  Predefined. */
3438/* EVSYS_DIGFILT_gp  Predefined. */
3439/* EVSYS_DIGFILT0_bm  Predefined. */
3440/* EVSYS_DIGFILT0_bp  Predefined. */
3441/* EVSYS_DIGFILT1_bm  Predefined. */
3442/* EVSYS_DIGFILT1_bp  Predefined. */
3443/* EVSYS_DIGFILT2_bm  Predefined. */
3444/* EVSYS_DIGFILT2_bp  Predefined. */
3445
3446
3447/* EVSYS.CH2CTRL  bit masks and bit positions */
3448/* EVSYS_QDIRM_gm  Predefined. */
3449/* EVSYS_QDIRM_gp  Predefined. */
3450/* EVSYS_QDIRM0_bm  Predefined. */
3451/* EVSYS_QDIRM0_bp  Predefined. */
3452/* EVSYS_QDIRM1_bm  Predefined. */
3453/* EVSYS_QDIRM1_bp  Predefined. */
3454
3455/* EVSYS_QDIEN_bm  Predefined. */
3456/* EVSYS_QDIEN_bp  Predefined. */
3457
3458/* EVSYS_QDEN_bm  Predefined. */
3459/* EVSYS_QDEN_bp  Predefined. */
3460
3461/* EVSYS_DIGFILT_gm  Predefined. */
3462/* EVSYS_DIGFILT_gp  Predefined. */
3463/* EVSYS_DIGFILT0_bm  Predefined. */
3464/* EVSYS_DIGFILT0_bp  Predefined. */
3465/* EVSYS_DIGFILT1_bm  Predefined. */
3466/* EVSYS_DIGFILT1_bp  Predefined. */
3467/* EVSYS_DIGFILT2_bm  Predefined. */
3468/* EVSYS_DIGFILT2_bp  Predefined. */
3469
3470
3471/* EVSYS.CH3CTRL  bit masks and bit positions */
3472/* EVSYS_DIGFILT_gm  Predefined. */
3473/* EVSYS_DIGFILT_gp  Predefined. */
3474/* EVSYS_DIGFILT0_bm  Predefined. */
3475/* EVSYS_DIGFILT0_bp  Predefined. */
3476/* EVSYS_DIGFILT1_bm  Predefined. */
3477/* EVSYS_DIGFILT1_bp  Predefined. */
3478/* EVSYS_DIGFILT2_bm  Predefined. */
3479/* EVSYS_DIGFILT2_bp  Predefined. */
3480
3481
3482/* NVM - Non Volatile Memory Controller */
3483/* NVM.CMD  bit masks and bit positions */
3484#define NVM_CMD_gm  0xFF  /* Command group mask. */
3485#define NVM_CMD_gp  0  /* Command group position. */
3486#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
3487#define NVM_CMD0_bp  0  /* Command bit 0 position. */
3488#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
3489#define NVM_CMD1_bp  1  /* Command bit 1 position. */
3490#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
3491#define NVM_CMD2_bp  2  /* Command bit 2 position. */
3492#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
3493#define NVM_CMD3_bp  3  /* Command bit 3 position. */
3494#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
3495#define NVM_CMD4_bp  4  /* Command bit 4 position. */
3496#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
3497#define NVM_CMD5_bp  5  /* Command bit 5 position. */
3498#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
3499#define NVM_CMD6_bp  6  /* Command bit 6 position. */
3500#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
3501#define NVM_CMD7_bp  7  /* Command bit 7 position. */
3502
3503
3504/* NVM.CTRLA  bit masks and bit positions */
3505#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
3506#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
3507
3508
3509/* NVM.CTRLB  bit masks and bit positions */
3510#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
3511#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
3512
3513#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
3514#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
3515
3516#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
3517#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
3518
3519#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
3520#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
3521
3522
3523/* NVM.INTCTRL  bit masks and bit positions */
3524#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
3525#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
3526#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
3527#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
3528#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
3529#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
3530
3531#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
3532#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
3533#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
3534#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
3535#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
3536#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
3537
3538
3539/* NVM.STATUS  bit masks and bit positions */
3540#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
3541#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
3542
3543#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
3544#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
3545
3546#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
3547#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
3548
3549#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
3550#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
3551
3552
3553/* NVM.LOCKBITS  bit masks and bit positions */
3554#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
3555#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
3556#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
3557#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
3558#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
3559#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
3560
3561#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
3562#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
3563#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
3564#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
3565#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
3566#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
3567
3568#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
3569#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
3570#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
3571#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
3572#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
3573#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
3574
3575#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
3576#define NVM_LB_gp  0  /* Lock Bits group position. */
3577#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
3578#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
3579#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
3580#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
3581
3582
3583/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
3584#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
3585#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
3586#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
3587#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
3588#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
3589#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
3590
3591#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
3592#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
3593#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
3594#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
3595#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
3596#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
3597
3598#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
3599#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
3600#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
3601#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
3602#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
3603#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
3604
3605#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
3606#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
3607#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
3608#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
3609#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
3610#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
3611
3612
3613/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
3614#define NVM_FUSES_USERID_gm  0xFF  /* User ID group mask. */
3615#define NVM_FUSES_USERID_gp  0  /* User ID group position. */
3616#define NVM_FUSES_USERID0_bm  (1<<0)  /* User ID bit 0 mask. */
3617#define NVM_FUSES_USERID0_bp  0  /* User ID bit 0 position. */
3618#define NVM_FUSES_USERID1_bm  (1<<1)  /* User ID bit 1 mask. */
3619#define NVM_FUSES_USERID1_bp  1  /* User ID bit 1 position. */
3620#define NVM_FUSES_USERID2_bm  (1<<2)  /* User ID bit 2 mask. */
3621#define NVM_FUSES_USERID2_bp  2  /* User ID bit 2 position. */
3622#define NVM_FUSES_USERID3_bm  (1<<3)  /* User ID bit 3 mask. */
3623#define NVM_FUSES_USERID3_bp  3  /* User ID bit 3 position. */
3624#define NVM_FUSES_USERID4_bm  (1<<4)  /* User ID bit 4 mask. */
3625#define NVM_FUSES_USERID4_bp  4  /* User ID bit 4 position. */
3626#define NVM_FUSES_USERID5_bm  (1<<5)  /* User ID bit 5 mask. */
3627#define NVM_FUSES_USERID5_bp  5  /* User ID bit 5 position. */
3628#define NVM_FUSES_USERID6_bm  (1<<6)  /* User ID bit 6 mask. */
3629#define NVM_FUSES_USERID6_bp  6  /* User ID bit 6 position. */
3630#define NVM_FUSES_USERID7_bm  (1<<7)  /* User ID bit 7 mask. */
3631#define NVM_FUSES_USERID7_bp  7  /* User ID bit 7 position. */
3632
3633
3634/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
3635#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
3636#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
3637#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
3638#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
3639#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
3640#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
3641#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
3642#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
3643#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
3644#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
3645
3646#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
3647#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
3648#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
3649#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
3650#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
3651#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
3652#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
3653#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
3654#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
3655#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
3656
3657
3658/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
3659#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
3660#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
3661
3662#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
3663#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
3664
3665#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
3666#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
3667#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
3668#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
3669#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
3670#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
3671
3672
3673/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
3674#define NVM_FUSES_RSTDISBL_bm  0x10  /* External Reset Disable bit mask. */
3675#define NVM_FUSES_RSTDISBL_bp  4  /* External Reset Disable bit position. */
3676
3677#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
3678#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
3679#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
3680#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
3681#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
3682#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
3683
3684#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
3685#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
3686
3687
3688/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
3689#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
3690#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
3691#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
3692#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
3693#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
3694#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
3695
3696#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
3697#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
3698
3699#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
3700#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
3701#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
3702#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
3703#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
3704#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
3705#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
3706#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
3707
3708
3709/* AC - Analog Comparator */
3710/* AC.AC0CTRL  bit masks and bit positions */
3711#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
3712#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
3713#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
3714#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
3715#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
3716#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
3717
3718#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
3719#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
3720#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
3721#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
3722#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
3723#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
3724
3725#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
3726#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
3727
3728#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
3729#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
3730#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
3731#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
3732#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
3733#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
3734
3735#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
3736#define AC_ENABLE_bp  0  /* Enable bit position. */
3737
3738
3739/* AC.AC1CTRL  bit masks and bit positions */
3740/* AC_INTMODE_gm  Predefined. */
3741/* AC_INTMODE_gp  Predefined. */
3742/* AC_INTMODE0_bm  Predefined. */
3743/* AC_INTMODE0_bp  Predefined. */
3744/* AC_INTMODE1_bm  Predefined. */
3745/* AC_INTMODE1_bp  Predefined. */
3746
3747/* AC_INTLVL_gm  Predefined. */
3748/* AC_INTLVL_gp  Predefined. */
3749/* AC_INTLVL0_bm  Predefined. */
3750/* AC_INTLVL0_bp  Predefined. */
3751/* AC_INTLVL1_bm  Predefined. */
3752/* AC_INTLVL1_bp  Predefined. */
3753
3754/* AC_HSMODE_bm  Predefined. */
3755/* AC_HSMODE_bp  Predefined. */
3756
3757/* AC_HYSMODE_gm  Predefined. */
3758/* AC_HYSMODE_gp  Predefined. */
3759/* AC_HYSMODE0_bm  Predefined. */
3760/* AC_HYSMODE0_bp  Predefined. */
3761/* AC_HYSMODE1_bm  Predefined. */
3762/* AC_HYSMODE1_bp  Predefined. */
3763
3764/* AC_ENABLE_bm  Predefined. */
3765/* AC_ENABLE_bp  Predefined. */
3766
3767
3768/* AC.AC0MUXCTRL  bit masks and bit positions */
3769#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
3770#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
3771#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
3772#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
3773#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
3774#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
3775#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
3776#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
3777
3778#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
3779#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
3780#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
3781#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
3782#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
3783#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
3784#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
3785#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
3786
3787
3788/* AC.AC1MUXCTRL  bit masks and bit positions */
3789/* AC_MUXPOS_gm  Predefined. */
3790/* AC_MUXPOS_gp  Predefined. */
3791/* AC_MUXPOS0_bm  Predefined. */
3792/* AC_MUXPOS0_bp  Predefined. */
3793/* AC_MUXPOS1_bm  Predefined. */
3794/* AC_MUXPOS1_bp  Predefined. */
3795/* AC_MUXPOS2_bm  Predefined. */
3796/* AC_MUXPOS2_bp  Predefined. */
3797
3798/* AC_MUXNEG_gm  Predefined. */
3799/* AC_MUXNEG_gp  Predefined. */
3800/* AC_MUXNEG0_bm  Predefined. */
3801/* AC_MUXNEG0_bp  Predefined. */
3802/* AC_MUXNEG1_bm  Predefined. */
3803/* AC_MUXNEG1_bp  Predefined. */
3804/* AC_MUXNEG2_bm  Predefined. */
3805/* AC_MUXNEG2_bp  Predefined. */
3806
3807
3808/* AC.CTRLA  bit masks and bit positions */
3809#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
3810#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
3811
3812
3813/* AC.CTRLB  bit masks and bit positions */
3814#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
3815#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
3816#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
3817#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
3818#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
3819#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
3820#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
3821#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
3822#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
3823#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
3824#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
3825#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
3826#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
3827#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
3828
3829
3830/* AC.WINCTRL  bit masks and bit positions */
3831#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
3832#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
3833
3834#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
3835#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
3836#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
3837#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
3838#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
3839#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
3840
3841#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
3842#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
3843#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
3844#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
3845#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
3846#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
3847
3848
3849/* AC.STATUS  bit masks and bit positions */
3850#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
3851#define AC_WSTATE_gp  6  /* Window Mode State group position. */
3852#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
3853#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
3854#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
3855#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
3856
3857#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
3858#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
3859
3860#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
3861#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
3862
3863#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
3864#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
3865
3866#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
3867#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
3868
3869#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
3870#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
3871
3872
3873/* ADC - Analog/Digital Converter */
3874/* ADC_CH.CTRL  bit masks and bit positions */
3875#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
3876#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
3877
3878#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
3879#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
3880#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
3881#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
3882#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
3883#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
3884#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
3885#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
3886
3887#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
3888#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
3889#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
3890#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
3891#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
3892#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
3893
3894
3895/* ADC_CH.MUXCTRL  bit masks and bit positions */
3896#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
3897#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
3898#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
3899#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
3900#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
3901#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
3902#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
3903#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
3904#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
3905#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
3906
3907#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
3908#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
3909#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
3910#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
3911#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
3912#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
3913
3914
3915/* ADC_CH.INTCTRL  bit masks and bit positions */
3916#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
3917#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
3918#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
3919#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
3920#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
3921#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
3922
3923#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
3924#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
3925#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
3926#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
3927#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
3928#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
3929
3930
3931/* ADC_CH.INTFLAGS  bit masks and bit positions */
3932#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
3933#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
3934
3935
3936/* ADC.CTRLA  bit masks and bit positions */
3937#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
3938#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
3939
3940#define ADC_FLUSH_bm  0x02  /* ADC Flush bit mask. */
3941#define ADC_FLUSH_bp  1  /* ADC Flush bit position. */
3942
3943#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
3944#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
3945
3946
3947/* ADC.CTRLB  bit masks and bit positions */
3948#define ADC_CURRLIMIT_gm  0x60  /* Current Limitation group mask. */
3949#define ADC_CURRLIMIT_gp  5  /* Current Limitation group position. */
3950#define ADC_CURRLIMIT0_bm  (1<<5)  /* Current Limitation bit 0 mask. */
3951#define ADC_CURRLIMIT0_bp  5  /* Current Limitation bit 0 position. */
3952#define ADC_CURRLIMIT1_bm  (1<<6)  /* Current Limitation bit 1 mask. */
3953#define ADC_CURRLIMIT1_bp  6  /* Current Limitation bit 1 position. */
3954
3955#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
3956#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
3957
3958#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
3959#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
3960
3961#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
3962#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
3963#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
3964#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
3965#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
3966#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
3967
3968
3969/* ADC.REFCTRL  bit masks and bit positions */
3970#define ADC_REFSEL_gm  0x70  /* Reference Selection group mask. */
3971#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
3972#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
3973#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
3974#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
3975#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
3976#define ADC_REFSEL2_bm  (1<<6)  /* Reference Selection bit 2 mask. */
3977#define ADC_REFSEL2_bp  6  /* Reference Selection bit 2 position. */
3978
3979#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
3980#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
3981
3982#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
3983#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
3984
3985
3986/* ADC.EVCTRL  bit masks and bit positions */
3987#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
3988#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
3989#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
3990#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
3991#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
3992#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
3993#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
3994#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
3995
3996#define ADC_EVACT_bm  0x01  /* Event Action Select bit mask. */
3997#define ADC_EVACT_bp  0  /* Event Action Select bit position. */
3998
3999
4000/* ADC.PRESCALER  bit masks and bit positions */
4001#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
4002#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
4003#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
4004#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
4005#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
4006#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
4007#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
4008#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
4009
4010
4011/* ADC.INTFLAGS  bit masks and bit positions */
4012#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
4013#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
4014
4015
4016/* RTC - Real-Time Clounter */
4017/* RTC.CTRL  bit masks and bit positions */
4018#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
4019#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
4020#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
4021#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
4022#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
4023#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
4024#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
4025#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
4026
4027
4028/* RTC.STATUS  bit masks and bit positions */
4029#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
4030#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
4031
4032
4033/* RTC.INTCTRL  bit masks and bit positions */
4034#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
4035#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
4036#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
4037#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
4038#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
4039#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
4040
4041#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
4042#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
4043#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
4044#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
4045#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
4046#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
4047
4048
4049/* RTC.INTFLAGS  bit masks and bit positions */
4050#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
4051#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
4052
4053#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
4054#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
4055
4056
4057/* EBI - External Bus Interface */
4058/* EBI_CS.CTRLA  bit masks and bit positions */
4059#define EBI_CS_ASIZE_gm  0x7C  /* Address Size group mask. */
4060#define EBI_CS_ASIZE_gp  2  /* Address Size group position. */
4061#define EBI_CS_ASIZE0_bm  (1<<2)  /* Address Size bit 0 mask. */
4062#define EBI_CS_ASIZE0_bp  2  /* Address Size bit 0 position. */
4063#define EBI_CS_ASIZE1_bm  (1<<3)  /* Address Size bit 1 mask. */
4064#define EBI_CS_ASIZE1_bp  3  /* Address Size bit 1 position. */
4065#define EBI_CS_ASIZE2_bm  (1<<4)  /* Address Size bit 2 mask. */
4066#define EBI_CS_ASIZE2_bp  4  /* Address Size bit 2 position. */
4067#define EBI_CS_ASIZE3_bm  (1<<5)  /* Address Size bit 3 mask. */
4068#define EBI_CS_ASIZE3_bp  5  /* Address Size bit 3 position. */
4069#define EBI_CS_ASIZE4_bm  (1<<6)  /* Address Size bit 4 mask. */
4070#define EBI_CS_ASIZE4_bp  6  /* Address Size bit 4 position. */
4071
4072#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
4073#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
4074#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
4075#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
4076#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
4077#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
4078
4079
4080/* EBI_CS.CTRLB  bit masks and bit positions */
4081#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
4082#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
4083#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
4084#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
4085#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
4086#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
4087#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
4088#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
4089
4090#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
4091#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
4092
4093#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
4094#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
4095
4096#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
4097#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
4098#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
4099#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
4100#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
4101#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
4102
4103
4104/* EBI.CTRL  bit masks and bit positions */
4105#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
4106#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
4107#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
4108#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
4109#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
4110#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
4111
4112#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
4113#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
4114#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
4115#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
4116#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
4117#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
4118
4119#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
4120#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
4121#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
4122#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
4123#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
4124#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
4125
4126#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
4127#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
4128#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
4129#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
4130#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
4131#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
4132
4133
4134/* EBI.SDRAMCTRLA  bit masks and bit positions */
4135#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
4136#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
4137
4138#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
4139#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
4140
4141#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
4142#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
4143#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
4144#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
4145#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
4146#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
4147
4148
4149/* EBI.SDRAMCTRLB  bit masks and bit positions */
4150#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
4151#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
4152#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
4153#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
4154#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
4155#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
4156
4157#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
4158#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
4159#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
4160#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
4161#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
4162#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
4163#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
4164#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
4165
4166#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
4167#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
4168#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
4169#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
4170#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
4171#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
4172#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
4173#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
4174
4175
4176/* EBI.SDRAMCTRLC  bit masks and bit positions */
4177#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
4178#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
4179#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
4180#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
4181#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
4182#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
4183
4184#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
4185#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
4186#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
4187#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
4188#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
4189#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
4190#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
4191#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
4192
4193#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
4194#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
4195#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
4196#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
4197#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
4198#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
4199#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
4200#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
4201
4202
4203/* TWI - Two-Wire Interface */
4204/* TWI_MASTER.CTRLA  bit masks and bit positions */
4205#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
4206#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
4207#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
4208#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
4209#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
4210#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
4211
4212#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
4213#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
4214
4215#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
4216#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
4217
4218#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
4219#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
4220
4221
4222/* TWI_MASTER.CTRLB  bit masks and bit positions */
4223#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
4224#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
4225#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
4226#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
4227#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
4228#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
4229
4230#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
4231#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
4232
4233#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
4234#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
4235
4236
4237/* TWI_MASTER.CTRLC  bit masks and bit positions */
4238#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
4239#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
4240
4241#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
4242#define TWI_MASTER_CMD_gp  0  /* Command group position. */
4243#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
4244#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
4245#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
4246#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
4247
4248
4249/* TWI_MASTER.STATUS  bit masks and bit positions */
4250#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
4251#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
4252
4253#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
4254#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
4255
4256#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
4257#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
4258
4259#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
4260#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
4261
4262#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
4263#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
4264
4265#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
4266#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
4267
4268#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
4269#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
4270#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
4271#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
4272#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
4273#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
4274
4275
4276/* TWI_SLAVE.CTRLA  bit masks and bit positions */
4277#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
4278#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
4279#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
4280#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
4281#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
4282#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
4283
4284#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
4285#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
4286
4287#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
4288#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
4289
4290#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
4291#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
4292
4293#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
4294#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
4295
4296#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
4297#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
4298
4299#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
4300#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
4301
4302
4303/* TWI_SLAVE.CTRLB  bit masks and bit positions */
4304#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
4305#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
4306
4307#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
4308#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
4309#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
4310#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
4311#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
4312#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
4313
4314
4315/* TWI_SLAVE.STATUS  bit masks and bit positions */
4316#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
4317#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
4318
4319#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
4320#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
4321
4322#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
4323#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
4324
4325#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
4326#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
4327
4328#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
4329#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
4330
4331#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
4332#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
4333
4334#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
4335#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
4336
4337#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
4338#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
4339
4340
4341/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
4342#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
4343#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
4344#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
4345#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
4346#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
4347#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
4348#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
4349#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
4350#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
4351#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
4352#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
4353#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
4354#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
4355#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
4356#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
4357#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
4358
4359#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
4360#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
4361
4362
4363/* TWI.CTRL  bit masks and bit positions */
4364#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
4365#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
4366
4367#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
4368#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
4369
4370
4371/* PORT - Port Configuration */
4372/* PORTCFG.VPCTRLA  bit masks and bit positions */
4373#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
4374#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
4375#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
4376#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
4377#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
4378#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
4379#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
4380#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
4381#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
4382#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
4383
4384#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
4385#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
4386#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
4387#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
4388#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
4389#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
4390#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
4391#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
4392#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
4393#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
4394
4395
4396/* PORTCFG.VPCTRLB  bit masks and bit positions */
4397#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
4398#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
4399#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
4400#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
4401#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
4402#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
4403#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
4404#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
4405#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
4406#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
4407
4408#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
4409#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
4410#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
4411#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
4412#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
4413#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
4414#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
4415#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
4416#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
4417#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
4418
4419
4420/* PORTCFG.CLKEVOUT  bit masks and bit positions */
4421#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
4422#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
4423#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
4424#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
4425#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
4426#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
4427
4428#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
4429#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
4430#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
4431#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
4432#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
4433#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
4434
4435
4436/* VPORT.INTFLAGS  bit masks and bit positions */
4437#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
4438#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
4439
4440#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
4441#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
4442
4443
4444/* PORT.INTCTRL  bit masks and bit positions */
4445#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
4446#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
4447#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
4448#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
4449#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
4450#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
4451
4452#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
4453#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
4454#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
4455#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
4456#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
4457#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
4458
4459
4460/* PORT.INTFLAGS  bit masks and bit positions */
4461#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
4462#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
4463
4464#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
4465#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
4466
4467
4468/* PORT.PIN0CTRL  bit masks and bit positions */
4469#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
4470#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
4471
4472#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
4473#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
4474
4475#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
4476#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
4477#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
4478#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
4479#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
4480#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
4481#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
4482#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
4483
4484#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
4485#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
4486#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
4487#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
4488#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
4489#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
4490#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
4491#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
4492
4493
4494/* PORT.PIN1CTRL  bit masks and bit positions */
4495/* PORT_SRLEN_bm  Predefined. */
4496/* PORT_SRLEN_bp  Predefined. */
4497
4498/* PORT_INVEN_bm  Predefined. */
4499/* PORT_INVEN_bp  Predefined. */
4500
4501/* PORT_OPC_gm  Predefined. */
4502/* PORT_OPC_gp  Predefined. */
4503/* PORT_OPC0_bm  Predefined. */
4504/* PORT_OPC0_bp  Predefined. */
4505/* PORT_OPC1_bm  Predefined. */
4506/* PORT_OPC1_bp  Predefined. */
4507/* PORT_OPC2_bm  Predefined. */
4508/* PORT_OPC2_bp  Predefined. */
4509
4510/* PORT_ISC_gm  Predefined. */
4511/* PORT_ISC_gp  Predefined. */
4512/* PORT_ISC0_bm  Predefined. */
4513/* PORT_ISC0_bp  Predefined. */
4514/* PORT_ISC1_bm  Predefined. */
4515/* PORT_ISC1_bp  Predefined. */
4516/* PORT_ISC2_bm  Predefined. */
4517/* PORT_ISC2_bp  Predefined. */
4518
4519
4520/* PORT.PIN2CTRL  bit masks and bit positions */
4521/* PORT_SRLEN_bm  Predefined. */
4522/* PORT_SRLEN_bp  Predefined. */
4523
4524/* PORT_INVEN_bm  Predefined. */
4525/* PORT_INVEN_bp  Predefined. */
4526
4527/* PORT_OPC_gm  Predefined. */
4528/* PORT_OPC_gp  Predefined. */
4529/* PORT_OPC0_bm  Predefined. */
4530/* PORT_OPC0_bp  Predefined. */
4531/* PORT_OPC1_bm  Predefined. */
4532/* PORT_OPC1_bp  Predefined. */
4533/* PORT_OPC2_bm  Predefined. */
4534/* PORT_OPC2_bp  Predefined. */
4535
4536/* PORT_ISC_gm  Predefined. */
4537/* PORT_ISC_gp  Predefined. */
4538/* PORT_ISC0_bm  Predefined. */
4539/* PORT_ISC0_bp  Predefined. */
4540/* PORT_ISC1_bm  Predefined. */
4541/* PORT_ISC1_bp  Predefined. */
4542/* PORT_ISC2_bm  Predefined. */
4543/* PORT_ISC2_bp  Predefined. */
4544
4545
4546/* PORT.PIN3CTRL  bit masks and bit positions */
4547/* PORT_SRLEN_bm  Predefined. */
4548/* PORT_SRLEN_bp  Predefined. */
4549
4550/* PORT_INVEN_bm  Predefined. */
4551/* PORT_INVEN_bp  Predefined. */
4552
4553/* PORT_OPC_gm  Predefined. */
4554/* PORT_OPC_gp  Predefined. */
4555/* PORT_OPC0_bm  Predefined. */
4556/* PORT_OPC0_bp  Predefined. */
4557/* PORT_OPC1_bm  Predefined. */
4558/* PORT_OPC1_bp  Predefined. */
4559/* PORT_OPC2_bm  Predefined. */
4560/* PORT_OPC2_bp  Predefined. */
4561
4562/* PORT_ISC_gm  Predefined. */
4563/* PORT_ISC_gp  Predefined. */
4564/* PORT_ISC0_bm  Predefined. */
4565/* PORT_ISC0_bp  Predefined. */
4566/* PORT_ISC1_bm  Predefined. */
4567/* PORT_ISC1_bp  Predefined. */
4568/* PORT_ISC2_bm  Predefined. */
4569/* PORT_ISC2_bp  Predefined. */
4570
4571
4572/* PORT.PIN4CTRL  bit masks and bit positions */
4573/* PORT_SRLEN_bm  Predefined. */
4574/* PORT_SRLEN_bp  Predefined. */
4575
4576/* PORT_INVEN_bm  Predefined. */
4577/* PORT_INVEN_bp  Predefined. */
4578
4579/* PORT_OPC_gm  Predefined. */
4580/* PORT_OPC_gp  Predefined. */
4581/* PORT_OPC0_bm  Predefined. */
4582/* PORT_OPC0_bp  Predefined. */
4583/* PORT_OPC1_bm  Predefined. */
4584/* PORT_OPC1_bp  Predefined. */
4585/* PORT_OPC2_bm  Predefined. */
4586/* PORT_OPC2_bp  Predefined. */
4587
4588/* PORT_ISC_gm  Predefined. */
4589/* PORT_ISC_gp  Predefined. */
4590/* PORT_ISC0_bm  Predefined. */
4591/* PORT_ISC0_bp  Predefined. */
4592/* PORT_ISC1_bm  Predefined. */
4593/* PORT_ISC1_bp  Predefined. */
4594/* PORT_ISC2_bm  Predefined. */
4595/* PORT_ISC2_bp  Predefined. */
4596
4597
4598/* PORT.PIN5CTRL  bit masks and bit positions */
4599/* PORT_SRLEN_bm  Predefined. */
4600/* PORT_SRLEN_bp  Predefined. */
4601
4602/* PORT_INVEN_bm  Predefined. */
4603/* PORT_INVEN_bp  Predefined. */
4604
4605/* PORT_OPC_gm  Predefined. */
4606/* PORT_OPC_gp  Predefined. */
4607/* PORT_OPC0_bm  Predefined. */
4608/* PORT_OPC0_bp  Predefined. */
4609/* PORT_OPC1_bm  Predefined. */
4610/* PORT_OPC1_bp  Predefined. */
4611/* PORT_OPC2_bm  Predefined. */
4612/* PORT_OPC2_bp  Predefined. */
4613
4614/* PORT_ISC_gm  Predefined. */
4615/* PORT_ISC_gp  Predefined. */
4616/* PORT_ISC0_bm  Predefined. */
4617/* PORT_ISC0_bp  Predefined. */
4618/* PORT_ISC1_bm  Predefined. */
4619/* PORT_ISC1_bp  Predefined. */
4620/* PORT_ISC2_bm  Predefined. */
4621/* PORT_ISC2_bp  Predefined. */
4622
4623
4624/* PORT.PIN6CTRL  bit masks and bit positions */
4625/* PORT_SRLEN_bm  Predefined. */
4626/* PORT_SRLEN_bp  Predefined. */
4627
4628/* PORT_INVEN_bm  Predefined. */
4629/* PORT_INVEN_bp  Predefined. */
4630
4631/* PORT_OPC_gm  Predefined. */
4632/* PORT_OPC_gp  Predefined. */
4633/* PORT_OPC0_bm  Predefined. */
4634/* PORT_OPC0_bp  Predefined. */
4635/* PORT_OPC1_bm  Predefined. */
4636/* PORT_OPC1_bp  Predefined. */
4637/* PORT_OPC2_bm  Predefined. */
4638/* PORT_OPC2_bp  Predefined. */
4639
4640/* PORT_ISC_gm  Predefined. */
4641/* PORT_ISC_gp  Predefined. */
4642/* PORT_ISC0_bm  Predefined. */
4643/* PORT_ISC0_bp  Predefined. */
4644/* PORT_ISC1_bm  Predefined. */
4645/* PORT_ISC1_bp  Predefined. */
4646/* PORT_ISC2_bm  Predefined. */
4647/* PORT_ISC2_bp  Predefined. */
4648
4649
4650/* PORT.PIN7CTRL  bit masks and bit positions */
4651/* PORT_SRLEN_bm  Predefined. */
4652/* PORT_SRLEN_bp  Predefined. */
4653
4654/* PORT_INVEN_bm  Predefined. */
4655/* PORT_INVEN_bp  Predefined. */
4656
4657/* PORT_OPC_gm  Predefined. */
4658/* PORT_OPC_gp  Predefined. */
4659/* PORT_OPC0_bm  Predefined. */
4660/* PORT_OPC0_bp  Predefined. */
4661/* PORT_OPC1_bm  Predefined. */
4662/* PORT_OPC1_bp  Predefined. */
4663/* PORT_OPC2_bm  Predefined. */
4664/* PORT_OPC2_bp  Predefined. */
4665
4666/* PORT_ISC_gm  Predefined. */
4667/* PORT_ISC_gp  Predefined. */
4668/* PORT_ISC0_bm  Predefined. */
4669/* PORT_ISC0_bp  Predefined. */
4670/* PORT_ISC1_bm  Predefined. */
4671/* PORT_ISC1_bp  Predefined. */
4672/* PORT_ISC2_bm  Predefined. */
4673/* PORT_ISC2_bp  Predefined. */
4674
4675
4676/* TC - 16-bit Timer/Counter With PWM */
4677/* TC0.CTRLA  bit masks and bit positions */
4678#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4679#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
4680#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4681#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4682#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4683#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4684#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4685#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4686#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4687#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4688
4689
4690/* TC0.CTRLB  bit masks and bit positions */
4691#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
4692#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
4693
4694#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
4695#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
4696
4697#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
4698#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
4699
4700#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
4701#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
4702
4703#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
4704#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
4705#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
4706#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
4707#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
4708#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
4709#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
4710#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
4711
4712
4713/* TC0.CTRLC  bit masks and bit positions */
4714#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
4715#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
4716
4717#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
4718#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
4719
4720#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
4721#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
4722
4723#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
4724#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
4725
4726
4727/* TC0.CTRLD  bit masks and bit positions */
4728#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
4729#define TC0_EVACT_gp  5  /* Event Action group position. */
4730#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
4731#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
4732#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
4733#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
4734#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
4735#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
4736
4737#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
4738#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
4739
4740#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
4741#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
4742#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
4743#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
4744#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
4745#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
4746#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
4747#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
4748#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
4749#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
4750
4751
4752/* TC0.CTRLE  bit masks and bit positions */
4753#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
4754#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
4755
4756
4757/* TC0.INTCTRLA  bit masks and bit positions */
4758#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
4759#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
4760#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
4761#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
4762#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
4763#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
4764
4765#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
4766#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
4767#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
4768#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
4769#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
4770#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
4771
4772
4773/* TC0.INTCTRLB  bit masks and bit positions */
4774#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
4775#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
4776#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
4777#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
4778#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
4779#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
4780
4781#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
4782#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
4783#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
4784#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
4785#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
4786#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
4787
4788#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
4789#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
4790#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
4791#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
4792#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
4793#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
4794
4795#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
4796#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
4797#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
4798#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
4799#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
4800#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
4801
4802
4803/* TC0.CTRLFCLR  bit masks and bit positions */
4804#define TC0_CMD_gm  0x0C  /* Command group mask. */
4805#define TC0_CMD_gp  2  /* Command group position. */
4806#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
4807#define TC0_CMD0_bp  2  /* Command bit 0 position. */
4808#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
4809#define TC0_CMD1_bp  3  /* Command bit 1 position. */
4810
4811#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
4812#define TC0_LUPD_bp  1  /* Lock Update bit position. */
4813
4814#define TC0_DIR_bm  0x01  /* Direction bit mask. */
4815#define TC0_DIR_bp  0  /* Direction bit position. */
4816
4817
4818/* TC0.CTRLFSET  bit masks and bit positions */
4819/* TC0_CMD_gm  Predefined. */
4820/* TC0_CMD_gp  Predefined. */
4821/* TC0_CMD0_bm  Predefined. */
4822/* TC0_CMD0_bp  Predefined. */
4823/* TC0_CMD1_bm  Predefined. */
4824/* TC0_CMD1_bp  Predefined. */
4825
4826/* TC0_LUPD_bm  Predefined. */
4827/* TC0_LUPD_bp  Predefined. */
4828
4829/* TC0_DIR_bm  Predefined. */
4830/* TC0_DIR_bp  Predefined. */
4831
4832
4833/* TC0.CTRLGCLR  bit masks and bit positions */
4834#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
4835#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
4836
4837#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
4838#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
4839
4840#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
4841#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
4842
4843#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
4844#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
4845
4846#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
4847#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
4848
4849
4850/* TC0.CTRLGSET  bit masks and bit positions */
4851/* TC0_CCDBV_bm  Predefined. */
4852/* TC0_CCDBV_bp  Predefined. */
4853
4854/* TC0_CCCBV_bm  Predefined. */
4855/* TC0_CCCBV_bp  Predefined. */
4856
4857/* TC0_CCBBV_bm  Predefined. */
4858/* TC0_CCBBV_bp  Predefined. */
4859
4860/* TC0_CCABV_bm  Predefined. */
4861/* TC0_CCABV_bp  Predefined. */
4862
4863/* TC0_PERBV_bm  Predefined. */
4864/* TC0_PERBV_bp  Predefined. */
4865
4866
4867/* TC0.INTFLAGS  bit masks and bit positions */
4868#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
4869#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
4870
4871#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
4872#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
4873
4874#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
4875#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
4876
4877#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
4878#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
4879
4880#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
4881#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
4882
4883#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
4884#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
4885
4886
4887/* TC1.CTRLA  bit masks and bit positions */
4888#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4889#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
4890#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4891#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4892#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4893#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4894#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4895#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4896#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4897#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4898
4899
4900/* TC1.CTRLB  bit masks and bit positions */
4901#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
4902#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
4903
4904#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
4905#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
4906
4907#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
4908#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
4909#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
4910#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
4911#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
4912#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
4913#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
4914#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
4915
4916
4917/* TC1.CTRLC  bit masks and bit positions */
4918#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
4919#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
4920
4921#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
4922#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
4923
4924
4925/* TC1.CTRLD  bit masks and bit positions */
4926#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
4927#define TC1_EVACT_gp  5  /* Event Action group position. */
4928#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
4929#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
4930#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
4931#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
4932#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
4933#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
4934
4935#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
4936#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
4937
4938#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
4939#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
4940#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
4941#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
4942#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
4943#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
4944#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
4945#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
4946#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
4947#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
4948
4949
4950/* TC1.CTRLE  bit masks and bit positions */
4951#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
4952#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
4953
4954
4955/* TC1.INTCTRLA  bit masks and bit positions */
4956#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
4957#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
4958#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
4959#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
4960#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
4961#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
4962
4963#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
4964#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
4965#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
4966#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
4967#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
4968#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
4969
4970
4971/* TC1.INTCTRLB  bit masks and bit positions */
4972#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
4973#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
4974#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
4975#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
4976#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
4977#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
4978
4979#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
4980#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
4981#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
4982#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
4983#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
4984#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
4985
4986
4987/* TC1.CTRLFCLR  bit masks and bit positions */
4988#define TC1_CMD_gm  0x0C  /* Command group mask. */
4989#define TC1_CMD_gp  2  /* Command group position. */
4990#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
4991#define TC1_CMD0_bp  2  /* Command bit 0 position. */
4992#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
4993#define TC1_CMD1_bp  3  /* Command bit 1 position. */
4994
4995#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
4996#define TC1_LUPD_bp  1  /* Lock Update bit position. */
4997
4998#define TC1_DIR_bm  0x01  /* Direction bit mask. */
4999#define TC1_DIR_bp  0  /* Direction bit position. */
5000
5001
5002/* TC1.CTRLFSET  bit masks and bit positions */
5003/* TC1_CMD_gm  Predefined. */
5004/* TC1_CMD_gp  Predefined. */
5005/* TC1_CMD0_bm  Predefined. */
5006/* TC1_CMD0_bp  Predefined. */
5007/* TC1_CMD1_bm  Predefined. */
5008/* TC1_CMD1_bp  Predefined. */
5009
5010/* TC1_LUPD_bm  Predefined. */
5011/* TC1_LUPD_bp  Predefined. */
5012
5013/* TC1_DIR_bm  Predefined. */
5014/* TC1_DIR_bp  Predefined. */
5015
5016
5017/* TC1.CTRLGCLR  bit masks and bit positions */
5018#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
5019#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
5020
5021#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
5022#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
5023
5024#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
5025#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
5026
5027
5028/* TC1.CTRLGSET  bit masks and bit positions */
5029/* TC1_CCBBV_bm  Predefined. */
5030/* TC1_CCBBV_bp  Predefined. */
5031
5032/* TC1_CCABV_bm  Predefined. */
5033/* TC1_CCABV_bp  Predefined. */
5034
5035/* TC1_PERBV_bm  Predefined. */
5036/* TC1_PERBV_bp  Predefined. */
5037
5038
5039/* TC1.INTFLAGS  bit masks and bit positions */
5040#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
5041#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
5042
5043#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
5044#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
5045
5046#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
5047#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
5048
5049#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
5050#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
5051
5052
5053/* AWEX.CTRL  bit masks and bit positions */
5054#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
5055#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
5056
5057#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
5058#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
5059
5060#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
5061#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
5062
5063#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
5064#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
5065
5066#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
5067#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
5068
5069#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
5070#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
5071
5072
5073/* AWEX.FDCTRL  bit masks and bit positions */
5074#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
5075#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
5076
5077#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
5078#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
5079
5080#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
5081#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
5082#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
5083#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
5084#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
5085#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
5086
5087
5088/* AWEX.STATUS  bit masks and bit positions */
5089#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
5090#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
5091
5092#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
5093#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
5094
5095#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
5096#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
5097
5098
5099/* HIRES.CTRLA  bit masks and bit positions */
5100#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
5101#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
5102#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
5103#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
5104#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
5105#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
5106
5107
5108/* USART - Universal Asynchronous Receiver-Transmitter */
5109/* USART.STATUS  bit masks and bit positions */
5110#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
5111#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
5112
5113#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
5114#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
5115
5116#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
5117#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
5118
5119#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
5120#define USART_FERR_bp  4  /* Frame Error bit position. */
5121
5122#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
5123#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
5124
5125#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
5126#define USART_PERR_bp  2  /* Parity Error bit position. */
5127
5128#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
5129#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
5130
5131
5132/* USART.CTRLA  bit masks and bit positions */
5133#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
5134#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
5135#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
5136#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
5137#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
5138#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
5139
5140#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
5141#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
5142#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
5143#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
5144#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
5145#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
5146
5147#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
5148#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
5149#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
5150#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
5151#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
5152#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
5153
5154
5155/* USART.CTRLB  bit masks and bit positions */
5156#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
5157#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
5158
5159#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
5160#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
5161
5162#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
5163#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
5164
5165#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
5166#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
5167
5168#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
5169#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
5170
5171
5172/* USART.CTRLC  bit masks and bit positions */
5173#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
5174#define USART_CMODE_gp  6  /* Communication Mode group position. */
5175#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
5176#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
5177#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
5178#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
5179
5180#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
5181#define USART_PMODE_gp  4  /* Parity Mode group position. */
5182#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
5183#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
5184#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
5185#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
5186
5187#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
5188#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
5189
5190#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
5191#define USART_CHSIZE_gp  0  /* Character Size group position. */
5192#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
5193#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
5194#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
5195#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
5196#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
5197#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
5198
5199
5200/* USART.BAUDCTRLA  bit masks and bit positions */
5201#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
5202#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
5203#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
5204#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
5205#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
5206#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
5207#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
5208#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
5209#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
5210#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
5211#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
5212#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
5213#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
5214#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
5215#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
5216#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
5217#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
5218#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
5219
5220
5221/* USART.BAUDCTRLB  bit masks and bit positions */
5222#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
5223#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
5224#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
5225#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
5226#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
5227#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
5228#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
5229#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
5230#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
5231#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
5232
5233/* USART_BSEL_gm  Predefined. */
5234/* USART_BSEL_gp  Predefined. */
5235/* USART_BSEL0_bm  Predefined. */
5236/* USART_BSEL0_bp  Predefined. */
5237/* USART_BSEL1_bm  Predefined. */
5238/* USART_BSEL1_bp  Predefined. */
5239/* USART_BSEL2_bm  Predefined. */
5240/* USART_BSEL2_bp  Predefined. */
5241/* USART_BSEL3_bm  Predefined. */
5242/* USART_BSEL3_bp  Predefined. */
5243
5244
5245/* SPI - Serial Peripheral Interface */
5246/* SPI.CTRL  bit masks and bit positions */
5247#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
5248#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
5249
5250#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
5251#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
5252
5253#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
5254#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
5255
5256#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
5257#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
5258
5259#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
5260#define SPI_MODE_gp  2  /* SPI Mode group position. */
5261#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
5262#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
5263#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
5264#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
5265
5266#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
5267#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
5268#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
5269#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
5270#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
5271#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
5272
5273
5274/* SPI.INTCTRL  bit masks and bit positions */
5275#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
5276#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
5277#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
5278#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
5279#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
5280#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
5281
5282
5283/* SPI.STATUS  bit masks and bit positions */
5284#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
5285#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
5286
5287#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
5288#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
5289
5290
5291/* IRCOM - IR Communication Module */
5292/* IRCOM.CTRL  bit masks and bit positions */
5293#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
5294#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
5295#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
5296#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
5297#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
5298#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
5299#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
5300#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
5301#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
5302#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
5303
5304
5305
5306// Generic Port Pins
5307
5308#define PIN0_bm 0x01
5309#define PIN0_bp 0
5310#define PIN1_bm 0x02
5311#define PIN1_bp 1
5312#define PIN2_bm 0x04
5313#define PIN2_bp 2
5314#define PIN3_bm 0x08
5315#define PIN3_bp 3
5316#define PIN4_bm 0x10
5317#define PIN4_bp 4
5318#define PIN5_bm 0x20
5319#define PIN5_bp 5
5320#define PIN6_bm 0x40
5321#define PIN6_bp 6
5322#define PIN7_bm 0x80
5323#define PIN7_bp 7
5324
5325
5326/* ========== Interrupt Vector Definitions ========== */
5327/* Vector 0 is the reset vector */
5328
5329/* OSC interrupt vectors */
5330#define OSC_XOSCF_vect_num  1
5331#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
5332
5333/* PORTC interrupt vectors */
5334#define PORTC_INT0_vect_num  2
5335#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
5336#define PORTC_INT1_vect_num  3
5337#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
5338
5339/* PORTR interrupt vectors */
5340#define PORTR_INT0_vect_num  4
5341#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
5342#define PORTR_INT1_vect_num  5
5343#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
5344
5345/* RTC interrupt vectors */
5346#define RTC_OVF_vect_num  10
5347#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
5348#define RTC_COMP_vect_num  11
5349#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
5350
5351/* TWIC interrupt vectors */
5352#define TWIC_TWIS_vect_num  12
5353#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
5354#define TWIC_TWIM_vect_num  13
5355#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
5356
5357/* TCC0 interrupt vectors */
5358#define TCC0_OVF_vect_num  14
5359#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
5360#define TCC0_ERR_vect_num  15
5361#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
5362#define TCC0_CCA_vect_num  16
5363#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
5364#define TCC0_CCB_vect_num  17
5365#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
5366#define TCC0_CCC_vect_num  18
5367#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
5368#define TCC0_CCD_vect_num  19
5369#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
5370
5371/* TCC1 interrupt vectors */
5372#define TCC1_OVF_vect_num  20
5373#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
5374#define TCC1_ERR_vect_num  21
5375#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
5376#define TCC1_CCA_vect_num  22
5377#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
5378#define TCC1_CCB_vect_num  23
5379#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
5380
5381/* SPIC interrupt vectors */
5382#define SPIC_INT_vect_num  24
5383#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
5384
5385/* USARTC0 interrupt vectors */
5386#define USARTC0_RXC_vect_num  25
5387#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
5388#define USARTC0_DRE_vect_num  26
5389#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
5390#define USARTC0_TXC_vect_num  27
5391#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
5392
5393/* NVM interrupt vectors */
5394#define NVM_EE_vect_num  32
5395#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
5396#define NVM_SPM_vect_num  33
5397#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
5398
5399/* PORTB interrupt vectors */
5400#define PORTB_INT0_vect_num  34
5401#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
5402#define PORTB_INT1_vect_num  35
5403#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
5404
5405/* PORTE interrupt vectors */
5406#define PORTE_INT0_vect_num  43
5407#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
5408#define PORTE_INT1_vect_num  44
5409#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
5410
5411/* TWIE interrupt vectors */
5412#define TWIE_TWIS_vect_num  45
5413#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
5414#define TWIE_TWIM_vect_num  46
5415#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
5416
5417/* TCE0 interrupt vectors */
5418#define TCE0_OVF_vect_num  47
5419#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
5420#define TCE0_ERR_vect_num  48
5421#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
5422#define TCE0_CCA_vect_num  49
5423#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
5424#define TCE0_CCB_vect_num  50
5425#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
5426#define TCE0_CCC_vect_num  51
5427#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
5428#define TCE0_CCD_vect_num  52
5429#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
5430
5431/* USARTE0 interrupt vectors */
5432#define USARTE0_RXC_vect_num  58
5433#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
5434#define USARTE0_DRE_vect_num  59
5435#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
5436#define USARTE0_TXC_vect_num  60
5437#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
5438
5439/* PORTD interrupt vectors */
5440#define PORTD_INT0_vect_num  64
5441#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
5442#define PORTD_INT1_vect_num  65
5443#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
5444
5445/* PORTA interrupt vectors */
5446#define PORTA_INT0_vect_num  66
5447#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
5448#define PORTA_INT1_vect_num  67
5449#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
5450
5451/* ACA interrupt vectors */
5452#define ACA_AC0_vect_num  68
5453#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
5454#define ACA_AC1_vect_num  69
5455#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
5456#define ACA_ACW_vect_num  70
5457#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
5458
5459/* ADCA interrupt vectors */
5460#define ADCA_CH0_vect_num  71
5461#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
5462
5463/* TCD0 interrupt vectors */
5464#define TCD0_OVF_vect_num  77
5465#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
5466#define TCD0_ERR_vect_num  78
5467#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
5468#define TCD0_CCA_vect_num  79
5469#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
5470#define TCD0_CCB_vect_num  80
5471#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
5472#define TCD0_CCC_vect_num  81
5473#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
5474#define TCD0_CCD_vect_num  82
5475#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
5476
5477/* SPID interrupt vectors */
5478#define SPID_INT_vect_num  87
5479#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
5480
5481/* USARTD0 interrupt vectors */
5482#define USARTD0_RXC_vect_num  88
5483#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
5484#define USARTD0_DRE_vect_num  89
5485#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
5486#define USARTD0_TXC_vect_num  90
5487#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
5488
5489/* PORTF interrupt vectors */
5490#define PORTF_INT0_vect_num  104
5491#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
5492#define PORTF_INT1_vect_num  105
5493#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
5494
5495/* TCF0 interrupt vectors */
5496#define TCF0_OVF_vect_num  108
5497#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
5498#define TCF0_ERR_vect_num  109
5499#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
5500#define TCF0_CCA_vect_num  110
5501#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
5502#define TCF0_CCB_vect_num  111
5503#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
5504#define TCF0_CCC_vect_num  112
5505#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
5506#define TCF0_CCD_vect_num  113
5507#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
5508
5509
5510#define _VECTOR_SIZE 4 /* Size of individual vector. */
5511#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
5512
5513
5514/* ========== Constants ========== */
5515
5516#define PROGMEM_START     (0x0000)
5517#define PROGMEM_SIZE      (270336)
5518#define PROGMEM_PAGE_SIZE (512)
5519#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
5520
5521#define APP_SECTION_START     (0x0000)
5522#define APP_SECTION_SIZE      (262144)
5523#define APP_SECTION_PAGE_SIZE (512)
5524#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
5525
5526#define APPTABLE_SECTION_START     (0x3E000)
5527#define APPTABLE_SECTION_SIZE      (8192)
5528#define APPTABLE_SECTION_PAGE_SIZE (512)
5529#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
5530
5531#define BOOT_SECTION_START     (0x40000)
5532#define BOOT_SECTION_SIZE      (8192)
5533#define BOOT_SECTION_PAGE_SIZE (512)
5534#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
5535
5536#define DATAMEM_START     (0x0000)
5537#define DATAMEM_SIZE      (24576)
5538#define DATAMEM_PAGE_SIZE (0)
5539#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
5540
5541#define IO_START     (0x0000)
5542#define IO_SIZE      (4096)
5543#define IO_PAGE_SIZE (0)
5544#define IO_END       (IO_START + IO_SIZE - 1)
5545
5546#define MAPPED_EEPROM_START     (0x1000)
5547#define MAPPED_EEPROM_SIZE      (4096)
5548#define MAPPED_EEPROM_PAGE_SIZE (0)
5549#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
5550
5551#define INTERNAL_SRAM_START     (0x2000)
5552#define INTERNAL_SRAM_SIZE      (16384)
5553#define INTERNAL_SRAM_PAGE_SIZE (0)
5554#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
5555
5556#define EEPROM_START     (0x0000)
5557#define EEPROM_SIZE      (4096)
5558#define EEPROM_PAGE_SIZE (32)
5559#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
5560
5561#define FUSE_START     (0x0000)
5562#define FUSE_SIZE      (6)
5563#define FUSE_PAGE_SIZE (0)
5564#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
5565
5566#define LOCKBIT_START     (0x0000)
5567#define LOCKBIT_SIZE      (1)
5568#define LOCKBIT_PAGE_SIZE (0)
5569#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
5570
5571#define SIGNATURES_START     (0x0000)
5572#define SIGNATURES_SIZE      (3)
5573#define SIGNATURES_PAGE_SIZE (0)
5574#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
5575
5576#define USER_SIGNATURES_START     (0x0000)
5577#define USER_SIGNATURES_SIZE      (512)
5578#define USER_SIGNATURES_PAGE_SIZE (0)
5579#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
5580
5581#define PROD_SIGNATURES_START     (0x0000)
5582#define PROD_SIGNATURES_SIZE      (52)
5583#define PROD_SIGNATURES_PAGE_SIZE (0)
5584#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
5585
5586#define FLASHEND     PROGMEM_END
5587#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
5588#define RAMSTART     INTERNAL_SRAM_START
5589#define RAMSIZE      INTERNAL_SRAM_SIZE
5590#define RAMEND       INTERNAL_SRAM_END
5591#define XRAMSTART    EXTERNAL_SRAM_START
5592#define XRAMSIZE     EXTERNAL_SRAM_SIZE
5593#define XRAMEND      INTERNAL_SRAM_END
5594#define E2END        EEPROM_END
5595#define E2PAGESIZE   EEPROM_PAGE_SIZE
5596
5597
5598/* ========== Fuses ========== */
5599#define FUSE_MEMORY_SIZE 6
5600
5601/* Fuse Byte 0 */
5602#define FUSE_USERID0  (unsigned char)~_BV(0)  /* User ID Bit 0 */
5603#define FUSE_USERID1  (unsigned char)~_BV(1)  /* User ID Bit 1 */
5604#define FUSE_USERID2  (unsigned char)~_BV(2)  /* User ID Bit 2 */
5605#define FUSE_USERID3  (unsigned char)~_BV(3)  /* User ID Bit 3 */
5606#define FUSE_USERID4  (unsigned char)~_BV(4)  /* User ID Bit 4 */
5607#define FUSE_USERID5  (unsigned char)~_BV(5)  /* User ID Bit 5 */
5608#define FUSE_USERID6  (unsigned char)~_BV(6)  /* User ID Bit 6 */
5609#define FUSE_USERID7  (unsigned char)~_BV(7)  /* User ID Bit 7 */
5610#define FUSE0_DEFAULT  (0xFF)
5611
5612/* Fuse Byte 1 */
5613#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
5614#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
5615#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
5616#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
5617#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
5618#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
5619#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
5620#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
5621#define FUSE1_DEFAULT  (0xFF)
5622
5623/* Fuse Byte 2 */
5624#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
5625#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
5626#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
5627#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
5628#define FUSE2_DEFAULT  (0xFF)
5629
5630/* Fuse Byte 3 Reserved */
5631
5632/* Fuse Byte 4 */
5633#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
5634#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
5635#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
5636#define FUSE_RSTDISBL  (unsigned char)~_BV(4)  /* External Reset Disable */
5637#define FUSE4_DEFAULT  (0xFF)
5638
5639/* Fuse Byte 5 */
5640#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
5641#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
5642#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
5643#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
5644#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
5645#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
5646#define FUSE5_DEFAULT  (0xFF)
5647
5648
5649/* ========== Lock Bits ========== */
5650#define __LOCK_BITS_EXIST
5651#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
5652#define __BOOT_LOCK_APPLICATION_BITS_EXIST
5653#define __BOOT_LOCK_BOOT_BITS_EXIST
5654
5655
5656/* ========== Signature ========== */
5657#define SIGNATURE_0 0x1E
5658#define SIGNATURE_1 0x98
5659#define SIGNATURE_2 0x44
5660
5661
5662#endif /* _AVR_ATxmega256D3_H_ */
5663
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