source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iox256d3.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 2 years ago

Adding new version

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1/* Copyright (c) 2009-2010 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iox256d3.h 2162 2010-06-11 17:26:12Z arcanum $ */
32
33/* avr/iox256d3.h - definitions for ATxmega256D3 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iox256d3.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_ATxmega256D3_H_
49#define _AVR_ATxmega256D3_H_ 1
50
51
52/* Ungrouped common registers */
53#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
54#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
55#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
56#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
57#define GPIOR4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
58#define GPIOR5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
59#define GPIOR6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
60#define GPIOR7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
61#define GPIOR8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
62#define GPIOR9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
63#define GPIORA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
64#define GPIORB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
65#define GPIORC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
66#define GPIORD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
67#define GPIORE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
68#define GPIORF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
69
70#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
71#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
72#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
73#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
74#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
75#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
76#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
77#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
78#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
79
80
81/* C Language Only */
82#if !defined (__ASSEMBLER__)
83
84#include <stdint.h>
85
86typedef volatile uint8_t register8_t;
87typedef volatile uint16_t register16_t;
88typedef volatile uint32_t register32_t;
89
90
91#ifdef _WORDREGISTER
92#undef _WORDREGISTER
93#endif
94#define _WORDREGISTER(regname)   \
95    __extension__ union \
96    { \
97        register16_t regname; \
98        struct \
99        { \
100            register8_t regname ## L; \
101            register8_t regname ## H; \
102        }; \
103    }
104
105#ifdef _DWORDREGISTER
106#undef _DWORDREGISTER
107#endif
108#define _DWORDREGISTER(regname)  \
109    __extension__ union \
110    { \
111        register32_t regname; \
112        struct \
113        { \
114            register8_t regname ## 0; \
115            register8_t regname ## 1; \
116            register8_t regname ## 2; \
117            register8_t regname ## 3; \
118        }; \
119    }
120
121
122/*
123==========================================================================
124IO Module Structures
125==========================================================================
126*/
127
128
129/*
130--------------------------------------------------------------------------
131XOCD - On-Chip Debug System
132--------------------------------------------------------------------------
133*/
134
135/* On-Chip Debug System */
136typedef struct OCD_struct
137{
138    register8_t OCDR0;  /* OCD Register 0 */
139    register8_t OCDR1;  /* OCD Register 1 */
140} OCD_t;
141
142
143/* CCP signatures */
144typedef enum CCP_enum
145{
146    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
147    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
148} CCP_t;
149
150
151/*
152--------------------------------------------------------------------------
153CLK - Clock System
154--------------------------------------------------------------------------
155*/
156
157/* Clock System */
158typedef struct CLK_struct
159{
160    register8_t CTRL;  /* Control Register */
161    register8_t PSCTRL;  /* Prescaler Control Register */
162    register8_t LOCK;  /* Lock register */
163    register8_t RTCCTRL;  /* RTC Control Register */
164} CLK_t;
165
166
167/* Power Reduction */
168typedef struct PR_struct
169{
170    register8_t PRGEN;  /* General Power Reduction */
171    register8_t PRPA;  /* Power Reduction Port A */
172    register8_t reserved_0x02;
173    register8_t PRPC;  /* Power Reduction Port C */
174    register8_t PRPD;  /* Power Reduction Port D */
175    register8_t PRPE;  /* Power Reduction Port E */
176    register8_t PRPF;  /* Power Reduction Port F */
177} PR_t;
178
179/* System Clock Selection */
180typedef enum CLK_SCLKSEL_enum
181{
182    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
183    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
184    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
185    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
186    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
187} CLK_SCLKSEL_t;
188
189/* Prescaler A Division Factor */
190typedef enum CLK_PSADIV_enum
191{
192    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
193    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
194    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
195    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
196    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
197    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
198    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
199    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
200    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
201    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
202} CLK_PSADIV_t;
203
204/* Prescaler B and C Division Factor */
205typedef enum CLK_PSBCDIV_enum
206{
207    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
208    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
209    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
210    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
211} CLK_PSBCDIV_t;
212
213/* RTC Clock Source */
214typedef enum CLK_RTCSRC_enum
215{
216    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
217    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
218    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
219    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
220} CLK_RTCSRC_t;
221
222
223/*
224--------------------------------------------------------------------------
225SLEEP - Sleep Controller
226--------------------------------------------------------------------------
227*/
228
229/* Sleep Controller */
230typedef struct SLEEP_struct
231{
232    register8_t CTRL;  /* Control Register */
233} SLEEP_t;
234
235/* Sleep Mode */
236typedef enum SLEEP_SMODE_enum
237{
238    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
239    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
240    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
241    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
242    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
243} SLEEP_SMODE_t;
244
245
246#define SLEEP_MODE_IDLE (0x00<<1)
247#define SLEEP_MODE_PWR_DOWN (0x02<<1)
248#define SLEEP_MODE_PWR_SAVE (0x03<<1)
249#define SLEEP_MODE_STANDBY (0x06<<1)
250#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
251
252
253/*
254--------------------------------------------------------------------------
255OSC - Oscillator
256--------------------------------------------------------------------------
257*/
258
259/* Oscillator */
260typedef struct OSC_struct
261{
262    register8_t CTRL;  /* Control Register */
263    register8_t STATUS;  /* Status Register */
264    register8_t XOSCCTRL;  /* External Oscillator Control Register */
265    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
266    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
267    register8_t PLLCTRL;  /* PLL Control REgister */
268    register8_t DFLLCTRL;  /* DFLL Control Register */
269} OSC_t;
270
271/* Oscillator Frequency Range */
272typedef enum OSC_FRQRANGE_enum
273{
274    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
275    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
276    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
277    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
278} OSC_FRQRANGE_t;
279
280/* External Oscillator Selection and Startup Time */
281typedef enum OSC_XOSCSEL_enum
282{
283    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
284    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
285    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
286    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
287    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
288} OSC_XOSCSEL_t;
289
290/* PLL Clock Source */
291typedef enum OSC_PLLSRC_enum
292{
293    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
294    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
295    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
296} OSC_PLLSRC_t;
297
298
299/*
300--------------------------------------------------------------------------
301DFLL - DFLL
302--------------------------------------------------------------------------
303*/
304
305/* DFLL */
306typedef struct DFLL_struct
307{
308    register8_t CTRL;  /* Control Register */
309    register8_t reserved_0x01;
310    register8_t CALA;  /* Calibration Register A */
311    register8_t CALB;  /* Calibration Register B */
312    register8_t COMP0;  /* Oscillator Compare Register 0 */
313    register8_t COMP1;  /* Oscillator Compare Register 1 */
314    register8_t COMP2;  /* Oscillator Compare Register 2 */
315    register8_t reserved_0x07;
316} DFLL_t;
317
318
319/*
320--------------------------------------------------------------------------
321RST - Reset
322--------------------------------------------------------------------------
323*/
324
325/* Reset */
326typedef struct RST_struct
327{
328    register8_t STATUS;  /* Status Register */
329    register8_t CTRL;  /* Control Register */
330} RST_t;
331
332
333/*
334--------------------------------------------------------------------------
335WDT - Watch-Dog Timer
336--------------------------------------------------------------------------
337*/
338
339/* Watch-Dog Timer */
340typedef struct WDT_struct
341{
342    register8_t CTRL;  /* Control */
343    register8_t WINCTRL;  /* Windowed Mode Control */
344    register8_t STATUS;  /* Status */
345} WDT_t;
346
347/* Period setting */
348typedef enum WDT_PER_enum
349{
350    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
351    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
352    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
353    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
354    WDT_PER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
355    WDT_PER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
356    WDT_PER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
357    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
358    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
359    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
360    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
361} WDT_PER_t;
362
363/* Closed window period */
364typedef enum WDT_WPER_enum
365{
366    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
367    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
368    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
369    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
370    WDT_WPER_125CLK_gc = (0x04<<2),  /* 125 cycles (0.125s @ 3.3V) */
371    WDT_WPER_250CLK_gc = (0x05<<2),  /* 250 cycles (0.25s @ 3.3V) */
372    WDT_WPER_500CLK_gc = (0x06<<2),  /* 500 cycles (0.5s @ 3.3V) */
373    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
374    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
375    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
376    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
377} WDT_WPER_t;
378
379
380/*
381--------------------------------------------------------------------------
382MCU - MCU Control
383--------------------------------------------------------------------------
384*/
385
386/* MCU Control */
387typedef struct MCU_struct
388{
389    register8_t DEVID0;  /* Device ID byte 0 */
390    register8_t DEVID1;  /* Device ID byte 1 */
391    register8_t DEVID2;  /* Device ID byte 2 */
392    register8_t REVID;  /* Revision ID */
393    register8_t JTAGUID;  /* JTAG User ID */
394    register8_t reserved_0x05;
395    register8_t MCUCR;  /* MCU Control */
396    register8_t reserved_0x07;
397    register8_t EVSYSLOCK;  /* Event System Lock */
398    register8_t AWEXLOCK;  /* AWEX Lock */
399    register8_t reserved_0x0A;
400    register8_t reserved_0x0B;
401} MCU_t;
402
403
404/*
405--------------------------------------------------------------------------
406PMIC - Programmable Multi-level Interrupt Controller
407--------------------------------------------------------------------------
408*/
409
410/* Programmable Multi-level Interrupt Controller */
411typedef struct PMIC_struct
412{
413    register8_t STATUS;  /* Status Register */
414    register8_t INTPRI;  /* Interrupt Priority */
415    register8_t CTRL;  /* Control Register */
416} PMIC_t;
417
418
419/*
420--------------------------------------------------------------------------
421CRC - Cyclic Redundancy Checker
422--------------------------------------------------------------------------
423*/
424
425/* Cyclic Redundancy Checker */
426typedef struct CRC_struct
427{
428    register8_t CTRL;  /* Control Register */
429    register8_t STATUS;  /* Status Register */
430    register8_t reserved_0x02;
431    register8_t DATAIN;  /* Data Input */
432    register8_t CHECKSUM0;  /* Checksum byte 0 */
433    register8_t CHECKSUM1;  /* Checksum byte 1 */
434    register8_t CHECKSUM2;  /* Checksum byte 2 */
435    register8_t CHECKSUM3;  /* Checksum byte 3 */
436} CRC_t;
437
438/* Reset */
439typedef enum CRC_RESET_enum
440{
441    CRC_RESET_NO_gc = (0x00<<6),  /* No Reset */
442    CRC_RESET_RESET0_gc = (0x02<<6),  /* Reset CRC with CHECKSUM to all zeros */
443    CRC_RESET_RESET1_gc = (0x03<<6),  /* Reset CRC with CHECKSUM to all ones */
444} CRC_RESET_t;
445
446/* Input Source */
447typedef enum CRC_SOURCE_enum
448{
449    CRC_SOURCE_DISABLE_gc = (0x00<<0),  /* Disabled */
450    CRC_SOURCE_IO_gc = (0x01<<0),  /* I/O Interface */
451    CRC_SOURCE_FLASH_gc = (0x02<<0),  /* Flash */
452    CRC_SOURCE_DMAC0_gc = (0x04<<0),  /* DMAC Channel 0 */
453    CRC_SOURCE_DMAC1_gc = (0x05<<0),  /* DMAC Channel 1 */
454    CRC_SOURCE_DMAC2_gc = (0x06<<0),  /* DMAC Channel 2 */
455    CRC_SOURCE_DMAC3_gc = (0x07<<0),  /* DMAC Channel 3 */
456} CRC_SOURCE_t;
457
458
459/*
460--------------------------------------------------------------------------
461EVSYS - Event System
462--------------------------------------------------------------------------
463*/
464
465/* Event System */
466typedef struct EVSYS_struct
467{
468    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
469    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
470    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
471    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
472    register8_t reserved_0x04;
473    register8_t reserved_0x05;
474    register8_t reserved_0x06;
475    register8_t reserved_0x07;
476    register8_t CH0CTRL;  /* Channel 0 Control Register */
477    register8_t CH1CTRL;  /* Channel 1 Control Register */
478    register8_t CH2CTRL;  /* Channel 2 Control Register */
479    register8_t CH3CTRL;  /* Channel 3 Control Register */
480    register8_t reserved_0x0C;
481    register8_t reserved_0x0D;
482    register8_t reserved_0x0E;
483    register8_t reserved_0x0F;
484    register8_t STROBE;  /* Event Strobe */
485    register8_t DATA;  /* Event Data */
486} EVSYS_t;
487
488/* Quadrature Decoder Index Recognition Mode */
489typedef enum EVSYS_QDIRM_enum
490{
491    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
492    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
493    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
494    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
495} EVSYS_QDIRM_t;
496
497/* Digital filter coefficient */
498typedef enum EVSYS_DIGFILT_enum
499{
500    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
501    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
502    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
503    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
504    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
505    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
506    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
507    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
508} EVSYS_DIGFILT_t;
509
510/* Event Channel multiplexer input selection */
511typedef enum EVSYS_CHMUX_enum
512{
513    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
514    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
515    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
516    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
517    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
518    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
519    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
520    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
521    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
522    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
523    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
524    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
525    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
526    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
527    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
528    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
529    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
530    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
531    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
532    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
533    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
534    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
535    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
536    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
537    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
538    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
539    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
540    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
541    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
542    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
543    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
544    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
545    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
546    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
547    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
548    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
549    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
550    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
551    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
552    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
553    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
554    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
555    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
556    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
557    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
558    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
559    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
560    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
561    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
562    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
563    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
564    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
565    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
566    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
567    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
568    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
569    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
570    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
571    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
572    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
573    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
574    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
575    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
576    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
577    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
578    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
579    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
580    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
581    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
582    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
583    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
584    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
585    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
586    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
587    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
588    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
589    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
590    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
591    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
592    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
593    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
594    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
595    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
596    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
597    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
598    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
599    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
600    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
601    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
602    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
603    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
604    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
605    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
606    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
607    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
608    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
609    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
610    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
611    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
612    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
613    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
614    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
615    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
616    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
617    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
618    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
619    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
620    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
621    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
622    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
623    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
624} EVSYS_CHMUX_t;
625
626
627/*
628--------------------------------------------------------------------------
629NVM - Non Volatile Memory Controller
630--------------------------------------------------------------------------
631*/
632
633/* Non-volatile Memory Controller */
634typedef struct NVM_struct
635{
636    register8_t ADDR0;  /* Address Register 0 */
637    register8_t ADDR1;  /* Address Register 1 */
638    register8_t ADDR2;  /* Address Register 2 */
639    register8_t reserved_0x03;
640    register8_t DATA0;  /* Data Register 0 */
641    register8_t DATA1;  /* Data Register 1 */
642    register8_t DATA2;  /* Data Register 2 */
643    register8_t reserved_0x07;
644    register8_t reserved_0x08;
645    register8_t reserved_0x09;
646    register8_t CMD;  /* Command */
647    register8_t CTRLA;  /* Control Register A */
648    register8_t CTRLB;  /* Control Register B */
649    register8_t INTCTRL;  /* Interrupt Control */
650    register8_t reserved_0x0E;
651    register8_t STATUS;  /* Status */
652    register8_t LOCK_BITS;  /* Lock Bits */
653} NVM_t;
654
655/*
656--------------------------------------------------------------------------
657NVM - Non Volatile Memory Controller
658--------------------------------------------------------------------------
659*/
660
661/* Lock Bits */
662typedef struct NVM_LOCKBITS_struct
663{
664    register8_t LOCKBITS;  /* Lock Bits */
665} NVM_LOCKBITS_t;
666
667/*
668--------------------------------------------------------------------------
669NVM - Non Volatile Memory Controller
670--------------------------------------------------------------------------
671*/
672
673/* Fuses */
674typedef struct NVM_FUSES_struct
675{
676    register8_t FUSEBYTE0;  /* User ID */
677    register8_t FUSEBYTE1;  /* Watchdog Configuration */
678    register8_t FUSEBYTE2;  /* Reset Configuration */
679    register8_t reserved_0x03;
680    register8_t FUSEBYTE4;  /* Start-up Configuration */
681    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
682} NVM_FUSES_t;
683
684/*
685--------------------------------------------------------------------------
686NVM - Non Volatile Memory Controller
687--------------------------------------------------------------------------
688*/
689
690/* Production Signatures */
691typedef struct NVM_PROD_SIGNATURES_struct
692{
693    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
694    register8_t reserved_0x01;
695    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
696    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
697    register8_t reserved_0x04;
698    register8_t reserved_0x05;
699    register8_t reserved_0x06;
700    register8_t reserved_0x07;
701    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
702    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
703    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
704    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
705    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
706    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
707    register8_t reserved_0x0E;
708    register8_t reserved_0x0F;
709    register8_t WAFNUM;  /* Wafer Number */
710    register8_t reserved_0x11;
711    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
712    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
713    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
714    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
715    register8_t reserved_0x16;
716    register8_t reserved_0x17;
717    register8_t reserved_0x18;
718    register8_t reserved_0x19;
719    register8_t reserved_0x1A;
720    register8_t reserved_0x1B;
721    register8_t reserved_0x1C;
722    register8_t reserved_0x1D;
723    register8_t reserved_0x1E;
724    register8_t reserved_0x1F;
725    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
726    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
727    register8_t reserved_0x22;
728    register8_t reserved_0x23;
729    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
730    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
731    register8_t reserved_0x26;
732    register8_t reserved_0x27;
733    register8_t reserved_0x28;
734    register8_t reserved_0x29;
735    register8_t reserved_0x2A;
736    register8_t reserved_0x2B;
737    register8_t reserved_0x2C;
738    register8_t reserved_0x2D;
739    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
740    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
741    register8_t reserved_0x30;
742    register8_t reserved_0x31;
743    register8_t reserved_0x32;
744    register8_t reserved_0x33;
745    register8_t reserved_0x34;
746    register8_t reserved_0x35;
747    register8_t reserved_0x36;
748    register8_t reserved_0x37;
749    register8_t reserved_0x38;
750    register8_t reserved_0x39;
751    register8_t reserved_0x3A;
752    register8_t reserved_0x3B;
753    register8_t reserved_0x3C;
754    register8_t reserved_0x3D;
755    register8_t reserved_0x3E;
756} NVM_PROD_SIGNATURES_t;
757
758/* NVM Command */
759typedef enum NVM_CMD_enum
760{
761    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
762    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
763    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
764    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
765    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
766    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
767    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
768    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
769    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
770    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
771    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
772    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
773    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
774    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
775    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
776    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
777    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
778    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
779    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
780    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
781    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
782    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
783    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
784    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
785    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
786    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
787} NVM_CMD_t;
788
789/* SPM ready interrupt level */
790typedef enum NVM_SPMLVL_enum
791{
792    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
793    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
794    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
795    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
796} NVM_SPMLVL_t;
797
798/* EEPROM ready interrupt level */
799typedef enum NVM_EELVL_enum
800{
801    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
802    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
803    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
804    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
805} NVM_EELVL_t;
806
807/* Boot lock bits - boot setcion */
808typedef enum NVM_BLBB_enum
809{
810    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
811    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
812    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
813    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
814} NVM_BLBB_t;
815
816/* Boot lock bits - application section */
817typedef enum NVM_BLBA_enum
818{
819    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
820    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
821    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
822    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
823} NVM_BLBA_t;
824
825/* Boot lock bits - application table section */
826typedef enum NVM_BLBAT_enum
827{
828    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
829    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
830    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
831    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
832} NVM_BLBAT_t;
833
834/* Lock bits */
835typedef enum NVM_LB_enum
836{
837    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
838    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
839    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
840} NVM_LB_t;
841
842/* Boot Loader Section Reset Vector */
843typedef enum BOOTRST_enum
844{
845    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
846    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
847} BOOTRST_t;
848
849/* BOD operation */
850typedef enum BOD_enum
851{
852    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
853    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
854    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
855} BOD_t;
856
857/* Watchdog (Window) Timeout Period */
858typedef enum WD_enum
859{
860    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
861    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
862    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
863    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
864    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
865    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
866    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
867    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
868    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
869    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
870    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
871} WD_t;
872
873/* Start-up Time */
874typedef enum SUT_enum
875{
876    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
877    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
878    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
879} SUT_t;
880
881/* Brown Out Detection Voltage Level */
882typedef enum BODLVL_enum
883{
884    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
885    BODLVL_1V8_gc = (0x06<<0),  /* 1.8 V */
886    BODLVL_2V0_gc = (0x05<<0),  /* 2.0 V */
887    BODLVL_2V2_gc = (0x04<<0),  /* 2.2 V */
888    BODLVL_2V4_gc = (0x03<<0),  /* 2.4 V */
889    BODLVL_2V6_gc = (0x02<<0),  /* 2.6 V */
890    BODLVL_2V8_gc = (0x01<<0),  /* 2.8 V */
891    BODLVL_3V0_gc = (0x00<<0),  /* 3.0 V */
892} BODLVL_t;
893
894
895/*
896--------------------------------------------------------------------------
897AC - Analog Comparator
898--------------------------------------------------------------------------
899*/
900
901/* Analog Comparator */
902typedef struct AC_struct
903{
904    register8_t AC0CTRL;  /* Comparator 0 Control */
905    register8_t AC1CTRL;  /* Comparator 1 Control */
906    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
907    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
908    register8_t CTRLA;  /* Control Register A */
909    register8_t CTRLB;  /* Control Register B */
910    register8_t WINCTRL;  /* Window Mode Control */
911    register8_t STATUS;  /* Status */
912} AC_t;
913
914/* Interrupt mode */
915typedef enum AC_INTMODE_enum
916{
917    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
918    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
919    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
920} AC_INTMODE_t;
921
922/* Interrupt level */
923typedef enum AC_INTLVL_enum
924{
925    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
926    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
927    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
928    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
929} AC_INTLVL_t;
930
931/* Hysteresis mode selection */
932typedef enum AC_HYSMODE_enum
933{
934    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
935    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
936    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
937} AC_HYSMODE_t;
938
939/* Positive input multiplexer selection */
940typedef enum AC_MUXPOS_enum
941{
942    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
943    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
944    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
945    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
946    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
947    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
948    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
949} AC_MUXPOS_t;
950
951/* Negative input multiplexer selection */
952typedef enum AC_MUXNEG_enum
953{
954    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
955    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
956    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
957    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
958    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
959    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
960    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
961} AC_MUXNEG_t;
962
963/* Windows interrupt mode */
964typedef enum AC_WINTMODE_enum
965{
966    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
967    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
968    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
969    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
970} AC_WINTMODE_t;
971
972/* Window interrupt level */
973typedef enum AC_WINTLVL_enum
974{
975    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
976    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
977    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
978    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
979} AC_WINTLVL_t;
980
981/* Window mode state */
982typedef enum AC_WSTATE_enum
983{
984    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
985    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
986    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
987} AC_WSTATE_t;
988
989
990/*
991--------------------------------------------------------------------------
992ADC - Analog/Digital Converter
993--------------------------------------------------------------------------
994*/
995
996/* ADC Channel */
997typedef struct ADC_CH_struct
998{
999    register8_t CTRL;  /* Control Register */
1000    register8_t MUXCTRL;  /* MUX Control */
1001    register8_t INTCTRL;  /* Channel Interrupt Control */
1002    register8_t INTFLAGS;  /* Interrupt Flags */
1003    _WORDREGISTER(RES);  /* Channel Result */
1004    register8_t reserved_0x6;
1005    register8_t reserved_0x7;
1006} ADC_CH_t;
1007
1008/*
1009--------------------------------------------------------------------------
1010ADC - Analog/Digital Converter
1011--------------------------------------------------------------------------
1012*/
1013
1014/* Analog-to-Digital Converter */
1015typedef struct ADC_struct
1016{
1017    register8_t CTRLA;  /* Control Register A */
1018    register8_t CTRLB;  /* Control Register B */
1019    register8_t REFCTRL;  /* Reference Control */
1020    register8_t EVCTRL;  /* Event Control */
1021    register8_t PRESCALER;  /* Clock Prescaler */
1022    register8_t reserved_0x05;
1023    register8_t INTFLAGS;  /* Interrupt Flags */
1024    register8_t TEMP;  /* ACD Temporary Register */
1025    register8_t reserved_0x08;
1026    register8_t reserved_0x09;
1027    register8_t reserved_0x0A;
1028    register8_t reserved_0x0B;
1029    _WORDREGISTER(CAL);  /* Calibration Value */
1030    register8_t reserved_0x0E;
1031    register8_t reserved_0x0F;
1032    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
1033    register8_t reserved_0x12;
1034    register8_t reserved_0x13;
1035    register8_t reserved_0x14;
1036    register8_t reserved_0x15;
1037    register8_t reserved_0x16;
1038    register8_t reserved_0x17;
1039    _WORDREGISTER(CMP);  /* Compare Value */
1040    register8_t reserved_0x1A;
1041    register8_t reserved_0x1B;
1042    register8_t reserved_0x1C;
1043    register8_t reserved_0x1D;
1044    register8_t reserved_0x1E;
1045    register8_t reserved_0x1F;
1046    ADC_CH_t CH0;  /* ADC Channel 0 */
1047} ADC_t;
1048
1049/* Current Limitation */
1050typedef enum ADC_CURRLIMIT_enum
1051{
1052    ADC_CURRLIMIT_NO_gc = (0x00<<5),  /* No current limit,     300ksps max sampling rate */
1053    ADC_CURRLIMIT_LOW_gc = (0x01<<5),  /* Low current limit,    225ksps max sampling rate */
1054    ADC_CURRLIMIT_MED_gc = (0x02<<5),  /* Medium current limit, 150ksps max sampling rate */
1055    ADC_CURRLIMIT_HIGH_gc = (0x03<<5),  /* High current limit,   75ksps max sampling rate */
1056} ADC_CURRLIMIT_t;
1057
1058/* Positive input multiplexer selection */
1059typedef enum ADC_CH_MUXPOS_enum
1060{
1061    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
1062    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
1063    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
1064    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
1065    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
1066    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
1067    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
1068    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
1069} ADC_CH_MUXPOS_t;
1070
1071/* Negative input multiplexer selection */
1072typedef enum ADC_CH_MUXNEG_enum
1073{
1074    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
1075    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
1076    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
1077    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
1078    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
1079    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
1080    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
1081    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
1082} ADC_CH_MUXNEG_t;
1083
1084/* Input mode */
1085typedef enum ADC_CH_INPUTMODE_enum
1086{
1087    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
1088    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
1089    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
1090    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
1091} ADC_CH_INPUTMODE_t;
1092
1093/* Gain factor */
1094typedef enum ADC_CH_GAIN_enum
1095{
1096    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
1097    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
1098    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
1099    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
1100    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
1101    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
1102    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
1103    ADC_CH_GAIN_DIV2_gc = (0x07<<2),  /* x/2 gain */           
1104} ADC_CH_GAIN_t;
1105
1106/* Conversion result resolution */
1107typedef enum ADC_RESOLUTION_enum
1108{
1109    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
1110    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
1111    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
1112} ADC_RESOLUTION_t;
1113
1114/* Voltage reference selection */
1115typedef enum ADC_REFSEL_enum
1116{
1117    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
1118    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC/1.6V */
1119    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
1120    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
1121} ADC_REFSEL_t;
1122
1123/* Event channel input selection */
1124typedef enum ADC_EVSEL_enum
1125{
1126    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
1127    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
1128    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
1129    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
1130    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
1131    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
1132    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
1133    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
1134} ADC_EVSEL_t;
1135
1136/* Event action selection */
1137typedef enum ADC_EVACT_enum
1138{
1139    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
1140    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
1141} ADC_EVACT_t;
1142
1143/* Interupt mode */
1144typedef enum ADC_CH_INTMODE_enum
1145{
1146    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
1147    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
1148    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
1149} ADC_CH_INTMODE_t;
1150
1151/* Interrupt level */
1152typedef enum ADC_CH_INTLVL_enum
1153{
1154    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
1155    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
1156    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
1157    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
1158} ADC_CH_INTLVL_t;
1159
1160/* Clock prescaler */
1161typedef enum ADC_PRESCALER_enum
1162{
1163    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
1164    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
1165    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
1166    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
1167    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
1168    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
1169    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
1170    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
1171} ADC_PRESCALER_t;
1172
1173
1174/*
1175--------------------------------------------------------------------------
1176RTC - Real-Time Clounter
1177--------------------------------------------------------------------------
1178*/
1179
1180/* Real-Time Counter */
1181typedef struct RTC_struct
1182{
1183    register8_t CTRL;  /* Control Register */
1184    register8_t STATUS;  /* Status Register */
1185    register8_t INTCTRL;  /* Interrupt Control Register */
1186    register8_t INTFLAGS;  /* Interrupt Flags */
1187    register8_t TEMP;  /* Temporary register */
1188    register8_t reserved_0x05;
1189    register8_t reserved_0x06;
1190    register8_t reserved_0x07;
1191    _WORDREGISTER(CNT);  /* Count Register */
1192    _WORDREGISTER(PER);  /* Period Register */
1193    _WORDREGISTER(COMP);  /* Compare Register */
1194} RTC_t;
1195
1196/* Prescaler Factor */
1197typedef enum RTC_PRESCALER_enum
1198{
1199    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
1200    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
1201    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
1202    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
1203    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
1204    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
1205    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
1206    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
1207} RTC_PRESCALER_t;
1208
1209/* Compare Interrupt level */
1210typedef enum RTC_COMPINTLVL_enum
1211{
1212    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1213    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1214    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1215    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
1216} RTC_COMPINTLVL_t;
1217
1218/* Overflow Interrupt level */
1219typedef enum RTC_OVFINTLVL_enum
1220{
1221    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1222    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1223    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1224    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
1225} RTC_OVFINTLVL_t;
1226
1227
1228/*
1229--------------------------------------------------------------------------
1230EBI - External Bus Interface
1231--------------------------------------------------------------------------
1232*/
1233
1234/* EBI Chip Select Module */
1235typedef struct EBI_CS_struct
1236{
1237    register8_t CTRLA;  /* Chip Select Control Register A */
1238    register8_t CTRLB;  /* Chip Select Control Register B */
1239    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
1240} EBI_CS_t;
1241
1242/*
1243--------------------------------------------------------------------------
1244EBI - External Bus Interface
1245--------------------------------------------------------------------------
1246*/
1247
1248/* External Bus Interface */
1249typedef struct EBI_struct
1250{
1251    register8_t CTRL;  /* Control */
1252    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
1253    register8_t reserved_0x02;
1254    register8_t reserved_0x03;
1255    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
1256    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
1257    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
1258    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
1259    register8_t reserved_0x0A;
1260    register8_t reserved_0x0B;
1261    register8_t reserved_0x0C;
1262    register8_t reserved_0x0D;
1263    register8_t reserved_0x0E;
1264    register8_t reserved_0x0F;
1265    EBI_CS_t CS0;  /* Chip Select 0 */
1266    EBI_CS_t CS1;  /* Chip Select 1 */
1267    EBI_CS_t CS2;  /* Chip Select 2 */
1268    EBI_CS_t CS3;  /* Chip Select 3 */
1269} EBI_t;
1270
1271/* Chip Select adress space */
1272typedef enum EBI_CS_ASIZE_enum
1273{
1274    EBI_CS_ASIZE_256B_gc = (0x00<<2),  /* 256 bytes */
1275    EBI_CS_ASIZE_512B_gc = (0x01<<2),  /* 512 bytes */
1276    EBI_CS_ASIZE_1KB_gc = (0x02<<2),  /* 1K bytes */
1277    EBI_CS_ASIZE_2KB_gc = (0x03<<2),  /* 2K bytes */
1278    EBI_CS_ASIZE_4KB_gc = (0x04<<2),  /* 4K bytes */
1279    EBI_CS_ASIZE_8KB_gc = (0x05<<2),  /* 8K bytes */
1280    EBI_CS_ASIZE_16KB_gc = (0x06<<2),  /* 16K bytes */
1281    EBI_CS_ASIZE_32KB_gc = (0x07<<2),  /* 32K bytes */
1282    EBI_CS_ASIZE_64KB_gc = (0x08<<2),  /* 64K bytes */
1283    EBI_CS_ASIZE_128KB_gc = (0x09<<2),  /* 128K bytes */
1284    EBI_CS_ASIZE_256KB_gc = (0x0A<<2),  /* 256K bytes */
1285    EBI_CS_ASIZE_512KB_gc = (0x0B<<2),  /* 512K bytes */
1286    EBI_CS_ASIZE_1MB_gc = (0x0C<<2),  /* 1M bytes */
1287    EBI_CS_ASIZE_2MB_gc = (0x0D<<2),  /* 2M bytes */
1288    EBI_CS_ASIZE_4MB_gc = (0x0E<<2),  /* 4M bytes */
1289    EBI_CS_ASIZE_8MB_gc = (0x0F<<2),  /* 8M bytes */
1290    EBI_CS_ASIZE_16M_gc = (0x10<<2),  /* 16M bytes */
1291} EBI_CS_ASIZE_t;
1292
1293/*  */
1294typedef enum EBI_CS_SRWS_enum
1295{
1296    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
1297    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
1298    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
1299    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
1300    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
1301    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
1302    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
1303    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
1304} EBI_CS_SRWS_t;
1305
1306/* Chip Select address mode */
1307typedef enum EBI_CS_MODE_enum
1308{
1309    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
1310    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
1311    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
1312    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
1313} EBI_CS_MODE_t;
1314
1315/* Chip Select SDRAM mode */
1316typedef enum EBI_CS_SDMODE_enum
1317{
1318    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
1319    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
1320} EBI_CS_SDMODE_t;
1321
1322/*  */
1323typedef enum EBI_SDDATAW_enum
1324{
1325    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
1326    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
1327} EBI_SDDATAW_t;
1328
1329/*  */
1330typedef enum EBI_LPCMODE_enum
1331{
1332    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
1333    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
1334} EBI_LPCMODE_t;
1335
1336/*  */
1337typedef enum EBI_SRMODE_enum
1338{
1339    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
1340    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
1341    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
1342    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
1343} EBI_SRMODE_t;
1344
1345/*  */
1346typedef enum EBI_IFMODE_enum
1347{
1348    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
1349    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
1350    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
1351    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
1352} EBI_IFMODE_t;
1353
1354/*  */
1355typedef enum EBI_SDCOL_enum
1356{
1357    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
1358    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
1359    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
1360    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
1361} EBI_SDCOL_t;
1362
1363/*  */
1364typedef enum EBI_MRDLY_enum
1365{
1366    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
1367    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
1368    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
1369    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
1370} EBI_MRDLY_t;
1371
1372/*  */
1373typedef enum EBI_ROWCYCDLY_enum
1374{
1375    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
1376    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
1377    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
1378    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
1379    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
1380    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
1381    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
1382    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
1383} EBI_ROWCYCDLY_t;
1384
1385/*  */
1386typedef enum EBI_RPDLY_enum
1387{
1388    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
1389    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
1390    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
1391    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
1392    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
1393    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
1394    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
1395    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
1396} EBI_RPDLY_t;
1397
1398/*  */
1399typedef enum EBI_WRDLY_enum
1400{
1401    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
1402    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
1403    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
1404    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
1405} EBI_WRDLY_t;
1406
1407/*  */
1408typedef enum EBI_ESRDLY_enum
1409{
1410    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
1411    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
1412    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
1413    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
1414    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
1415    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
1416    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
1417    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
1418} EBI_ESRDLY_t;
1419
1420/*  */
1421typedef enum EBI_ROWCOLDLY_enum
1422{
1423    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
1424    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
1425    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
1426    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
1427    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
1428    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
1429    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
1430    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
1431} EBI_ROWCOLDLY_t;
1432
1433
1434/*
1435--------------------------------------------------------------------------
1436TWI - Two-Wire Interface
1437--------------------------------------------------------------------------
1438*/
1439
1440/*  */
1441typedef struct TWI_MASTER_struct
1442{
1443    register8_t CTRLA;  /* Control Register A */
1444    register8_t CTRLB;  /* Control Register B */
1445    register8_t CTRLC;  /* Control Register C */
1446    register8_t STATUS;  /* Status Register */
1447    register8_t BAUD;  /* Baurd Rate Control Register */
1448    register8_t ADDR;  /* Address Register */
1449    register8_t DATA;  /* Data Register */
1450} TWI_MASTER_t;
1451
1452/*
1453--------------------------------------------------------------------------
1454TWI - Two-Wire Interface
1455--------------------------------------------------------------------------
1456*/
1457
1458/*  */
1459typedef struct TWI_SLAVE_struct
1460{
1461    register8_t CTRLA;  /* Control Register A */
1462    register8_t CTRLB;  /* Control Register B */
1463    register8_t STATUS;  /* Status Register */
1464    register8_t ADDR;  /* Address Register */
1465    register8_t DATA;  /* Data Register */
1466    register8_t ADDRMASK;  /* Address Mask Register */
1467} TWI_SLAVE_t;
1468
1469/*
1470--------------------------------------------------------------------------
1471TWI - Two-Wire Interface
1472--------------------------------------------------------------------------
1473*/
1474
1475/* Two-Wire Interface */
1476typedef struct TWI_struct
1477{
1478    register8_t CTRL;  /* TWI Common Control Register */
1479    TWI_MASTER_t MASTER;  /* TWI master module */
1480    TWI_SLAVE_t SLAVE;  /* TWI slave module */
1481} TWI_t;
1482
1483/* Master Interrupt Level */
1484typedef enum TWI_MASTER_INTLVL_enum
1485{
1486    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1487    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
1488    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1489    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
1490} TWI_MASTER_INTLVL_t;
1491
1492/* Inactive Timeout */
1493typedef enum TWI_MASTER_TIMEOUT_enum
1494{
1495    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
1496    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
1497    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
1498    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
1499} TWI_MASTER_TIMEOUT_t;
1500
1501/* Master Command */
1502typedef enum TWI_MASTER_CMD_enum
1503{
1504    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
1505    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
1506    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
1507    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
1508} TWI_MASTER_CMD_t;
1509
1510/* Master Bus State */
1511typedef enum TWI_MASTER_BUSSTATE_enum
1512{
1513    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
1514    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
1515    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
1516    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
1517} TWI_MASTER_BUSSTATE_t;
1518
1519/* Slave Interrupt Level */
1520typedef enum TWI_SLAVE_INTLVL_enum
1521{
1522    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1523    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
1524    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1525    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
1526} TWI_SLAVE_INTLVL_t;
1527
1528/* Slave Command */
1529typedef enum TWI_SLAVE_CMD_enum
1530{
1531    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
1532    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
1533    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
1534} TWI_SLAVE_CMD_t;
1535
1536
1537/*
1538--------------------------------------------------------------------------
1539PORT - Port Configuration
1540--------------------------------------------------------------------------
1541*/
1542
1543/* I/O port Configuration */
1544typedef struct PORTCFG_struct
1545{
1546    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
1547    register8_t reserved_0x01;
1548    register8_t VPCTRLA;  /* Virtual Port Control Register A */
1549    register8_t VPCTRLB;  /* Virtual Port Control Register B */
1550    register8_t CLKEVOUT;  /* Clock and Event Out Register */
1551} PORTCFG_t;
1552
1553/*
1554--------------------------------------------------------------------------
1555PORT - Port Configuration
1556--------------------------------------------------------------------------
1557*/
1558
1559/* Virtual Port */
1560typedef struct VPORT_struct
1561{
1562    register8_t DIR;  /* I/O Port Data Direction */
1563    register8_t OUT;  /* I/O Port Output */
1564    register8_t IN;  /* I/O Port Input */
1565    register8_t INTFLAGS;  /* Interrupt Flag Register */
1566} VPORT_t;
1567
1568/*
1569--------------------------------------------------------------------------
1570PORT - Port Configuration
1571--------------------------------------------------------------------------
1572*/
1573
1574/* I/O Ports */
1575typedef struct PORT_struct
1576{
1577    register8_t DIR;  /* I/O Port Data Direction */
1578    register8_t DIRSET;  /* I/O Port Data Direction Set */
1579    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
1580    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
1581    register8_t OUT;  /* I/O Port Output */
1582    register8_t OUTSET;  /* I/O Port Output Set */
1583    register8_t OUTCLR;  /* I/O Port Output Clear */
1584    register8_t OUTTGL;  /* I/O Port Output Toggle */
1585    register8_t IN;  /* I/O port Input */
1586    register8_t INTCTRL;  /* Interrupt Control Register */
1587    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
1588    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
1589    register8_t INTFLAGS;  /* Interrupt Flag Register */
1590    register8_t reserved_0x0D;
1591    register8_t reserved_0x0E;
1592    register8_t reserved_0x0F;
1593    register8_t PIN0CTRL;  /* Pin 0 Control Register */
1594    register8_t PIN1CTRL;  /* Pin 1 Control Register */
1595    register8_t PIN2CTRL;  /* Pin 2 Control Register */
1596    register8_t PIN3CTRL;  /* Pin 3 Control Register */
1597    register8_t PIN4CTRL;  /* Pin 4 Control Register */
1598    register8_t PIN5CTRL;  /* Pin 5 Control Register */
1599    register8_t PIN6CTRL;  /* Pin 6 Control Register */
1600    register8_t PIN7CTRL;  /* Pin 7 Control Register */
1601} PORT_t;
1602
1603/* Virtual Port 0 Mapping */
1604typedef enum PORTCFG_VP0MAP_enum
1605{
1606    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
1607    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
1608    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
1609    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
1610    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
1611    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
1612    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
1613    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
1614    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
1615    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
1616    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
1617    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
1618    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
1619    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
1620    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
1621    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
1622} PORTCFG_VP0MAP_t;
1623
1624/* Virtual Port 1 Mapping */
1625typedef enum PORTCFG_VP1MAP_enum
1626{
1627    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
1628    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
1629    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
1630    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
1631    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
1632    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
1633    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
1634    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
1635    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
1636    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
1637    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
1638    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
1639    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
1640    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
1641    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
1642    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
1643} PORTCFG_VP1MAP_t;
1644
1645/* Virtual Port 2 Mapping */
1646typedef enum PORTCFG_VP2MAP_enum
1647{
1648    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
1649    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
1650    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
1651    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
1652    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
1653    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
1654    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
1655    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
1656    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
1657    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
1658    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
1659    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
1660    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
1661    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
1662    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
1663    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
1664} PORTCFG_VP2MAP_t;
1665
1666/* Virtual Port 3 Mapping */
1667typedef enum PORTCFG_VP3MAP_enum
1668{
1669    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
1670    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
1671    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
1672    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
1673    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
1674    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
1675    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
1676    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
1677    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
1678    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
1679    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
1680    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
1681    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
1682    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
1683    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
1684    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
1685} PORTCFG_VP3MAP_t;
1686
1687/* Clock Output Port */
1688typedef enum PORTCFG_CLKOUT_enum
1689{
1690    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
1691    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
1692    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
1693    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
1694} PORTCFG_CLKOUT_t;
1695
1696/* Event Output Port */
1697typedef enum PORTCFG_EVOUT_enum
1698{
1699    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
1700    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
1701    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
1702    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
1703} PORTCFG_EVOUT_t;
1704
1705/* Port Interrupt 0 Level */
1706typedef enum PORT_INT0LVL_enum
1707{
1708    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1709    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
1710    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
1711    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
1712} PORT_INT0LVL_t;
1713
1714/* Port Interrupt 1 Level */
1715typedef enum PORT_INT1LVL_enum
1716{
1717    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1718    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
1719    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
1720    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
1721} PORT_INT1LVL_t;
1722
1723/* Output/Pull Configuration */
1724typedef enum PORT_OPC_enum
1725{
1726    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
1727    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
1728    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
1729    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
1730    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
1731    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
1732    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
1733    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
1734} PORT_OPC_t;
1735
1736/* Input/Sense Configuration */
1737typedef enum PORT_ISC_enum
1738{
1739    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
1740    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
1741    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
1742    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
1743    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
1744} PORT_ISC_t;
1745
1746
1747/*
1748--------------------------------------------------------------------------
1749TC - 16-bit Timer/Counter With PWM
1750--------------------------------------------------------------------------
1751*/
1752
1753/* 16-bit Timer/Counter 0 */
1754typedef struct TC0_struct
1755{
1756    register8_t CTRLA;  /* Control  Register A */
1757    register8_t CTRLB;  /* Control Register B */
1758    register8_t CTRLC;  /* Control register C */
1759    register8_t CTRLD;  /* Control Register D */
1760    register8_t CTRLE;  /* Control Register E */
1761    register8_t reserved_0x05;
1762    register8_t INTCTRLA;  /* Interrupt Control Register A */
1763    register8_t INTCTRLB;  /* Interrupt Control Register B */
1764    register8_t CTRLFCLR;  /* Control Register F Clear */
1765    register8_t CTRLFSET;  /* Control Register F Set */
1766    register8_t CTRLGCLR;  /* Control Register G Clear */
1767    register8_t CTRLGSET;  /* Control Register G Set */
1768    register8_t INTFLAGS;  /* Interrupt Flag Register */
1769    register8_t reserved_0x0D;
1770    register8_t reserved_0x0E;
1771    register8_t TEMP;  /* Temporary Register For 16-bit Access */
1772    register8_t reserved_0x10;
1773    register8_t reserved_0x11;
1774    register8_t reserved_0x12;
1775    register8_t reserved_0x13;
1776    register8_t reserved_0x14;
1777    register8_t reserved_0x15;
1778    register8_t reserved_0x16;
1779    register8_t reserved_0x17;
1780    register8_t reserved_0x18;
1781    register8_t reserved_0x19;
1782    register8_t reserved_0x1A;
1783    register8_t reserved_0x1B;
1784    register8_t reserved_0x1C;
1785    register8_t reserved_0x1D;
1786    register8_t reserved_0x1E;
1787    register8_t reserved_0x1F;
1788    _WORDREGISTER(CNT);  /* Count */
1789    register8_t reserved_0x22;
1790    register8_t reserved_0x23;
1791    register8_t reserved_0x24;
1792    register8_t reserved_0x25;
1793    _WORDREGISTER(PER);  /* Period */
1794    _WORDREGISTER(CCA);  /* Compare or Capture A */
1795    _WORDREGISTER(CCB);  /* Compare or Capture B */
1796    _WORDREGISTER(CCC);  /* Compare or Capture C */
1797    _WORDREGISTER(CCD);  /* Compare or Capture D */
1798    register8_t reserved_0x30;
1799    register8_t reserved_0x31;
1800    register8_t reserved_0x32;
1801    register8_t reserved_0x33;
1802    register8_t reserved_0x34;
1803    register8_t reserved_0x35;
1804    _WORDREGISTER(PERBUF);  /* Period Buffer */
1805    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
1806    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
1807    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
1808    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
1809} TC0_t;
1810
1811/*
1812--------------------------------------------------------------------------
1813TC - 16-bit Timer/Counter With PWM
1814--------------------------------------------------------------------------
1815*/
1816
1817/* 16-bit Timer/Counter 1 */
1818typedef struct TC1_struct
1819{
1820    register8_t CTRLA;  /* Control  Register A */
1821    register8_t CTRLB;  /* Control Register B */
1822    register8_t CTRLC;  /* Control register C */
1823    register8_t CTRLD;  /* Control Register D */
1824    register8_t CTRLE;  /* Control Register E */
1825    register8_t reserved_0x05;
1826    register8_t INTCTRLA;  /* Interrupt Control Register A */
1827    register8_t INTCTRLB;  /* Interrupt Control Register B */
1828    register8_t CTRLFCLR;  /* Control Register F Clear */
1829    register8_t CTRLFSET;  /* Control Register F Set */
1830    register8_t CTRLGCLR;  /* Control Register G Clear */
1831    register8_t CTRLGSET;  /* Control Register G Set */
1832    register8_t INTFLAGS;  /* Interrupt Flag Register */
1833    register8_t reserved_0x0D;
1834    register8_t reserved_0x0E;
1835    register8_t TEMP;  /* Temporary Register For 16-bit Access */
1836    register8_t reserved_0x10;
1837    register8_t reserved_0x11;
1838    register8_t reserved_0x12;
1839    register8_t reserved_0x13;
1840    register8_t reserved_0x14;
1841    register8_t reserved_0x15;
1842    register8_t reserved_0x16;
1843    register8_t reserved_0x17;
1844    register8_t reserved_0x18;
1845    register8_t reserved_0x19;
1846    register8_t reserved_0x1A;
1847    register8_t reserved_0x1B;
1848    register8_t reserved_0x1C;
1849    register8_t reserved_0x1D;
1850    register8_t reserved_0x1E;
1851    register8_t reserved_0x1F;
1852    _WORDREGISTER(CNT);  /* Count */
1853    register8_t reserved_0x22;
1854    register8_t reserved_0x23;
1855    register8_t reserved_0x24;
1856    register8_t reserved_0x25;
1857    _WORDREGISTER(PER);  /* Period */
1858    _WORDREGISTER(CCA);  /* Compare or Capture A */
1859    _WORDREGISTER(CCB);  /* Compare or Capture B */
1860    register8_t reserved_0x2C;
1861    register8_t reserved_0x2D;
1862    register8_t reserved_0x2E;
1863    register8_t reserved_0x2F;
1864    register8_t reserved_0x30;
1865    register8_t reserved_0x31;
1866    register8_t reserved_0x32;
1867    register8_t reserved_0x33;
1868    register8_t reserved_0x34;
1869    register8_t reserved_0x35;
1870    _WORDREGISTER(PERBUF);  /* Period Buffer */
1871    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
1872    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
1873} TC1_t;
1874
1875/*
1876--------------------------------------------------------------------------
1877TC - 16-bit Timer/Counter With PWM
1878--------------------------------------------------------------------------
1879*/
1880
1881/* Advanced Waveform Extension */
1882typedef struct AWEX_struct
1883{
1884    register8_t CTRL;  /* Control Register */
1885    register8_t reserved_0x01;
1886    register8_t FDEMASK;  /* Fault Detection Event Mask */
1887    register8_t FDCTRL;  /* Fault Detection Control Register */
1888    register8_t STATUS;  /* Status Register */
1889    register8_t reserved_0x05;
1890    register8_t DTBOTH;  /* Dead Time Both Sides */
1891    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
1892    register8_t DTLS;  /* Dead Time Low Side */
1893    register8_t DTHS;  /* Dead Time High Side */
1894    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
1895    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
1896    register8_t OUTOVEN;  /* Output Override Enable */
1897} AWEX_t;
1898
1899/*
1900--------------------------------------------------------------------------
1901TC - 16-bit Timer/Counter With PWM
1902--------------------------------------------------------------------------
1903*/
1904
1905/* High-Resolution Extension */
1906typedef struct HIRES_struct
1907{
1908    register8_t CTRLA;  /* Control Register */
1909} HIRES_t;
1910
1911/* Clock Selection */
1912typedef enum TC_CLKSEL_enum
1913{
1914    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
1915    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
1916    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
1917    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
1918    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
1919    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
1920    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
1921    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
1922    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
1923    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
1924    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
1925    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
1926    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
1927    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
1928    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
1929    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
1930} TC_CLKSEL_t;
1931
1932/* Waveform Generation Mode */
1933typedef enum TC_WGMODE_enum
1934{
1935    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
1936    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
1937    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
1938    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
1939    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
1940    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
1941} TC_WGMODE_t;
1942
1943/* Event Action */
1944typedef enum TC_EVACT_enum
1945{
1946    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
1947    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
1948    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
1949    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
1950    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
1951    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
1952    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
1953} TC_EVACT_t;
1954
1955/* Event Selection */
1956typedef enum TC_EVSEL_enum
1957{
1958    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
1959    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
1960    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
1961    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
1962    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
1963    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
1964    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
1965    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
1966    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
1967} TC_EVSEL_t;
1968
1969/* Error Interrupt Level */
1970typedef enum TC_ERRINTLVL_enum
1971{
1972    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1973    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1974    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1975    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
1976} TC_ERRINTLVL_t;
1977
1978/* Overflow Interrupt Level */
1979typedef enum TC_OVFINTLVL_enum
1980{
1981    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1982    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1983    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1984    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
1985} TC_OVFINTLVL_t;
1986
1987/* Compare or Capture D Interrupt Level */
1988typedef enum TC_CCDINTLVL_enum
1989{
1990    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1991    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
1992    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1993    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
1994} TC_CCDINTLVL_t;
1995
1996/* Compare or Capture C Interrupt Level */
1997typedef enum TC_CCCINTLVL_enum
1998{
1999    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
2000    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
2001    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
2002    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
2003} TC_CCCINTLVL_t;
2004
2005/* Compare or Capture B Interrupt Level */
2006typedef enum TC_CCBINTLVL_enum
2007{
2008    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
2009    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
2010    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
2011    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
2012} TC_CCBINTLVL_t;
2013
2014/* Compare or Capture A Interrupt Level */
2015typedef enum TC_CCAINTLVL_enum
2016{
2017    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2018    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
2019    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2020    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
2021} TC_CCAINTLVL_t;
2022
2023/* Timer/Counter Command */
2024typedef enum TC_CMD_enum
2025{
2026    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
2027    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
2028    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
2029    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
2030} TC_CMD_t;
2031
2032/* Fault Detect Action */
2033typedef enum AWEX_FDACT_enum
2034{
2035    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
2036    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
2037    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
2038} AWEX_FDACT_t;
2039
2040/* High Resolution Enable */
2041typedef enum HIRES_HREN_enum
2042{
2043    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
2044    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
2045    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
2046    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
2047} HIRES_HREN_t;
2048
2049
2050/*
2051--------------------------------------------------------------------------
2052USART - Universal Asynchronous Receiver-Transmitter
2053--------------------------------------------------------------------------
2054*/
2055
2056/* Universal Synchronous/Asynchronous Receiver/Transmitter */
2057typedef struct USART_struct
2058{
2059    register8_t DATA;  /* Data Register */
2060    register8_t STATUS;  /* Status Register */
2061    register8_t reserved_0x02;
2062    register8_t CTRLA;  /* Control Register A */
2063    register8_t CTRLB;  /* Control Register B */
2064    register8_t CTRLC;  /* Control Register C */
2065    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
2066    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
2067} USART_t;
2068
2069/* Receive Complete Interrupt level */
2070typedef enum USART_RXCINTLVL_enum
2071{
2072    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
2073    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
2074    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
2075    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
2076} USART_RXCINTLVL_t;
2077
2078/* Transmit Complete Interrupt level */
2079typedef enum USART_TXCINTLVL_enum
2080{
2081    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
2082    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
2083    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
2084    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
2085} USART_TXCINTLVL_t;
2086
2087/* Data Register Empty Interrupt level */
2088typedef enum USART_DREINTLVL_enum
2089{
2090    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2091    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
2092    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2093    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
2094} USART_DREINTLVL_t;
2095
2096/* Character Size */
2097typedef enum USART_CHSIZE_enum
2098{
2099    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
2100    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
2101    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
2102    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
2103    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
2104} USART_CHSIZE_t;
2105
2106/* Communication Mode */
2107typedef enum USART_CMODE_enum
2108{
2109    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
2110    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
2111    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
2112    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
2113} USART_CMODE_t;
2114
2115/* Parity Mode */
2116typedef enum USART_PMODE_enum
2117{
2118    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
2119    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
2120    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
2121} USART_PMODE_t;
2122
2123
2124/*
2125--------------------------------------------------------------------------
2126SPI - Serial Peripheral Interface
2127--------------------------------------------------------------------------
2128*/
2129
2130/* Serial Peripheral Interface */
2131typedef struct SPI_struct
2132{
2133    register8_t CTRL;  /* Control Register */
2134    register8_t INTCTRL;  /* Interrupt Control Register */
2135    register8_t STATUS;  /* Status Register */
2136    register8_t DATA;  /* Data Register */
2137} SPI_t;
2138
2139/* SPI Mode */
2140typedef enum SPI_MODE_enum
2141{
2142    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
2143    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
2144    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
2145    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
2146} SPI_MODE_t;
2147
2148/* Prescaler setting */
2149typedef enum SPI_PRESCALER_enum
2150{
2151    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
2152    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
2153    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
2154    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
2155} SPI_PRESCALER_t;
2156
2157/* Interrupt level */
2158typedef enum SPI_INTLVL_enum
2159{
2160    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2161    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
2162    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2163    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
2164} SPI_INTLVL_t;
2165
2166
2167/*
2168--------------------------------------------------------------------------
2169IRCOM - IR Communication Module
2170--------------------------------------------------------------------------
2171*/
2172
2173/* IR Communication Module */
2174typedef struct IRCOM_struct
2175{
2176    register8_t CTRL;  /* Control Register */
2177    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
2178    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
2179} IRCOM_t;
2180
2181/* Event channel selection */
2182typedef enum IRDA_EVSEL_enum
2183{
2184    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
2185    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
2186    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
2187    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
2188    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
2189    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
2190    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
2191    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
2192    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
2193} IRDA_EVSEL_t;
2194
2195
2196
2197/*
2198==========================================================================
2199IO Module Instances. Mapped to memory.
2200==========================================================================
2201*/
2202
2203#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
2204#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
2205#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
2206#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
2207#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
2208#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
2209#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
2210#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
2211#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
2212#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
2213#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
2214#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
2215#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
2216#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
2217#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
2218#define CRC    (*(CRC_t *) 0x00D0)  /* Cyclic Redundancy Checker */
2219#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
2220#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
2221#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
2222#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
2223#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
2224#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
2225#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
2226#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
2227#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
2228#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
2229#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
2230#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
2231#define PORTF    (*(PORT_t *) 0x06A0)  /* Port F */
2232#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
2233#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
2234#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
2235#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
2236#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
2237#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
2238#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
2239#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
2240#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
2241#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
2242#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
2243#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
2244#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
2245#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
2246#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
2247#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
2248
2249
2250#endif /* !defined (__ASSEMBLER__) */
2251
2252
2253/* ========== Flattened fully qualified IO register names ========== */
2254
2255/* GPIO - General Purpose IO Registers */
2256#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
2257#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
2258#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
2259#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
2260#define GPIO_GPIOR4  _SFR_MEM8(0x0004)
2261#define GPIO_GPIOR5  _SFR_MEM8(0x0005)
2262#define GPIO_GPIOR6  _SFR_MEM8(0x0006)
2263#define GPIO_GPIOR7  _SFR_MEM8(0x0007)
2264#define GPIO_GPIOR8  _SFR_MEM8(0x0008)
2265#define GPIO_GPIOR9  _SFR_MEM8(0x0009)
2266#define GPIO_GPIORA  _SFR_MEM8(0x000A)
2267#define GPIO_GPIORB  _SFR_MEM8(0x000B)
2268#define GPIO_GPIORC  _SFR_MEM8(0x000C)
2269#define GPIO_GPIORD  _SFR_MEM8(0x000D)
2270#define GPIO_GPIORE  _SFR_MEM8(0x000E)
2271#define GPIO_GPIORF  _SFR_MEM8(0x000F)
2272
2273/* VPORT0 - Virtual Port 0 */
2274#define VPORT0_DIR  _SFR_MEM8(0x0010)
2275#define VPORT0_OUT  _SFR_MEM8(0x0011)
2276#define VPORT0_IN  _SFR_MEM8(0x0012)
2277#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
2278
2279/* VPORT1 - Virtual Port 1 */
2280#define VPORT1_DIR  _SFR_MEM8(0x0014)
2281#define VPORT1_OUT  _SFR_MEM8(0x0015)
2282#define VPORT1_IN  _SFR_MEM8(0x0016)
2283#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
2284
2285/* VPORT2 - Virtual Port 2 */
2286#define VPORT2_DIR  _SFR_MEM8(0x0018)
2287#define VPORT2_OUT  _SFR_MEM8(0x0019)
2288#define VPORT2_IN  _SFR_MEM8(0x001A)
2289#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
2290
2291/* VPORT3 - Virtual Port 3 */
2292#define VPORT3_DIR  _SFR_MEM8(0x001C)
2293#define VPORT3_OUT  _SFR_MEM8(0x001D)
2294#define VPORT3_IN  _SFR_MEM8(0x001E)
2295#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
2296
2297/* OCD - On-Chip Debug System */
2298#define OCD_OCDR0  _SFR_MEM8(0x002E)
2299#define OCD_OCDR1  _SFR_MEM8(0x002F)
2300
2301/* CPU - CPU Registers */
2302#define CPU_CCP  _SFR_MEM8(0x0034)
2303#define CPU_RAMPD  _SFR_MEM8(0x0038)
2304#define CPU_RAMPX  _SFR_MEM8(0x0039)
2305#define CPU_RAMPY  _SFR_MEM8(0x003A)
2306#define CPU_RAMPZ  _SFR_MEM8(0x003B)
2307#define CPU_EIND  _SFR_MEM8(0x003C)
2308#define CPU_SPL  _SFR_MEM8(0x003D)
2309#define CPU_SPH  _SFR_MEM8(0x003E)
2310#define CPU_SREG  _SFR_MEM8(0x003F)
2311
2312/* CLK - Clock System */
2313#define CLK_CTRL  _SFR_MEM8(0x0040)
2314#define CLK_PSCTRL  _SFR_MEM8(0x0041)
2315#define CLK_LOCK  _SFR_MEM8(0x0042)
2316#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
2317
2318/* SLEEP - Sleep Controller */
2319#define SLEEP_CTRL  _SFR_MEM8(0x0048)
2320
2321/* OSC - Oscillator Control */
2322#define OSC_CTRL  _SFR_MEM8(0x0050)
2323#define OSC_STATUS  _SFR_MEM8(0x0051)
2324#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
2325#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
2326#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
2327#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
2328#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
2329
2330/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
2331#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
2332#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
2333#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
2334#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
2335#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
2336#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
2337
2338/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
2339#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
2340#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
2341#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
2342#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
2343#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
2344#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
2345
2346/* PR - Power Reduction */
2347#define PR_PRGEN  _SFR_MEM8(0x0070)
2348#define PR_PRPA  _SFR_MEM8(0x0071)
2349#define PR_PRPC  _SFR_MEM8(0x0073)
2350#define PR_PRPD  _SFR_MEM8(0x0074)
2351#define PR_PRPE  _SFR_MEM8(0x0075)
2352#define PR_PRPF  _SFR_MEM8(0x0076)
2353
2354/* RST - Reset Controller */
2355#define RST_STATUS  _SFR_MEM8(0x0078)
2356#define RST_CTRL  _SFR_MEM8(0x0079)
2357
2358/* WDT - Watch-Dog Timer */
2359#define WDT_CTRL  _SFR_MEM8(0x0080)
2360#define WDT_WINCTRL  _SFR_MEM8(0x0081)
2361#define WDT_STATUS  _SFR_MEM8(0x0082)
2362
2363/* MCU - MCU Control */
2364#define MCU_DEVID0  _SFR_MEM8(0x0090)
2365#define MCU_DEVID1  _SFR_MEM8(0x0091)
2366#define MCU_DEVID2  _SFR_MEM8(0x0092)
2367#define MCU_REVID  _SFR_MEM8(0x0093)
2368#define MCU_JTAGUID  _SFR_MEM8(0x0094)
2369#define MCU_MCUCR  _SFR_MEM8(0x0096)
2370#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
2371#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
2372
2373/* PMIC - Programmable Interrupt Controller */
2374#define PMIC_STATUS  _SFR_MEM8(0x00A0)
2375#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
2376#define PMIC_CTRL  _SFR_MEM8(0x00A2)
2377
2378/* PORTCFG - Port Configuration */
2379#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
2380#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
2381#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
2382#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
2383
2384/* CRC - Cyclic Redundancy Checker */
2385#define CRC_CTRL  _SFR_MEM8(0x00D0)
2386#define CRC_STATUS  _SFR_MEM8(0x00D1)
2387#define CRC_DATAIN  _SFR_MEM8(0x00D3)
2388#define CRC_CHECKSUM0  _SFR_MEM8(0x00D4)
2389#define CRC_CHECKSUM1  _SFR_MEM8(0x00D5)
2390#define CRC_CHECKSUM2  _SFR_MEM8(0x00D6)
2391#define CRC_CHECKSUM3  _SFR_MEM8(0x00D7)
2392
2393/* EVSYS - Event System */
2394#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
2395#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
2396#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
2397#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
2398#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
2399#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
2400#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
2401#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
2402#define EVSYS_STROBE  _SFR_MEM8(0x0190)
2403#define EVSYS_DATA  _SFR_MEM8(0x0191)
2404
2405/* NVM - Non Volatile Memory Controller */
2406#define NVM_ADDR0  _SFR_MEM8(0x01C0)
2407#define NVM_ADDR1  _SFR_MEM8(0x01C1)
2408#define NVM_ADDR2  _SFR_MEM8(0x01C2)
2409#define NVM_DATA0  _SFR_MEM8(0x01C4)
2410#define NVM_DATA1  _SFR_MEM8(0x01C5)
2411#define NVM_DATA2  _SFR_MEM8(0x01C6)
2412#define NVM_CMD  _SFR_MEM8(0x01CA)
2413#define NVM_CTRLA  _SFR_MEM8(0x01CB)
2414#define NVM_CTRLB  _SFR_MEM8(0x01CC)
2415#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
2416#define NVM_STATUS  _SFR_MEM8(0x01CF)
2417#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
2418
2419/* ADCA - Analog to Digital Converter A */
2420#define ADCA_CTRLA  _SFR_MEM8(0x0200)
2421#define ADCA_CTRLB  _SFR_MEM8(0x0201)
2422#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
2423#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
2424#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
2425#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
2426#define ADCA_TEMP  _SFR_MEM8(0x0207)
2427#define ADCA_CAL  _SFR_MEM16(0x020C)
2428#define ADCA_CH0RES  _SFR_MEM16(0x0210)
2429#define ADCA_CMP  _SFR_MEM16(0x0218)
2430#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
2431#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
2432#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
2433#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
2434#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
2435
2436/* ACA - Analog Comparator A */
2437#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
2438#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
2439#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
2440#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
2441#define ACA_CTRLA  _SFR_MEM8(0x0384)
2442#define ACA_CTRLB  _SFR_MEM8(0x0385)
2443#define ACA_WINCTRL  _SFR_MEM8(0x0386)
2444#define ACA_STATUS  _SFR_MEM8(0x0387)
2445
2446/* RTC - Real-Time Counter */
2447#define RTC_CTRL  _SFR_MEM8(0x0400)
2448#define RTC_STATUS  _SFR_MEM8(0x0401)
2449#define RTC_INTCTRL  _SFR_MEM8(0x0402)
2450#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
2451#define RTC_TEMP  _SFR_MEM8(0x0404)
2452#define RTC_CNT  _SFR_MEM16(0x0408)
2453#define RTC_PER  _SFR_MEM16(0x040A)
2454#define RTC_COMP  _SFR_MEM16(0x040C)
2455
2456/* TWIC - Two-Wire Interface C */
2457#define TWIC_CTRL  _SFR_MEM8(0x0480)
2458#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
2459#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
2460#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
2461#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
2462#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
2463#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
2464#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
2465#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
2466#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
2467#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
2468#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
2469#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
2470#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
2471
2472/* TWIE - Two-Wire Interface E */
2473#define TWIE_CTRL  _SFR_MEM8(0x04A0)
2474#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
2475#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
2476#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
2477#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
2478#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
2479#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
2480#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
2481#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
2482#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
2483#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
2484#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
2485#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
2486#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
2487
2488/* PORTA - Port A */
2489#define PORTA_DIR  _SFR_MEM8(0x0600)
2490#define PORTA_DIRSET  _SFR_MEM8(0x0601)
2491#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
2492#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
2493#define PORTA_OUT  _SFR_MEM8(0x0604)
2494#define PORTA_OUTSET  _SFR_MEM8(0x0605)
2495#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
2496#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
2497#define PORTA_IN  _SFR_MEM8(0x0608)
2498#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
2499#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
2500#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
2501#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
2502#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
2503#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
2504#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
2505#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
2506#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
2507#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
2508#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
2509#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
2510
2511/* PORTB - Port B */
2512#define PORTB_DIR  _SFR_MEM8(0x0620)
2513#define PORTB_DIRSET  _SFR_MEM8(0x0621)
2514#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
2515#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
2516#define PORTB_OUT  _SFR_MEM8(0x0624)
2517#define PORTB_OUTSET  _SFR_MEM8(0x0625)
2518#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
2519#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
2520#define PORTB_IN  _SFR_MEM8(0x0628)
2521#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
2522#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
2523#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
2524#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
2525#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
2526#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
2527#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
2528#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
2529#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
2530#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
2531#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
2532#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
2533
2534/* PORTC - Port C */
2535#define PORTC_DIR  _SFR_MEM8(0x0640)
2536#define PORTC_DIRSET  _SFR_MEM8(0x0641)
2537#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
2538#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
2539#define PORTC_OUT  _SFR_MEM8(0x0644)
2540#define PORTC_OUTSET  _SFR_MEM8(0x0645)
2541#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
2542#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
2543#define PORTC_IN  _SFR_MEM8(0x0648)
2544#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
2545#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
2546#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
2547#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
2548#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
2549#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
2550#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
2551#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
2552#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
2553#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
2554#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
2555#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
2556
2557/* PORTD - Port D */
2558#define PORTD_DIR  _SFR_MEM8(0x0660)
2559#define PORTD_DIRSET  _SFR_MEM8(0x0661)
2560#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
2561#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
2562#define PORTD_OUT  _SFR_MEM8(0x0664)
2563#define PORTD_OUTSET  _SFR_MEM8(0x0665)
2564#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
2565#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
2566#define PORTD_IN  _SFR_MEM8(0x0668)
2567#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
2568#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
2569#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
2570#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
2571#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
2572#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
2573#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
2574#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
2575#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
2576#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
2577#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
2578#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
2579
2580/* PORTE - Port E */
2581#define PORTE_DIR  _SFR_MEM8(0x0680)
2582#define PORTE_DIRSET  _SFR_MEM8(0x0681)
2583#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
2584#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
2585#define PORTE_OUT  _SFR_MEM8(0x0684)
2586#define PORTE_OUTSET  _SFR_MEM8(0x0685)
2587#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
2588#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
2589#define PORTE_IN  _SFR_MEM8(0x0688)
2590#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
2591#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
2592#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
2593#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
2594#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
2595#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
2596#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
2597#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
2598#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
2599#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
2600#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
2601#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
2602
2603/* PORTF - Port F */
2604#define PORTF_DIR  _SFR_MEM8(0x06A0)
2605#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
2606#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
2607#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
2608#define PORTF_OUT  _SFR_MEM8(0x06A4)
2609#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
2610#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
2611#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
2612#define PORTF_IN  _SFR_MEM8(0x06A8)
2613#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
2614#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
2615#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
2616#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
2617#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
2618#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
2619#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
2620#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
2621#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
2622#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
2623#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
2624#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
2625
2626/* PORTR - Port R */
2627#define PORTR_DIR  _SFR_MEM8(0x07E0)
2628#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
2629#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
2630#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
2631#define PORTR_OUT  _SFR_MEM8(0x07E4)
2632#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
2633#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
2634#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
2635#define PORTR_IN  _SFR_MEM8(0x07E8)
2636#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
2637#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
2638#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
2639#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
2640#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
2641#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
2642#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
2643#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
2644#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
2645#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
2646#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
2647#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
2648
2649/* TCC0 - Timer/Counter C0 */
2650#define TCC0_CTRLA  _SFR_MEM8(0x0800)
2651#define TCC0_CTRLB  _SFR_MEM8(0x0801)
2652#define TCC0_CTRLC  _SFR_MEM8(0x0802)
2653#define TCC0_CTRLD  _SFR_MEM8(0x0803)
2654#define TCC0_CTRLE  _SFR_MEM8(0x0804)
2655#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
2656#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
2657#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
2658#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
2659#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
2660#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
2661#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
2662#define TCC0_TEMP  _SFR_MEM8(0x080F)
2663#define TCC0_CNT  _SFR_MEM16(0x0820)
2664#define TCC0_PER  _SFR_MEM16(0x0826)
2665#define TCC0_CCA  _SFR_MEM16(0x0828)
2666#define TCC0_CCB  _SFR_MEM16(0x082A)
2667#define TCC0_CCC  _SFR_MEM16(0x082C)
2668#define TCC0_CCD  _SFR_MEM16(0x082E)
2669#define TCC0_PERBUF  _SFR_MEM16(0x0836)
2670#define TCC0_CCABUF  _SFR_MEM16(0x0838)
2671#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
2672#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
2673#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
2674
2675/* TCC1 - Timer/Counter C1 */
2676#define TCC1_CTRLA  _SFR_MEM8(0x0840)
2677#define TCC1_CTRLB  _SFR_MEM8(0x0841)
2678#define TCC1_CTRLC  _SFR_MEM8(0x0842)
2679#define TCC1_CTRLD  _SFR_MEM8(0x0843)
2680#define TCC1_CTRLE  _SFR_MEM8(0x0844)
2681#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
2682#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
2683#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
2684#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
2685#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
2686#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
2687#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
2688#define TCC1_TEMP  _SFR_MEM8(0x084F)
2689#define TCC1_CNT  _SFR_MEM16(0x0860)
2690#define TCC1_PER  _SFR_MEM16(0x0866)
2691#define TCC1_CCA  _SFR_MEM16(0x0868)
2692#define TCC1_CCB  _SFR_MEM16(0x086A)
2693#define TCC1_PERBUF  _SFR_MEM16(0x0876)
2694#define TCC1_CCABUF  _SFR_MEM16(0x0878)
2695#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
2696
2697/* AWEXC - Advanced Waveform Extension C */
2698#define AWEXC_CTRL  _SFR_MEM8(0x0880)
2699#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
2700#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
2701#define AWEXC_STATUS  _SFR_MEM8(0x0884)
2702#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
2703#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
2704#define AWEXC_DTLS  _SFR_MEM8(0x0888)
2705#define AWEXC_DTHS  _SFR_MEM8(0x0889)
2706#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
2707#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
2708#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
2709
2710/* HIRESC - High-Resolution Extension C */
2711#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
2712
2713/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
2714#define USARTC0_DATA  _SFR_MEM8(0x08A0)
2715#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
2716#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
2717#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
2718#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
2719#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
2720#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
2721
2722/* SPIC - Serial Peripheral Interface C */
2723#define SPIC_CTRL  _SFR_MEM8(0x08C0)
2724#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
2725#define SPIC_STATUS  _SFR_MEM8(0x08C2)
2726#define SPIC_DATA  _SFR_MEM8(0x08C3)
2727
2728/* IRCOM - IR Communication Module */
2729#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
2730#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
2731#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
2732
2733/* TCD0 - Timer/Counter D0 */
2734#define TCD0_CTRLA  _SFR_MEM8(0x0900)
2735#define TCD0_CTRLB  _SFR_MEM8(0x0901)
2736#define TCD0_CTRLC  _SFR_MEM8(0x0902)
2737#define TCD0_CTRLD  _SFR_MEM8(0x0903)
2738#define TCD0_CTRLE  _SFR_MEM8(0x0904)
2739#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
2740#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
2741#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
2742#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
2743#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
2744#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
2745#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
2746#define TCD0_TEMP  _SFR_MEM8(0x090F)
2747#define TCD0_CNT  _SFR_MEM16(0x0920)
2748#define TCD0_PER  _SFR_MEM16(0x0926)
2749#define TCD0_CCA  _SFR_MEM16(0x0928)
2750#define TCD0_CCB  _SFR_MEM16(0x092A)
2751#define TCD0_CCC  _SFR_MEM16(0x092C)
2752#define TCD0_CCD  _SFR_MEM16(0x092E)
2753#define TCD0_PERBUF  _SFR_MEM16(0x0936)
2754#define TCD0_CCABUF  _SFR_MEM16(0x0938)
2755#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
2756#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
2757#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
2758
2759/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
2760#define USARTD0_DATA  _SFR_MEM8(0x09A0)
2761#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
2762#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
2763#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
2764#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
2765#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
2766#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
2767
2768/* SPID - Serial Peripheral Interface D */
2769#define SPID_CTRL  _SFR_MEM8(0x09C0)
2770#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
2771#define SPID_STATUS  _SFR_MEM8(0x09C2)
2772#define SPID_DATA  _SFR_MEM8(0x09C3)
2773
2774/* TCE0 - Timer/Counter E0 */
2775#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
2776#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
2777#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
2778#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
2779#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
2780#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
2781#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
2782#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
2783#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
2784#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
2785#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
2786#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
2787#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
2788#define TCE0_CNT  _SFR_MEM16(0x0A20)
2789#define TCE0_PER  _SFR_MEM16(0x0A26)
2790#define TCE0_CCA  _SFR_MEM16(0x0A28)
2791#define TCE0_CCB  _SFR_MEM16(0x0A2A)
2792#define TCE0_CCC  _SFR_MEM16(0x0A2C)
2793#define TCE0_CCD  _SFR_MEM16(0x0A2E)
2794#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
2795#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
2796#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
2797#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
2798#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
2799
2800/* AWEXE - Advanced Waveform Extension E */
2801#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
2802#define AWEXE_FDEMASK  _SFR_MEM8(0x0A82)
2803#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
2804#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
2805#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
2806#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
2807#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
2808#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
2809#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
2810#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
2811#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
2812
2813/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
2814#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
2815#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
2816#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
2817#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
2818#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
2819#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
2820#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
2821
2822/* SPIE - Serial Peripheral Interface E */
2823#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
2824#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
2825#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
2826#define SPIE_DATA  _SFR_MEM8(0x0AC3)
2827
2828/* TCF0 - Timer/Counter F0 */
2829#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
2830#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
2831#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
2832#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
2833#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
2834#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
2835#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
2836#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
2837#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
2838#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
2839#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
2840#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
2841#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
2842#define TCF0_CNT  _SFR_MEM16(0x0B20)
2843#define TCF0_PER  _SFR_MEM16(0x0B26)
2844#define TCF0_CCA  _SFR_MEM16(0x0B28)
2845#define TCF0_CCB  _SFR_MEM16(0x0B2A)
2846#define TCF0_CCC  _SFR_MEM16(0x0B2C)
2847#define TCF0_CCD  _SFR_MEM16(0x0B2E)
2848#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
2849#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
2850#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
2851#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
2852#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
2853
2854
2855
2856/*================== Bitfield Definitions ================== */
2857
2858/* XOCD - On-Chip Debug System */
2859/* OCD.OCDR1  bit masks and bit positions */
2860#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
2861#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
2862
2863
2864/* CPU - CPU */
2865/* CPU.CCP  bit masks and bit positions */
2866#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
2867#define CPU_CCP_gp  0  /* CCP signature group position. */
2868#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
2869#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
2870#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
2871#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
2872#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
2873#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
2874#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
2875#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
2876#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
2877#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
2878#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
2879#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
2880#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
2881#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
2882#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
2883#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
2884
2885
2886/* CPU.SREG  bit masks and bit positions */
2887#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
2888#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
2889
2890#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
2891#define CPU_T_bp  6  /* Transfer Bit bit position. */
2892
2893#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
2894#define CPU_H_bp  5  /* Half Carry Flag bit position. */
2895
2896#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
2897#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
2898
2899#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
2900#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
2901
2902#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
2903#define CPU_N_bp  2  /* Negative Flag bit position. */
2904
2905#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
2906#define CPU_Z_bp  1  /* Zero Flag bit position. */
2907
2908#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
2909#define CPU_C_bp  0  /* Carry Flag bit position. */
2910
2911
2912/* CLK - Clock System */
2913/* CLK.CTRL  bit masks and bit positions */
2914#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
2915#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
2916#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
2917#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
2918#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
2919#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
2920#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
2921#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
2922
2923
2924/* CLK.PSCTRL  bit masks and bit positions */
2925#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
2926#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
2927#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
2928#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
2929#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
2930#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
2931#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
2932#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
2933#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
2934#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
2935#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
2936#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
2937
2938#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
2939#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
2940#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
2941#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
2942#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
2943#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
2944
2945
2946/* CLK.LOCK  bit masks and bit positions */
2947#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
2948#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
2949
2950
2951/* CLK.RTCCTRL  bit masks and bit positions */
2952#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
2953#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
2954#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
2955#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
2956#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
2957#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
2958#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
2959#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
2960
2961#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
2962#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
2963
2964/* PR.PRGEN  bit masks and bit positions */
2965#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
2966#define PR_RTC_bp  2  /* Real-time Counter bit position. */
2967
2968#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
2969#define PR_EVSYS_bp  1  /* Event System bit position. */
2970
2971/* PR.PRPA  bit masks and bit positions */
2972#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
2973#define PR_ADC_bp  1  /* Port A ADC bit position. */
2974
2975#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
2976#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
2977
2978/* PR.PRPC  bit masks and bit positions */
2979#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
2980#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
2981
2982#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
2983#define PR_USART0_bp  4  /* Port C USART0 bit position. */
2984
2985#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
2986#define PR_SPI_bp  3  /* Port C SPI bit position. */
2987
2988#define PR_HIRES_bm  0x04  /* Port C HIRES bit mask. */
2989#define PR_HIRES_bp  2  /* Port C HIRES bit position. */
2990
2991#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
2992#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
2993
2994#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
2995#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
2996
2997/* PR.PRPD  bit masks and bit positions */
2998/* PR_USART0  Predefined. */
2999/* PR_USART0  Predefined. */
3000
3001/* PR_SPI  Predefined. */
3002/* PR_SPI  Predefined. */
3003
3004/* PR_TC0  Predefined. */
3005/* PR_TC0  Predefined. */
3006
3007/* PR.PRPE  bit masks and bit positions */
3008/* PR_TWI  Predefined. */
3009/* PR_TWI  Predefined. */
3010
3011/* PR_USART0  Predefined. */
3012/* PR_USART0  Predefined. */
3013
3014/* PR_TC0  Predefined. */
3015/* PR_TC0  Predefined. */
3016
3017/* PR.PRPF  bit masks and bit positions */
3018/* PR_USART0  Predefined. */
3019/* PR_USART0  Predefined. */
3020
3021/* PR_TC0  Predefined. */
3022/* PR_TC0  Predefined. */
3023
3024/* SLEEP - Sleep Controller */
3025/* SLEEP.CTRL  bit masks and bit positions */
3026#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
3027#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
3028#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
3029#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
3030#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
3031#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
3032#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
3033#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
3034
3035#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
3036#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
3037
3038
3039/* OSC - Oscillator */
3040/* OSC.CTRL  bit masks and bit positions */
3041#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
3042#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
3043
3044#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
3045#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
3046
3047#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
3048#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
3049
3050#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
3051#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
3052
3053#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
3054#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
3055
3056
3057/* OSC.STATUS  bit masks and bit positions */
3058#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
3059#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
3060
3061#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
3062#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
3063
3064#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
3065#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
3066
3067#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
3068#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
3069
3070#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
3071#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
3072
3073
3074/* OSC.XOSCCTRL  bit masks and bit positions */
3075#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
3076#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
3077#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
3078#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
3079#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
3080#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
3081
3082#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
3083#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
3084
3085#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
3086#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
3087#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
3088#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
3089#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
3090#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
3091#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
3092#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
3093#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
3094#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
3095
3096
3097/* OSC.XOSCFAIL  bit masks and bit positions */
3098#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
3099#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
3100
3101#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
3102#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
3103
3104
3105/* OSC.PLLCTRL  bit masks and bit positions */
3106#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
3107#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
3108#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
3109#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
3110#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
3111#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
3112
3113#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
3114#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
3115#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
3116#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
3117#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
3118#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
3119#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
3120#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
3121#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
3122#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
3123#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
3124#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
3125
3126
3127/* OSC.DFLLCTRL  bit masks and bit positions */
3128#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
3129#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
3130
3131#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
3132#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
3133
3134
3135/* DFLL - DFLL */
3136/* DFLL.CTRL  bit masks and bit positions */
3137#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
3138#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
3139
3140
3141/* DFLL.CALA  bit masks and bit positions */
3142#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
3143#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
3144#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
3145#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
3146#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
3147#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
3148#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
3149#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
3150#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
3151#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
3152#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
3153#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
3154#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
3155#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
3156#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
3157#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
3158
3159
3160/* DFLL.CALB  bit masks and bit positions */
3161#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
3162#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
3163#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
3164#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
3165#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
3166#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
3167#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
3168#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
3169#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
3170#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
3171#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
3172#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
3173#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
3174#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
3175
3176
3177/* RST - Reset */
3178/* RST.STATUS  bit masks and bit positions */
3179#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
3180#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
3181
3182#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
3183#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
3184
3185#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
3186#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
3187
3188#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
3189#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
3190
3191#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
3192#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
3193
3194#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
3195#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
3196
3197#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
3198#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
3199
3200
3201/* RST.CTRL  bit masks and bit positions */
3202#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
3203#define RST_SWRST_bp  0  /* Software Reset bit position. */
3204
3205
3206/* WDT - Watch-Dog Timer */
3207/* WDT.CTRL  bit masks and bit positions */
3208#define WDT_PER_gm  0x3C  /* Period group mask. */
3209#define WDT_PER_gp  2  /* Period group position. */
3210#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
3211#define WDT_PER0_bp  2  /* Period bit 0 position. */
3212#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
3213#define WDT_PER1_bp  3  /* Period bit 1 position. */
3214#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
3215#define WDT_PER2_bp  4  /* Period bit 2 position. */
3216#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
3217#define WDT_PER3_bp  5  /* Period bit 3 position. */
3218
3219#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
3220#define WDT_ENABLE_bp  1  /* Enable bit position. */
3221
3222#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
3223#define WDT_CEN_bp  0  /* Change Enable bit position. */
3224
3225
3226/* WDT.WINCTRL  bit masks and bit positions */
3227#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
3228#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
3229#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
3230#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
3231#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
3232#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
3233#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
3234#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
3235#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
3236#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
3237
3238#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
3239#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
3240
3241#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
3242#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
3243
3244
3245/* WDT.STATUS  bit masks and bit positions */
3246#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
3247#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
3248
3249
3250/* MCU - MCU Control */
3251/* MCU.MCUCR  bit masks and bit positions */
3252#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
3253#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
3254
3255
3256/* MCU.EVSYSLOCK  bit masks and bit positions */
3257#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
3258#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
3259
3260#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
3261#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
3262
3263
3264/* MCU.AWEXLOCK  bit masks and bit positions */
3265#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
3266#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
3267
3268#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
3269#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
3270
3271
3272/* PMIC - Programmable Multi-level Interrupt Controller */
3273/* PMIC.STATUS  bit masks and bit positions */
3274#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
3275#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
3276
3277#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
3278#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
3279
3280#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
3281#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
3282
3283#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
3284#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
3285
3286
3287/* PMIC.CTRL  bit masks and bit positions */
3288#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
3289#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
3290
3291#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
3292#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
3293
3294#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
3295#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
3296
3297#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
3298#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
3299
3300#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
3301#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
3302
3303
3304/* CRC - Cyclic Redundancy Checker */
3305/* CRC.CTRL  bit masks and bit positions */
3306#define CRC_RESET_gm  0xC0  /* Reset group mask. */
3307#define CRC_RESET_gp  6  /* Reset group position. */
3308#define CRC_RESET0_bm  (1<<6)  /* Reset bit 0 mask. */
3309#define CRC_RESET0_bp  6  /* Reset bit 0 position. */
3310#define CRC_RESET1_bm  (1<<7)  /* Reset bit 1 mask. */
3311#define CRC_RESET1_bp  7  /* Reset bit 1 position. */
3312
3313#define CRC_CRC32_bm  0x20  /* CRC Mode bit mask. */
3314#define CRC_CRC32_bp  5  /* CRC Mode bit position. */
3315
3316#define CRC_SOURCE_gm  0x0F  /* Input Source group mask. */
3317#define CRC_SOURCE_gp  0  /* Input Source group position. */
3318#define CRC_SOURCE0_bm  (1<<0)  /* Input Source bit 0 mask. */
3319#define CRC_SOURCE0_bp  0  /* Input Source bit 0 position. */
3320#define CRC_SOURCE1_bm  (1<<1)  /* Input Source bit 1 mask. */
3321#define CRC_SOURCE1_bp  1  /* Input Source bit 1 position. */
3322#define CRC_SOURCE2_bm  (1<<2)  /* Input Source bit 2 mask. */
3323#define CRC_SOURCE2_bp  2  /* Input Source bit 2 position. */
3324#define CRC_SOURCE3_bm  (1<<3)  /* Input Source bit 3 mask. */
3325#define CRC_SOURCE3_bp  3  /* Input Source bit 3 position. */
3326
3327/* CRC.STATUS  bit masks and bit positions */
3328#define CRC_ZERO_bm  0x02  /* Zero detection bit mask. */
3329#define CRC_ZERO_bp  1  /* Zero detection bit position. */
3330
3331#define CRC_BUSY_bm  0x01  /* Busy bit mask. */
3332#define CRC_BUSY_bp  0  /* Busy bit position. */
3333
3334
3335/* EVSYS - Event System */
3336/* EVSYS.CH0MUX  bit masks and bit positions */
3337#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
3338#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
3339#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
3340#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
3341#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
3342#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
3343#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
3344#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
3345#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
3346#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
3347#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
3348#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
3349#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
3350#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
3351#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
3352#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
3353#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
3354#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
3355
3356
3357/* EVSYS.CH1MUX  bit masks and bit positions */
3358/* EVSYS_CHMUX_gm  Predefined. */
3359/* EVSYS_CHMUX_gp  Predefined. */
3360/* EVSYS_CHMUX0_bm  Predefined. */
3361/* EVSYS_CHMUX0_bp  Predefined. */
3362/* EVSYS_CHMUX1_bm  Predefined. */
3363/* EVSYS_CHMUX1_bp  Predefined. */
3364/* EVSYS_CHMUX2_bm  Predefined. */
3365/* EVSYS_CHMUX2_bp  Predefined. */
3366/* EVSYS_CHMUX3_bm  Predefined. */
3367/* EVSYS_CHMUX3_bp  Predefined. */
3368/* EVSYS_CHMUX4_bm  Predefined. */
3369/* EVSYS_CHMUX4_bp  Predefined. */
3370/* EVSYS_CHMUX5_bm  Predefined. */
3371/* EVSYS_CHMUX5_bp  Predefined. */
3372/* EVSYS_CHMUX6_bm  Predefined. */
3373/* EVSYS_CHMUX6_bp  Predefined. */
3374/* EVSYS_CHMUX7_bm  Predefined. */
3375/* EVSYS_CHMUX7_bp  Predefined. */
3376
3377
3378/* EVSYS.CH2MUX  bit masks and bit positions */
3379/* EVSYS_CHMUX_gm  Predefined. */
3380/* EVSYS_CHMUX_gp  Predefined. */
3381/* EVSYS_CHMUX0_bm  Predefined. */
3382/* EVSYS_CHMUX0_bp  Predefined. */
3383/* EVSYS_CHMUX1_bm  Predefined. */
3384/* EVSYS_CHMUX1_bp  Predefined. */
3385/* EVSYS_CHMUX2_bm  Predefined. */
3386/* EVSYS_CHMUX2_bp  Predefined. */
3387/* EVSYS_CHMUX3_bm  Predefined. */
3388/* EVSYS_CHMUX3_bp  Predefined. */
3389/* EVSYS_CHMUX4_bm  Predefined. */
3390/* EVSYS_CHMUX4_bp  Predefined. */
3391/* EVSYS_CHMUX5_bm  Predefined. */
3392/* EVSYS_CHMUX5_bp  Predefined. */
3393/* EVSYS_CHMUX6_bm  Predefined. */
3394/* EVSYS_CHMUX6_bp  Predefined. */
3395/* EVSYS_CHMUX7_bm  Predefined. */
3396/* EVSYS_CHMUX7_bp  Predefined. */
3397
3398
3399/* EVSYS.CH3MUX  bit masks and bit positions */
3400/* EVSYS_CHMUX_gm  Predefined. */
3401/* EVSYS_CHMUX_gp  Predefined. */
3402/* EVSYS_CHMUX0_bm  Predefined. */
3403/* EVSYS_CHMUX0_bp  Predefined. */
3404/* EVSYS_CHMUX1_bm  Predefined. */
3405/* EVSYS_CHMUX1_bp  Predefined. */
3406/* EVSYS_CHMUX2_bm  Predefined. */
3407/* EVSYS_CHMUX2_bp  Predefined. */
3408/* EVSYS_CHMUX3_bm  Predefined. */
3409/* EVSYS_CHMUX3_bp  Predefined. */
3410/* EVSYS_CHMUX4_bm  Predefined. */
3411/* EVSYS_CHMUX4_bp  Predefined. */
3412/* EVSYS_CHMUX5_bm  Predefined. */
3413/* EVSYS_CHMUX5_bp  Predefined. */
3414/* EVSYS_CHMUX6_bm  Predefined. */
3415/* EVSYS_CHMUX6_bp  Predefined. */
3416/* EVSYS_CHMUX7_bm  Predefined. */
3417/* EVSYS_CHMUX7_bp  Predefined. */
3418
3419
3420/* EVSYS.CH0CTRL  bit masks and bit positions */
3421#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
3422#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
3423#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
3424#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
3425#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
3426#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
3427
3428#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
3429#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
3430
3431#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
3432#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
3433
3434#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
3435#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
3436#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
3437#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
3438#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
3439#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
3440#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
3441#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
3442
3443
3444/* EVSYS.CH1CTRL  bit masks and bit positions */
3445/* EVSYS_DIGFILT_gm  Predefined. */
3446/* EVSYS_DIGFILT_gp  Predefined. */
3447/* EVSYS_DIGFILT0_bm  Predefined. */
3448/* EVSYS_DIGFILT0_bp  Predefined. */
3449/* EVSYS_DIGFILT1_bm  Predefined. */
3450/* EVSYS_DIGFILT1_bp  Predefined. */
3451/* EVSYS_DIGFILT2_bm  Predefined. */
3452/* EVSYS_DIGFILT2_bp  Predefined. */
3453
3454
3455/* EVSYS.CH2CTRL  bit masks and bit positions */
3456/* EVSYS_QDIRM_gm  Predefined. */
3457/* EVSYS_QDIRM_gp  Predefined. */
3458/* EVSYS_QDIRM0_bm  Predefined. */
3459/* EVSYS_QDIRM0_bp  Predefined. */
3460/* EVSYS_QDIRM1_bm  Predefined. */
3461/* EVSYS_QDIRM1_bp  Predefined. */
3462
3463/* EVSYS_QDIEN_bm  Predefined. */
3464/* EVSYS_QDIEN_bp  Predefined. */
3465
3466/* EVSYS_QDEN_bm  Predefined. */
3467/* EVSYS_QDEN_bp  Predefined. */
3468
3469/* EVSYS_DIGFILT_gm  Predefined. */
3470/* EVSYS_DIGFILT_gp  Predefined. */
3471/* EVSYS_DIGFILT0_bm  Predefined. */
3472/* EVSYS_DIGFILT0_bp  Predefined. */
3473/* EVSYS_DIGFILT1_bm  Predefined. */
3474/* EVSYS_DIGFILT1_bp  Predefined. */
3475/* EVSYS_DIGFILT2_bm  Predefined. */
3476/* EVSYS_DIGFILT2_bp  Predefined. */
3477
3478
3479/* EVSYS.CH3CTRL  bit masks and bit positions */
3480/* EVSYS_DIGFILT_gm  Predefined. */
3481/* EVSYS_DIGFILT_gp  Predefined. */
3482/* EVSYS_DIGFILT0_bm  Predefined. */
3483/* EVSYS_DIGFILT0_bp  Predefined. */
3484/* EVSYS_DIGFILT1_bm  Predefined. */
3485/* EVSYS_DIGFILT1_bp  Predefined. */
3486/* EVSYS_DIGFILT2_bm  Predefined. */
3487/* EVSYS_DIGFILT2_bp  Predefined. */
3488
3489
3490/* NVM - Non Volatile Memory Controller */
3491/* NVM.CMD  bit masks and bit positions */
3492#define NVM_CMD_gm  0xFF  /* Command group mask. */
3493#define NVM_CMD_gp  0  /* Command group position. */
3494#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
3495#define NVM_CMD0_bp  0  /* Command bit 0 position. */
3496#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
3497#define NVM_CMD1_bp  1  /* Command bit 1 position. */
3498#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
3499#define NVM_CMD2_bp  2  /* Command bit 2 position. */
3500#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
3501#define NVM_CMD3_bp  3  /* Command bit 3 position. */
3502#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
3503#define NVM_CMD4_bp  4  /* Command bit 4 position. */
3504#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
3505#define NVM_CMD5_bp  5  /* Command bit 5 position. */
3506#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
3507#define NVM_CMD6_bp  6  /* Command bit 6 position. */
3508#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
3509#define NVM_CMD7_bp  7  /* Command bit 7 position. */
3510
3511
3512/* NVM.CTRLA  bit masks and bit positions */
3513#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
3514#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
3515
3516
3517/* NVM.CTRLB  bit masks and bit positions */
3518#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
3519#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
3520
3521#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
3522#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
3523
3524#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
3525#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
3526
3527#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
3528#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
3529
3530
3531/* NVM.INTCTRL  bit masks and bit positions */
3532#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
3533#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
3534#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
3535#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
3536#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
3537#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
3538
3539#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
3540#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
3541#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
3542#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
3543#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
3544#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
3545
3546
3547/* NVM.STATUS  bit masks and bit positions */
3548#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
3549#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
3550
3551#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
3552#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
3553
3554#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
3555#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
3556
3557#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
3558#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
3559
3560
3561/* NVM.LOCKBITS  bit masks and bit positions */
3562#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
3563#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
3564#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
3565#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
3566#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
3567#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
3568
3569#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
3570#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
3571#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
3572#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
3573#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
3574#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
3575
3576#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
3577#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
3578#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
3579#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
3580#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
3581#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
3582
3583#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
3584#define NVM_LB_gp  0  /* Lock Bits group position. */
3585#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
3586#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
3587#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
3588#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
3589
3590
3591/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
3592#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
3593#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
3594#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
3595#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
3596#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
3597#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
3598
3599#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
3600#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
3601#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
3602#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
3603#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
3604#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
3605
3606#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
3607#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
3608#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
3609#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
3610#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
3611#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
3612
3613#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
3614#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
3615#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
3616#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
3617#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
3618#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
3619
3620
3621/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
3622#define NVM_FUSES_USERID_gm  0xFF  /* User ID group mask. */
3623#define NVM_FUSES_USERID_gp  0  /* User ID group position. */
3624#define NVM_FUSES_USERID0_bm  (1<<0)  /* User ID bit 0 mask. */
3625#define NVM_FUSES_USERID0_bp  0  /* User ID bit 0 position. */
3626#define NVM_FUSES_USERID1_bm  (1<<1)  /* User ID bit 1 mask. */
3627#define NVM_FUSES_USERID1_bp  1  /* User ID bit 1 position. */
3628#define NVM_FUSES_USERID2_bm  (1<<2)  /* User ID bit 2 mask. */
3629#define NVM_FUSES_USERID2_bp  2  /* User ID bit 2 position. */
3630#define NVM_FUSES_USERID3_bm  (1<<3)  /* User ID bit 3 mask. */
3631#define NVM_FUSES_USERID3_bp  3  /* User ID bit 3 position. */
3632#define NVM_FUSES_USERID4_bm  (1<<4)  /* User ID bit 4 mask. */
3633#define NVM_FUSES_USERID4_bp  4  /* User ID bit 4 position. */
3634#define NVM_FUSES_USERID5_bm  (1<<5)  /* User ID bit 5 mask. */
3635#define NVM_FUSES_USERID5_bp  5  /* User ID bit 5 position. */
3636#define NVM_FUSES_USERID6_bm  (1<<6)  /* User ID bit 6 mask. */
3637#define NVM_FUSES_USERID6_bp  6  /* User ID bit 6 position. */
3638#define NVM_FUSES_USERID7_bm  (1<<7)  /* User ID bit 7 mask. */
3639#define NVM_FUSES_USERID7_bp  7  /* User ID bit 7 position. */
3640
3641
3642/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
3643#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
3644#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
3645#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
3646#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
3647#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
3648#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
3649#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
3650#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
3651#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
3652#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
3653
3654#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
3655#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
3656#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
3657#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
3658#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
3659#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
3660#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
3661#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
3662#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
3663#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
3664
3665
3666/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
3667#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
3668#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
3669
3670#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
3671#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
3672
3673#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
3674#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
3675#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
3676#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
3677#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
3678#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
3679
3680
3681/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
3682#define NVM_FUSES_RSTDISBL_bm  0x10  /* External Reset Disable bit mask. */
3683#define NVM_FUSES_RSTDISBL_bp  4  /* External Reset Disable bit position. */
3684
3685#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
3686#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
3687#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
3688#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
3689#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
3690#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
3691
3692#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
3693#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
3694
3695
3696/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
3697#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
3698#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
3699#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
3700#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
3701#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
3702#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
3703
3704#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
3705#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
3706
3707#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
3708#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
3709#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
3710#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
3711#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
3712#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
3713#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
3714#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
3715
3716
3717/* AC - Analog Comparator */
3718/* AC.AC0CTRL  bit masks and bit positions */
3719#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
3720#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
3721#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
3722#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
3723#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
3724#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
3725
3726#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
3727#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
3728#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
3729#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
3730#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
3731#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
3732
3733#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
3734#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
3735
3736#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
3737#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
3738#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
3739#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
3740#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
3741#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
3742
3743#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
3744#define AC_ENABLE_bp  0  /* Enable bit position. */
3745
3746
3747/* AC.AC1CTRL  bit masks and bit positions */
3748/* AC_INTMODE_gm  Predefined. */
3749/* AC_INTMODE_gp  Predefined. */
3750/* AC_INTMODE0_bm  Predefined. */
3751/* AC_INTMODE0_bp  Predefined. */
3752/* AC_INTMODE1_bm  Predefined. */
3753/* AC_INTMODE1_bp  Predefined. */
3754
3755/* AC_INTLVL_gm  Predefined. */
3756/* AC_INTLVL_gp  Predefined. */
3757/* AC_INTLVL0_bm  Predefined. */
3758/* AC_INTLVL0_bp  Predefined. */
3759/* AC_INTLVL1_bm  Predefined. */
3760/* AC_INTLVL1_bp  Predefined. */
3761
3762/* AC_HSMODE_bm  Predefined. */
3763/* AC_HSMODE_bp  Predefined. */
3764
3765/* AC_HYSMODE_gm  Predefined. */
3766/* AC_HYSMODE_gp  Predefined. */
3767/* AC_HYSMODE0_bm  Predefined. */
3768/* AC_HYSMODE0_bp  Predefined. */
3769/* AC_HYSMODE1_bm  Predefined. */
3770/* AC_HYSMODE1_bp  Predefined. */
3771
3772/* AC_ENABLE_bm  Predefined. */
3773/* AC_ENABLE_bp  Predefined. */
3774
3775
3776/* AC.AC0MUXCTRL  bit masks and bit positions */
3777#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
3778#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
3779#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
3780#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
3781#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
3782#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
3783#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
3784#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
3785
3786#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
3787#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
3788#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
3789#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
3790#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
3791#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
3792#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
3793#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
3794
3795
3796/* AC.AC1MUXCTRL  bit masks and bit positions */
3797/* AC_MUXPOS_gm  Predefined. */
3798/* AC_MUXPOS_gp  Predefined. */
3799/* AC_MUXPOS0_bm  Predefined. */
3800/* AC_MUXPOS0_bp  Predefined. */
3801/* AC_MUXPOS1_bm  Predefined. */
3802/* AC_MUXPOS1_bp  Predefined. */
3803/* AC_MUXPOS2_bm  Predefined. */
3804/* AC_MUXPOS2_bp  Predefined. */
3805
3806/* AC_MUXNEG_gm  Predefined. */
3807/* AC_MUXNEG_gp  Predefined. */
3808/* AC_MUXNEG0_bm  Predefined. */
3809/* AC_MUXNEG0_bp  Predefined. */
3810/* AC_MUXNEG1_bm  Predefined. */
3811/* AC_MUXNEG1_bp  Predefined. */
3812/* AC_MUXNEG2_bm  Predefined. */
3813/* AC_MUXNEG2_bp  Predefined. */
3814
3815
3816/* AC.CTRLA  bit masks and bit positions */
3817#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
3818#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
3819
3820
3821/* AC.CTRLB  bit masks and bit positions */
3822#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
3823#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
3824#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
3825#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
3826#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
3827#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
3828#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
3829#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
3830#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
3831#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
3832#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
3833#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
3834#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
3835#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
3836
3837
3838/* AC.WINCTRL  bit masks and bit positions */
3839#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
3840#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
3841
3842#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
3843#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
3844#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
3845#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
3846#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
3847#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
3848
3849#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
3850#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
3851#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
3852#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
3853#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
3854#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
3855
3856
3857/* AC.STATUS  bit masks and bit positions */
3858#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
3859#define AC_WSTATE_gp  6  /* Window Mode State group position. */
3860#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
3861#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
3862#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
3863#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
3864
3865#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
3866#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
3867
3868#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
3869#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
3870
3871#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
3872#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
3873
3874#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
3875#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
3876
3877#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
3878#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
3879
3880
3881/* ADC - Analog/Digital Converter */
3882/* ADC_CH.CTRL  bit masks and bit positions */
3883#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
3884#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
3885
3886#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
3887#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
3888#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
3889#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
3890#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
3891#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
3892#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
3893#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
3894
3895#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
3896#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
3897#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
3898#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
3899#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
3900#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
3901
3902
3903/* ADC_CH.MUXCTRL  bit masks and bit positions */
3904#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
3905#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
3906#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
3907#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
3908#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
3909#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
3910#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
3911#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
3912#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
3913#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
3914
3915#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
3916#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
3917#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
3918#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
3919#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
3920#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
3921
3922
3923/* ADC_CH.INTCTRL  bit masks and bit positions */
3924#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
3925#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
3926#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
3927#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
3928#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
3929#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
3930
3931#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
3932#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
3933#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
3934#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
3935#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
3936#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
3937
3938
3939/* ADC_CH.INTFLAGS  bit masks and bit positions */
3940#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
3941#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
3942
3943
3944/* ADC.CTRLA  bit masks and bit positions */
3945#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
3946#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
3947
3948#define ADC_FLUSH_bm  0x02  /* ADC Flush bit mask. */
3949#define ADC_FLUSH_bp  1  /* ADC Flush bit position. */
3950
3951#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
3952#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
3953
3954
3955/* ADC.CTRLB  bit masks and bit positions */
3956#define ADC_CURRLIMIT_gm  0x60  /* Current Limitation group mask. */
3957#define ADC_CURRLIMIT_gp  5  /* Current Limitation group position. */
3958#define ADC_CURRLIMIT0_bm  (1<<5)  /* Current Limitation bit 0 mask. */
3959#define ADC_CURRLIMIT0_bp  5  /* Current Limitation bit 0 position. */
3960#define ADC_CURRLIMIT1_bm  (1<<6)  /* Current Limitation bit 1 mask. */
3961#define ADC_CURRLIMIT1_bp  6  /* Current Limitation bit 1 position. */
3962
3963#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
3964#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
3965
3966#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
3967#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
3968
3969#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
3970#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
3971#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
3972#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
3973#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
3974#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
3975
3976
3977/* ADC.REFCTRL  bit masks and bit positions */
3978#define ADC_REFSEL_gm  0x70  /* Reference Selection group mask. */
3979#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
3980#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
3981#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
3982#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
3983#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
3984#define ADC_REFSEL2_bm  (1<<6)  /* Reference Selection bit 2 mask. */
3985#define ADC_REFSEL2_bp  6  /* Reference Selection bit 2 position. */
3986
3987#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
3988#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
3989
3990#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
3991#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
3992
3993
3994/* ADC.EVCTRL  bit masks and bit positions */
3995#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
3996#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
3997#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
3998#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
3999#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
4000#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
4001#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
4002#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
4003
4004#define ADC_EVACT_bm  0x01  /* Event Action Select bit mask. */
4005#define ADC_EVACT_bp  0  /* Event Action Select bit position. */
4006
4007
4008/* ADC.PRESCALER  bit masks and bit positions */
4009#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
4010#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
4011#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
4012#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
4013#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
4014#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
4015#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
4016#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
4017
4018
4019/* ADC.INTFLAGS  bit masks and bit positions */
4020#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
4021#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
4022
4023
4024/* RTC - Real-Time Clounter */
4025/* RTC.CTRL  bit masks and bit positions */
4026#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
4027#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
4028#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
4029#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
4030#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
4031#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
4032#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
4033#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
4034
4035
4036/* RTC.STATUS  bit masks and bit positions */
4037#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
4038#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
4039
4040
4041/* RTC.INTCTRL  bit masks and bit positions */
4042#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
4043#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
4044#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
4045#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
4046#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
4047#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
4048
4049#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
4050#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
4051#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
4052#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
4053#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
4054#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
4055
4056
4057/* RTC.INTFLAGS  bit masks and bit positions */
4058#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
4059#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
4060
4061#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
4062#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
4063
4064
4065/* EBI - External Bus Interface */
4066/* EBI_CS.CTRLA  bit masks and bit positions */
4067#define EBI_CS_ASIZE_gm  0x7C  /* Address Size group mask. */
4068#define EBI_CS_ASIZE_gp  2  /* Address Size group position. */
4069#define EBI_CS_ASIZE0_bm  (1<<2)  /* Address Size bit 0 mask. */
4070#define EBI_CS_ASIZE0_bp  2  /* Address Size bit 0 position. */
4071#define EBI_CS_ASIZE1_bm  (1<<3)  /* Address Size bit 1 mask. */
4072#define EBI_CS_ASIZE1_bp  3  /* Address Size bit 1 position. */
4073#define EBI_CS_ASIZE2_bm  (1<<4)  /* Address Size bit 2 mask. */
4074#define EBI_CS_ASIZE2_bp  4  /* Address Size bit 2 position. */
4075#define EBI_CS_ASIZE3_bm  (1<<5)  /* Address Size bit 3 mask. */
4076#define EBI_CS_ASIZE3_bp  5  /* Address Size bit 3 position. */
4077#define EBI_CS_ASIZE4_bm  (1<<6)  /* Address Size bit 4 mask. */
4078#define EBI_CS_ASIZE4_bp  6  /* Address Size bit 4 position. */
4079
4080#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
4081#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
4082#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
4083#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
4084#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
4085#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
4086
4087
4088/* EBI_CS.CTRLB  bit masks and bit positions */
4089#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
4090#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
4091#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
4092#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
4093#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
4094#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
4095#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
4096#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
4097
4098#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
4099#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
4100
4101#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
4102#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
4103
4104#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
4105#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
4106#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
4107#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
4108#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
4109#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
4110
4111
4112/* EBI.CTRL  bit masks and bit positions */
4113#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
4114#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
4115#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
4116#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
4117#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
4118#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
4119
4120#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
4121#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
4122#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
4123#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
4124#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
4125#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
4126
4127#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
4128#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
4129#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
4130#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
4131#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
4132#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
4133
4134#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
4135#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
4136#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
4137#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
4138#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
4139#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
4140
4141
4142/* EBI.SDRAMCTRLA  bit masks and bit positions */
4143#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
4144#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
4145
4146#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
4147#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
4148
4149#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
4150#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
4151#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
4152#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
4153#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
4154#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
4155
4156
4157/* EBI.SDRAMCTRLB  bit masks and bit positions */
4158#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
4159#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
4160#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
4161#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
4162#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
4163#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
4164
4165#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
4166#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
4167#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
4168#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
4169#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
4170#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
4171#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
4172#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
4173
4174#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
4175#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
4176#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
4177#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
4178#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
4179#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
4180#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
4181#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
4182
4183
4184/* EBI.SDRAMCTRLC  bit masks and bit positions */
4185#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
4186#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
4187#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
4188#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
4189#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
4190#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
4191
4192#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
4193#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
4194#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
4195#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
4196#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
4197#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
4198#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
4199#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
4200
4201#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
4202#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
4203#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
4204#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
4205#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
4206#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
4207#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
4208#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
4209
4210
4211/* TWI - Two-Wire Interface */
4212/* TWI_MASTER.CTRLA  bit masks and bit positions */
4213#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
4214#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
4215#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
4216#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
4217#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
4218#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
4219
4220#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
4221#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
4222
4223#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
4224#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
4225
4226#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
4227#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
4228
4229
4230/* TWI_MASTER.CTRLB  bit masks and bit positions */
4231#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
4232#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
4233#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
4234#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
4235#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
4236#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
4237
4238#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
4239#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
4240
4241#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
4242#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
4243
4244
4245/* TWI_MASTER.CTRLC  bit masks and bit positions */
4246#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
4247#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
4248
4249#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
4250#define TWI_MASTER_CMD_gp  0  /* Command group position. */
4251#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
4252#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
4253#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
4254#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
4255
4256
4257/* TWI_MASTER.STATUS  bit masks and bit positions */
4258#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
4259#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
4260
4261#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
4262#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
4263
4264#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
4265#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
4266
4267#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
4268#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
4269
4270#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
4271#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
4272
4273#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
4274#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
4275
4276#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
4277#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
4278#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
4279#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
4280#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
4281#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
4282
4283
4284/* TWI_SLAVE.CTRLA  bit masks and bit positions */
4285#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
4286#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
4287#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
4288#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
4289#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
4290#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
4291
4292#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
4293#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
4294
4295#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
4296#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
4297
4298#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
4299#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
4300
4301#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
4302#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
4303
4304#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
4305#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
4306
4307#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
4308#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
4309
4310
4311/* TWI_SLAVE.CTRLB  bit masks and bit positions */
4312#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
4313#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
4314
4315#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
4316#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
4317#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
4318#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
4319#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
4320#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
4321
4322
4323/* TWI_SLAVE.STATUS  bit masks and bit positions */
4324#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
4325#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
4326
4327#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
4328#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
4329
4330#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
4331#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
4332
4333#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
4334#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
4335
4336#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
4337#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
4338
4339#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
4340#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
4341
4342#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
4343#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
4344
4345#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
4346#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
4347
4348
4349/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
4350#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
4351#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
4352#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
4353#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
4354#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
4355#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
4356#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
4357#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
4358#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
4359#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
4360#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
4361#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
4362#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
4363#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
4364#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
4365#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
4366
4367#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
4368#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
4369
4370
4371/* TWI.CTRL  bit masks and bit positions */
4372#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
4373#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
4374
4375#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
4376#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
4377
4378
4379/* PORT - Port Configuration */
4380/* PORTCFG.VPCTRLA  bit masks and bit positions */
4381#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
4382#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
4383#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
4384#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
4385#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
4386#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
4387#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
4388#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
4389#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
4390#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
4391
4392#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
4393#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
4394#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
4395#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
4396#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
4397#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
4398#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
4399#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
4400#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
4401#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
4402
4403
4404/* PORTCFG.VPCTRLB  bit masks and bit positions */
4405#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
4406#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
4407#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
4408#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
4409#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
4410#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
4411#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
4412#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
4413#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
4414#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
4415
4416#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
4417#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
4418#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
4419#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
4420#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
4421#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
4422#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
4423#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
4424#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
4425#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
4426
4427
4428/* PORTCFG.CLKEVOUT  bit masks and bit positions */
4429#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
4430#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
4431#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
4432#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
4433#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
4434#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
4435
4436#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
4437#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
4438#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
4439#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
4440#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
4441#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
4442
4443
4444/* VPORT.INTFLAGS  bit masks and bit positions */
4445#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
4446#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
4447
4448#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
4449#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
4450
4451
4452/* PORT.INTCTRL  bit masks and bit positions */
4453#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
4454#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
4455#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
4456#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
4457#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
4458#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
4459
4460#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
4461#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
4462#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
4463#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
4464#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
4465#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
4466
4467
4468/* PORT.INTFLAGS  bit masks and bit positions */
4469#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
4470#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
4471
4472#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
4473#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
4474
4475
4476/* PORT.PIN0CTRL  bit masks and bit positions */
4477#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
4478#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
4479
4480#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
4481#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
4482
4483#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
4484#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
4485#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
4486#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
4487#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
4488#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
4489#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
4490#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
4491
4492#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
4493#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
4494#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
4495#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
4496#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
4497#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
4498#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
4499#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
4500
4501
4502/* PORT.PIN1CTRL  bit masks and bit positions */
4503/* PORT_SRLEN_bm  Predefined. */
4504/* PORT_SRLEN_bp  Predefined. */
4505
4506/* PORT_INVEN_bm  Predefined. */
4507/* PORT_INVEN_bp  Predefined. */
4508
4509/* PORT_OPC_gm  Predefined. */
4510/* PORT_OPC_gp  Predefined. */
4511/* PORT_OPC0_bm  Predefined. */
4512/* PORT_OPC0_bp  Predefined. */
4513/* PORT_OPC1_bm  Predefined. */
4514/* PORT_OPC1_bp  Predefined. */
4515/* PORT_OPC2_bm  Predefined. */
4516/* PORT_OPC2_bp  Predefined. */
4517
4518/* PORT_ISC_gm  Predefined. */
4519/* PORT_ISC_gp  Predefined. */
4520/* PORT_ISC0_bm  Predefined. */
4521/* PORT_ISC0_bp  Predefined. */
4522/* PORT_ISC1_bm  Predefined. */
4523/* PORT_ISC1_bp  Predefined. */
4524/* PORT_ISC2_bm  Predefined. */
4525/* PORT_ISC2_bp  Predefined. */
4526
4527
4528/* PORT.PIN2CTRL  bit masks and bit positions */
4529/* PORT_SRLEN_bm  Predefined. */
4530/* PORT_SRLEN_bp  Predefined. */
4531
4532/* PORT_INVEN_bm  Predefined. */
4533/* PORT_INVEN_bp  Predefined. */
4534
4535/* PORT_OPC_gm  Predefined. */
4536/* PORT_OPC_gp  Predefined. */
4537/* PORT_OPC0_bm  Predefined. */
4538/* PORT_OPC0_bp  Predefined. */
4539/* PORT_OPC1_bm  Predefined. */
4540/* PORT_OPC1_bp  Predefined. */
4541/* PORT_OPC2_bm  Predefined. */
4542/* PORT_OPC2_bp  Predefined. */
4543
4544/* PORT_ISC_gm  Predefined. */
4545/* PORT_ISC_gp  Predefined. */
4546/* PORT_ISC0_bm  Predefined. */
4547/* PORT_ISC0_bp  Predefined. */
4548/* PORT_ISC1_bm  Predefined. */
4549/* PORT_ISC1_bp  Predefined. */
4550/* PORT_ISC2_bm  Predefined. */
4551/* PORT_ISC2_bp  Predefined. */
4552
4553
4554/* PORT.PIN3CTRL  bit masks and bit positions */
4555/* PORT_SRLEN_bm  Predefined. */
4556/* PORT_SRLEN_bp  Predefined. */
4557
4558/* PORT_INVEN_bm  Predefined. */
4559/* PORT_INVEN_bp  Predefined. */
4560
4561/* PORT_OPC_gm  Predefined. */
4562/* PORT_OPC_gp  Predefined. */
4563/* PORT_OPC0_bm  Predefined. */
4564/* PORT_OPC0_bp  Predefined. */
4565/* PORT_OPC1_bm  Predefined. */
4566/* PORT_OPC1_bp  Predefined. */
4567/* PORT_OPC2_bm  Predefined. */
4568/* PORT_OPC2_bp  Predefined. */
4569
4570/* PORT_ISC_gm  Predefined. */
4571/* PORT_ISC_gp  Predefined. */
4572/* PORT_ISC0_bm  Predefined. */
4573/* PORT_ISC0_bp  Predefined. */
4574/* PORT_ISC1_bm  Predefined. */
4575/* PORT_ISC1_bp  Predefined. */
4576/* PORT_ISC2_bm  Predefined. */
4577/* PORT_ISC2_bp  Predefined. */
4578
4579
4580/* PORT.PIN4CTRL  bit masks and bit positions */
4581/* PORT_SRLEN_bm  Predefined. */
4582/* PORT_SRLEN_bp  Predefined. */
4583
4584/* PORT_INVEN_bm  Predefined. */
4585/* PORT_INVEN_bp  Predefined. */
4586
4587/* PORT_OPC_gm  Predefined. */
4588/* PORT_OPC_gp  Predefined. */
4589/* PORT_OPC0_bm  Predefined. */
4590/* PORT_OPC0_bp  Predefined. */
4591/* PORT_OPC1_bm  Predefined. */
4592/* PORT_OPC1_bp  Predefined. */
4593/* PORT_OPC2_bm  Predefined. */
4594/* PORT_OPC2_bp  Predefined. */
4595
4596/* PORT_ISC_gm  Predefined. */
4597/* PORT_ISC_gp  Predefined. */
4598/* PORT_ISC0_bm  Predefined. */
4599/* PORT_ISC0_bp  Predefined. */
4600/* PORT_ISC1_bm  Predefined. */
4601/* PORT_ISC1_bp  Predefined. */
4602/* PORT_ISC2_bm  Predefined. */
4603/* PORT_ISC2_bp  Predefined. */
4604
4605
4606/* PORT.PIN5CTRL  bit masks and bit positions */
4607/* PORT_SRLEN_bm  Predefined. */
4608/* PORT_SRLEN_bp  Predefined. */
4609
4610/* PORT_INVEN_bm  Predefined. */
4611/* PORT_INVEN_bp  Predefined. */
4612
4613/* PORT_OPC_gm  Predefined. */
4614/* PORT_OPC_gp  Predefined. */
4615/* PORT_OPC0_bm  Predefined. */
4616/* PORT_OPC0_bp  Predefined. */
4617/* PORT_OPC1_bm  Predefined. */
4618/* PORT_OPC1_bp  Predefined. */
4619/* PORT_OPC2_bm  Predefined. */
4620/* PORT_OPC2_bp  Predefined. */
4621
4622/* PORT_ISC_gm  Predefined. */
4623/* PORT_ISC_gp  Predefined. */
4624/* PORT_ISC0_bm  Predefined. */
4625/* PORT_ISC0_bp  Predefined. */
4626/* PORT_ISC1_bm  Predefined. */
4627/* PORT_ISC1_bp  Predefined. */
4628/* PORT_ISC2_bm  Predefined. */
4629/* PORT_ISC2_bp  Predefined. */
4630
4631
4632/* PORT.PIN6CTRL  bit masks and bit positions */
4633/* PORT_SRLEN_bm  Predefined. */
4634/* PORT_SRLEN_bp  Predefined. */
4635
4636/* PORT_INVEN_bm  Predefined. */
4637/* PORT_INVEN_bp  Predefined. */
4638
4639/* PORT_OPC_gm  Predefined. */
4640/* PORT_OPC_gp  Predefined. */
4641/* PORT_OPC0_bm  Predefined. */
4642/* PORT_OPC0_bp  Predefined. */
4643/* PORT_OPC1_bm  Predefined. */
4644/* PORT_OPC1_bp  Predefined. */
4645/* PORT_OPC2_bm  Predefined. */
4646/* PORT_OPC2_bp  Predefined. */
4647
4648/* PORT_ISC_gm  Predefined. */
4649/* PORT_ISC_gp  Predefined. */
4650/* PORT_ISC0_bm  Predefined. */
4651/* PORT_ISC0_bp  Predefined. */
4652/* PORT_ISC1_bm  Predefined. */
4653/* PORT_ISC1_bp  Predefined. */
4654/* PORT_ISC2_bm  Predefined. */
4655/* PORT_ISC2_bp  Predefined. */
4656
4657
4658/* PORT.PIN7CTRL  bit masks and bit positions */
4659/* PORT_SRLEN_bm  Predefined. */
4660/* PORT_SRLEN_bp  Predefined. */
4661
4662/* PORT_INVEN_bm  Predefined. */
4663/* PORT_INVEN_bp  Predefined. */
4664
4665/* PORT_OPC_gm  Predefined. */
4666/* PORT_OPC_gp  Predefined. */
4667/* PORT_OPC0_bm  Predefined. */
4668/* PORT_OPC0_bp  Predefined. */
4669/* PORT_OPC1_bm  Predefined. */
4670/* PORT_OPC1_bp  Predefined. */
4671/* PORT_OPC2_bm  Predefined. */
4672/* PORT_OPC2_bp  Predefined. */
4673
4674/* PORT_ISC_gm  Predefined. */
4675/* PORT_ISC_gp  Predefined. */
4676/* PORT_ISC0_bm  Predefined. */
4677/* PORT_ISC0_bp  Predefined. */
4678/* PORT_ISC1_bm  Predefined. */
4679/* PORT_ISC1_bp  Predefined. */
4680/* PORT_ISC2_bm  Predefined. */
4681/* PORT_ISC2_bp  Predefined. */
4682
4683
4684/* TC - 16-bit Timer/Counter With PWM */
4685/* TC0.CTRLA  bit masks and bit positions */
4686#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4687#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
4688#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4689#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4690#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4691#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4692#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4693#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4694#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4695#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4696
4697
4698/* TC0.CTRLB  bit masks and bit positions */
4699#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
4700#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
4701
4702#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
4703#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
4704
4705#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
4706#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
4707
4708#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
4709#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
4710
4711#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
4712#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
4713#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
4714#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
4715#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
4716#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
4717#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
4718#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
4719
4720
4721/* TC0.CTRLC  bit masks and bit positions */
4722#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
4723#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
4724
4725#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
4726#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
4727
4728#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
4729#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
4730
4731#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
4732#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
4733
4734
4735/* TC0.CTRLD  bit masks and bit positions */
4736#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
4737#define TC0_EVACT_gp  5  /* Event Action group position. */
4738#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
4739#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
4740#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
4741#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
4742#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
4743#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
4744
4745#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
4746#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
4747
4748#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
4749#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
4750#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
4751#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
4752#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
4753#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
4754#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
4755#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
4756#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
4757#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
4758
4759
4760/* TC0.CTRLE  bit masks and bit positions */
4761#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
4762#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
4763
4764
4765/* TC0.INTCTRLA  bit masks and bit positions */
4766#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
4767#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
4768#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
4769#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
4770#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
4771#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
4772
4773#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
4774#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
4775#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
4776#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
4777#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
4778#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
4779
4780
4781/* TC0.INTCTRLB  bit masks and bit positions */
4782#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
4783#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
4784#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
4785#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
4786#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
4787#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
4788
4789#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
4790#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
4791#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
4792#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
4793#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
4794#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
4795
4796#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
4797#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
4798#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
4799#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
4800#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
4801#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
4802
4803#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
4804#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
4805#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
4806#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
4807#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
4808#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
4809
4810
4811/* TC0.CTRLFCLR  bit masks and bit positions */
4812#define TC0_CMD_gm  0x0C  /* Command group mask. */
4813#define TC0_CMD_gp  2  /* Command group position. */
4814#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
4815#define TC0_CMD0_bp  2  /* Command bit 0 position. */
4816#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
4817#define TC0_CMD1_bp  3  /* Command bit 1 position. */
4818
4819#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
4820#define TC0_LUPD_bp  1  /* Lock Update bit position. */
4821
4822#define TC0_DIR_bm  0x01  /* Direction bit mask. */
4823#define TC0_DIR_bp  0  /* Direction bit position. */
4824
4825
4826/* TC0.CTRLFSET  bit masks and bit positions */
4827/* TC0_CMD_gm  Predefined. */
4828/* TC0_CMD_gp  Predefined. */
4829/* TC0_CMD0_bm  Predefined. */
4830/* TC0_CMD0_bp  Predefined. */
4831/* TC0_CMD1_bm  Predefined. */
4832/* TC0_CMD1_bp  Predefined. */
4833
4834/* TC0_LUPD_bm  Predefined. */
4835/* TC0_LUPD_bp  Predefined. */
4836
4837/* TC0_DIR_bm  Predefined. */
4838/* TC0_DIR_bp  Predefined. */
4839
4840
4841/* TC0.CTRLGCLR  bit masks and bit positions */
4842#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
4843#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
4844
4845#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
4846#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
4847
4848#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
4849#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
4850
4851#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
4852#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
4853
4854#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
4855#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
4856
4857
4858/* TC0.CTRLGSET  bit masks and bit positions */
4859/* TC0_CCDBV_bm  Predefined. */
4860/* TC0_CCDBV_bp  Predefined. */
4861
4862/* TC0_CCCBV_bm  Predefined. */
4863/* TC0_CCCBV_bp  Predefined. */
4864
4865/* TC0_CCBBV_bm  Predefined. */
4866/* TC0_CCBBV_bp  Predefined. */
4867
4868/* TC0_CCABV_bm  Predefined. */
4869/* TC0_CCABV_bp  Predefined. */
4870
4871/* TC0_PERBV_bm  Predefined. */
4872/* TC0_PERBV_bp  Predefined. */
4873
4874
4875/* TC0.INTFLAGS  bit masks and bit positions */
4876#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
4877#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
4878
4879#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
4880#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
4881
4882#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
4883#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
4884
4885#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
4886#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
4887
4888#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
4889#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
4890
4891#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
4892#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
4893
4894
4895/* TC1.CTRLA  bit masks and bit positions */
4896#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4897#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
4898#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4899#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4900#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4901#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4902#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4903#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4904#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4905#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4906
4907
4908/* TC1.CTRLB  bit masks and bit positions */
4909#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
4910#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
4911
4912#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
4913#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
4914
4915#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
4916#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
4917#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
4918#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
4919#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
4920#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
4921#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
4922#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
4923
4924
4925/* TC1.CTRLC  bit masks and bit positions */
4926#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
4927#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
4928
4929#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
4930#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
4931
4932
4933/* TC1.CTRLD  bit masks and bit positions */
4934#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
4935#define TC1_EVACT_gp  5  /* Event Action group position. */
4936#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
4937#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
4938#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
4939#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
4940#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
4941#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
4942
4943#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
4944#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
4945
4946#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
4947#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
4948#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
4949#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
4950#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
4951#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
4952#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
4953#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
4954#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
4955#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
4956
4957
4958/* TC1.CTRLE  bit masks and bit positions */
4959#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
4960#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
4961
4962
4963/* TC1.INTCTRLA  bit masks and bit positions */
4964#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
4965#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
4966#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
4967#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
4968#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
4969#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
4970
4971#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
4972#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
4973#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
4974#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
4975#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
4976#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
4977
4978
4979/* TC1.INTCTRLB  bit masks and bit positions */
4980#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
4981#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
4982#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
4983#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
4984#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
4985#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
4986
4987#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
4988#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
4989#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
4990#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
4991#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
4992#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
4993
4994
4995/* TC1.CTRLFCLR  bit masks and bit positions */
4996#define TC1_CMD_gm  0x0C  /* Command group mask. */
4997#define TC1_CMD_gp  2  /* Command group position. */
4998#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
4999#define TC1_CMD0_bp  2  /* Command bit 0 position. */
5000#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
5001#define TC1_CMD1_bp  3  /* Command bit 1 position. */
5002
5003#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
5004#define TC1_LUPD_bp  1  /* Lock Update bit position. */
5005
5006#define TC1_DIR_bm  0x01  /* Direction bit mask. */
5007#define TC1_DIR_bp  0  /* Direction bit position. */
5008
5009
5010/* TC1.CTRLFSET  bit masks and bit positions */
5011/* TC1_CMD_gm  Predefined. */
5012/* TC1_CMD_gp  Predefined. */
5013/* TC1_CMD0_bm  Predefined. */
5014/* TC1_CMD0_bp  Predefined. */
5015/* TC1_CMD1_bm  Predefined. */
5016/* TC1_CMD1_bp  Predefined. */
5017
5018/* TC1_LUPD_bm  Predefined. */
5019/* TC1_LUPD_bp  Predefined. */
5020
5021/* TC1_DIR_bm  Predefined. */
5022/* TC1_DIR_bp  Predefined. */
5023
5024
5025/* TC1.CTRLGCLR  bit masks and bit positions */
5026#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
5027#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
5028
5029#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
5030#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
5031
5032#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
5033#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
5034
5035
5036/* TC1.CTRLGSET  bit masks and bit positions */
5037/* TC1_CCBBV_bm  Predefined. */
5038/* TC1_CCBBV_bp  Predefined. */
5039
5040/* TC1_CCABV_bm  Predefined. */
5041/* TC1_CCABV_bp  Predefined. */
5042
5043/* TC1_PERBV_bm  Predefined. */
5044/* TC1_PERBV_bp  Predefined. */
5045
5046
5047/* TC1.INTFLAGS  bit masks and bit positions */
5048#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
5049#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
5050
5051#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
5052#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
5053
5054#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
5055#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
5056
5057#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
5058#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
5059
5060
5061/* AWEX.CTRL  bit masks and bit positions */
5062#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
5063#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
5064
5065#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
5066#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
5067
5068#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
5069#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
5070
5071#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
5072#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
5073
5074#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
5075#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
5076
5077#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
5078#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
5079
5080
5081/* AWEX.FDCTRL  bit masks and bit positions */
5082#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
5083#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
5084
5085#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
5086#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
5087
5088#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
5089#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
5090#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
5091#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
5092#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
5093#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
5094
5095
5096/* AWEX.STATUS  bit masks and bit positions */
5097#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
5098#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
5099
5100#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
5101#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
5102
5103#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
5104#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
5105
5106
5107/* HIRES.CTRLA  bit masks and bit positions */
5108#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
5109#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
5110#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
5111#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
5112#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
5113#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
5114
5115
5116/* USART - Universal Asynchronous Receiver-Transmitter */
5117/* USART.STATUS  bit masks and bit positions */
5118#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
5119#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
5120
5121#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
5122#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
5123
5124#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
5125#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
5126
5127#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
5128#define USART_FERR_bp  4  /* Frame Error bit position. */
5129
5130#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
5131#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
5132
5133#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
5134#define USART_PERR_bp  2  /* Parity Error bit position. */
5135
5136#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
5137#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
5138
5139
5140/* USART.CTRLA  bit masks and bit positions */
5141#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
5142#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
5143#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
5144#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
5145#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
5146#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
5147
5148#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
5149#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
5150#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
5151#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
5152#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
5153#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
5154
5155#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
5156#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
5157#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
5158#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
5159#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
5160#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
5161
5162
5163/* USART.CTRLB  bit masks and bit positions */
5164#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
5165#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
5166
5167#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
5168#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
5169
5170#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
5171#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
5172
5173#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
5174#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
5175
5176#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
5177#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
5178
5179
5180/* USART.CTRLC  bit masks and bit positions */
5181#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
5182#define USART_CMODE_gp  6  /* Communication Mode group position. */
5183#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
5184#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
5185#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
5186#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
5187
5188#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
5189#define USART_PMODE_gp  4  /* Parity Mode group position. */
5190#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
5191#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
5192#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
5193#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
5194
5195#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
5196#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
5197
5198#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
5199#define USART_CHSIZE_gp  0  /* Character Size group position. */
5200#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
5201#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
5202#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
5203#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
5204#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
5205#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
5206
5207
5208/* USART.BAUDCTRLA  bit masks and bit positions */
5209#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
5210#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
5211#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
5212#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
5213#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
5214#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
5215#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
5216#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
5217#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
5218#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
5219#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
5220#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
5221#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
5222#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
5223#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
5224#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
5225#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
5226#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
5227
5228
5229/* USART.BAUDCTRLB  bit masks and bit positions */
5230#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
5231#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
5232#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
5233#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
5234#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
5235#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
5236#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
5237#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
5238#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
5239#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
5240
5241/* USART_BSEL_gm  Predefined. */
5242/* USART_BSEL_gp  Predefined. */
5243/* USART_BSEL0_bm  Predefined. */
5244/* USART_BSEL0_bp  Predefined. */
5245/* USART_BSEL1_bm  Predefined. */
5246/* USART_BSEL1_bp  Predefined. */
5247/* USART_BSEL2_bm  Predefined. */
5248/* USART_BSEL2_bp  Predefined. */
5249/* USART_BSEL3_bm  Predefined. */
5250/* USART_BSEL3_bp  Predefined. */
5251
5252
5253/* SPI - Serial Peripheral Interface */
5254/* SPI.CTRL  bit masks and bit positions */
5255#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
5256#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
5257
5258#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
5259#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
5260
5261#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
5262#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
5263
5264#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
5265#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
5266
5267#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
5268#define SPI_MODE_gp  2  /* SPI Mode group position. */
5269#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
5270#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
5271#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
5272#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
5273
5274#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
5275#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
5276#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
5277#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
5278#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
5279#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
5280
5281
5282/* SPI.INTCTRL  bit masks and bit positions */
5283#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
5284#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
5285#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
5286#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
5287#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
5288#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
5289
5290
5291/* SPI.STATUS  bit masks and bit positions */
5292#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
5293#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
5294
5295#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
5296#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
5297
5298
5299/* IRCOM - IR Communication Module */
5300/* IRCOM.CTRL  bit masks and bit positions */
5301#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
5302#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
5303#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
5304#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
5305#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
5306#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
5307#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
5308#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
5309#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
5310#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
5311
5312
5313
5314// Generic Port Pins
5315
5316#define PIN0_bm 0x01
5317#define PIN0_bp 0
5318#define PIN1_bm 0x02
5319#define PIN1_bp 1
5320#define PIN2_bm 0x04
5321#define PIN2_bp 2
5322#define PIN3_bm 0x08
5323#define PIN3_bp 3
5324#define PIN4_bm 0x10
5325#define PIN4_bp 4
5326#define PIN5_bm 0x20
5327#define PIN5_bp 5
5328#define PIN6_bm 0x40
5329#define PIN6_bp 6
5330#define PIN7_bm 0x80
5331#define PIN7_bp 7
5332
5333
5334/* ========== Interrupt Vector Definitions ========== */
5335/* Vector 0 is the reset vector */
5336
5337/* OSC interrupt vectors */
5338#define OSC_XOSCF_vect_num  1
5339#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
5340
5341/* PORTC interrupt vectors */
5342#define PORTC_INT0_vect_num  2
5343#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
5344#define PORTC_INT1_vect_num  3
5345#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
5346
5347/* PORTR interrupt vectors */
5348#define PORTR_INT0_vect_num  4
5349#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
5350#define PORTR_INT1_vect_num  5
5351#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
5352
5353/* RTC interrupt vectors */
5354#define RTC_OVF_vect_num  10
5355#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
5356#define RTC_COMP_vect_num  11
5357#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
5358
5359/* TWIC interrupt vectors */
5360#define TWIC_TWIS_vect_num  12
5361#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
5362#define TWIC_TWIM_vect_num  13
5363#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
5364
5365/* TCC0 interrupt vectors */
5366#define TCC0_OVF_vect_num  14
5367#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
5368#define TCC0_ERR_vect_num  15
5369#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
5370#define TCC0_CCA_vect_num  16
5371#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
5372#define TCC0_CCB_vect_num  17
5373#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
5374#define TCC0_CCC_vect_num  18
5375#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
5376#define TCC0_CCD_vect_num  19
5377#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
5378
5379/* TCC1 interrupt vectors */
5380#define TCC1_OVF_vect_num  20
5381#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
5382#define TCC1_ERR_vect_num  21
5383#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
5384#define TCC1_CCA_vect_num  22
5385#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
5386#define TCC1_CCB_vect_num  23
5387#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
5388
5389/* SPIC interrupt vectors */
5390#define SPIC_INT_vect_num  24
5391#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
5392
5393/* USARTC0 interrupt vectors */
5394#define USARTC0_RXC_vect_num  25
5395#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
5396#define USARTC0_DRE_vect_num  26
5397#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
5398#define USARTC0_TXC_vect_num  27
5399#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
5400
5401/* NVM interrupt vectors */
5402#define NVM_EE_vect_num  32
5403#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
5404#define NVM_SPM_vect_num  33
5405#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
5406
5407/* PORTB interrupt vectors */
5408#define PORTB_INT0_vect_num  34
5409#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
5410#define PORTB_INT1_vect_num  35
5411#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
5412
5413/* PORTE interrupt vectors */
5414#define PORTE_INT0_vect_num  43
5415#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
5416#define PORTE_INT1_vect_num  44
5417#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
5418
5419/* TWIE interrupt vectors */
5420#define TWIE_TWIS_vect_num  45
5421#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
5422#define TWIE_TWIM_vect_num  46
5423#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
5424
5425/* TCE0 interrupt vectors */
5426#define TCE0_OVF_vect_num  47
5427#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
5428#define TCE0_ERR_vect_num  48
5429#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
5430#define TCE0_CCA_vect_num  49
5431#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
5432#define TCE0_CCB_vect_num  50
5433#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
5434#define TCE0_CCC_vect_num  51
5435#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
5436#define TCE0_CCD_vect_num  52
5437#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
5438
5439/* USARTE0 interrupt vectors */
5440#define USARTE0_RXC_vect_num  58
5441#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
5442#define USARTE0_DRE_vect_num  59
5443#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
5444#define USARTE0_TXC_vect_num  60
5445#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
5446
5447/* PORTD interrupt vectors */
5448#define PORTD_INT0_vect_num  64
5449#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
5450#define PORTD_INT1_vect_num  65
5451#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
5452
5453/* PORTA interrupt vectors */
5454#define PORTA_INT0_vect_num  66
5455#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
5456#define PORTA_INT1_vect_num  67
5457#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
5458
5459/* ACA interrupt vectors */
5460#define ACA_AC0_vect_num  68
5461#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
5462#define ACA_AC1_vect_num  69
5463#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
5464#define ACA_ACW_vect_num  70
5465#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
5466
5467/* ADCA interrupt vectors */
5468#define ADCA_CH0_vect_num  71
5469#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
5470
5471/* TCD0 interrupt vectors */
5472#define TCD0_OVF_vect_num  77
5473#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
5474#define TCD0_ERR_vect_num  78
5475#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
5476#define TCD0_CCA_vect_num  79
5477#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
5478#define TCD0_CCB_vect_num  80
5479#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
5480#define TCD0_CCC_vect_num  81
5481#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
5482#define TCD0_CCD_vect_num  82
5483#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
5484
5485/* SPID interrupt vectors */
5486#define SPID_INT_vect_num  87
5487#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
5488
5489/* USARTD0 interrupt vectors */
5490#define USARTD0_RXC_vect_num  88
5491#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
5492#define USARTD0_DRE_vect_num  89
5493#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
5494#define USARTD0_TXC_vect_num  90
5495#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
5496
5497/* PORTF interrupt vectors */
5498#define PORTF_INT0_vect_num  104
5499#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
5500#define PORTF_INT1_vect_num  105
5501#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
5502
5503/* TCF0 interrupt vectors */
5504#define TCF0_OVF_vect_num  108
5505#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
5506#define TCF0_ERR_vect_num  109
5507#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
5508#define TCF0_CCA_vect_num  110
5509#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
5510#define TCF0_CCB_vect_num  111
5511#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
5512#define TCF0_CCC_vect_num  112
5513#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
5514#define TCF0_CCD_vect_num  113
5515#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
5516
5517
5518#define _VECTOR_SIZE 4 /* Size of individual vector. */
5519#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
5520
5521
5522/* ========== Constants ========== */
5523
5524#define PROGMEM_START     (0x0000)
5525#define PROGMEM_SIZE      (270336)
5526#define PROGMEM_PAGE_SIZE (512)
5527#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
5528
5529#define APP_SECTION_START     (0x0000)
5530#define APP_SECTION_SIZE      (262144)
5531#define APP_SECTION_PAGE_SIZE (512)
5532#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
5533
5534#define APPTABLE_SECTION_START     (0x3E000)
5535#define APPTABLE_SECTION_SIZE      (8192)
5536#define APPTABLE_SECTION_PAGE_SIZE (512)
5537#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
5538
5539#define BOOT_SECTION_START     (0x40000)
5540#define BOOT_SECTION_SIZE      (8192)
5541#define BOOT_SECTION_PAGE_SIZE (512)
5542#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
5543
5544#define DATAMEM_START     (0x0000)
5545#define DATAMEM_SIZE      (24576)
5546#define DATAMEM_PAGE_SIZE (0)
5547#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
5548
5549#define IO_START     (0x0000)
5550#define IO_SIZE      (4096)
5551#define IO_PAGE_SIZE (0)
5552#define IO_END       (IO_START + IO_SIZE - 1)
5553
5554#define MAPPED_EEPROM_START     (0x1000)
5555#define MAPPED_EEPROM_SIZE      (4096)
5556#define MAPPED_EEPROM_PAGE_SIZE (0)
5557#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
5558
5559#define INTERNAL_SRAM_START     (0x2000)
5560#define INTERNAL_SRAM_SIZE      (16384)
5561#define INTERNAL_SRAM_PAGE_SIZE (0)
5562#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
5563
5564#define EEPROM_START     (0x0000)
5565#define EEPROM_SIZE      (4096)
5566#define EEPROM_PAGE_SIZE (32)
5567#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
5568
5569#define FUSE_START     (0x0000)
5570#define FUSE_SIZE      (6)
5571#define FUSE_PAGE_SIZE (0)
5572#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
5573
5574#define LOCKBIT_START     (0x0000)
5575#define LOCKBIT_SIZE      (1)
5576#define LOCKBIT_PAGE_SIZE (0)
5577#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
5578
5579#define SIGNATURES_START     (0x0000)
5580#define SIGNATURES_SIZE      (3)
5581#define SIGNATURES_PAGE_SIZE (0)
5582#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
5583
5584#define USER_SIGNATURES_START     (0x0000)
5585#define USER_SIGNATURES_SIZE      (512)
5586#define USER_SIGNATURES_PAGE_SIZE (0)
5587#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
5588
5589#define PROD_SIGNATURES_START     (0x0000)
5590#define PROD_SIGNATURES_SIZE      (52)
5591#define PROD_SIGNATURES_PAGE_SIZE (0)
5592#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
5593
5594#define FLASHEND     PROGMEM_END
5595#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
5596#define RAMSTART     INTERNAL_SRAM_START
5597#define RAMSIZE      INTERNAL_SRAM_SIZE
5598#define RAMEND       INTERNAL_SRAM_END
5599#define XRAMSTART    EXTERNAL_SRAM_START
5600#define XRAMSIZE     EXTERNAL_SRAM_SIZE
5601#define XRAMEND      INTERNAL_SRAM_END
5602#define E2END        EEPROM_END
5603#define E2PAGESIZE   EEPROM_PAGE_SIZE
5604
5605
5606/* ========== Fuses ========== */
5607#define FUSE_MEMORY_SIZE 6
5608
5609/* Fuse Byte 0 */
5610#define FUSE_USERID0  (unsigned char)~_BV(0)  /* User ID Bit 0 */
5611#define FUSE_USERID1  (unsigned char)~_BV(1)  /* User ID Bit 1 */
5612#define FUSE_USERID2  (unsigned char)~_BV(2)  /* User ID Bit 2 */
5613#define FUSE_USERID3  (unsigned char)~_BV(3)  /* User ID Bit 3 */
5614#define FUSE_USERID4  (unsigned char)~_BV(4)  /* User ID Bit 4 */
5615#define FUSE_USERID5  (unsigned char)~_BV(5)  /* User ID Bit 5 */
5616#define FUSE_USERID6  (unsigned char)~_BV(6)  /* User ID Bit 6 */
5617#define FUSE_USERID7  (unsigned char)~_BV(7)  /* User ID Bit 7 */
5618#define FUSE0_DEFAULT  (0xFF)
5619
5620/* Fuse Byte 1 */
5621#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
5622#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
5623#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
5624#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
5625#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
5626#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
5627#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
5628#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
5629#define FUSE1_DEFAULT  (0xFF)
5630
5631/* Fuse Byte 2 */
5632#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
5633#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
5634#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
5635#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
5636#define FUSE2_DEFAULT  (0xFF)
5637
5638/* Fuse Byte 3 Reserved */
5639
5640/* Fuse Byte 4 */
5641#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
5642#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
5643#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
5644#define FUSE_RSTDISBL  (unsigned char)~_BV(4)  /* External Reset Disable */
5645#define FUSE4_DEFAULT  (0xFF)
5646
5647/* Fuse Byte 5 */
5648#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
5649#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
5650#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
5651#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
5652#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
5653#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
5654#define FUSE5_DEFAULT  (0xFF)
5655
5656
5657/* ========== Lock Bits ========== */
5658#define __LOCK_BITS_EXIST
5659#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
5660#define __BOOT_LOCK_APPLICATION_BITS_EXIST
5661#define __BOOT_LOCK_BOOT_BITS_EXIST
5662
5663
5664/* ========== Signature ========== */
5665#define SIGNATURE_0 0x1E
5666#define SIGNATURE_1 0x98
5667#define SIGNATURE_2 0x44
5668
5669/* ========== Power Reduction Condition Definitions ========== */
5670
5671/* PR.PRGEN */
5672#define __AVR_HAVE_PRGEN        (PR_RTC_bm|PR_EVSYS_bm)
5673#define __AVR_HAVE_PRGEN_RTC
5674#define __AVR_HAVE_PRGEN_EVSYS
5675
5676/* PR.PRPA */
5677#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm)
5678#define __AVR_HAVE_PRPA_ADC
5679#define __AVR_HAVE_PRPA_AC
5680
5681/* PR.PRPC */
5682#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
5683#define __AVR_HAVE_PRPC_TWI
5684#define __AVR_HAVE_PRPC_USART0
5685#define __AVR_HAVE_PRPC_SPI
5686#define __AVR_HAVE_PRPC_HIRES
5687#define __AVR_HAVE_PRPC_TC1
5688#define __AVR_HAVE_PRPC_TC0
5689
5690/* PR.PRPD */
5691#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm)
5692#define __AVR_HAVE_PRPD_USART0
5693#define __AVR_HAVE_PRPD_SPI
5694#define __AVR_HAVE_PRPD_TC0
5695
5696/* PR.PRPE */
5697#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm)
5698#define __AVR_HAVE_PRPE_TWI
5699#define __AVR_HAVE_PRPE_USART0
5700#define __AVR_HAVE_PRPE_TC0
5701
5702/* PR.PRPF */
5703#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm)
5704#define __AVR_HAVE_PRPF_USART0
5705#define __AVR_HAVE_PRPF_TC0
5706
5707
5708#endif /* _AVR_ATxmega256D3_H_ */
5709
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